Home
last modified time | relevance | path

Searched refs:REG_READ (Results 1 - 25 of 218) sorted by relevance

123456789

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn32.c271 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn32_get_inbox1_wptr()
276 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn32_get_inbox1_rptr()
297 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn32_get_outbox1_wptr()
314 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn32_is_hw_init()
341 test.all = REG_READ(DMCUB_GPINT_DATAIN1); in dmub_dcn32_is_gpint_acked()
348 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn32_get_gpint_response()
353 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); in dmub_dcn32_get_gpint_dataout()
370 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn32_get_fw_boot_status()
386 boot_options.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn32_skip_dmub_panel_power_sequence()
401 return REG_READ(DMCUB_OUTBOX0_WPT in dmub_dcn32_get_outbox0_wptr()
[all...]
H A Ddmub_dcn31.c247 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn31_get_inbox1_wptr()
252 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn31_get_inbox1_rptr()
273 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn31_get_outbox1_wptr()
290 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn31_is_hw_init()
322 test.all = REG_READ(DMCUB_GPINT_DATAIN1); in dmub_dcn31_is_gpint_acked()
329 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn31_get_gpint_response()
334 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); in dmub_dcn31_get_gpint_dataout()
351 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn31_get_fw_boot_status()
359 option.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn31_get_fw_boot_option()
382 boot_options.all = REG_READ(DMCUB_SCRATCH1 in dmub_dcn31_skip_dmub_panel_power_sequence()
[all...]
H A Ddmub_dcn20.c287 return REG_READ(DMCUB_INBOX1_WPTR); in dmub_dcn20_get_inbox1_wptr()
292 return REG_READ(DMCUB_INBOX1_RPTR); in dmub_dcn20_get_inbox1_rptr()
318 return REG_READ(DMCUB_OUTBOX1_WPTR); in dmub_dcn20_get_outbox1_wptr()
340 return REG_READ(DMCUB_OUTBOX0_WPTR); in dmub_dcn20_get_outbox0_wptr()
378 test.all = REG_READ(DMCUB_GPINT_DATAIN1); in dmub_dcn20_is_gpint_acked()
385 return REG_READ(DMCUB_SCRATCH7); in dmub_dcn20_get_gpint_response()
392 status.all = REG_READ(DMCUB_SCRATCH0); in dmub_dcn20_get_fw_boot_status()
406 boot_options.all = REG_READ(DMCUB_SCRATCH14); in dmub_dcn20_skip_dmub_panel_power_sequence()
413 return REG_READ(DMCUB_TIMER_CURRENT); in dmub_dcn20_get_current_time()
428 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH in dmub_dcn20_get_diagnostic_data()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
75 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
80 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
98 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
134 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
265 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_ in cdv_save_display_registers()
[all...]
H A Dmdfld_intel_display.c64 temp = REG_READ(map->conf); in mdfldWaitForPipeDisable()
92 temp = REG_READ(map->conf); in mdfldWaitForPipeEnable()
106 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
170 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
193 REG_READ(map->linoff); in mdfld__intel_pipe_set_base()
195 REG_READ(map->surf); in mdfld__intel_pipe_set_base()
220 temp = REG_READ(map->cntr); in mdfld_disable_crtc()
225 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
226 REG_READ(map->base); in mdfld_disable_crtc()
232 temp = REG_READ(ma in mdfld_disable_crtc()
[all...]
H A Dgma_display.c85 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
117 REG_READ(map->base); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
122 REG_READ(map->surf); in gma_pipe_set_base()
215 temp = REG_READ(map->dpll); in gma_crtc_dpms()
218 REG_READ(map->dpll); in gma_crtc_dpms()
222 REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
232 temp = REG_READ(map->cntr); in gma_crtc_dpms()
237 REG_WRITE(map->base, REG_READ(ma in gma_crtc_dpms()
[all...]
H A Dcdv_intel_display.c133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
151 *val = REG_READ(SB_DATA); in cdv_sb_read()
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
202 REG_READ(DPIO_CFG); in cdv_sb_reset()
471 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
475 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
483 REG_READ(OV_OVAD in cdv_disable_sr()
[all...]
H A Dpsb_intel_lvds.c66 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
78 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
190 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
221 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
224 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
263 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
264 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
265 lvds_priv->saveLVDS = REG_READ(LVD in psb_intel_lvds_save()
[all...]
H A Dpsb_intel_display.c82 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
191 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
215 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
224 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
245 REG_READ(LVDS); in psb_intel_crtc_mode_set()
250 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
257 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
282 REG_READ(map->conf); in psb_intel_crtc_mode_set()
311 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
313 fp = REG_READ(ma in psb_intel_crtc_clock_get()
[all...]
H A Doaktrail_hdmi.c292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
356 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
362 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
366 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
369 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
392 temp = REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
395 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
397 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); in oaktrail_crtc_hdmi_dpms()
398 REG_READ(DSPBSUR in oaktrail_crtc_hdmi_dpms()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dcdv_device.c36 REG_READ(vga_reg); in cdv_disable_vga()
51 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
53 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
57 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
59 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
71 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
76 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
94 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
124 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
240 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_ in cdv_save_display_registers()
[all...]
H A Dgma_display.c93 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
125 REG_READ(map->base); in gma_pipe_set_base()
128 REG_READ(map->base); in gma_pipe_set_base()
130 REG_READ(map->surf); in gma_pipe_set_base()
223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
240 temp = REG_READ(map->cntr); in gma_crtc_dpms()
245 REG_WRITE(map->base, REG_READ(ma in gma_crtc_dpms()
[all...]
H A Dcdv_intel_display.c134 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
146 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
152 *val = REG_READ(SB_DATA); in cdv_sb_read()
169 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
182 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
203 REG_READ(DPIO_CFG); in cdv_sb_reset()
472 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
475 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
476 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
484 REG_READ(OV_OVAD in cdv_disable_sr()
[all...]
H A Dpsb_intel_lvds.c67 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
79 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
189 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
223 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
231 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
234 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
261 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
262 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
263 lvds_priv->saveLVDS = REG_READ(LVD in psb_intel_lvds_save()
[all...]
H A Dpsb_intel_display.c84 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
197 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
221 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
230 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
251 REG_READ(LVDS); in psb_intel_crtc_mode_set()
256 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
263 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
288 REG_READ(map->conf); in psb_intel_crtc_mode_set()
317 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
319 fp = REG_READ(ma in psb_intel_crtc_clock_get()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk in rv1_dump_clk_registers()
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider in rv1_dump_clk_registers()
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow in rv1_dump_clk_registers()
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk in rv1_dump_clk_registers()
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk in rv1_dump_clk_registers()
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; in rv1_dump_clk_registers()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c496 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
498 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
500 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
501 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
503 s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub2_wm_read_state()
507 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
509 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
511 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
512 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
514 s->dram_clk_change = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_ in hubbub2_wm_read_state()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c499 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
501 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); in hubbub2_wm_read_state()
503 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); in hubbub2_wm_read_state()
504 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); in hubbub2_wm_read_state()
506 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); in hubbub2_wm_read_state()
510 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
512 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); in hubbub2_wm_read_state()
514 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); in hubbub2_wm_read_state()
515 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); in hubbub2_wm_read_state()
517 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_ in hubbub2_wm_read_state()
[all...]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(a in ath9k_hw_wow_set_arwr_reg()
[all...]
H A Dar9002_calib.c88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
135 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
156 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
176 (int32_t) REG_READ(a in ar9002_hw_adc_dccal_collect()
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
H A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(a in ath9k_hw_wow_set_arwr_reg()
[all...]
H A Dar9002_calib.c88 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
131 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
133 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
135 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
150 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
152 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
154 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
156 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
176 (int32_t) REG_READ(a in ar9002_hw_adc_dccal_collect()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c58 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL); in dce_get_16_bit_backlight_from_pwm()
62 bl_pwm_cntl = REG_READ(BL_PWM_CNTL); in dce_get_16_bit_backlight_from_pwm()
131 REG_READ(BL_PWM_CNTL); in dce_panel_cntl_hw_init()
133 REG_READ(BL_PWM_CNTL2); in dce_panel_cntl_hw_init()
135 REG_READ(BL_PWM_PERIOD_CNTL); in dce_panel_cntl_hw_init()
143 value = REG_READ(BIOS_SCRATCH_2); in dce_panel_cntl_hw_init()
190 REG_READ(BL_PWM_CNTL); in dce_store_backlight_level()
192 REG_READ(BL_PWM_CNTL2); in dce_store_backlight_level()
194 REG_READ(BL_PWM_PERIOD_CNTL); in dce_store_backlight_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.c57 REG_READ(BL_PWM_PERIOD_CNTL); in dce_get_16_bit_backlight_from_pwm()
61 REG_READ(BL_PWM_CNTL); in dce_get_16_bit_backlight_from_pwm()
113 REG_READ(BL_PWM_CNTL); in dce_panel_cntl_hw_init()
115 REG_READ(BL_PWM_CNTL2); in dce_panel_cntl_hw_init()
117 REG_READ(BL_PWM_PERIOD_CNTL); in dce_panel_cntl_hw_init()
131 value = REG_READ(BIOS_SCRATCH_2); in dce_panel_cntl_hw_init()
178 REG_READ(BL_PWM_CNTL); in dce_store_backlight_level()
180 REG_READ(BL_PWM_CNTL2); in dce_store_backlight_level()
182 REG_READ(BL_PWM_PERIOD_CNTL); in dce_store_backlight_level()

Completed in 16 milliseconds

123456789