Searched refs:ETH_PLL_CTL0 (Results 1 - 2 of 2) sorted by relevance
| /kernel/linux/linux-5.10/drivers/net/mdio/ |
| H A D | mdio-mux-meson-g12a.c | 19 #define ETH_PLL_CTL0 0x44 macro
77 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()
87 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
91 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
95 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
102 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()
111 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
114 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
122 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_is_enabled()
132 writel(0x29c0040a, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_init()
[all...] |
| /kernel/linux/linux-6.6/drivers/net/mdio/ |
| H A D | mdio-mux-meson-g12a.c | 19 #define ETH_PLL_CTL0 0x44 macro
75 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()
85 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
89 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
93 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
100 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()
109 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
112 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
120 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_is_enabled()
130 writel(0x29c0040a, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_init()
[all...] |
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