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Searched refs:CXL (Results 1 - 23 of 23) sorted by relevance

/kernel/linux/linux-6.6/tools/testing/cxl/test/
H A Dmock.c150 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_setup_hdm, CXL);
165 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_passthrough_decoder, CXL);
182 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_enumerate_decoders, CXL);
197 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_port_enumerate_dports, CXL);
212 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
229 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
245 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_rr_decode, CXL);
269 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, CXL);
286 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, CXL);
290 MODULE_IMPORT_NS(CXL); variable
[all...]
H A Dmem.c94 /* See CXL 2.0 Table 181 Get Health Info Output Payload */
669 * CXL spec rev3.0 8.2.9.8.6.2, The master pasphrase shall only be set in in mock_set_passphrase()
869 * as a CXL secure erase command without passphrase (0x4401). in mock_passphrase_secure_erase()
885 * CXL rev3 8.2.9.8.6.3 Disable Passphrase in mock_passphrase_secure_erase()
899 * it will behave the same as a CXL secure erase command without in mock_passphrase_secure_erase()
915 * CXL rev3 Table 8-118 in mock_passphrase_secure_erase()
1135 * A real CXL device will write pi->write_data to the address in mock_clear_poison()
1556 MODULE_IMPORT_NS(CXL); variable
H A Dcxl.c1457 MODULE_IMPORT_NS(CXL); variable
/kernel/linux/linux-6.6/drivers/cxl/core/
H A Dpmem.c13 * The core CXL PMEM infrastructure supports persistent memory
14 * provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
15 * 'bridge' device is added at the root of a CXL device topology if
17 * CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus'
18 * device. Then for each cxl_memdev in the CXL device topology a bridge
20 * are registered native LIBNVDIMM uapis are translated to CXL
52 EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm_bridge, CXL);
58 EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm_bridge, CXL);
81 EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);
126 * @port: CXL por
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H A Dregs.c16 * CXL device capabilities are enumerated by PCI DVSEC (Designated
19 * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
28 * cxl_probe_component_regs() - Detect CXL Component register blocks
33 * See CXL 2.0 8.2.4 Component Register Layout and Definition
34 * See CXL 2.0 8.2.5.5 CXL Device Register Interface
47 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in in cxl_probe_component_regs()
48 * CXL 2.0 8.2.4 Table 141. in cxl_probe_component_regs()
56 "Couldn't locate the CXL in cxl_probe_component_regs()
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H A Dport.c20 * The CXL core provides a set of interfaces that can be consumed by CXL aware
22 * regions, memory devices, ports, and decoders. CXL aware drivers must register
23 * with the CXL core via these interfaces in order to be able to participate in
24 * cross-device interleave coordination. The CXL core also establishes and
27 * CXL core introduces sysfs hierarchy to control the devices that are
428 EXPORT_SYMBOL_NS_GPL(to_cxl_root_decoder, CXL);
462 EXPORT_SYMBOL_NS_GPL(is_endpoint_decoder, CXL);
468 EXPORT_SYMBOL_NS_GPL(is_root_decoder, CXL);
474 EXPORT_SYMBOL_NS_GPL(is_switch_decoder, CXL);
[all...]
H A Dsuspend.c18 EXPORT_SYMBOL_NS_GPL(cxl_mem_active_inc, CXL);
24 EXPORT_SYMBOL_NS_GPL(cxl_mem_active_dec, CXL);
H A Dpci.c17 * Compute Express Link protocols are layered on top of PCIe. CXL core provides
18 * a set of helpers for CXL interactions which occur via PCIe.
102 EXPORT_SYMBOL_NS_GPL(devm_cxl_port_enumerate_dports, CXL);
210 EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
218 * Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high in wait_for_valid()
220 * deassertion of reset to CXL device. Likely it is already set by the in wait_for_valid()
350 * HDM decoders (values > 2 are also undefined as of CXL 2.0). As this in cxl_dvsec_rr_decode()
351 * driver is for a spec defined class code which must be CXL.mem in cxl_dvsec_rr_decode()
352 * capable, there is no point in continuing to enable CXL.mem. in cxl_dvsec_rr_decode()
424 EXPORT_SYMBOL_NS_GPL(cxl_dvsec_rr_decode, CXL);
[all...]
H A Dmemdev.c199 /* CXL 3.0 Spec 8.2.9.8.4.1 Separate pmem and ram poison requests */ in cxl_get_poison_by_memdev()
252 EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL);
375 EXPORT_SYMBOL_NS_GPL(cxl_inject_poison, CXL);
404 * In CXL 3.0 Spec 8.2.9.8.4.3, the Clear Poison mailbox command in cxl_clear_poison()
439 EXPORT_SYMBOL_NS_GPL(cxl_clear_poison, CXL);
533 EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL);
552 EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, CXL);
567 EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, CXL);
694 * See CXL-3.0 8.2.9.3.1 Get FW Info
728 * See CXL
[all...]
H A Dmbox.c20 * Core implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The
280 EXPORT_SYMBOL_NS_GPL(cxl_internal_send_cmd, CXL);
772 /* See CXL 2.0 Table 170. Get Log Input Payload */
784 * CXL devices have optional support for certain commands. This function will
837 EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL);
841 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
849 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44
857 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
1020 * See CXL rev 3.0 @8.2.9.2.2 Get Event Records
1021 * See CXL re
[all...]
H A Dpmu.c68 EXPORT_SYMBOL_NS_GPL(devm_cxl_pmu_add, CXL);
H A Dhdm.c14 * CXL 2.0 specification, is managed by an array of HDM Decoder register
15 * instances per CXL port and per CXL endpoint. Define common helpers
43 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
47 * CXL region is enumerated / activated.
68 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
199 EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_hdm, CXL);
221 EXPORT_SYMBOL_NS_GPL(cxl_dpa_debug, CXL);
358 EXPORT_SYMBOL_NS_GPL(devm_cxl_dpa_reserve, CXL);
[all...]
H A Dregion.c18 * CXL Regions represent mapped memory capacity in system physical address
19 * space. Whereas the CXL Root Decoders identify the bounds of potential CXL
768 * Per CXL Spec 3.1 8.2.4.20.12 software must commit decoders in auto_order_ok()
925 * The attach event is an opportunity to validate CXL decode setup
1396 dev_err(&cxlr->dev, "mismatched CXL topologies detected\n"); in cxl_region_setup_targets()
2105 EXPORT_SYMBOL_NS_GPL(is_cxl_region, CXL);
2381 EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, CXL);
2390 EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, CXL);
2459 * CXL 3. in poison_by_decoder()
3034 MODULE_IMPORT_NS(CXL); global() variable
[all...]
/kernel/linux/linux-6.6/drivers/dax/
H A Dcxl.c47 MODULE_IMPORT_NS(CXL); variable
/kernel/linux/linux-6.6/drivers/cxl/
H A Dport.c16 * port. All descendant ports of a CXL root port (described by platform
24 * status) the connectivity of the CXL.mem protocol throughout the
124 * This can't fail in practice as CXL root exit unregisters all in cxl_endpoint_port_probe()
206 MODULE_IMPORT_NS(CXL); variable
H A Dmem.c14 * CXL memory endpoint devices and switches are CXL capable devices that are
15 * participating in CXL.mem protocol. Their functionality builds on top of the
16 * CXL.io protocol that allows enumerating and configuring components via
19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem
20 * capability. With the detection of a CXL capable endpoint, the driver will
24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
152 dev_err(dev, "CXL port topology not found\n"); in cxl_mem_probe()
163 dev_err(dev, "CXL port topology %s not enabled\n", in cxl_mem_probe()
185 * The kernel may be operating out of CXL memor in cxl_mem_probe()
256 MODULE_IMPORT_NS(CXL); global() variable
[all...]
H A Dpmem.c268 .provider_name = "CXL", in cxl_nvdimm_bridge_probe()
392 * TODO enable CXL labels which skip the need for 'interleave-set cookie' in cxl_pmem_region_probe()
461 MODULE_IMPORT_NS(CXL); variable
H A Dacpi.c22 * CXL Specification 3.0 Table 9-22
93 /* Does this CXIMS entry apply to the given CXL Window? */ in cxl_parse_cxims()
233 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++); in __cxl_parse_cfmws()
434 * VH mode it will be bound to the CXL host bridge's port in add_host_bridge_dport()
482 dev_info(bridge, "host supports CXL (restricted)\n"); in add_host_bridge_uport()
492 "CXL CHBS version mismatch, skip port registration\n"); in add_host_bridge_uport()
509 dev_info(bridge, "host supports CXL\n"); in add_host_bridge_uport()
581 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
582 * @cxl_res: A standalone resource tree where each CXL window is a sibling
584 * Walk each CXL windo
773 MODULE_IMPORT_NS(CXL); global() variable
[all...]
H A Dpci.c21 * This implements the PCI exclusive functionality for a CXL device as it is
22 * defined by the Compute Express Link specification. CXL devices may surface
23 * certain functionality even if it isn't CXL enabled. While this driver is
24 * focused around the PCI specific aspects of a CXL device, it binds to the
25 * specific CXL memory device class code, and therefore the implementation of
26 * cxl_pci is focused around CXL memory devices.
29 * - Create the memX device and register on the CXL bus.
32 * - Registers a CXL mailbox with cxl_core.
39 /* CXL 2.0 - 8.2.8.4 */
43 * CXL 2.
973 MODULE_IMPORT_NS(CXL); global() variable
[all...]
/kernel/linux/linux-6.6/drivers/perf/
H A Dcxl_pmu.c6 * The CXL 3.0 specification includes a standard Performance Monitoring Unit,
7 * called the CXL PMU, or CPMU. In order to allow a high degree of
11 * Details in CXL rev 3.0 section 8.2.7 CPMU Register Interface
66 /* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
346 /* For CXL spec defined events */
352 /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
368 /* CXL rev 3.0 Table 3-20 - D2H Repsonse Encodings */
376 /* CXL rev 3.0 Table 3-21 - CXL
987 MODULE_IMPORT_NS(CXL); global() variable
[all...]
/kernel/linux/linux-6.6/kernel/
H A Dresource.c897 * resource discovery, and late discovery of CXL resources are expected
899 * CXL, is a module.
901 EXPORT_SYMBOL_NS_GPL(insert_resource_expand_to_fit, CXL);
1946 * Buses like CXL, that can dynamically instantiate new memory regions,
1961 EXPORT_SYMBOL_NS_GPL(alloc_free_mem_region, CXL);
/kernel/linux/linux-6.6/arch/x86/events/amd/
H A Dibs.c753 [IBS_DATA_SRC_EXT_EXT_MEM] = LN(CXL),
/kernel/linux/linux-6.6/drivers/pci/pcie/
H A Daer.c233 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, CXL);

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