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Searched refs:CLK_TOP_NFI2X_SEL (Results 1 - 15 of 15) sorted by relevance

/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h106 #define CLK_TOP_NFI2X_SEL 96 macro
H A Dmt2701-clk.h111 #define CLK_TOP_NFI2X_SEL 100 macro
H A Dmt2712-clk.h153 #define CLK_TOP_NFI2X_SEL 122 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmediatek,mt8365-clk.h106 #define CLK_TOP_NFI2X_SEL 96 macro
H A Dmt2701-clk.h111 #define CLK_TOP_NFI2X_SEL 100 macro
H A Dmt2712-clk.h153 #define CLK_TOP_NFI2X_SEL 122 macro
/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt2701-clk.h111 #define CLK_TOP_NFI2X_SEL 100 macro
H A Dmt2712-clk.h153 #define CLK_TOP_NFI2X_SEL 122 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dmt2701-clk.h111 #define CLK_TOP_NFI2X_SEL 100 macro
H A Dmt2712-clk.h153 #define CLK_TOP_NFI2X_SEL 122 macro
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mt2712.c683 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7),
H A Dclk-mt2701.c541 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
H A Dclk-mt8365.c508 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mt2701.c542 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
H A Dclk-mt2712.c790 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",

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