/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/ |
H A D | mt7622-clk.h | 80 #define CLK_TOP_MSDC30_0_SEL 68 macro
|
H A D | mt7629-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 85 macro
|
H A D | mt8135-clk.h | 97 #define CLK_TOP_MSDC30_0_SEL 86 macro
|
H A D | mt2701-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 84 macro
|
/kernel/linux/linux-5.10/include/dt-bindings/clock/ |
H A D | mt7622-clk.h | 80 #define CLK_TOP_MSDC30_0_SEL 68 macro
|
H A D | mt7629-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 85 macro
|
H A D | mt8135-clk.h | 97 #define CLK_TOP_MSDC30_0_SEL 86 macro
|
H A D | mt2701-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 84 macro
|
/kernel/linux/linux-6.6/include/dt-bindings/clock/ |
H A D | mt7622-clk.h | 80 #define CLK_TOP_MSDC30_0_SEL 68 macro
|
H A D | mt7629-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 85 macro
|
H A D | mt8135-clk.h | 97 #define CLK_TOP_MSDC30_0_SEL 86 macro
|
H A D | mt2701-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 84 macro
|
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/ |
H A D | mt7622-clk.h | 80 #define CLK_TOP_MSDC30_0_SEL 68 macro
|
H A D | mt7629-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 85 macro
|
H A D | mt8135-clk.h | 97 #define CLK_TOP_MSDC30_0_SEL 86 macro
|
H A D | mt2701-clk.h | 95 #define CLK_TOP_MSDC30_0_SEL 84 macro
|
/kernel/linux/linux-6.6/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 416 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
|
H A D | clk-mt8135.c | 388 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
|
H A D | clk-mt7629.c | 489 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
|
H A D | clk-mt2701.c | 511 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
|
/kernel/linux/linux-5.10/drivers/clk/mediatek/ |
H A D | clk-mt7622.c | 545 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
|
H A D | clk-mt7629.c | 514 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
|
H A D | clk-mt8135.c | 386 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
|
H A D | clk-mt2701.c | 512 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
|