Home
last modified time | relevance | path

Searched refs:CG_SPLL_FUNC_CNTL (Results 1 - 25 of 50) sorted by relevance

12

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drv740d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
H A Drv730d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
H A Drs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
H A Drs780_dpm.c212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
988 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1010 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
H A Drv740_dpm.c293 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
H A Dr600_dpm.c322 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
324 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
332 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
H A Drv730_dpm.c202 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
H A Drv770d.h89 #define CG_SPLL_FUNC_CNTL 0x600 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drv740d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
H A Drv730d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
H A Drs780d.h26 #define CG_SPLL_FUNC_CNTL 0x600 macro
H A Drs780_dpm.c212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
987 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1009 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
H A Drv740_dpm.c292 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
H A Dr600_dpm.c322 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
324 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
332 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
H A Drv730_dpm.c200 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1224 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
1226 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
1255 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
1257 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
1259 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
1261 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1334 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
1336 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
1365 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
1367 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
1369 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
1371 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c886 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
888 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
1344 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
1346 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
H A Diceland_smumgr.c826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
1462 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1464 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
H A Dci_smumgr.c326 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
328 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
1415 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in ci_populate_smc_acpi_level()
1417 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in ci_populate_smc_acpi_level()
H A Dtonga_smumgr.c569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
1210 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
1212 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c885 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
887 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
1343 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
1345 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
H A Diceland_smumgr.c826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
1462 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1464 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
H A Dtonga_smumgr.c569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
1210 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
1212 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
H A Dci_smumgr.c327 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
329 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in ci_calculate_sclk_params()
1416 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in ci_populate_smc_acpi_level()
1418 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in ci_populate_smc_acpi_level()

Completed in 51 milliseconds

12