Home
last modified time | relevance | path

Searched refs:CCR (Results 1 - 25 of 44) sorted by relevance

12

/kernel/linux/linux-5.10/arch/arm/plat-omap/
H A Ddma.c160 ccr = p->dma_read(CCR, lch); in omap_set_dma_priority()
165 p->dma_write(ccr, CCR, lch); in omap_set_dma_priority()
184 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
188 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
200 val = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
225 p->dma_write(val, CCR, lch); in omap_set_dma_transfer_params()
262 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
265 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
343 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
346 p->dma_write(l, CCR, lc in omap_set_dma_dest_params()
[all...]
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Domap-dma.c158 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
162 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
200 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
203 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
268 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
271 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
418 p->dma_write(dev_id | (1 << 10), CCR, free_ch); in omap_request_dma()
420 p->dma_write(dev_id, CCR, free_ch); in omap_request_dma()
443 p->dma_write(0, CCR, lch); in omap_free_dma()
510 l = p->dma_read(CCR, lc in omap_start_dma()
[all...]
H A Ddma.c57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
/kernel/linux/linux-5.10/drivers/dma/
H A Dtxx9dmac.h77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
H A Dtxx9dmac.c288 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", in txx9dmac_dump_regs()
295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
300 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, des in txx9dmac_dump_desc()
[all...]
/kernel/linux/linux-6.6/drivers/dma/
H A Dtxx9dmac.h77 TXX9_DMA_REG32(CCR); /* Channel Control Register */
87 u32 CCR; member
278 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
280 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
294 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
298 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
H A Dtxx9dmac.c288 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", in txx9dmac_dump_regs()
295 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
300 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", in txx9dmac_dump_regs()
307 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
326 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
365 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
386 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
391 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
480 desc->SAIR, desc->DAIR, desc->CCR, des in txx9dmac_dump_desc()
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
H A Dpm-imx6.c29 #define CCR 0x0 macro
253 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
256 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
259 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
262 writel(val, ccm_base + CCR); in imx6_enable_rbc()
286 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
289 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-atmel-tcb.c104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
325 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
333 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
349 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
/kernel/linux/linux-6.6/arch/arm/mach-imx/
H A Dpm-imx6.c31 #define CCR 0x0 macro
255 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
258 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
261 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
264 writel(val, ccm_base + CCR); in imx6_enable_rbc()
288 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
291 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-atmel-tcb.c104 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); in tc_clksrc_resume()
166 writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
215 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
225 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
325 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
333 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
349 writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Ddma.c57 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
214 l = dma_read(CCR, lch); in omap1_clear_dma()
216 dma_write(l, CCR, lch); in omap1_clear_dma()
/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-atmel-tcb.c189 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
193 ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
277 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_enable()
493 base + ATMEL_TC_REG(i, CCR)); in atmel_tcb_pwm_resume()
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-atmel-tcb.c167 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
172 ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_disable()
257 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR), in atmel_tcb_pwm_enable()
522 ATMEL_TC_REG(channel, CCR)); in atmel_tcb_pwm_resume()
/kernel/linux/linux-5.10/drivers/counter/
H A Dmicrochip-tcb-capture.c141 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_set()
148 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_set()
/kernel/linux/linux-6.6/drivers/counter/
H A Dmicrochip-tcb-capture.c130 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR), in mchp_tc_count_function_write()
137 ATMEL_TC_REG(priv->channel[1], CCR), in mchp_tc_count_function_write()
/kernel/linux/linux-5.10/drivers/dma/ti/
H A Domap-dma.c121 uint32_t ccr; /* CCR value */
457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
926 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1538 if (omap_dma_chan_read(c, CCR) in omap_dma_busy()
[all...]
/kernel/linux/linux-6.6/drivers/dma/ti/
H A Domap-dma.c121 uint32_t ccr; /* CCR value */
457 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
469 val = omap_dma_chan_read(c, CCR); in omap_dma_drain_chan()
495 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
504 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
506 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
517 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
587 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
931 uint32_t ccr = omap_dma_chan_read(c, CCR); in omap_dma_tx_status()
1543 if (omap_dma_chan_read(c, CCR) in omap_dma_busy()
[all...]
/kernel/linux/linux-6.6/include/sound/
H A Demu10k1.h475 #define CCR 0x09 /* Cache control register */ macro
476 SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
482 SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
483 SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
486 SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
H A Ddma.c53 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
H A Ddma.c54 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
/kernel/linux/linux-5.10/sound/soc/dwc/
H A Dlocal.h24 #define CCR 0x010 macro
/kernel/linux/linux-5.10/sound/soc/intel/keembay/
H A Dkmb_platform.h22 #define CCR 0x010 macro
/kernel/linux/linux-6.6/sound/soc/dwc/
H A Dlocal.h24 #define CCR 0x010 macro
/kernel/linux/linux-6.6/sound/soc/intel/keembay/
H A Dkmb_platform.h23 #define CCR 0x010 macro

Completed in 28 milliseconds

12