18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Intel KeemBay Platform driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2020 Intel Corporation. 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci */ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#ifndef KMB_PLATFORM_H_ 108c2ecf20Sopenharmony_ci#define KMB_PLATFORM_H_ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/bits.h> 138c2ecf20Sopenharmony_ci#include <linux/bitfield.h> 148c2ecf20Sopenharmony_ci#include <linux/types.h> 158c2ecf20Sopenharmony_ci 168c2ecf20Sopenharmony_ci/* Register values with reference to KMB databook v1.1 */ 178c2ecf20Sopenharmony_ci/* common register for all channel */ 188c2ecf20Sopenharmony_ci#define IER 0x000 198c2ecf20Sopenharmony_ci#define IRER 0x004 208c2ecf20Sopenharmony_ci#define ITER 0x008 218c2ecf20Sopenharmony_ci#define CER 0x00C 228c2ecf20Sopenharmony_ci#define CCR 0x010 238c2ecf20Sopenharmony_ci#define RXFFR 0x014 248c2ecf20Sopenharmony_ci#define TXFFR 0x018 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci/* Interrupt status register fields */ 278c2ecf20Sopenharmony_ci#define ISR_TXFO BIT(5) 288c2ecf20Sopenharmony_ci#define ISR_TXFE BIT(4) 298c2ecf20Sopenharmony_ci#define ISR_RXFO BIT(1) 308c2ecf20Sopenharmony_ci#define ISR_RXDA BIT(0) 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_ci/* I2S Tx Rx Registers for all channels */ 338c2ecf20Sopenharmony_ci#define LRBR_LTHR(x) (0x40 * (x) + 0x020) 348c2ecf20Sopenharmony_ci#define RRBR_RTHR(x) (0x40 * (x) + 0x024) 358c2ecf20Sopenharmony_ci#define RER(x) (0x40 * (x) + 0x028) 368c2ecf20Sopenharmony_ci#define TER(x) (0x40 * (x) + 0x02C) 378c2ecf20Sopenharmony_ci#define RCR(x) (0x40 * (x) + 0x030) 388c2ecf20Sopenharmony_ci#define TCR(x) (0x40 * (x) + 0x034) 398c2ecf20Sopenharmony_ci#define ISR(x) (0x40 * (x) + 0x038) 408c2ecf20Sopenharmony_ci#define IMR(x) (0x40 * (x) + 0x03C) 418c2ecf20Sopenharmony_ci#define ROR(x) (0x40 * (x) + 0x040) 428c2ecf20Sopenharmony_ci#define TOR(x) (0x40 * (x) + 0x044) 438c2ecf20Sopenharmony_ci#define RFCR(x) (0x40 * (x) + 0x048) 448c2ecf20Sopenharmony_ci#define TFCR(x) (0x40 * (x) + 0x04C) 458c2ecf20Sopenharmony_ci#define RFF(x) (0x40 * (x) + 0x050) 468c2ecf20Sopenharmony_ci#define TFF(x) (0x40 * (x) + 0x054) 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci/* I2S COMP Registers */ 498c2ecf20Sopenharmony_ci#define I2S_COMP_PARAM_2 0x01F0 508c2ecf20Sopenharmony_ci#define I2S_COMP_PARAM_1 0x01F4 518c2ecf20Sopenharmony_ci#define I2S_COMP_VERSION 0x01F8 528c2ecf20Sopenharmony_ci#define I2S_COMP_TYPE 0x01FC 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_ci/* PSS_GEN_CTRL_I2S_GEN_CFG_0 Registers */ 558c2ecf20Sopenharmony_ci#define I2S_GEN_CFG_0 0x000 568c2ecf20Sopenharmony_ci#define PSS_CPR_RST_EN 0x010 578c2ecf20Sopenharmony_ci#define PSS_CPR_RST_SET 0x014 588c2ecf20Sopenharmony_ci#define PSS_CPR_CLK_CLR 0x000 598c2ecf20Sopenharmony_ci#define PSS_CPR_AUX_RST_EN 0x070 608c2ecf20Sopenharmony_ci 618c2ecf20Sopenharmony_ci#define MASTER_MODE BIT(13) 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci/* Interrupt Flag */ 648c2ecf20Sopenharmony_ci#define TX_INT_FLAG GENMASK(5, 4) 658c2ecf20Sopenharmony_ci#define RX_INT_FLAG GENMASK(1, 0) 668c2ecf20Sopenharmony_ci/* 678c2ecf20Sopenharmony_ci * Component parameter register fields - define the I2S block's 688c2ecf20Sopenharmony_ci * configuration. 698c2ecf20Sopenharmony_ci */ 708c2ecf20Sopenharmony_ci#define COMP1_TX_WORDSIZE_3(r) FIELD_GET(GENMASK(27, 25), (r)) 718c2ecf20Sopenharmony_ci#define COMP1_TX_WORDSIZE_2(r) FIELD_GET(GENMASK(24, 22), (r)) 728c2ecf20Sopenharmony_ci#define COMP1_TX_WORDSIZE_1(r) FIELD_GET(GENMASK(21, 19), (r)) 738c2ecf20Sopenharmony_ci#define COMP1_TX_WORDSIZE_0(r) FIELD_GET(GENMASK(18, 16), (r)) 748c2ecf20Sopenharmony_ci#define COMP1_RX_ENABLED(r) FIELD_GET(BIT(6), (r)) 758c2ecf20Sopenharmony_ci#define COMP1_TX_ENABLED(r) FIELD_GET(BIT(5), (r)) 768c2ecf20Sopenharmony_ci#define COMP1_MODE_EN(r) FIELD_GET(BIT(4), (r)) 778c2ecf20Sopenharmony_ci#define COMP1_APB_DATA_WIDTH(r) FIELD_GET(GENMASK(1, 0), (r)) 788c2ecf20Sopenharmony_ci#define COMP2_RX_WORDSIZE_3(r) FIELD_GET(GENMASK(12, 10), (r)) 798c2ecf20Sopenharmony_ci#define COMP2_RX_WORDSIZE_2(r) FIELD_GET(GENMASK(9, 7), (r)) 808c2ecf20Sopenharmony_ci#define COMP2_RX_WORDSIZE_1(r) FIELD_GET(GENMASK(5, 3), (r)) 818c2ecf20Sopenharmony_ci#define COMP2_RX_WORDSIZE_0(r) FIELD_GET(GENMASK(2, 0), (r)) 828c2ecf20Sopenharmony_ci 838c2ecf20Sopenharmony_ci/* Add 1 to the below registers to indicate the actual size */ 848c2ecf20Sopenharmony_ci#define COMP1_TX_CHANNELS(r) (FIELD_GET(GENMASK(10, 9), (r)) + 1) 858c2ecf20Sopenharmony_ci#define COMP1_RX_CHANNELS(r) (FIELD_GET(GENMASK(8, 7), (r)) + 1) 868c2ecf20Sopenharmony_ci#define COMP1_FIFO_DEPTH(r) (FIELD_GET(GENMASK(3, 2), (r)) + 1) 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ci/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ 898c2ecf20Sopenharmony_ci#define COMP_MAX_WORDSIZE 8 /* 3 bits register width */ 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ci#define MAX_CHANNEL_NUM 8 928c2ecf20Sopenharmony_ci#define MIN_CHANNEL_NUM 2 938c2ecf20Sopenharmony_ci#define MAX_ISR 4 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci#define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */ 968c2ecf20Sopenharmony_ci#define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */ 978c2ecf20Sopenharmony_ci#define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */ 988c2ecf20Sopenharmony_ci#define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */ 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci#define DWC_I2S_PLAY BIT(0) 1018c2ecf20Sopenharmony_ci#define DWC_I2S_RECORD BIT(1) 1028c2ecf20Sopenharmony_ci#define DW_I2S_SLAVE BIT(2) 1038c2ecf20Sopenharmony_ci#define DW_I2S_MASTER BIT(3) 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci#define I2S_RXDMA 0x01C0 1068c2ecf20Sopenharmony_ci#define I2S_TXDMA 0x01C8 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci/* 1098c2ecf20Sopenharmony_ci * struct i2s_clk_config_data - represent i2s clk configuration data 1108c2ecf20Sopenharmony_ci * @chan_nr: number of channel 1118c2ecf20Sopenharmony_ci * @data_width: number of bits per sample (8/16/24/32 bit) 1128c2ecf20Sopenharmony_ci * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz) 1138c2ecf20Sopenharmony_ci */ 1148c2ecf20Sopenharmony_cistruct i2s_clk_config_data { 1158c2ecf20Sopenharmony_ci int chan_nr; 1168c2ecf20Sopenharmony_ci u32 data_width; 1178c2ecf20Sopenharmony_ci u32 sample_rate; 1188c2ecf20Sopenharmony_ci}; 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_cistruct kmb_i2s_info { 1218c2ecf20Sopenharmony_ci void __iomem *i2s_base; 1228c2ecf20Sopenharmony_ci void __iomem *pss_base; 1238c2ecf20Sopenharmony_ci struct clk *clk_i2s; 1248c2ecf20Sopenharmony_ci struct clk *clk_apb; 1258c2ecf20Sopenharmony_ci int active; 1268c2ecf20Sopenharmony_ci unsigned int capability; 1278c2ecf20Sopenharmony_ci unsigned int i2s_reg_comp1; 1288c2ecf20Sopenharmony_ci unsigned int i2s_reg_comp2; 1298c2ecf20Sopenharmony_ci struct device *dev; 1308c2ecf20Sopenharmony_ci u32 ccr; 1318c2ecf20Sopenharmony_ci u32 xfer_resolution; 1328c2ecf20Sopenharmony_ci u32 fifo_th; 1338c2ecf20Sopenharmony_ci bool master; 1348c2ecf20Sopenharmony_ci 1358c2ecf20Sopenharmony_ci struct i2s_clk_config_data config; 1368c2ecf20Sopenharmony_ci int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); 1378c2ecf20Sopenharmony_ci 1388c2ecf20Sopenharmony_ci /* data related to PIO transfers */ 1398c2ecf20Sopenharmony_ci bool use_pio; 1408c2ecf20Sopenharmony_ci struct snd_pcm_substream *tx_substream; 1418c2ecf20Sopenharmony_ci struct snd_pcm_substream *rx_substream; 1428c2ecf20Sopenharmony_ci unsigned int tx_ptr; 1438c2ecf20Sopenharmony_ci unsigned int rx_ptr; 1448c2ecf20Sopenharmony_ci}; 1458c2ecf20Sopenharmony_ci 1468c2ecf20Sopenharmony_ci#endif /* KMB_PLATFORM_H_ */ 147