18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * This file is licensed under the terms of the GNU General Public
58c2ecf20Sopenharmony_ci * License version 2. This program is licensed "as is" without any
68c2ecf20Sopenharmony_ci * warranty of any kind, whether express or implied.
78c2ecf20Sopenharmony_ci */
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci#ifndef __DESIGNWARE_LOCAL_H
108c2ecf20Sopenharmony_ci#define __DESIGNWARE_LOCAL_H
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_ci#include <linux/clk.h>
138c2ecf20Sopenharmony_ci#include <linux/device.h>
148c2ecf20Sopenharmony_ci#include <linux/types.h>
158c2ecf20Sopenharmony_ci#include <sound/dmaengine_pcm.h>
168c2ecf20Sopenharmony_ci#include <sound/pcm.h>
178c2ecf20Sopenharmony_ci#include <sound/designware_i2s.h>
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci/* common register for all channel */
208c2ecf20Sopenharmony_ci#define IER		0x000
218c2ecf20Sopenharmony_ci#define IRER		0x004
228c2ecf20Sopenharmony_ci#define ITER		0x008
238c2ecf20Sopenharmony_ci#define CER		0x00C
248c2ecf20Sopenharmony_ci#define CCR		0x010
258c2ecf20Sopenharmony_ci#define RXFFR		0x014
268c2ecf20Sopenharmony_ci#define TXFFR		0x018
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci/* Interrupt status register fields */
298c2ecf20Sopenharmony_ci#define ISR_TXFO	BIT(5)
308c2ecf20Sopenharmony_ci#define ISR_TXFE	BIT(4)
318c2ecf20Sopenharmony_ci#define ISR_RXFO	BIT(1)
328c2ecf20Sopenharmony_ci#define ISR_RXDA	BIT(0)
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_ci/* I2STxRxRegisters for all channels */
358c2ecf20Sopenharmony_ci#define LRBR_LTHR(x)	(0x40 * x + 0x020)
368c2ecf20Sopenharmony_ci#define RRBR_RTHR(x)	(0x40 * x + 0x024)
378c2ecf20Sopenharmony_ci#define RER(x)		(0x40 * x + 0x028)
388c2ecf20Sopenharmony_ci#define TER(x)		(0x40 * x + 0x02C)
398c2ecf20Sopenharmony_ci#define RCR(x)		(0x40 * x + 0x030)
408c2ecf20Sopenharmony_ci#define TCR(x)		(0x40 * x + 0x034)
418c2ecf20Sopenharmony_ci#define ISR(x)		(0x40 * x + 0x038)
428c2ecf20Sopenharmony_ci#define IMR(x)		(0x40 * x + 0x03C)
438c2ecf20Sopenharmony_ci#define ROR(x)		(0x40 * x + 0x040)
448c2ecf20Sopenharmony_ci#define TOR(x)		(0x40 * x + 0x044)
458c2ecf20Sopenharmony_ci#define RFCR(x)		(0x40 * x + 0x048)
468c2ecf20Sopenharmony_ci#define TFCR(x)		(0x40 * x + 0x04C)
478c2ecf20Sopenharmony_ci#define RFF(x)		(0x40 * x + 0x050)
488c2ecf20Sopenharmony_ci#define TFF(x)		(0x40 * x + 0x054)
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci/* I2SCOMPRegisters */
518c2ecf20Sopenharmony_ci#define I2S_COMP_PARAM_2	0x01F0
528c2ecf20Sopenharmony_ci#define I2S_COMP_PARAM_1	0x01F4
538c2ecf20Sopenharmony_ci#define I2S_COMP_VERSION	0x01F8
548c2ecf20Sopenharmony_ci#define I2S_COMP_TYPE		0x01FC
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci/*
578c2ecf20Sopenharmony_ci * Component parameter register fields - define the I2S block's
588c2ecf20Sopenharmony_ci * configuration.
598c2ecf20Sopenharmony_ci */
608c2ecf20Sopenharmony_ci#define	COMP1_TX_WORDSIZE_3(r)	(((r) & GENMASK(27, 25)) >> 25)
618c2ecf20Sopenharmony_ci#define	COMP1_TX_WORDSIZE_2(r)	(((r) & GENMASK(24, 22)) >> 22)
628c2ecf20Sopenharmony_ci#define	COMP1_TX_WORDSIZE_1(r)	(((r) & GENMASK(21, 19)) >> 19)
638c2ecf20Sopenharmony_ci#define	COMP1_TX_WORDSIZE_0(r)	(((r) & GENMASK(18, 16)) >> 16)
648c2ecf20Sopenharmony_ci#define	COMP1_TX_CHANNELS(r)	(((r) & GENMASK(10, 9)) >> 9)
658c2ecf20Sopenharmony_ci#define	COMP1_RX_CHANNELS(r)	(((r) & GENMASK(8, 7)) >> 7)
668c2ecf20Sopenharmony_ci#define	COMP1_RX_ENABLED(r)	(((r) & BIT(6)) >> 6)
678c2ecf20Sopenharmony_ci#define	COMP1_TX_ENABLED(r)	(((r) & BIT(5)) >> 5)
688c2ecf20Sopenharmony_ci#define	COMP1_MODE_EN(r)	(((r) & BIT(4)) >> 4)
698c2ecf20Sopenharmony_ci#define	COMP1_FIFO_DEPTH_GLOBAL(r)	(((r) & GENMASK(3, 2)) >> 2)
708c2ecf20Sopenharmony_ci#define	COMP1_APB_DATA_WIDTH(r)	(((r) & GENMASK(1, 0)) >> 0)
718c2ecf20Sopenharmony_ci
728c2ecf20Sopenharmony_ci#define	COMP2_RX_WORDSIZE_3(r)	(((r) & GENMASK(12, 10)) >> 10)
738c2ecf20Sopenharmony_ci#define	COMP2_RX_WORDSIZE_2(r)	(((r) & GENMASK(9, 7)) >> 7)
748c2ecf20Sopenharmony_ci#define	COMP2_RX_WORDSIZE_1(r)	(((r) & GENMASK(5, 3)) >> 3)
758c2ecf20Sopenharmony_ci#define	COMP2_RX_WORDSIZE_0(r)	(((r) & GENMASK(2, 0)) >> 0)
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
788c2ecf20Sopenharmony_ci#define	COMP_MAX_WORDSIZE	(1 << 3)
798c2ecf20Sopenharmony_ci#define	COMP_MAX_DATA_WIDTH	(1 << 2)
808c2ecf20Sopenharmony_ci
818c2ecf20Sopenharmony_ci#define MAX_CHANNEL_NUM		8
828c2ecf20Sopenharmony_ci#define MIN_CHANNEL_NUM		2
838c2ecf20Sopenharmony_ci
848c2ecf20Sopenharmony_ciunion dw_i2s_snd_dma_data {
858c2ecf20Sopenharmony_ci	struct i2s_dma_data pd;
868c2ecf20Sopenharmony_ci	struct snd_dmaengine_dai_dma_data dt;
878c2ecf20Sopenharmony_ci};
888c2ecf20Sopenharmony_ci
898c2ecf20Sopenharmony_cistruct dw_i2s_dev {
908c2ecf20Sopenharmony_ci	void __iomem *i2s_base;
918c2ecf20Sopenharmony_ci	struct clk *clk;
928c2ecf20Sopenharmony_ci	int active;
938c2ecf20Sopenharmony_ci	unsigned int capability;
948c2ecf20Sopenharmony_ci	unsigned int quirks;
958c2ecf20Sopenharmony_ci	unsigned int i2s_reg_comp1;
968c2ecf20Sopenharmony_ci	unsigned int i2s_reg_comp2;
978c2ecf20Sopenharmony_ci	struct device *dev;
988c2ecf20Sopenharmony_ci	u32 ccr;
998c2ecf20Sopenharmony_ci	u32 xfer_resolution;
1008c2ecf20Sopenharmony_ci	u32 fifo_th;
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_ci	/* data related to DMA transfers b/w i2s and DMAC */
1038c2ecf20Sopenharmony_ci	union dw_i2s_snd_dma_data play_dma_data;
1048c2ecf20Sopenharmony_ci	union dw_i2s_snd_dma_data capture_dma_data;
1058c2ecf20Sopenharmony_ci	struct i2s_clk_config_data config;
1068c2ecf20Sopenharmony_ci	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
1078c2ecf20Sopenharmony_ci
1088c2ecf20Sopenharmony_ci	/* data related to PIO transfers */
1098c2ecf20Sopenharmony_ci	bool use_pio;
1108c2ecf20Sopenharmony_ci	struct snd_pcm_substream __rcu *tx_substream;
1118c2ecf20Sopenharmony_ci	struct snd_pcm_substream __rcu *rx_substream;
1128c2ecf20Sopenharmony_ci	unsigned int (*tx_fn)(struct dw_i2s_dev *dev,
1138c2ecf20Sopenharmony_ci			struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
1148c2ecf20Sopenharmony_ci			bool *period_elapsed);
1158c2ecf20Sopenharmony_ci	unsigned int (*rx_fn)(struct dw_i2s_dev *dev,
1168c2ecf20Sopenharmony_ci			struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
1178c2ecf20Sopenharmony_ci			bool *period_elapsed);
1188c2ecf20Sopenharmony_ci	unsigned int tx_ptr;
1198c2ecf20Sopenharmony_ci	unsigned int rx_ptr;
1208c2ecf20Sopenharmony_ci};
1218c2ecf20Sopenharmony_ci
1228c2ecf20Sopenharmony_ci#if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)
1238c2ecf20Sopenharmony_civoid dw_pcm_push_tx(struct dw_i2s_dev *dev);
1248c2ecf20Sopenharmony_civoid dw_pcm_pop_rx(struct dw_i2s_dev *dev);
1258c2ecf20Sopenharmony_ciint dw_pcm_register(struct platform_device *pdev);
1268c2ecf20Sopenharmony_ci#else
1278c2ecf20Sopenharmony_civoid dw_pcm_push_tx(struct dw_i2s_dev *dev) { }
1288c2ecf20Sopenharmony_civoid dw_pcm_pop_rx(struct dw_i2s_dev *dev) { }
1298c2ecf20Sopenharmony_ciint dw_pcm_register(struct platform_device *pdev)
1308c2ecf20Sopenharmony_ci{
1318c2ecf20Sopenharmony_ci	return -EINVAL;
1328c2ecf20Sopenharmony_ci}
1338c2ecf20Sopenharmony_ci#endif
1348c2ecf20Sopenharmony_ci
1358c2ecf20Sopenharmony_ci#endif
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