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Help
Searched
refs:BIT_5
(Results
1 - 25
of
40
) sorted by relevance
1
2
/kernel/linux/linux-5.10/drivers/scsi/
H
A
D
qla1280.h
22
#define
BIT_5
0x20
macro
125
#define ISP_CFG0_1040C
BIT_5
/* ISP1040C */
128
#define ISP_CFG1_F64 BIT_4|
BIT_5
/* 128-byte FIFO threshold */
129
#define ISP_CFG1_F32
BIT_5
/* 128-byte FIFO threshold */
312
#define TP_PPR
BIT_5
/* PPR */
H
A
D
qla1280.c
445
return
BIT_5
;
in qla1280_data_direction()
449
return
BIT_5
| BIT_6;
in qla1280_data_direction()
1922
status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 |
BIT_5
|
in qla1280_init_rings()
2191
cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 |
BIT_5
| BIT_6);
in qla1280_nvram_config()
2263
mb[1] |=
BIT_5
;
in qla1280_nvram_config()
2268
mb[2] |=
BIT_5
;
in qla1280_nvram_config()
3913
if ((mb[2] &
BIT_5
) && ((mb[6] >> 8) & 0xff) >= 2)
in qla1280_get_target_parameters()
/kernel/linux/linux-6.6/drivers/scsi/
H
A
D
qla1280.h
22
#define
BIT_5
0x20
macro
124
#define ISP_CFG0_1040C
BIT_5
/* ISP1040C */
127
#define ISP_CFG1_F64 BIT_4|
BIT_5
/* 128-byte FIFO threshold */
128
#define ISP_CFG1_F32
BIT_5
/* 128-byte FIFO threshold */
311
#define TP_PPR
BIT_5
/* PPR */
H
A
D
qla1280.c
445
return
BIT_5
;
in qla1280_data_direction()
449
return
BIT_5
| BIT_6;
in qla1280_data_direction()
1912
status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 |
BIT_5
|
in qla1280_init_rings()
2181
cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 |
BIT_5
| BIT_6);
in qla1280_nvram_config()
2253
mb[1] |=
BIT_5
;
in qla1280_nvram_config()
2258
mb[2] |=
BIT_5
;
in qla1280_nvram_config()
3903
if ((mb[2] &
BIT_5
) && ((mb[6] >> 8) & 0xff) >= 2)
in qla1280_get_target_parameters()
/kernel/linux/linux-6.6/drivers/scsi/qla2xxx/
H
A
D
qla_target.h
85
#define OF_EXPL_CONF
BIT_5
/* Explicit Confirmation Requested */
179
#define NOTIFY_ACK_FLAGS_FCSP
BIT_5
480
#define CTIO7_FLAGS_EXPLICIT_CONFORM
BIT_5
749
#define NOTIFY_ACK_CLEAR_LIP_RESET
BIT_5
845
TRC_XMIT_STATUS =
BIT_5
,
H
A
D
qla_def.h
112
#define
BIT_5
0x20
macro
420
#define SRB_CRC_CTX_DSD_VALID
BIT_5
/* DIF: dsd_list valid */
538
#define SRB_LOGIN_FCSP
BIT_5
924
#define HCCR_RISC_PAUSE
BIT_5
/* Pause mode bit */
1243
#define FO1_DISABLE_100MS_LOS_WAIT
BIT_5
1264
#define ADD_FO2_ENABLE_SEL_CLS2
BIT_5
1418
#define MBX_5
BIT_5
2012
#define CF_READ
BIT_5
2080
#define PO_DISABLE_INCR_REF_TAG
BIT_5
2172
#define RF_INV_E_ORDER
BIT_5
/* Invali
[all...]
H
A
D
qla_fw.h
23
#define FO2_ENABLE_SEL_CLASS2
BIT_5
43
#define PDF_FCP2_CONF
BIT_5
908
#define LCF_SKIP_PRLI
BIT_5
/* Skip PRLI after PLOGI. */
909
#define LCF_IMPL_LOGO_ALL
BIT_5
/* Implicit LOGO to all ports. */
1188
#define CSRX_MAX_WRT_BURST_MASK (
BIT_5
|BIT_4)
1229
#define HCCRX_RISC_RESET
BIT_5
/* RISC Reset mode bit. */
1510
VP_FLAGS_NAME_VALID =
BIT_5
,
H
A
D
qla_init.c
4477
(BIT_7 | BIT_6 |
BIT_5
| BIT_4)) >> 4;
in qla2x00_update_fw_options()
4484
ha->fw_options[10] |=
BIT_5
|
in qla2x00_update_fw_options()
4490
(BIT_7 | BIT_6 |
BIT_5
)) >> 5;
in qla2x00_update_fw_options()
4495
(BIT_7 | BIT_6 |
BIT_5
| BIT_4)) >> 4;
in qla2x00_update_fw_options()
4502
ha->fw_options[11] |=
BIT_5
|
in qla2x00_update_fw_options()
5247
nv->firmware_options[1] = BIT_7 |
BIT_5
;
in qla2x00_nvram_config()
5248
nv->add_firmware_options[0] =
BIT_5
;
in qla2x00_nvram_config()
5249
nv->add_firmware_options[1] =
BIT_5
| BIT_4;
in qla2x00_nvram_config()
5254
nv->firmware_options[1] = BIT_7 |
BIT_5
;
in qla2x00_nvram_config()
5255
nv->add_firmware_options[0] =
BIT_5
;
in qla2x00_nvram_config()
[all...]
H
A
D
qla_mid.c
759
options |=
BIT_5
;
in qla25xx_create_req_que()
877
options |=
BIT_5
;
in qla25xx_create_rsp_que()
H
A
D
qla_mbx.c
731
mcp->in_mb |=
BIT_5
;
in qla2x00_execute_fw()
2352
mcp->mb[1] |=
BIT_5
;
in qla24xx_link_initialize()
4262
vpmod->options_idx1 = BIT_3|BIT_4|
BIT_5
;
in qla24xx_modify_vp_config()
6352
if (!(subcode & (BIT_2 |
BIT_5
)))
in qla83xx_access_control()
6365
if (subcode &
BIT_5
)
in qla83xx_access_control()
6701
if ((pd->prli_svc_param_word_3[0] &
BIT_5
) == 0)
in __qla24xx_parse_gpdb()
/kernel/linux/linux-5.10/drivers/scsi/qla2xxx/
H
A
D
qla_target.h
85
#define OF_EXPL_CONF
BIT_5
/* Explicit Confirmation Requested */
466
#define CTIO7_FLAGS_EXPLICIT_CONFORM
BIT_5
735
#define NOTIFY_ACK_CLEAR_LIP_RESET
BIT_5
834
TRC_XMIT_STATUS =
BIT_5
,
H
A
D
qla_fw.h
23
#define FO2_ENABLE_SEL_CLASS2
BIT_5
43
#define PDF_FCP2_CONF
BIT_5
901
#define LCF_SKIP_PRLI
BIT_5
/* Skip PRLI after PLOGI. */
902
#define LCF_IMPL_LOGO_ALL
BIT_5
/* Implicit LOGO to all ports. */
1160
#define CSRX_MAX_WRT_BURST_MASK (
BIT_5
|BIT_4)
1201
#define HCCRX_RISC_RESET
BIT_5
/* RISC Reset mode bit. */
1482
VP_FLAGS_NAME_VALID =
BIT_5
,
H
A
D
qla_def.h
86
#define
BIT_5
0x20
macro
370
#define SRB_CRC_CTX_DSD_VALID
BIT_5
/* DIF: dsd_list valid */
814
#define HCCR_RISC_PAUSE
BIT_5
/* Pause mode bit */
1127
#define FO1_DISABLE_100MS_LOS_WAIT
BIT_5
1148
#define ADD_FO2_ENABLE_SEL_CLS2
BIT_5
1302
#define MBX_5
BIT_5
1896
#define CF_READ
BIT_5
1964
#define PO_DISABLE_INCR_REF_TAG
BIT_5
2056
#define RF_INV_E_ORDER
BIT_5
/* Invalid entry order. */
2481
#define NVME_PRLI_SP_INITIATOR
BIT_5
[all...]
H
A
D
qla_init.c
4007
(BIT_7 | BIT_6 |
BIT_5
| BIT_4)) >> 4;
in qla2x00_update_fw_options()
4014
ha->fw_options[10] |=
BIT_5
|
in qla2x00_update_fw_options()
4020
(BIT_7 | BIT_6 |
BIT_5
)) >> 5;
in qla2x00_update_fw_options()
4025
(BIT_7 | BIT_6 |
BIT_5
| BIT_4)) >> 4;
in qla2x00_update_fw_options()
4032
ha->fw_options[11] |=
BIT_5
|
in qla2x00_update_fw_options()
4752
nv->firmware_options[1] = BIT_7 |
BIT_5
;
in qla2x00_nvram_config()
4753
nv->add_firmware_options[0] =
BIT_5
;
in qla2x00_nvram_config()
4754
nv->add_firmware_options[1] =
BIT_5
| BIT_4;
in qla2x00_nvram_config()
4759
nv->firmware_options[1] = BIT_7 |
BIT_5
;
in qla2x00_nvram_config()
4760
nv->add_firmware_options[0] =
BIT_5
;
in qla2x00_nvram_config()
[all...]
H
A
D
qla_mid.c
753
options |=
BIT_5
;
in qla25xx_create_req_que()
871
options |=
BIT_5
;
in qla25xx_create_rsp_que()
H
A
D
qla_mbx.c
702
mcp->in_mb |=
BIT_5
;
in qla2x00_execute_fw()
2299
mcp->mb[1] |=
BIT_5
;
in qla24xx_link_initialize()
4190
vpmod->options_idx1 = BIT_3|BIT_4|
BIT_5
;
in qla24xx_modify_vp_config()
6269
if (!(subcode & (BIT_2 |
BIT_5
)))
in qla83xx_access_control()
6282
if (subcode &
BIT_5
)
in qla83xx_access_control()
6565
if ((pd->prli_svc_param_word_3[0] &
BIT_5
) == 0)
in __qla24xx_parse_gpdb()
H
A
D
qla_target.c
6869
nv->firmware_options_1 |= cpu_to_le32(
BIT_5
);
in qlt_24xx_config_nvram_stage1()
6896
tmp = ~(BIT_4|
BIT_5
|BIT_6);
in qlt_24xx_config_nvram_stage1()
6975
nv->firmware_options_1 |= cpu_to_le32(
BIT_5
);
in qlt_81xx_config_nvram_stage1()
7000
tmp = ~(BIT_4|
BIT_5
|BIT_6);
in qlt_81xx_config_nvram_stage1()
7062
vpmod->options_idx1 &= ~
BIT_5
;
in qlt_modify_vp_config()
/kernel/linux/linux-5.10/drivers/net/ethernet/qlogic/qlcnic/
H
A
D
qlcnic_ctx.c
1372
arg1 |= (BIT_2 |
BIT_5
);
in qlcnic_config_switch_port()
1376
arg1 |= (BIT_3 |
BIT_5
);
in qlcnic_config_switch_port()
1427
esw_cfg->host_vlan_tag = !!(arg1 &
BIT_5
);
in qlcnic_get_eswitch_port_config()
H
A
D
qlcnic_hdr.h
200
#define
BIT_5
0x20
macro
H
A
D
qlcnic_minidump.c
28
#define QLCNIC_DUMP_RD_SAVE
BIT_5
/kernel/linux/linux-6.6/drivers/net/ethernet/qlogic/qlcnic/
H
A
D
qlcnic_ctx.c
1372
arg1 |= (BIT_2 |
BIT_5
);
in qlcnic_config_switch_port()
1376
arg1 |= (BIT_3 |
BIT_5
);
in qlcnic_config_switch_port()
1427
esw_cfg->host_vlan_tag = !!(arg1 &
BIT_5
);
in qlcnic_get_eswitch_port_config()
H
A
D
qlcnic_hdr.h
200
#define
BIT_5
0x20
macro
H
A
D
qlcnic_minidump.c
28
#define QLCNIC_DUMP_RD_SAVE
BIT_5
/kernel/linux/linux-5.10/drivers/scsi/qla4xxx/
H
A
D
ql4_def.h
86
#define
BIT_5
0x20
macro
/kernel/linux/linux-6.6/drivers/scsi/qla4xxx/
H
A
D
ql4_def.h
85
#define
BIT_5
0x20
macro
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