Lines Matching refs:BIT_5
86 #define BIT_5 0x20
370 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
814 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
1127 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1148 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1302 #define MBX_5 BIT_5
1896 #define CF_READ BIT_5
1964 #define PO_DISABLE_INCR_REF_TAG BIT_5
2056 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2481 #define NVME_PRLI_SP_INITIATOR BIT_5
2610 #define FCF_ASYNC_ACTIVE BIT_5
4050 #define DT_ISP6312 BIT_5
4735 #define DFLG_DEV_FAILED BIT_5
5071 #define FC_LL_I BIT_5 /* Intermidiate*/
5081 #define FC_TEC_SL BIT_5 /* short wave with OFC */
5089 #define FC_MED_MI BIT_5 /* Min Coax */
5098 #define FC_SP_16 BIT_5