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Searched refs:ARM_CKCTL (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Dsram.S29 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
H A Dpm.c204 #define EN_DSPCK 13 /* ARM_CKCTL */
269 ARM_SAVE(ARM_CKCTL); in omap1_pm_suspend()
292 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); in omap1_pm_suspend()
360 ARM_RESTORE(ARM_CKCTL); in omap1_pm_suspend()
418 ARM_SAVE(ARM_CKCTL); in omap_pm_debug_show()
473 ARM_SHOW(ARM_CKCTL), in omap_pm_debug_show()
H A Dclock_data.c202 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
212 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
817 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", in omap1_clk_init()
819 omap_readw(ARM_CKCTL)); in omap1_clk_init()
873 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); in omap1_clk_init()
875 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); in omap1_clk_init() local
H A Dclock.c167 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
267 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
271 omap_writew(regval, ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dsram.S29 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
H A Dpm.c196 #define EN_DSPCK 13 /* ARM_CKCTL */
251 ARM_SAVE(ARM_CKCTL); in omap1_pm_suspend()
273 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); in omap1_pm_suspend()
341 ARM_RESTORE(ARM_CKCTL); in omap1_pm_suspend()
393 ARM_SAVE(ARM_CKCTL); in omap_pm_debug_show()
441 ARM_SHOW(ARM_CKCTL), in omap_pm_debug_show()
H A Dclock.c169 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
309 /* protect ARM_CKCTL register from concurrent access via clk_enable/disable() */ in omap1_clk_set_rate_ckctl_arm()
312 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
316 omap_writew(regval, ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
541 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_enable_generic()
562 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_enable_generic()
586 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_disable_generic()
607 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_disable_generic()
H A Dclock_data.c191 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
731 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", in omap1_clk_init()
733 omap_readw(ARM_CKCTL)); in omap1_clk_init()
776 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); in omap1_clk_init()
/kernel/linux/linux-6.6/include/linux/soc/ti/
H A Domap1-io.h71 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro
/kernel/linux/linux-5.10/arch/arm/mach-omap1/include/mach/
H A Dhardware.h107 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro

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