| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| H A D | clk-pxa910.c | 33 #define APBC_SSP0 0x1c macro
241 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa910_clk_init()
245 apbc_base + APBC_SSP0, 10, 0, &clk_lock); in pxa910_clk_init()
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| H A D | clk-of-pxa168.c | 36 #define APBC_SSP0 0x81c macro
134 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
156 {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
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| H A D | clk-of-pxa910.c | 35 #define APBC_SSP0 0x1c macro
131 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
153 {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
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| H A D | clk-mmp2.c | 40 #define APBC_SSP0 0x50 macro
292 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
296 apbc_base + APBC_SSP0, 10, 0, &clk_lock); in mmp2_clk_init()
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| H A D | clk-pxa168.c | 33 #define APBC_SSP0 0x81c macro
236 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
239 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, in pxa168_clk_init()
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| H A D | clk-of-mmp2.c | 46 #define APBC_SSP0 0x50 macro
244 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
270 {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
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| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| H A D | clk-of-pxa168.c | 39 #define APBC_SSP0 0x81c macro
173 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
194 {PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
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| H A D | clk-of-pxa910.c | 32 #define APBC_SSP0 0x1c macro
130 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
152 {PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_lock},
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| H A D | clk-of-mmp2.c | 43 #define APBC_SSP0 0x50 macro
243 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
269 {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
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