Searched refs:APBC_PWM0 (Results 1 - 9 of 9) sorted by relevance
| /kernel/linux/linux-6.6/drivers/clk/mmp/ |
| H A D | clk-of-pxa168.c | 25 #define APBC_PWM0 0xc macro
166 {0, "pwm0_mux", pwm_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
187 {PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_lock},
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| H A D | clk-of-pxa910.c | 28 #define APBC_PWM0 0xc macro
145 {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
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| H A D | clk-of-mmp2.c | 39 #define APBC_PWM0 0x3c macro
260 {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
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| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| H A D | clk-pxa910.c | 29 #define APBC_PWM0 0xc macro
190 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa910_clk_init()
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| H A D | clk-of-pxa168.c | 31 #define APBC_PWM0 0xc macro
148 {PXA168_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
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| H A D | clk-of-pxa910.c | 31 #define APBC_PWM0 0xc macro
146 {PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
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| H A D | clk-mmp2.c | 36 #define APBC_PWM0 0x3c macro
230 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in mmp2_clk_init()
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| H A D | clk-pxa168.c | 29 #define APBC_PWM0 0xc macro
185 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
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| H A D | clk-of-mmp2.c | 42 #define APBC_PWM0 0x3c macro
261 {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
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