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/kernel/linux/linux-5.10/lib/crypto/
H A Dsha256.c48 u32 a, b, c, d, e, f, g, h, t1, t2; in sha256_transform() local
65 t1 = h + e1(e) + Ch(e, f, g) + 0x428a2f98 + W[0]; in sha256_transform()
66 t2 = e0(a) + Maj(a, b, c); d += t1; h = t1 + t2; in sha256_transform()
67 t1 = g + e1(d) + Ch(d, e, f) + 0x71374491 + W[1]; in sha256_transform()
68 t2 = e0(h) + Maj(h, a, b); c += t1; g = t1 + t2; in sha256_transform()
69 t1 = f + e1(c) + Ch(c, d, e) + 0xb5c0fbcf + W[2]; in sha256_transform()
70 t2 = e0(g) + Maj(g, h, a); b += t1; f = t1 in sha256_transform()
[all...]
/kernel/linux/linux-5.10/arch/loongarch/mm/
H A Dtlbex.S56 csrwr t1, EXCEPTION_KS1
64 csrrd t1, LOONGARCH_CSR_PGDL
69 alsl.d t1, ra, t1, 3
71 ld.d t1, t1, 0
73 alsl.d t1, ra, t1, 3
76 ld.d t1, t1,
[all...]
/kernel/linux/linux-6.6/arch/loongarch/mm/
H A Dtlbex.S48 csrwr t1, EXCEPTION_KS1
56 csrrd t1, LOONGARCH_CSR_PGDL
61 alsl.d t1, ra, t1, 3
63 ld.d t1, t1, 0
65 alsl.d t1, ra, t1, 3
68 ld.d t1, t1,
[all...]
/kernel/linux/linux-6.6/arch/mips/kernel/
H A Dcps-vec.S176 1: PTR_L t1, VPEBOOTCFG_PC(v1)
179 jr t1
239 PTR_LA t1, 1f
240 jr.hb t1
270 sll t1, ta1, VPECONF0_XTC_SHIFT
271 or t0, t0, t1
307 li t1, COREBOOTCFG_SIZE
308 mul t0, t0, t1
309 PTR_LA t1, mips_cps_core_bootcfg
310 PTR_L t1,
[all...]
H A Docteon_switch.S26 mfc0 t1, CP0_STATUS
27 LONG_S t1, THREAD_STATUS(a0)
41 li t1, -32768 /* Base address of CVMSEG */
46 LONG_L t8, 0(t1) /* Load from CVMSEG */
48 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
49 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
77 set_saved_sp t0, t1, t2
79 mfc0 t1, CP0_STATUS /* Do we really need this? */
81 and t1, a3
85 or a2, t1
[all...]
/kernel/linux/linux-5.10/arch/mips/netlogic/common/
H A Dreset.S60 mfcr t1, t0
63 or t1, t1, t2
64 mtcr t1, t0
67 mfcr t1, t0
68 ori t1, 0x1000 /* Enable Icache partitioning */
69 mtcr t1, t0
72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
73 mtcr t1, t0
83 li t1, (
[all...]
/kernel/linux/linux-5.10/arch/mips/kernel/
H A Dcps-vec.S179 1: PTR_L t1, VPEBOOTCFG_PC(v1)
182 jr t1
242 PTR_LA t1, 1f
243 jr.hb t1
273 sll t1, ta1, VPECONF0_XTC_SHIFT
274 or t0, t0, t1
311 li t1, COREBOOTCFG_SIZE
312 mul t0, t0, t1
313 PTR_LA t1, mips_cps_core_bootcfg
314 PTR_L t1,
[all...]
H A Docteon_switch.S27 mfc0 t1, CP0_STATUS
28 LONG_S t1, THREAD_STATUS(a0)
42 li t1, -32768 /* Base address of CVMSEG */
47 LONG_L t8, 0(t1) /* Load from CVMSEG */
49 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
50 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
78 set_saved_sp t0, t1, t2
80 mfc0 t1, CP0_STATUS /* Do we really need this? */
82 and t1, a3
86 or a2, t1
[all...]
/kernel/linux/linux-6.6/arch/loongarch/kernel/
H A Dlbt.S26 movscr2gr t1, $scr0 # save scr
27 stptr.d t1, a0, THREAD_SCR0
28 movscr2gr t1, $scr1
29 stptr.d t1, a0, THREAD_SCR1
30 movscr2gr t1, $scr2
31 stptr.d t1, a0, THREAD_SCR2
32 movscr2gr t1, $scr3
33 stptr.d t1, a0, THREAD_SCR3
35 x86mfflag t1, 0x3f # save eflags
36 stptr.d t1, a
[all...]
/kernel/linux/linux-6.6/arch/riscv/lib/
H A Dstrlen.S21 * t0, t1
23 mv t1, a0
25 lbu t0, 0(t1)
27 addi t1, t1, 1
30 sub a0, t1, a0
58 * t0, t1, t2, t3
72 REG_L t1, 0(t0)
79 SHIFT t1, t1, t
[all...]
H A Dmemmove.S41 * Both Copy Modes: t1 - Temporary for load-store
89 andi t1, t0, (SZREG - 1)
90 beqz t1, coaligned_copy
135 REG_L t1, (1 * SZREG)(a1)
138 sll t2, t1, a7
146 srl t1, t1, a6
148 or t2, t1, t2
195 REG_L t1, ( 0 * SZREG)(a4)
199 sll t1, t
[all...]
/kernel/linux/linux-5.10/arch/arm/crypto/
H A Dsha512-armv4.pl74 $t1="r10";
99 mov $t1,$Ehi,lsr#14
103 eor $t1,$t1,$Elo,lsl#18
106 eor $t1,$t1,$Ehi,lsr#18
108 eor $t1,$t1,$Elo,lsl#14
110 eor $t1,$t1,
[all...]
/kernel/linux/linux-6.6/arch/arm/crypto/
H A Dsha512-armv4.pl74 $t1="r10";
99 mov $t1,$Ehi,lsr#14
103 eor $t1,$t1,$Elo,lsl#18
106 eor $t1,$t1,$Ehi,lsr#18
108 eor $t1,$t1,$Elo,lsl#14
110 eor $t1,$t1,
[all...]
/kernel/linux/linux-5.10/lib/mpi/
H A Dmpi-inv.c33 MPI u, v, u1, u2 = NULL, u3, v1, v2 = NULL, v3, t1, t2 = NULL, t3; in mpi_invm() local
63 t1 = mpi_alloc_set_ui(0); in mpi_invm()
72 t1 = mpi_alloc_set_ui(1); in mpi_invm()
81 if (mpi_test_bit(t1, 0) || mpi_test_bit(t2, 0)) { in mpi_invm()
83 mpi_add(t1, t1, v); in mpi_invm()
86 mpi_rshift(t1, t1, 1); in mpi_invm()
90 if (mpi_test_bit(t1, 0)) in mpi_invm()
91 mpi_add(t1, t in mpi_invm()
[all...]
/kernel/linux/linux-6.6/lib/crypto/mpi/
H A Dmpi-inv.c33 MPI u, v, u1, u2 = NULL, u3, v1, v2 = NULL, v3, t1, t2 = NULL, t3; in mpi_invm() local
63 t1 = mpi_alloc_set_ui(0); in mpi_invm()
72 t1 = mpi_alloc_set_ui(1); in mpi_invm()
81 if (mpi_test_bit(t1, 0) || mpi_test_bit(t2, 0)) { in mpi_invm()
83 mpi_add(t1, t1, v); in mpi_invm()
86 mpi_rshift(t1, t1, 1); in mpi_invm()
90 if (mpi_test_bit(t1, 0)) in mpi_invm()
91 mpi_add(t1, t in mpi_invm()
[all...]
/kernel/linux/linux-5.10/drivers/soc/bcm/brcmstb/pm/
H A Ds2-mips.S52 addiu t1, s3, -1
53 not t1
56 and t0, t1
59 and t2, t1
68 2: move t1, s4
69 cache 0x1c, 0(t1)
70 addu t1, s3
89 li t1, ~(ST0_IM | ST0_IE)
90 and t0, t1
121 lw t1, TIMER_TIMER1_STA
[all...]
/kernel/linux/linux-6.6/drivers/soc/bcm/brcmstb/pm/
H A Ds2-mips.S52 addiu t1, s3, -1
53 not t1
56 and t0, t1
59 and t2, t1
68 2: move t1, s4
69 cache 0x1c, 0(t1)
70 addu t1, s3
89 li t1, ~(ST0_IM | ST0_IE)
90 and t0, t1
121 lw t1, TIMER_TIMER1_STA
[all...]
/kernel/linux/linux-5.10/arch/alpha/lib/
H A Dev6-stxcpy.S55 t1 == the first source word. */
60 mskqh t1, a1, t3 # U :
61 ornot t1, t2, t2 # E : (stall)
65 or t0, t3, t1 # E : (stall)
70 t1 == a source word not containing a null. */
74 stq_u t1, 0(a0) # L :
79 ldq_u t1, 0(a1) # L : Latency=3
81 cmpbge zero, t1, t8 # E : (3 cycle stall)
86 t1 == the source word containing the null
100 zapnot t1, t
[all...]
H A Dstxcpy.S44 t1 == the first source word. */
49 mskqh t1, a1, t3 # e0 :
50 ornot t1, t2, t2 # .. e1 :
53 or t0, t3, t1 # e0 :
58 t1 == a source word not containing a null. */
61 stq_u t1, 0(a0) # e0 :
63 ldq_u t1, 0(a1) # e0 :
65 cmpbge zero, t1, t8 # e0 (stall)
70 t1 == the source word containing the null
85 zapnot t1, t
[all...]
/kernel/linux/linux-6.6/arch/alpha/lib/
H A Dev6-stxcpy.S55 t1 == the first source word. */
60 mskqh t1, a1, t3 # U :
61 ornot t1, t2, t2 # E : (stall)
65 or t0, t3, t1 # E : (stall)
70 t1 == a source word not containing a null. */
74 stq_u t1, 0(a0) # L :
79 ldq_u t1, 0(a1) # L : Latency=3
81 cmpbge zero, t1, t8 # E : (3 cycle stall)
86 t1 == the source word containing the null
100 zapnot t1, t
[all...]
H A Dstxcpy.S44 t1 == the first source word. */
49 mskqh t1, a1, t3 # e0 :
50 ornot t1, t2, t2 # .. e1 :
53 or t0, t3, t1 # e0 :
58 t1 == a source word not containing a null. */
61 stq_u t1, 0(a0) # e0 :
63 ldq_u t1, 0(a1) # e0 :
65 cmpbge zero, t1, t8 # e0 (stall)
70 t1 == the source word containing the null
85 zapnot t1, t
[all...]
/kernel/linux/linux-5.10/arch/mips/net/
H A Dbpf_jit_asm.S64 PTR_ADDU t1, $r_skb_data, offset
66 lw $r_A, 0(t1)
74 srl t1, $r_A, 24
76 or t0, t0, t1
78 andi t1, $r_A, 0xff00
80 sll t1, t1, 8
81 or $r_A, t0, t1
93 PTR_ADDU t1, $r_skb_data, offset
94 lhu $r_A, 0(t1)
[all...]
/kernel/linux/linux-6.6/arch/loongarch/net/
H A Dbpf_jit.c212 u8 t1 = LOONGARCH_GPR_T1; in emit_bpf_tail_call() local
229 emit_insn(ctx, ldwu, t1, a1, off); in emit_bpf_tail_call()
230 /* bgeu $a2, $t1, jmp_offset */ in emit_bpf_tail_call()
231 if (emit_tailcall_jmp(ctx, BPF_JGE, a2, t1, jmp_offset) < 0) in emit_bpf_tail_call()
279 const u8 t1 = LOONGARCH_GPR_T1; in emit_atomic() local
289 move_imm(ctx, t1, off, false); in emit_atomic()
290 emit_insn(ctx, addd, t1, dst, t1); in emit_atomic()
297 emit_insn(ctx, amaddd, t2, t1, src); in emit_atomic()
299 emit_insn(ctx, amaddw, t2, t1, sr in emit_atomic()
458 const u8 t1 = LOONGARCH_GPR_T1; build_insn() local
[all...]
/kernel/linux/linux-5.10/arch/mips/dec/
H A Dint-handler.S133 mfc0 t1,CP0_STATUS
138 and t0,t1 # isolate allowed ones
150 # open coded PTR_LA t1, cpu_mask_nr_tbl
152 # open coded la t1, cpu_mask_nr_tbl
153 lui t1, %hi(cpu_mask_nr_tbl)
154 addiu t1, %lo(cpu_mask_nr_tbl)
158 1: lw t2,(t1)
162 addu t1,2*PTRSIZE # delay slot
167 lw a0,(-PTRSIZE)(t1)
186 andi t1,t
[all...]
/kernel/linux/linux-6.6/arch/mips/dec/
H A Dint-handler.S133 mfc0 t1,CP0_STATUS
138 and t0,t1 # isolate allowed ones
150 # open coded PTR_LA t1, cpu_mask_nr_tbl
152 # open coded la t1, cpu_mask_nr_tbl
153 lui t1, %hi(cpu_mask_nr_tbl)
154 addiu t1, %lo(cpu_mask_nr_tbl)
158 1: lw t2,(t1)
162 addu t1,2*PTRSIZE # delay slot
167 lw a0,(-PTRSIZE)(t1)
186 andi t1,t
[all...]

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