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/device/soc/hisilicon/common/platform/i2s/
H A Di2s_codec_hi35xx.c25 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_0); in GetI2sCodecInfo() local
26 I2S_PRINT_LOG_ERR("%s: AUDIO_ANA_CTRL_0[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_0, value); in GetI2sCodecInfo()
27 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_1); in GetI2sCodecInfo()
28 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_1[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_1, value); in GetI2sCodecInfo()
29 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_2); in GetI2sCodecInfo()
30 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_2[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_2, value); in GetI2sCodecInfo()
31 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_3); in GetI2sCodecInfo()
32 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_3[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_3, value); in GetI2sCodecInfo()
33 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_4); in GetI2sCodecInfo()
34 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_4[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_4, value); in GetI2sCodecInfo()
167 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_CTRL_REG_1); AudioCodecSetI2slFsSel() local
202 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_CTRL_REG_1); AudioCodecSetWidth() local
215 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + REG_ACODEC_REG18); AudioCodecSetAiaoChl() local
255 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_0); CodecAnaCtrl0Init() local
282 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_2); CodecInnerInit() local
373 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_2); CodecInit() local
[all...]
H A Di2s_aiao_hi35xx.c27 uint32_t value = Hi35xxI2sRegRead(i2sCfg->crg103Addr); in GetI2sAiaoRxInfo() local
28 I2S_PRINT_LOG_DBG("%s: PERI_CRG103[0x%px][0x%x]", __func__, i2sCfg->crg103Addr, value); in GetI2sAiaoRxInfo()
29 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_AIAO_SWITCH_RX_BCLK); in GetI2sAiaoRxInfo()
30 I2S_PRINT_LOG_DBG("%s: I2S_AIAO_SWITCH_RX_BCLK[0x%x][0x%08x]", __func__, I2S_AIAO_SWITCH_RX_BCLK, value); in GetI2sAiaoRxInfo()
31 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG0_00); in GetI2sAiaoRxInfo()
32 I2S_PRINT_LOG_DBG("%s: I2S_CRG_CFG0_00[0x%x][0x%08x]", __func__, I2S_CRG_CFG0_00, value); in GetI2sAiaoRxInfo()
33 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG1_00); in GetI2sAiaoRxInfo()
34 I2S_PRINT_LOG_DBG("%s: I2S_CRG_CFG1_00[0x%x][0x%08x]", __func__, I2S_CRG_CFG1_00, value); in GetI2sAiaoRxInfo()
35 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_IF_ATTR1); in GetI2sAiaoRxInfo()
36 I2S_PRINT_LOG_DBG("%s: RX_IF_ATTR1[0x%x][0x%08x]", __func__, RX_IF_ATTR1, value); in GetI2sAiaoRxInfo()
57 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG0_08); GetI2sAiaoTxInfo() local
260 uint32_t value; CfgSetI2sCrgCfg000() local
291 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG1_00); CfgSetI2sCrgCfg100() local
312 uint32_t value; CfgSetRxIfSAttr1() local
349 uint32_t value; CfgSetI2sCrgCfg008() local
370 uint32_t value; CfgSetI2sCrgCfg108() local
402 uint32_t value; CfgSetTxIfSAttr1() local
430 uint32_t value; CfgSetTxBuffInfo() local
464 uint32_t value; CfgSetRxBuffInfo() local
497 uint32_t value; CfgStartRecord() local
512 uint32_t value; CfgStartPlay() local
723 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_AIAO_SWITCH_RX_BCLK); AiaoInit() local
[all...]
/device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/csf/
H A Dmali_gpu_csf_registers.h117 #define CS_STATUS_CMD_PTR_LO 0x0040 /* () Program pointer current value, low word */
118 #define CS_STATUS_CMD_PTR_HI 0x0044 /* () Program pointer current value, high word */
123 #define CS_STATUS_WAIT_SYNC_VALUE 0x0058 /* () Sync object test value */
256 #define GLB_VERSION_PATCH_SET(reg_val, value) \
257 (((reg_val) & ~GLB_VERSION_PATCH_MASK) | (((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH_MASK))
261 #define GLB_VERSION_MINOR_SET(reg_val, value) \
262 (((reg_val) & ~GLB_VERSION_MINOR_MASK) | (((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR_MASK))
266 #define GLB_VERSION_MAJOR_SET(reg_val, value) \
267 (((reg_val) & ~GLB_VERSION_MAJOR_MASK) | (((value) << GLB_VERSION_MAJOR_SHIFT) & GLB_VERSION_MAJOR_MASK))
273 #define CS_REQ_STATE_SET(reg_val, value) \
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/csf/
H A Dmali_gpu_csf_registers.h111 #define CS_STATUS_CMD_PTR_LO 0x0040 /* () Program pointer current value, low word */
112 #define CS_STATUS_CMD_PTR_HI 0x0044 /* () Program pointer current value, high word */
117 #define CS_STATUS_WAIT_SYNC_VALUE 0x0058 /* () Sync object test value */
205 #define GLB_PROTM_COHERENCY 0x0020 /* () Configure COHERENCY_ENABLE register value to use in protected mode execution \
243 #define CS_REQ_STATE_SET(reg_val, value) \
244 (((reg_val) & ~CS_REQ_STATE_MASK) | (((value) << CS_REQ_STATE_SHIFT) & CS_REQ_STATE_MASK))
252 #define CS_REQ_EXTRACT_EVENT_SET(reg_val, value) \
253 (((reg_val) & ~CS_REQ_EXTRACT_EVENT_MASK) | (((value) << CS_REQ_EXTRACT_EVENT_SHIFT) & CS_REQ_EXTRACT_EVENT_MASK))
261 #define CS_REQ_ERROR_MODE_SET(reg_val, value) \
262 (((reg_val) & ~CS_REQ_ERROR_MODE_MASK) | (((value) << CS_REQ_ERROR_MODE_SHIF
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_linux_trace.h45 * @value: 64bits bitmask reporting either power status of the cores (1-ON, 0-OFF)
47 TRACE_EVENT(mali_pm_status, TP_PROTO(unsigned int event_id, unsigned long long value), TP_ARGS(event_id, value),
48 TP_STRUCT__entry(__field(unsigned int, event_id) __field(unsigned long long, value)),
49 TP_fast_assign(__entry->event_id = event_id; __entry->value = value;),
50 TP_printk("event %u = %llu", __entry->event_id, __entry->value));
55 * @value: 64bits bitmask reporting the cores to power up
57 TRACE_EVENT(mali_pm_power_on, TP_PROTO(unsigned int event_id, unsigned long long value), TP_ARGS(event_id, value),
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_linux_trace.h56 * @value: 64bits bitmask reporting either power status of the cores (1-ON, 0-OFF)
59 TP_PROTO(unsigned int event_id, unsigned long long value),
60 TP_ARGS(event_id, value),
63 __field(unsigned long long, value)
67 __entry->value = value;
69 TP_printk("event %u = %llu", __entry->event_id, __entry->value)
75 * @value: 64bits bitmask reporting the cores to power up
78 TP_PROTO(unsigned int event_id, unsigned long long value),
79 TP_ARGS(event_id, value),
[all...]
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Disp_params_v21.c33 u32 value; in isp_dpcc_config() local
36 value = rkisp_ioread32(params_vdev, ISP_DPCC0_MODE); in isp_dpcc_config()
37 value &= ISP_DPCC_EN; in isp_dpcc_config()
39 value |= (arg->stage1_enable & 0x01) << 0x02 | (arg->grayscale_mode & 0x01) << 1; in isp_dpcc_config()
40 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_MODE); in isp_dpcc_config()
41 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_MODE); in isp_dpcc_config()
43 value = (arg->sw_rk_out_sel & 0x03) << 0x05 | (arg->sw_dpcc_output_sel & 0x01) << 0x04 | in isp_dpcc_config()
46 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_OUTPUT_MODE); in isp_dpcc_config()
47 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_OUTPUT_MODE); in isp_dpcc_config()
49 value in isp_dpcc_config()
211 u32 value; isp_dpcc_enable() local
226 u32 new_control, value; isp_bls_config() local
538 u32 value; isp_debayer_config() local
612 u32 value; isp_ccm_config() local
668 u32 value; isp_goc_config() local
788 u32 value = rkisp_ioread32(params_vdev, ISP_RAWAF_CTRL); isp_rawaf_config() local
877 u32 block_hsize, block_vsize, value; isp_rawaelite_config() local
937 u32 addr, i, value, h_size, v_size; isp_rawaebig_config() local
1088 u32 i, value; isp_rawawb_config() local
1645 u32 value; isp_rawhstlite_config() local
1696 u32 i, j, wnd_num_idx, value; isp_rawhstbig_cfg_sram() local
1852 u32 value; isp_hdrmge_config() local
1889 u32 i, value; isp_hdrdrc_config() local
1949 u32 value; isp_hdrdrc_enable() local
1969 u32 value; isp_gic_config() local
2002 u32 value = 0; isp_gic_enable() local
2012 u32 i, value; isp_dhaz_config() local
2074 u32 value; isp_dhaz_enable() local
2096 u32 value, buf_idx, i; isp_3dlut_config() local
2127 u32 value; isp_3dlut_enable() local
2152 u32 value; isp_ldch_config() local
2206 u32 i, value; isp_ynr_config() local
2295 u32 ynr_ctrl, value = 0; isp_ynr_enable() local
2326 u32 value; isp_cnr_config() local
2368 u32 cnr_ctrl, value = 0; isp_cnr_enable() local
2394 u32 value; isp_sharp_config() local
2483 u32 value; isp_sharp_enable() local
2497 u32 i, value; isp_baynr_config() local
2537 u32 value; isp_baynr_enable() local
2551 u32 i, value; isp_bay3d_config() local
2589 u32 value, bay3d_ctrl; isp_bay3d_enable() local
3408 u32 value; rkisp_params_clear_fstflg() local
[all...]
H A Disp_params_v3x.c27 static inline void isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev, u32 value, u32 addr, u32 id) in isp3_param_write_direct() argument
30 rkisp_write(params_vdev->dev, addr, value, true); in isp3_param_write_direct()
32 rkisp_next_write(params_vdev->dev, addr, value, true); in isp3_param_write_direct()
36 static inline void isp3_param_write(struct rkisp_isp_params_vdev *params_vdev, u32 value, u32 addr, u32 id) in isp3_param_write() argument
39 rkisp_write(params_vdev->dev, addr, value, false); in isp3_param_write()
41 rkisp_next_write(params_vdev->dev, addr, value, false); in isp3_param_write()
101 u32 value; in isp_dpcc_config() local
104 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id); in isp_dpcc_config()
105 value &= ISP_DPCC_EN; in isp_dpcc_config()
107 value | in isp_dpcc_config()
314 u32 value; isp_dpcc_enable() local
330 u32 new_control, value; isp_bls_config() local
604 u32 value; isp_debayer_config() local
676 u32 value; isp_ccm_config() local
732 u32 value; isp_goc_config() local
852 u32 addr, value; isp_rawaebig_config_foraf() local
1049 u32 block_hsize, block_vsize, value; isp_rawaelite_config() local
1110 u32 addr, i, value, h_size, v_size; isp_rawaebig_config() local
1256 u32 i, value; isp_rawawb_config() local
1826 u32 value; isp_rawhstlite_config() local
1875 u32 i, j, wnd_num_idx, value; isp_rawhstbig_cfg_sram() local
2030 u32 value; isp_hdrmge_config() local
2079 u32 i, value; isp_hdrdrc_config() local
2136 u32 value; isp_hdrdrc_enable() local
2157 u32 value; isp_gic_config() local
2191 u32 value = 0; isp_gic_enable() local
2202 u32 i, value, ctrl; isp_dhaz_config() local
2295 u32 value; isp_dhaz_enable() local
2317 u32 value, buf_idx, i; isp_3dlut_config() local
2344 u32 value; isp_3dlut_enable() local
2370 u32 value; isp_ldch_config() local
2424 u32 i, value; isp_ynr_config() local
2538 u32 i, value, ctrl, gain_ctrl; isp_cnr_config() local
2612 u32 value; isp_sharp_config() local
2686 u32 value; isp_sharp_enable() local
2700 u32 i, value; isp_baynr_config() local
2742 u32 value; isp_baynr_enable() local
2757 u32 i, value; isp_bay3d_config() local
2805 u32 value, bay3d_ctrl; isp_bay3d_enable() local
3929 u32 value; rkisp_params_clear_fstflg() local
[all...]
H A Disp_stats_v21.c40 u32 value; in rkisp_stats_get_rawawb_meas_reg() local
43 value = rkisp_read(stats_vdev->dev, ISP21_RAWAWB_CTRL, true); in rkisp_stats_get_rawawb_meas_reg()
44 if (!(value & ISP2X_3A_MEAS_DONE)) { in rkisp_stats_get_rawawb_meas_reg()
54 value = rkisp_read(stats_vdev->dev, ISP21_RAWAWB_Y_HIST01 + CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT * i, true); in rkisp_stats_get_rawawb_meas_reg()
55 pbuf->params.rawawb.ro_yhist_bin[CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT * i] = value & 0xFFFF; in rkisp_stats_get_rawawb_meas_reg()
56 pbuf->params.rawawb.ro_yhist_bin[CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT * i + 1] = (value & 0xFFFF0000) >> 0x10; in rkisp_stats_get_rawawb_meas_reg()
90 u32 value, read_line; in rkisp_stats_get_rawaf_meas_reg() local
94 value = rkisp_read(stats_vdev->dev, ISP_RAWAF_CTRL, true); in rkisp_stats_get_rawaf_meas_reg()
95 if (!(value & ISP2X_3A_MEAS_DONE)) { in rkisp_stats_get_rawaf_meas_reg()
113 value in rkisp_stats_get_rawaf_meas_reg()
142 u32 addr, value; rkisp_stats_get_rawaebig_meas_reg() local
197 u32 addr, value; rkisp_stats_get_rawhstbig_meas_reg() local
337 u32 value; rkisp_stats_get_rawaelite_meas_reg() local
365 u32 value; rkisp_stats_get_rawhstlite_meas_reg() local
391 u32 value; rkisp_stats_get_bls_stats() local
437 u32 value, i; rkisp_stats_get_dhaz_stats() local
484 u32 value, rd_buf_idx; rkisp_stats_get_rawawb_meas_ddr() local
558 u32 i, value, addr, rd_buf_idx; rkisp_stats_get_rawaebig_meas_ddr() local
744 u32 i, value, rd_buf_idx; rkisp_stats_get_rawaelite_meas_ddr() local
803 u32 value; rkisp_stats_restart_rawawb_meas() local
814 u32 value; rkisp_stats_restart_rawaf_meas() local
826 u32 addr, value; rkisp_stats_restart_rawaebig_meas() local
852 u32 addr, value; rkisp_stats_restart_rawhstbig_meas() local
908 u32 value; rkisp_stats_restart_rawae0_meas() local
919 u32 value; rkisp_stats_restart_rawhst0_meas() local
[all...]
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Disp_params_v21.c39 u32 value; in isp_dpcc_config() local
42 value = rkisp_ioread32(params_vdev, ISP_DPCC0_MODE); in isp_dpcc_config()
43 value &= ISP_DPCC_EN; in isp_dpcc_config()
45 value |= (arg->stage1_enable & 0x01) << 2 | in isp_dpcc_config()
47 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_MODE); in isp_dpcc_config()
48 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_MODE); in isp_dpcc_config()
50 value = (arg->sw_rk_out_sel & 0x03) << 5 | in isp_dpcc_config()
56 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_OUTPUT_MODE); in isp_dpcc_config()
57 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_OUTPUT_MODE); in isp_dpcc_config()
59 value in isp_dpcc_config()
256 u32 value; isp_dpcc_enable() local
272 u32 new_control, value; isp_bls_config() local
669 u32 value; isp_debayer_config() local
781 u32 value; isp_ccm_config() local
840 u32 value; isp_goc_config() local
990 u32 value = rkisp_ioread32(params_vdev, ISP_RAWAF_CTRL); isp_rawaf_config() local
1086 u32 block_hsize, block_vsize, value; isp_rawaelite_config() local
1150 u32 addr, i, value, h_size, v_size; isp_rawaebig_config() local
1319 u32 i, value; isp_rawawb_config() local
2180 u32 value; isp_rawhstlite_config() local
2252 u32 i, j, wnd_num_idx, value; isp_rawhstbig_cfg_sram() local
2434 u32 value; isp_hdrmge_config() local
2475 u32 i, value; isp_hdrdrc_config() local
2542 u32 value; isp_hdrdrc_enable() local
2564 u32 value; isp_gic_config() local
2610 u32 value = 0; isp_gic_enable() local
2621 u32 i, value; isp_dhaz_config() local
2701 u32 value; isp_dhaz_enable() local
2725 u32 value, buf_idx, i; isp_3dlut_config() local
2757 u32 value; isp_3dlut_enable() local
2783 u32 value; isp_ldch_config() local
2840 u32 i, value; isp_ynr_config() local
2949 u32 ynr_ctrl, value = 0; isp_ynr_enable() local
2982 u32 value; isp_cnr_config() local
3028 u32 cnr_ctrl, value = 0; isp_cnr_enable() local
3056 u32 value; isp_sharp_config() local
3154 u32 value; isp_sharp_enable() local
3169 u32 i, value; isp_baynr_config() local
3210 u32 value; isp_baynr_enable() local
3225 u32 i, value; isp_bay3d_config() local
3265 u32 value, bay3d_ctrl; isp_bay3d_enable() local
4102 u32 value; rkisp_params_clear_fstflg() local
[all...]
H A Disp_params_v3x.c29 u32 value, u32 addr, u32 id) in isp3_param_write_direct()
32 rkisp_write(params_vdev->dev, addr, value, true); in isp3_param_write_direct()
34 rkisp_next_write(params_vdev->dev, addr, value, true); in isp3_param_write_direct()
39 u32 value, u32 addr, u32 id) in isp3_param_write()
42 rkisp_write(params_vdev->dev, addr, value, false); in isp3_param_write()
44 rkisp_next_write(params_vdev->dev, addr, value, false); in isp3_param_write()
110 u32 value; in isp_dpcc_config() local
113 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id); in isp_dpcc_config()
114 value &= ISP_DPCC_EN; in isp_dpcc_config()
116 value | in isp_dpcc_config()
28 isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev, u32 value, u32 addr, u32 id) isp3_param_write_direct() argument
38 isp3_param_write(struct rkisp_isp_params_vdev *params_vdev, u32 value, u32 addr, u32 id) isp3_param_write() argument
361 u32 value; isp_dpcc_enable() local
378 u32 new_control, value; isp_bls_config() local
682 u32 value; isp_debayer_config() local
789 u32 value; isp_ccm_config() local
847 u32 value; isp_goc_config() local
993 u32 addr, value; isp_rawaebig_config_foraf() local
1208 u32 block_hsize, block_vsize, value; isp_rawaelite_config() local
1271 u32 addr, i, value, h_size, v_size; isp_rawaebig_config() local
1426 u32 i, value; isp_rawawb_config() local
2322 u32 value; isp_rawhstlite_config() local
2385 u32 i, j, wnd_num_idx, value; isp_rawhstbig_cfg_sram() local
2561 u32 value; isp_hdrmge_config() local
2617 u32 i, value; isp_hdrdrc_config() local
2683 u32 value; isp_hdrdrc_enable() local
2706 u32 value; isp_gic_config() local
2751 u32 value = 0; isp_gic_enable() local
2763 u32 i, value, ctrl; isp_dhaz_config() local
2877 u32 value; isp_dhaz_enable() local
2901 u32 value, buf_idx, i; isp_3dlut_config() local
2929 u32 value; isp_3dlut_enable() local
2956 u32 value; isp_ldch_config() local
3012 u32 i, value; isp_ynr_config() local
3151 u32 i, value, ctrl, gain_ctrl; isp_cnr_config() local
3236 u32 value; isp_sharp_config() local
3335 u32 value; isp_sharp_enable() local
3350 u32 i, value; isp_baynr_config() local
3397 u32 value; isp_baynr_enable() local
3413 u32 i, value; isp_bay3d_config() local
3473 u32 value, bay3d_ctrl; isp_bay3d_enable() local
4547 u32 value; rkisp_params_clear_fstflg() local
[all...]
H A Disp_stats_v21.c41 u32 value; in rkisp_stats_get_rawawb_meas_reg() local
44 value = rkisp_read(stats_vdev->dev, ISP21_RAWAWB_CTRL, true); in rkisp_stats_get_rawawb_meas_reg()
45 if (!(value & ISP2X_3A_MEAS_DONE)) in rkisp_stats_get_rawawb_meas_reg()
53 value = rkisp_read(stats_vdev->dev, ISP21_RAWAWB_Y_HIST01 + 4 * i, true); in rkisp_stats_get_rawawb_meas_reg()
54 pbuf->params.rawawb.ro_yhist_bin[2 * i] = value & 0xFFFF; in rkisp_stats_get_rawawb_meas_reg()
55 pbuf->params.rawawb.ro_yhist_bin[2 * i + 1] = (value & 0xFFFF0000) >> 16; in rkisp_stats_get_rawawb_meas_reg()
90 u32 value, read_line; in rkisp_stats_get_rawaf_meas_reg() local
94 value = rkisp_read(stats_vdev->dev, ISP_RAWAF_CTRL, true); in rkisp_stats_get_rawaf_meas_reg()
95 if (!(value & ISP2X_3A_MEAS_DONE)) in rkisp_stats_get_rawaf_meas_reg()
111 value in rkisp_stats_get_rawaf_meas_reg()
138 u32 addr, value; rkisp_stats_get_rawaebig_meas_reg() local
186 u32 addr, value; rkisp_stats_get_rawhstbig_meas_reg() local
326 u32 value; rkisp_stats_get_rawaelite_meas_reg() local
353 u32 value; rkisp_stats_get_rawhstlite_meas_reg() local
378 u32 value; rkisp_stats_get_bls_stats() local
425 u32 value, i; rkisp_stats_get_dhaz_stats() local
472 u32 value, rd_buf_idx; rkisp_stats_get_rawawb_meas_ddr() local
551 u32 i, value, addr, rd_buf_idx; rkisp_stats_get_rawaebig_meas_ddr() local
730 u32 i, value, rd_buf_idx; rkisp_stats_get_rawaelite_meas_ddr() local
788 u32 value; rkisp_stats_restart_rawawb_meas() local
799 u32 value; rkisp_stats_restart_rawaf_meas() local
812 u32 addr, value; rkisp_stats_restart_rawaebig_meas() local
838 u32 addr, value; rkisp_stats_restart_rawhstbig_meas() local
900 u32 value; rkisp_stats_restart_rawae0_meas() local
911 u32 value; rkisp_stats_restart_rawhst0_meas() local
[all...]
/device/soc/rockchip/rk3568/hardware/omx_il/osal/
H A DRockchip_OSAL_Env.c29 OMX_ERRORTYPE Rockchip_OSAL_GetEnvU32(const char *name, OMX_U32 *value, OMX_U32 default_value) in Rockchip_OSAL_GetEnvU32() argument
38 *value = strtoul(prop, &endptr, base); in Rockchip_OSAL_GetEnvU32()
41 *value = default_value; in Rockchip_OSAL_GetEnvU32()
44 *value = default_value; in Rockchip_OSAL_GetEnvU32()
50 OMX_ERRORTYPE Rockchip_OSAL_GetEnvStr(const char *name, char *value, OMX_U32 valueSize, char *default_value) in Rockchip_OSAL_GetEnvStr() argument
53 if (value != NULL) { in Rockchip_OSAL_GetEnvStr()
54 int len = __system_property_get(name, value); in Rockchip_OSAL_GetEnvStr()
56 if (strcpy_s(value, strlen(default_value)+1, default_value) != EOK) { in Rockchip_OSAL_GetEnvStr()
63 omx_err("get env string failed, value is null"); in Rockchip_OSAL_GetEnvStr()
72 OMX_ERRORTYPE Rockchip_OSAL_SetEnvU32(const char *name, OMX_U32 value) in Rockchip_OSAL_SetEnvU32() argument
91 Rockchip_OSAL_SetEnvStr(const char *name, char *value) Rockchip_OSAL_SetEnvStr() argument
122 Rockchip_OSAL_GetEnvU32(const char *name, OMX_U32 *value, OMX_U32 default_value) Rockchip_OSAL_GetEnvU32() argument
143 Rockchip_OSAL_GetEnvStr(const char *name, char *value, OMX_U32 valueSize, char *default_value) Rockchip_OSAL_GetEnvStr() argument
157 Rockchip_OSAL_SetEnvU32(const char *name, OMX_U32 value) Rockchip_OSAL_SetEnvU32() argument
170 Rockchip_OSAL_SetEnvStr(const char *name, char *value) Rockchip_OSAL_SetEnvStr() argument
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/kernel/include/
H A Dlos_base.h77 * Read a UINT8 value from addr and stroed in value.
79 #define READ_UINT8(value, addr) ((value) = *((volatile UINT8 *)(addr)))
82 * Read a UINT16 value from addr and stroed in addr.
84 #define READ_UINT16(value, addr) ((value) = *((volatile UINT16 *)(addr)))
87 * Read a UINT32 value from addr and stroed in value.
89 #define READ_UINT32(value, add
[all...]
/device/soc/hisilicon/common/platform/timer/
H A Dtimer_hi35xx.c25 static int32_t TimerHi35xxRegWrite(uint32_t value, volatile uint8_t *addr) in TimerHi35xxRegWrite() argument
29 OSAL_WRITEL(value, addr); in TimerHi35xxRegWrite()
44 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL); in TimerHi35xxEnable() local
46 value &= ~TIMERx_CONTROL_TIMEREN; in TimerHi35xxEnable()
47 value |= (0x1 << TIMERx_CONTROL_TIMEREN_SHIFT); in TimerHi35xxEnable()
49 value &= ~TIMERx_CONTROL_TIMEREN; in TimerHi35xxEnable()
50 value |= (0x0 << TIMERx_CONTROL_TIMEREN_SHIFT); in TimerHi35xxEnable()
52 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL); in TimerHi35xxEnable()
61 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL); in TimerHi35xxSetMode() local
63 value in TimerHi35xxSetMode()
78 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL); TimerHi35xxSetPre() local
106 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL); TimerHi35xxIntEnable() local
129 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL); TimerHi35xxTimerSize() local
142 TimerHi35xxTimerLoadSet(struct TimerHi35xxInfo *info, uint32_t value) TimerHi35xxTimerLoadSet() argument
188 uint32_t value = TimerHi35xxRegRead(regBase); TimerHi35xxScCtrlSet() local
276 unsigned int value; TimerHi35xxSetTimeout() local
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_model_dummy.c72 /* Index of the last value register for each type of core, with the 1st value
77 /* Array for storing the value of SELECT register for each type of core */
226 /* Construct a value for the THREAD_FEATURES register, *except* the two most
465 u64 value = 0; in gpu_model_get_prfcnt_value() local
483 * IPA counters. If selected, the value returned for them will be zero. in gpu_model_get_prfcnt_value()
513 value += counters_data[event_index]; in gpu_model_get_prfcnt_value()
518 return (value & U32_MAX); in gpu_model_get_prfcnt_value()
520 return (value >> 32); in gpu_model_get_prfcnt_value()
1086 u8 midgard_model_write_reg(void *h, u32 addr, u32 value) argument
1441 midgard_model_read_reg(void *h, u32 addr, u32 * const value) global() argument
[all...]
/device/soc/hisilicon/common/platform/rtc/
H A Drtc_hi35xx.c34 static uint32_t HiSpiRead(struct RtcConfigInfo *rtcInfo, uint8_t regAdd, uint8_t *value) in HiSpiRead() argument
57 *value = readConfig.bits.spiReadData; in HiSpiRead()
61 static uint32_t HiRtcSpiRead(struct RtcConfigInfo *rtcInfo, uint8_t regAdd, uint8_t *value) in HiRtcSpiRead() argument
65 ret = HiSpiRead(rtcInfo, regAdd, value); in HiRtcSpiRead()
70 static uint32_t HiSpiWrite(struct RtcConfigInfo *rtcInfo, uint8_t regAdd, uint8_t value) in HiSpiWrite() argument
78 writeConfig.bits.spiWriteData = value; in HiSpiWrite()
97 static uint32_t HiRtcSpiWrite(struct RtcConfigInfo *rtcInfo, uint8_t regAdd, uint8_t value) in HiRtcSpiWrite() argument
101 ret = HiSpiWrite(rtcInfo, regAdd, value); in HiRtcSpiWrite()
160 uint8_t value = 0; in HiRtcReadPreviousConfig() local
162 ret = HiRtcSpiRead(rtcInfo, RTC_INT_RAW, &value); in HiRtcReadPreviousConfig()
201 uint8_t value; HiRtcReadTime() local
284 uint8_t value = 0; HiRtcWriteTime() local
401 uint8_t value = 0; HiAlarmInterruptEnable() local
435 uint16_t value; HiGetFreq() local
514 HiReadReg(struct RtcHost *host, uint8_t usrDefIndex, uint8_t *value) HiReadReg() argument
532 HiWriteReg(struct RtcHost *host, uint8_t usrDefIndex, uint8_t value) HiWriteReg() argument
567 uint32_t value; HiRtcAttachConfigData() local
613 uint32_t value; HiRtcConfigData() local
657 uint8_t value = 0; HiRtcIrqHandle() local
760 uint8_t value = 0; HiRtcHwInit() local
[all...]
/device/soc/hisilicon/common/platform/spi/
H A Dspi_hi35xx.c125 uint32_t value; in SpiCfgCs() local
134 value = OSAL_READL(pl022->regMiscCtrl); in SpiCfgCs()
135 value &= ~pl022->miscCtrlCs; in SpiCfgCs()
136 value |= (cs << pl022->miscCtrlCsShift); in SpiCfgCs()
137 OSAL_WRITEL(value, pl022->regMiscCtrl); in SpiCfgCs()
143 uint32_t value; in SpiHwInitCfg() local
145 value = OSAL_READL(pl022->regCrg); in SpiHwInitCfg()
146 value &= ~pl022->clkRstBit; in SpiHwInitCfg()
147 value |= pl022->clkEnBit; in SpiHwInitCfg()
148 OSAL_WRITEL(value, pl02 in SpiHwInitCfg()
154 uint32_t value; SpiHwExitCfg() local
165 uint32_t value; Pl022Enable() local
174 uint32_t value; Pl022Disable() local
183 uint32_t value; Pl022ConfigCPSR() local
194 uint32_t value; Pl022ConfigCR0() local
214 uint32_t value; Pl022ConfigCR1() local
231 uint32_t value; Pl022ConfigDma() local
254 unsigned long value; Pl022ConfigIrq() local
309 unsigned long value; Pl022CheckTimeout() local
327 uint32_t value; Pl022FlushFifo() local
362 unsigned long value; Pl022WriteFifo() local
376 unsigned long value; Pl022ReadFifo() local
863 unsigned long value; Pl022IrqHandleNoShare() local
[all...]
/device/board/hisilicon/hispark_taurus/audio_drivers/codec/hi3516/src/
H A Dhi3516_codec_impl.c52 // Read contrl reg bits value
60 regAttr->value = SysReadl((uintptr_t)g_regAcodecBase + regAttr->reg); in Hi3516CodecRegBitsRead()
61 *regValue = regAttr->value; in Hi3516CodecRegBitsRead()
62 regAttr->value = (*regValue >> regAttr->shift) & regAttr->mask; in Hi3516CodecRegBitsRead()
63 if (regAttr->value > regAttr->max || regAttr->value < regAttr->min) { in Hi3516CodecRegBitsRead()
64 AUDIO_DEVICE_LOG_DEBUG("invalid bitsValue=0x%x", regAttr->value); in Hi3516CodecRegBitsRead()
68 regAttr->value = regAttr->max - regAttr->value; in Hi3516CodecRegBitsRead()
73 // Update contrl reg bits value
289 AudioUpdateCodecAiaoRegBits(const struct AudioMixerControl *mixerControl, uint32_t value) AudioUpdateCodecAiaoRegBits() argument
316 uint32_t value; Hi3516CodecAiaoSetCtrlOps() local
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/linux/
H A Dosal_platform.c25 int osal_platform_get_modparam_uint(void *pdev, const char *name, unsigned int *value) in osal_platform_get_modparam_uint() argument
34 *value = temp_value; in osal_platform_get_modparam_uint()
39 int osal_platform_get_modparam_int(void *pdev, const char *name, int *value) in osal_platform_get_modparam_int() argument
48 *value = (int)temp_value; in osal_platform_get_modparam_int()
53 int osal_platform_get_modparam_uchar(void *pdev, const char *name, unsigned char *value) in osal_platform_get_modparam_uchar() argument
62 *value = temp_value; in osal_platform_get_modparam_uchar()
67 int osal_platform_get_modparam_ushort(void *pdev, const char *name, unsigned short *value) in osal_platform_get_modparam_ushort() argument
76 *value = temp_value; in osal_platform_get_modparam_ushort()
81 int osal_platform_get_modparam_string(void *pdev, const char *name, unsigned int size, char *value) in osal_platform_get_modparam_string() argument
90 if (strncpy_s(value, siz in osal_platform_get_modparam_string()
97 osal_of_property_read_u32(const void *np, const char *propname, unsigned int *value) osal_of_property_read_u32() argument
[all...]
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dbcmnvram.h49 char *value; member
54 * Get default value for an NVRAM variable
95 * Get the value of an NVRAM variable. The pointer returned may be
98 * @return value of variable or NULL if undefined
103 * Get the value of an NVRAM variable. The pointer returned may be
106 * @param bit bit value to get
107 * @return value of variable or NULL if undefined
112 * Read the reset GPIO value from the nvram and set the GPIO
118 * Get the value of an NVRAM variable.
120 * @return value o
139 const char *value = nvram_get(name); nvram_match() local
163 const char *value = nvram_get_bitflag(name, bit); nvram_match_bitflag() local
178 const char *value = nvram_get(name); nvram_invmatch() local
[all...]
/device/soc/rockchip/rk2206/sdk_liteos/platform/system/
H A Dprintf.c298 unsigned long value = l_value; in _ntoa_long() local
305 if (!value) { in _ntoa_long()
309 // write if precision != 0 and value is != 0 in _ntoa_long()
310 if (!(flags & FLAGS_PRECISION) || value) { in _ntoa_long()
316 const char digit = (char)(value % base); in _ntoa_long()
318 value /= base; in _ntoa_long()
319 } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); in _ntoa_long()
335 unsigned long long value = l_value; in _ntoa_long_long() local
341 if (!value) { in _ntoa_long_long()
345 // write if precision != 0 and value i in _ntoa_long_long()
386 double value = d_value; _ftoa() local
533 _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) _etoa() argument
852 const long long value = va_arg(va, long long); vsnprintf_s() local
858 const long value = va_arg(va, long); vsnprintf_s() local
863 const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) vsnprintf_s() local
881 const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) vsnprintf_s() local
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_ioctl.c189 * get -EINVAL, hence this is the return value we need to hand back for in drm_getclient()
238 req->value = 0; in drm_getcap()
243 req->value = 1; in drm_getcap()
246 req->value |= dev->driver->prime_fd_to_handle ? DRM_PRIME_CAP_IMPORT : 0; in drm_getcap()
247 req->value |= dev->driver->prime_handle_to_fd ? DRM_PRIME_CAP_EXPORT : 0; in drm_getcap()
250 req->value = drm_core_check_feature(dev, DRIVER_SYNCOBJ); in drm_getcap()
253 req->value = drm_core_check_feature(dev, DRIVER_SYNCOBJ_TIMELINE); in drm_getcap()
265 req->value = 1; in drm_getcap()
269 req->value = 1; in drm_getcap()
272 req->value in drm_getcap()
479 drm_copy_field(char __user *buf, size_t *buf_len, const char *value) drm_copy_field() argument
[all...]
/device/qemu/riscv32_virt/liteos_m/board/hardware/
H A Dosal_io_adapter.h28 #define writeb(value, address) ({ dsb(); WRITE_UINT8(value, address); })
29 #define writew(value, address) ({ dsb(); WRITE_UINT16(value, address); })
30 #define writel(value, address) ({ dsb(); WRITE_UINT32(value, address); })
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/hi_ir/
H A Dhiir.c61 #define write_reg(addr, value) ((*(volatile unsigned int *)(addr)) = value)
139 static void write_reg32(unsigned int value, unsigned int mask, const void *addr) in write_reg32() argument
145 t |= value & mask; in write_reg32()
182 unsigned int value; in hiir_config() local
189 value = (g_hiir_dev.dev_parm.codetype << 14); /* 14: [15:14] bits for code type */ in hiir_config()
190 value |= (g_hiir_dev.dev_parm.code_len - 1) << 8; /* 8: [13:8] bits for code len */ in hiir_config()
191 value |= (g_hiir_dev.dev_parm.frequence - 1); /* [6:0] bits for frequence */ in hiir_config()
192 write_reg(IR_CONFIG, value); in hiir_config()
194 value in hiir_config()
580 unsigned int value; init_ir_io() local
[all...]

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