Lines Matching refs:value
25 static int32_t TimerHi35xxRegWrite(uint32_t value, volatile uint8_t *addr)
29 OSAL_WRITEL(value, addr);
44 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
46 value &= ~TIMERx_CONTROL_TIMEREN;
47 value |= (0x1 << TIMERx_CONTROL_TIMEREN_SHIFT);
49 value &= ~TIMERx_CONTROL_TIMEREN;
50 value |= (0x0 << TIMERx_CONTROL_TIMEREN_SHIFT);
52 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
61 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
63 value &= ~TIMERx_CONTROL_TIMERMODE;
64 value |= (mode << TIMERx_CONTROL_TIMERMODE_SHIFT);
66 value &= ~TIMERx_CONTROL_ONESHOT;
67 value |= (TIMERx_CONTROL_TIMERMODE_ONESHOT_ONE << TIMERx_CONTROL_ONESHOT_SHIFT);
70 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
78 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
95 value &= ~TIMERx_CONTROL_TIMERPRE;
96 value |= (tmpVal << TIMERx_CONTROL_TIMERPRE_SHIFT);
97 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
106 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
108 value &= ~TIMERx_CONTROL_INTENABLE;
109 value |= (0x1 << TIMERx_CONTROL_INTENABLE_SHIFT);
111 value &= ~TIMERx_CONTROL_INTENABLE;
112 value |= (0x0 << TIMERx_CONTROL_INTENABLE_SHIFT);
114 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
129 uint32_t value = TimerHi35xxRegRead(info->regBase + HI35XX_TIMERx_CONTROL);
131 value &= ~TIMERx_CONTROL_TIMERSIZE;
132 value |= (0x1 << TIMERx_CONTROL_TIMERSIZE_SHIFT);
134 value &= ~TIMERx_CONTROL_TIMERSIZE;
135 value |= (0x0 << TIMERx_CONTROL_TIMERSIZE_SHIFT);
137 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_CONTROL);
141 // timer count value
142 static int32_t TimerHi35xxTimerLoadSet(struct TimerHi35xxInfo *info, uint32_t value)
146 TimerHi35xxRegWrite(value, info->regBase + HI35XX_TIMERx_LOAD);
188 uint32_t value = TimerHi35xxRegRead(regBase);
189 value &= ~HI35XX_SC_CTRL_TIMEREN0OV;
190 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN0OV_SHIFT);
191 value &= ~HI35XX_SC_CTRL_TIMEREN1OV;
192 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN1OV_SHIFT);
193 value &= ~HI35XX_SC_CTRL_TIMEREN2OV;
194 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN2OV_SHIFT);
195 value &= ~HI35XX_SC_CTRL_TIMEREN3OV;
196 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN3OV_SHIFT);
197 value &= ~HI35XX_SC_CTRL_TIMEREN4OV;
198 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN4OV_SHIFT);
199 value &= ~HI35XX_SC_CTRL_TIMEREN5OV;
200 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN5OV_SHIFT);
201 value &= ~HI35XX_SC_CTRL_TIMEREN6OV;
202 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN6OV_SHIFT);
203 value &= ~HI35XX_SC_CTRL_TIMEREN7OV;
204 value |= (0x0 << HI35XX_SC_CTRL_TIMEREN7OV_SHIFT);
205 TimerHi35xxRegWrite(value, regBase);
276 unsigned int value;
281 value = maxCnt;
283 value = (cntrl->info.useconds / HI35XX_TIMERx_US_TRANS_S) * HI35XX_TIMERx_CLOCK_HZ;
287 OSAL_WRITEL(value, info->regBase + HI35XX_TIMERx_LOAD);
289 HDF_LOGD("%s: timer[%u] [%u][%u][%u] ", __func__, info->number, maxSeconds, value, cntrl->info.useconds);