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/device/soc/hisilicon/hi3751v350/sdk_linux/source/common/include/
H A Dhi_log.h365 #define hi_err_print_null_pointer(val) HI_LOG_ERR("%s = %p, Null Pointer!\n", #val, val)
368 #define hi_err_print_s32(val) HI_LOG_ERR("%s = %d\n", #val, val)
369 #define hi_err_print_u32(val) HI_LOG_ERR("%s = %u\n", #val, val)
370 #define hi_err_print_s64(val) HI_LOG_ER
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/
H A Dprocfs.c21 u32 val; in isp20_show() local
23 val = rkisp_read(dev, ISP_DPCC0_MODE, false); in isp20_show()
24 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC0", (val & 1) ? "ON" : "OFF", val); in isp20_show()
25 val = rkisp_read(dev, ISP_DPCC1_MODE, false); in isp20_show()
26 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC1", (val & 1) ? "ON" : "OFF", val); in isp20_show()
27 val = rkisp_read(dev, ISP_DPCC2_MODE, false); in isp20_show()
28 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC2", (val & 1) ? "ON" : "OFF", val); in isp20_show()
105 u32 val, tmp; isp21_show() local
199 u32 val, tmp; isp30_show() local
535 u32 val = 0; isp_show() local
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/
H A Dprocfs.c29 u32 val; in isp20_show() local
31 val = rkisp_read(dev, ISP_DPCC0_MODE, false); in isp20_show()
32 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC0", (val & 1) ? "ON" : "OFF", val); in isp20_show()
33 val = rkisp_read(dev, ISP_DPCC1_MODE, false); in isp20_show()
34 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC1", (val & 1) ? "ON" : "OFF", val); in isp20_show()
35 val = rkisp_read(dev, ISP_DPCC2_MODE, false); in isp20_show()
36 seq_printf(p, "%-10s %s(0x%x)\n", "DPCC2", (val & 1) ? "ON" : "OFF", val); in isp20_show()
127 u32 val, tmp; isp21_show() local
239 u32 val, tmp; isp30_show() local
672 u32 val = 0; isp_show() local
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/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/common/cipher/src/drv/cipher_v1.0/osal/include/
H A Ddrv_osal_lib.h288 * \param[in] val The value of hex.
291 hi_void hex2str(char buf[MUL_VAL_2], hi_u32 buf_len, hi_u8 val);
298 hi_void module_reg_write(module_id id, hi_u32 offset, hi_u32 val);
302 #define symc_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_SYMC, offset, val)
306 #define hash_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_HASH, offset, val)
310 #define ifep_rsa_write(offset, val) module_reg_write(CRYPTO_MODULE_ID_IFEP_RSA, offset, val)
314 #define trng_write(offset, val) module_reg_writ
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/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dbcmendian.h40 #define BCMSWAP16(val) \
41 ((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
42 (((uint16)(val) & (uint16)0xff00U) >> 8)))
45 #define BCMSWAP32(val) \
46 ((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
47 (((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
48 (((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
49 (((uint32)(val) & (uint32)0xff000000U) >> 24)))
52 #define BCMSWAP32BY16(val) \
53 ((uint32)((((uint32)(val)
268 bcmswap16(uint16 val) bcmswap16() argument
274 bcmswap32(uint32 val) bcmswap32() argument
280 bcmswap64(uint64 val) bcmswap64() argument
286 bcmswap32by16(uint32 val) bcmswap32by16() argument
309 htol16_ua_store(uint16 val, uint8 *bytes) htol16_ua_store() argument
319 htol32_ua_store(uint32 val, uint8 *bytes) htol32_ua_store() argument
331 htol64_ua_store(uint64 val, uint8 *bytes) htol64_ua_store() argument
344 hton16_ua_store(uint16 val, uint8 *bytes) hton16_ua_store() argument
354 hton32_ua_store(uint32 val, uint8 *bytes) hton32_ua_store() argument
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/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c90 static inline bool param_read(struct regmap *base, const struct combphy_reg *reg, u32 val) in param_read() argument
103 return tmp == val; in param_read()
108 u32 val, mask, tmp; in param_write() local
112 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
114 return regmap_write(base, reg->offset, val); in param_write()
120 u32 mask, val; in rockchip_combphy_is_ready() local
124 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
125 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
127 return val; in rockchip_combphy_is_ready()
133 u32 val; rockchip_combphy_pcie_init() local
224 u32 val; rockchip_combphy_init() local
420 u32 val; rk3568_combphy_cfg() local
644 u32 val; rk3588_combphy_cfg() local
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c91 const struct combphy_reg *reg, u32 val) in param_read()
103 return tmp == val; in param_read()
109 u32 val, mask, tmp; in param_write() local
113 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in param_write()
115 return regmap_write(base, reg->offset, val); in param_write()
121 u32 mask, val; in rockchip_combphy_is_ready() local
126 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
127 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
129 return val; in rockchip_combphy_is_ready()
90 param_read(struct regmap *base, const struct combphy_reg *reg, u32 val) param_read() argument
135 u32 val; rockchip_combphy_pcie_init() local
226 u32 val; rockchip_combphy_init() local
425 u32 val; rk3568_combphy_cfg() local
649 u32 val; rk3588_combphy_cfg() local
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/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/ispp/
H A Dprocfs.c20 u32 val; in ispp_show() local
24 for (val = 0; val < dev->hw_dev->clks_num; val++) { in ispp_show()
25 seq_printf(p, "%-10s %ld\n", dev->hw_dev->match_data->clks[val], clk_get_rate(dev->hw_dev->clks[val])); in ispp_show()
36 for (val = STREAM_MB; val <= STREAM_S2; val++) { in ispp_show()
37 stream = &dev->stream_vdev.stream[val]; in ispp_show()
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/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/
H A Dprocfs.c20 u32 val; in ispp_show() local
27 for (val = 0; val < dev->hw_dev->clks_num; val++) { in ispp_show()
29 dev->hw_dev->match_data->clks[val], in ispp_show()
30 clk_get_rate(dev->hw_dev->clks[val])); in ispp_show()
49 for (val = STREAM_MB; val <= STREAM_S2; val++) { in ispp_show()
50 stream = &dev->stream_vdev.stream[val]; in ispp_show()
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/
H A Ddrm_atomic_uapi.c391 struct drm_property *property, uint64_t val) in drm_atomic_crtc_set_property()
399 state->active = val; in drm_atomic_crtc_set_property()
401 struct drm_property_blob *mode = drm_property_lookup_blob(dev, val); in drm_atomic_crtc_set_property()
406 state->vrr_enabled = val; in drm_atomic_crtc_set_property()
408 ret = drm_atomic_replace_property_blob_from_id(dev, &state->degamma_lut, val, -1, sizeof(struct drm_color_lut), in drm_atomic_crtc_set_property()
413 ret = drm_atomic_replace_property_blob_from_id(dev, &state->ctm, val, sizeof(struct drm_color_ctm), -1, in drm_atomic_crtc_set_property()
418 ret = drm_atomic_replace_property_blob_from_id(dev, &state->gamma_lut, val, -1, sizeof(struct drm_color_lut), in drm_atomic_crtc_set_property()
424 ret = drm_atomic_replace_property_blob_from_id(dev, &state->cubic_lut, val, -1, sizeof(struct drm_color_lut), in drm_atomic_crtc_set_property()
430 s32 __user *fence_ptr = u64_to_user_ptr(val); in drm_atomic_crtc_set_property()
442 return crtc->funcs->atomic_set_property(crtc, state, property, val); in drm_atomic_crtc_set_property()
390 drm_atomic_crtc_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, struct drm_property *property, uint64_t val) drm_atomic_crtc_set_property() argument
452 drm_atomic_crtc_get_property(struct drm_crtc *crtc, const struct drm_crtc_state *state, struct drm_property *property, uint64_t *val) drm_atomic_crtc_get_property() argument
485 drm_atomic_plane_set_property(struct drm_plane *plane, struct drm_plane_state *state, struct drm_file *file_priv, struct drm_property *property, uint64_t val) drm_atomic_plane_set_property() argument
568 drm_atomic_plane_get_property(struct drm_plane *plane, const struct drm_plane_state *state, struct drm_property *property, uint64_t *val) drm_atomic_plane_get_property() argument
637 drm_atomic_connector_set_property(struct drm_connector *connector, struct drm_connector_state *state, struct drm_file *file_priv, struct drm_property *property, uint64_t val) drm_atomic_connector_set_property() argument
744 drm_atomic_connector_get_property(struct drm_connector *connector, const struct drm_connector_state *state, struct drm_property *property, uint64_t *val) drm_atomic_connector_get_property() argument
814 drm_atomic_get_property(struct drm_mode_object *obj, struct drm_property *property, uint64_t *val) drm_atomic_get_property() argument
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_osk_atomics.c23 atomic_dec((atomic_t *)&atom->u.val); in mali_osk_atomic_dec()
28 return atomic_dec_return((atomic_t *)&atom->u.val); in mali_osk_atomic_dec_return()
33 atomic_inc((atomic_t *)&atom->u.val); in mali_osk_atomic_inc()
38 return atomic_inc_return((atomic_t *)&atom->u.val); in mali_osk_atomic_inc_return()
41 void mali_osk_atomic_init(_mali_osk_atomic_t *atom, u32 val) in mali_osk_atomic_init() argument
44 atomic_set((atomic_t *)&atom->u.val, val); in mali_osk_atomic_init()
49 return atomic_read((atomic_t *)&atom->u.val); in mali_osk_atomic_read()
57 u32 mali_osk_atomic_xchg(_mali_osk_atomic_t *atom, u32 val) in mali_osk_atomic_xchg() argument
59 return atomic_xchg((atomic_t *)&atom->u.val, va in mali_osk_atomic_xchg()
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_osk_atomics.c22 atomic_dec((atomic_t *)&atom->u.val); in _mali_osk_atomic_dec()
27 return atomic_dec_return((atomic_t *)&atom->u.val); in _mali_osk_atomic_dec_return()
32 atomic_inc((atomic_t *)&atom->u.val); in _mali_osk_atomic_inc()
37 return atomic_inc_return((atomic_t *)&atom->u.val); in _mali_osk_atomic_inc_return()
40 void _mali_osk_atomic_init(_mali_osk_atomic_t *atom, u32 val) in _mali_osk_atomic_init() argument
43 atomic_set((atomic_t *)&atom->u.val, val); in _mali_osk_atomic_init()
48 return atomic_read((atomic_t *)&atom->u.val); in _mali_osk_atomic_read()
56 u32 _mali_osk_atomic_xchg(_mali_osk_atomic_t *atom, u32 val) in _mali_osk_atomic_xchg() argument
58 return atomic_xchg((atomic_t *)&atom->u.val, va in _mali_osk_atomic_xchg()
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/device/soc/rockchip/common/hardware/mpp/include/
H A Drk_venc_cfg.h31 MPP_RET mpp_enc_cfg_set_s32(MppEncCfg cfg, const char *name, signed int val);
32 MPP_RET mpp_enc_cfg_set_u32(MppEncCfg cfg, const char *name, unsigned int val);
33 MPP_RET mpp_enc_cfg_set_s64(MppEncCfg cfg, const char *name, RK_S64 val);
34 MPP_RET mpp_enc_cfg_set_u64(MppEncCfg cfg, const char *name, RK_U64 val);
35 MPP_RET mpp_enc_cfg_set_ptr(MppEncCfg cfg, const char *name, void *val);
36 MPP_RET mpp_enc_cfg_set_st(MppEncCfg cfg, const char *name, void *val);
38 MPP_RET mpp_enc_cfg_get_s32(MppEncCfg cfg, const char *name, signed int *val);
39 MPP_RET mpp_enc_cfg_get_u32(MppEncCfg cfg, const char *name, unsigned int *val);
40 MPP_RET mpp_enc_cfg_get_s64(MppEncCfg cfg, const char *name, RK_S64 *val);
41 MPP_RET mpp_enc_cfg_get_u64(MppEncCfg cfg, const char *name, RK_U64 *val);
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H A Drk_vdec_cfg.h31 MPP_RET mpp_dec_cfg_set_s32(MppDecCfg cfg, const char *name, signed int val);
32 MPP_RET mpp_dec_cfg_set_u32(MppDecCfg cfg, const char *name, unsigned int val);
33 MPP_RET mpp_dec_cfg_set_s64(MppDecCfg cfg, const char *name, RK_S64 val);
34 MPP_RET mpp_dec_cfg_set_u64(MppDecCfg cfg, const char *name, RK_U64 val);
35 MPP_RET mpp_dec_cfg_set_ptr(MppDecCfg cfg, const char *name, void *val);
37 MPP_RET mpp_dec_cfg_get_s32(MppDecCfg cfg, const char *name, signed int *val);
38 MPP_RET mpp_dec_cfg_get_u32(MppDecCfg cfg, const char *name, unsigned int *val);
39 MPP_RET mpp_dec_cfg_get_s64(MppDecCfg cfg, const char *name, RK_S64 *val);
40 MPP_RET mpp_dec_cfg_get_u64(MppDecCfg cfg, const char *name, RK_U64 *val);
41 MPP_RET mpp_dec_cfg_get_ptr(MppDecCfg cfg, const char *name, void **val);
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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_jm.c55 void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val) in kbase_gpu_interrupt() argument
57 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ, NULL, val); in kbase_gpu_interrupt()
58 if (val & GPU_FAULT) { in kbase_gpu_interrupt()
59 kbase_report_gpu_fault(kbdev, val & MULTIPLE_GPU_FAULTS); in kbase_gpu_interrupt()
62 if (val & RESET_COMPLETED) { in kbase_gpu_interrupt()
66 if (val & PRFCNT_SAMPLE_COMPLETED) { in kbase_gpu_interrupt()
70 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val); in kbase_gpu_interrupt()
71 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val); in kbase_gpu_interrupt()
82 if (val & CLEAN_CACHES_COMPLETED) { in kbase_gpu_interrupt()
86 if (val in kbase_gpu_interrupt()
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/device/soc/rockchip/rk3399/hardware/mpp/include/
H A Drk_venc_cfg.h31 MPP_RET mpp_enc_cfg_set_s32(MppEncCfg cfg, const char *name, RK_S32 val);
32 MPP_RET mpp_enc_cfg_set_u32(MppEncCfg cfg, const char *name, RK_U32 val);
33 MPP_RET mpp_enc_cfg_set_s64(MppEncCfg cfg, const char *name, RK_S64 val);
34 MPP_RET mpp_enc_cfg_set_u64(MppEncCfg cfg, const char *name, RK_U64 val);
35 MPP_RET mpp_enc_cfg_set_ptr(MppEncCfg cfg, const char *name, void *val);
36 MPP_RET mpp_enc_cfg_set_st(MppEncCfg cfg, const char *name, void *val);
38 MPP_RET mpp_enc_cfg_get_s32(MppEncCfg cfg, const char *name, RK_S32 *val);
39 MPP_RET mpp_enc_cfg_get_u32(MppEncCfg cfg, const char *name, RK_U32 *val);
40 MPP_RET mpp_enc_cfg_get_s64(MppEncCfg cfg, const char *name, RK_S64 *val);
41 MPP_RET mpp_enc_cfg_get_u64(MppEncCfg cfg, const char *name, RK_U64 *val);
[all...]
H A Drk_vdec_cfg.h31 MPP_RET mpp_dec_cfg_set_s32(MppDecCfg cfg, const char *name, RK_S32 val);
32 MPP_RET mpp_dec_cfg_set_u32(MppDecCfg cfg, const char *name, RK_U32 val);
33 MPP_RET mpp_dec_cfg_set_s64(MppDecCfg cfg, const char *name, RK_S64 val);
34 MPP_RET mpp_dec_cfg_set_u64(MppDecCfg cfg, const char *name, RK_U64 val);
35 MPP_RET mpp_dec_cfg_set_ptr(MppDecCfg cfg, const char *name, void *val);
37 MPP_RET mpp_dec_cfg_get_s32(MppDecCfg cfg, const char *name, RK_S32 *val);
38 MPP_RET mpp_dec_cfg_get_u32(MppDecCfg cfg, const char *name, RK_U32 *val);
39 MPP_RET mpp_dec_cfg_get_s64(MppDecCfg cfg, const char *name, RK_S64 *val);
40 MPP_RET mpp_dec_cfg_get_u64(MppDecCfg cfg, const char *name, RK_U64 *val);
41 MPP_RET mpp_dec_cfg_get_ptr(MppDecCfg cfg, const char *name, void **val);
[all...]
/device/soc/rockchip/rk3568/hardware/mpp/include/
H A Drk_venc_cfg.h31 MPP_RET mpp_enc_cfg_set_s32(MppEncCfg cfg, const char *name, RK_S32 val);
32 MPP_RET mpp_enc_cfg_set_u32(MppEncCfg cfg, const char *name, RK_U32 val);
33 MPP_RET mpp_enc_cfg_set_s64(MppEncCfg cfg, const char *name, RK_S64 val);
34 MPP_RET mpp_enc_cfg_set_u64(MppEncCfg cfg, const char *name, RK_U64 val);
35 MPP_RET mpp_enc_cfg_set_ptr(MppEncCfg cfg, const char *name, void *val);
36 MPP_RET mpp_enc_cfg_set_st(MppEncCfg cfg, const char *name, void *val);
38 MPP_RET mpp_enc_cfg_get_s32(MppEncCfg cfg, const char *name, RK_S32 *val);
39 MPP_RET mpp_enc_cfg_get_u32(MppEncCfg cfg, const char *name, RK_U32 *val);
40 MPP_RET mpp_enc_cfg_get_s64(MppEncCfg cfg, const char *name, RK_S64 *val);
41 MPP_RET mpp_enc_cfg_get_u64(MppEncCfg cfg, const char *name, RK_U64 *val);
[all...]
H A Drk_vdec_cfg.h31 MPP_RET mpp_dec_cfg_set_s32(MppDecCfg cfg, const char *name, RK_S32 val);
32 MPP_RET mpp_dec_cfg_set_u32(MppDecCfg cfg, const char *name, RK_U32 val);
33 MPP_RET mpp_dec_cfg_set_s64(MppDecCfg cfg, const char *name, RK_S64 val);
34 MPP_RET mpp_dec_cfg_set_u64(MppDecCfg cfg, const char *name, RK_U64 val);
35 MPP_RET mpp_dec_cfg_set_ptr(MppDecCfg cfg, const char *name, void *val);
37 MPP_RET mpp_dec_cfg_get_s32(MppDecCfg cfg, const char *name, RK_S32 *val);
38 MPP_RET mpp_dec_cfg_get_u32(MppDecCfg cfg, const char *name, RK_U32 *val);
39 MPP_RET mpp_dec_cfg_get_s64(MppDecCfg cfg, const char *name, RK_S64 *val);
40 MPP_RET mpp_dec_cfg_get_u64(MppDecCfg cfg, const char *name, RK_U64 *val);
41 MPP_RET mpp_dec_cfg_get_ptr(MppDecCfg cfg, const char *name, void **val);
[all...]
/device/soc/rockchip/rk3588/hardware/mpp/include/
H A Drk_venc_cfg.h32 MPP_RET mpp_enc_cfg_set_s32(MppEncCfg cfg, const char *name, RK_S32 val);
33 MPP_RET mpp_enc_cfg_set_u32(MppEncCfg cfg, const char *name, RK_U32 val);
34 MPP_RET mpp_enc_cfg_set_s64(MppEncCfg cfg, const char *name, RK_S64 val);
35 MPP_RET mpp_enc_cfg_set_u64(MppEncCfg cfg, const char *name, RK_U64 val);
36 MPP_RET mpp_enc_cfg_set_ptr(MppEncCfg cfg, const char *name, void *val);
37 MPP_RET mpp_enc_cfg_set_st(MppEncCfg cfg, const char *name, void *val);
39 MPP_RET mpp_enc_cfg_get_s32(MppEncCfg cfg, const char *name, RK_S32 *val);
40 MPP_RET mpp_enc_cfg_get_u32(MppEncCfg cfg, const char *name, RK_U32 *val);
41 MPP_RET mpp_enc_cfg_get_s64(MppEncCfg cfg, const char *name, RK_S64 *val);
42 MPP_RET mpp_enc_cfg_get_u64(MppEncCfg cfg, const char *name, RK_U64 *val);
[all...]
H A Drk_vdec_cfg.h32 MPP_RET mpp_dec_cfg_set_s32(MppDecCfg cfg, const char *name, RK_S32 val);
33 MPP_RET mpp_dec_cfg_set_u32(MppDecCfg cfg, const char *name, RK_U32 val);
34 MPP_RET mpp_dec_cfg_set_s64(MppDecCfg cfg, const char *name, RK_S64 val);
35 MPP_RET mpp_dec_cfg_set_u64(MppDecCfg cfg, const char *name, RK_U64 val);
36 MPP_RET mpp_dec_cfg_set_ptr(MppDecCfg cfg, const char *name, void *val);
38 MPP_RET mpp_dec_cfg_get_s32(MppDecCfg cfg, const char *name, RK_S32 *val);
39 MPP_RET mpp_dec_cfg_get_u32(MppDecCfg cfg, const char *name, RK_U32 *val);
40 MPP_RET mpp_dec_cfg_get_s64(MppDecCfg cfg, const char *name, RK_S64 *val);
41 MPP_RET mpp_dec_cfg_get_u64(MppDecCfg cfg, const char *name, RK_U64 *val);
42 MPP_RET mpp_dec_cfg_get_ptr(MppDecCfg cfg, const char *name, void **val);
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_jm.c57 void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val) in kbase_gpu_interrupt() argument
59 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ, NULL, val); in kbase_gpu_interrupt()
60 if (val & GPU_FAULT) in kbase_gpu_interrupt()
61 kbase_report_gpu_fault(kbdev, val & MULTIPLE_GPU_FAULTS); in kbase_gpu_interrupt()
63 if (val & RESET_COMPLETED) in kbase_gpu_interrupt()
66 if (val & PRFCNT_SAMPLE_COMPLETED) in kbase_gpu_interrupt()
69 KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val); in kbase_gpu_interrupt()
70 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val); in kbase_gpu_interrupt()
81 if (val & CLEAN_CACHES_COMPLETED) in kbase_gpu_interrupt()
84 if (val in kbase_gpu_interrupt()
120 u32 val; kbase_reg_read() local
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dhi_types.h101 #define hi_set_bit_i(val, n) ((val) |= (1 << (n)))
102 #define hi_clr_bit_i(val, n) ((val) &= ~(1 << (n)))
103 #define hi_is_bit_set_i(val, n) ((val) & (1 << (n)))
104 #define hi_is_bit_clr_i(val, n) (~((val) & (1 << (n))))
105 #define hi_switch_bit_i(val, n) ((val)
[all...]
/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c34 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
186 int val = 0; in otg_mode_store() local
216 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_HOST, RK3288_UOC0_CON3_IDDIG_SET_MASK); in otg_mode_store()
219 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL, RK3288_UOC0_CON3_IDDIG_SET_MASK); in otg_mode_store()
222 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_OTG, RK3288_UOC0_CON3_IDDIG_SET_MASK); in otg_mode_store()
228 regmap_write(rk_phy->base->reg_base, RK3288_UOC0_CON3, val); in otg_mode_store()
251 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power() local
253 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
285 u32 val; in rockchip_usb_phy480m_is_enabled() local
306 unsigned int val; rk3288_usb_phy_init() local
442 unsigned int val; rk3288_usb_phy_otg_sm_work() local
529 unsigned int val; rk3288_chg_detect_work() local
655 unsigned int val; rk3288_usb_phy_bvalid_irq() local
683 unsigned int val; rk3288_usb_phy_probe_init() local
875 u32 val; rockchip_init_usb_uart_common() local
917 u32 val; rk3188_init_usb_uart() local
961 u32 val; rk3288_init_usb_uart() local
[all...]
/device/soc/hisilicon/common/platform/i2c/
H A Di2c_hi35xx.c171 unsigned int val; in Hi35xxI2cEnable() local
173 val = OSAL_READL(hi35xx->regBase + HI35XX_I2C_GLB); in Hi35xxI2cEnable()
174 val |= GLB_EN_MASK; in Hi35xxI2cEnable()
175 OSAL_WRITEL(val, hi35xx->regBase + HI35XX_I2C_GLB); in Hi35xxI2cEnable()
180 unsigned int val; in Hi35xxI2cDisable() local
182 val = OSAL_READL(hi35xx->regBase + HI35XX_I2C_GLB); in Hi35xxI2cDisable()
183 val &= ~GLB_EN_MASK; in Hi35xxI2cDisable()
184 OSAL_WRITEL(val, hi35xx->regBase + HI35XX_I2C_GLB); in Hi35xxI2cDisable()
189 unsigned int val; in Hi35xxI2cDisableIrq() local
191 val in Hi35xxI2cDisableIrq()
212 unsigned int val; Hi35xxI2cSetFreq() local
328 unsigned int val; Hi35xxI2cStartCmd() local
338 unsigned int val; Hi35xxI2cRescure() local
391 unsigned int val; Hi35xxI2cWaitRxNoempty() local
411 unsigned int val; Hi35xxI2cWaitTxNofull() local
431 unsigned int val; Hi35xxI2cWaitIdle() local
478 uint8_t val; Hi35xxI2cXferOneMsgPolling() local
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