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Searched refs:phy (Results 1 - 25 of 110) sorted by relevance

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/device/soc/rockchip/common/sdk_linux/include/linux/phy/
H A Dphy-rockchip-typec.h11 int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes, u8 swing, u8 pre_emp);
12 int tcphy_dp_set_lane_count(struct phy *phy, u8 lane_count);
13 int tcphy_dp_set_link_rate(struct phy *phy, int link_rate, bool ssc_on);
15 static inline int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes, u8 swing, u8 pre_emp) in tcphy_dp_set_phy_config() argument
20 static inline int tcphy_dp_set_lane_count(struct phy *phy, u argument
25 tcphy_dp_set_link_rate(struct phy *phy, int link_rate, bool ssc_on) tcphy_dp_set_link_rate() argument
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/device/soc/rockchip/rk3588/kernel/include/linux/phy/
H A Dphy-rockchip-typec.h11 int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, int lanes,
13 int tcphy_dp_set_lane_count(struct phy *phy, u8 lane_count);
14 int tcphy_dp_set_link_rate(struct phy *phy, int link_rate, bool ssc_on);
16 static inline int tcphy_dp_set_phy_config(struct phy *phy, int link_rate, in tcphy_dp_set_phy_config() argument
22 static inline int tcphy_dp_set_lane_count(struct phy *phy, u argument
27 tcphy_dp_set_link_rate(struct phy *phy, int link_rate, bool ssc_on) tcphy_dp_set_link_rate() argument
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/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.c3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy-snps-pcie3.h>
48 struct phy *phy; member
58 static int rockchip_p3phy_set_mode(struct phy *phy, enu argument
142 rochchip_p3phy_init(struct phy *phy) rochchip_p3phy_init() argument
165 rochchip_p3phy_exit(struct phy *phy) rochchip_p3phy_exit() argument
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H A Dphy-rockchip-inno-usb3.c30 #include <linux/phy/phy.h>
34 #include <linux/usb/phy.h>
104 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
105 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
106 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
107 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
128 struct phy *phy; member
360 dev_dbg(u3phy->dev, "deassert u2 and u3 phy powe in rockchip_u3phy_rest_deassert()
412 rockchip_u3phy_init(struct phy *phy) rockchip_u3phy_init() argument
417 rockchip_u3phy_exit(struct phy *phy) rockchip_u3phy_exit() argument
422 rockchip_u3phy_power_on(struct phy *phy) rockchip_u3phy_power_on() argument
470 rockchip_u3phy_power_off(struct phy *phy) rockchip_u3phy_power_off() argument
745 struct phy *phy; rockchip_u3phy_port_init() local
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H A Dphy-rockchip-naneng-edp.c18 #include <linux/phy/phy.h>
219 static int rockchip_edp_phy_configure(struct phy *phy, in rockchip_edp_phy_configure() argument
222 struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy); in rockchip_edp_phy_configure()
227 dev_err(edpphy->dev, "invalid params for phy configure\n"); in rockchip_edp_phy_configure()
264 static int rockchip_edp_phy_power_on(struct phy *phy) in rockchip_edp_phy_power_on() argument
266 struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy); in rockchip_edp_phy_power_on()
299 static int rockchip_edp_phy_power_off(struct phy *ph argument
328 struct phy *phy; rockchip_edp_phy_probe() local
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/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c23 #include <linux/phy/phy.h>
142 struct phy *phy; member
147 struct mutex mutex; /* protects registers of phy */
161 dev_err(dev, "Fail to get otg phy.\n"); in otg_mode_show()
189 dev_err(dev, "Fail to get otg phy.\n"); in otg_mode_store()
202 dev_err(&rk_phy->phy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n"); in otg_mode_store()
208 dev_warn(&rk_phy->phy->dev, "Same as current mode.\n"); in otg_mode_store()
238 /* Group all the usb2 phy attribute
249 rockchip_usb_phy_power(struct rockchip_usb_phy *phy, bool siddq) rockchip_usb_phy_power() argument
263 struct rockchip_usb_phy *phy = container_of(hw, struct rockchip_usb_phy, clk480m_hw); rockchip_usb_phy480m_disable() local
275 struct rockchip_usb_phy *phy = container_of(hw, struct rockchip_usb_phy, clk480m_hw); rockchip_usb_phy480m_enable() local
283 struct rockchip_usb_phy *phy = container_of(hw, struct rockchip_usb_phy, clk480m_hw); rockchip_usb_phy480m_is_enabled() local
304 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); rk3288_usb_phy_init() local
331 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); rk3288_usb_phy_exit() local
342 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); rockchip_usb_phy_power_off() local
355 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); rockchip_usb_phy_power_on() local
375 struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); rockchip_usb_phy_reset() local
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H A Dphy-rockchip-pcie.c17 #include <linux/phy/phy.h>
70 struct phy *phy; member
85 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev, struct of_phandle_args *args) in rockchip_pcie_phy_of_xlate()
90 return rk_phy->phys[0].phy; in rockchip_pcie_phy_of_xlate()
97 return rk_phy->phys[args->args[0]].phy; in rockchip_pcie_phy_of_xlate()
123 static int rockchip_pcie_phy_power_off(struct phy *phy) in rockchip_pcie_phy_power_off() argument
125 struct phy_pcie_instance *inst = phy_get_drvdata(phy); in rockchip_pcie_phy_power_off()
156 rockchip_pcie_phy_power_on(struct phy *phy) rockchip_pcie_phy_power_on() argument
254 rockchip_pcie_phy_init(struct phy *phy) rockchip_pcie_phy_init() argument
291 rockchip_pcie_phy_exit(struct phy *phy) rockchip_pcie_phy_exit() argument
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H A Dphy-rockchip-inno-dsidphy.c18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-mipi-dphy.h>
649 static int inno_dsidphy_power_on(struct phy *phy) in inno_dsidphy_power_on() argument
651 struct inno_dsidphy *inno = phy_get_drvdata(phy); in inno_dsidphy_power_on()
652 enum phy_mode mode = phy_get_mode(phy); in inno_dsidphy_power_on()
677 static int inno_dsidphy_power_off(struct phy *phy) in inno_dsidphy_power_off() argument
699 inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) inno_dsidphy_set_mode() argument
704 inno_dsidphy_configure(struct phy *phy, union phy_configure_opts *opts) inno_dsidphy_configure() argument
729 inno_dsidphy_init(struct phy *phy) inno_dsidphy_init() argument
740 inno_dsidphy_exit(struct phy *phy) inno_dsidphy_exit() argument
766 struct phy *phy; inno_dsidphy_probe() local
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H A Dphy-rockchip-inno-usb2.c23 #include <linux/phy/phy.h>
100 * @chg_mode: set phy in charge detection mode.
116 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
117 * @phy_sus: phy suspend register.
138 * @iddig_en: utmi iddig select between grf and phy,
139 * 0: from phy; 1: from grf
191 * struct rockchip_usb2phy_cfg - usb-phy configuration.
192 * @reg: the address offset of grf for usb-phy config.
193 * @num_ports: specify how many ports that the phy ha
244 struct phy *phy; global() member
681 rockchip_usb2phy_init(struct phy *phy) rockchip_usb2phy_init() argument
735 rockchip_usb2phy_power_on(struct phy *phy) rockchip_usb2phy_power_on() argument
799 rockchip_usb2phy_power_off(struct phy *phy) rockchip_usb2phy_power_off() argument
834 rockchip_usb2phy_exit(struct phy *phy) rockchip_usb2phy_exit() argument
871 rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) rockchip_usb2phy_set_mode() argument
2045 struct phy *phy; rockchip_usb2phy_probe() local
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/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-snps-pcie3.c3 * Rockchip PCIE3.0 phy driver
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy-snps-pcie3.h>
57 struct phy *phy; member
67 static int rockchip_p3phy_set_mode(struct phy *phy, enu argument
140 rochchip_p3phy_init(struct phy *phy) rochchip_p3phy_init() argument
164 rochchip_p3phy_exit(struct phy *phy) rochchip_p3phy_exit() argument
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H A Dphy-rockchip-inno-usb3.c30 #include <linux/phy/phy.h>
34 #include <linux/usb/phy.h>
106 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
107 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
108 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
109 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
126 struct phy *phy; member
349 dev_dbg(u3phy->dev, "deassert u2 and u3 phy powe in rockchip_u3phy_rest_deassert()
410 rockchip_u3phy_init(struct phy *phy) rockchip_u3phy_init() argument
415 rockchip_u3phy_exit(struct phy *phy) rockchip_u3phy_exit() argument
420 rockchip_u3phy_power_on(struct phy *phy) rockchip_u3phy_power_on() argument
465 rockchip_u3phy_power_off(struct phy *phy) rockchip_u3phy_power_off() argument
726 struct phy *phy; rockchip_u3phy_port_init() local
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H A Dphy-rockchip-naneng-edp.c18 #include <linux/phy/phy.h>
200 static int rockchip_edp_phy_configure(struct phy *phy, union phy_configure_opts *opts) in rockchip_edp_phy_configure() argument
202 struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy); in rockchip_edp_phy_configure()
207 dev_err(edpphy->dev, "invalid params for phy configure\n"); in rockchip_edp_phy_configure()
242 static int rockchip_edp_phy_power_on(struct phy *phy) in rockchip_edp_phy_power_on() argument
244 struct rockchip_edp_phy *edpphy = phy_get_drvdata(phy); in rockchip_edp_phy_power_on()
275 static int rockchip_edp_phy_power_off(struct phy *ph argument
302 struct phy *phy; rockchip_edp_phy_probe() local
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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_boot.c47 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
52 uart_early_put_hex(phy); in ddr_training_error()
132 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
196 /* error phy */ in ddr_training_error()
197 if (0 != phy) { in ddr_training_error()
202 uart_early_put_hex(phy); in ddr_training_error()
247 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/
H A Dddr_training_boot.c47 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
52 uart_early_put_hex(phy); in ddr_training_error()
132 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
196 /* error phy */ in ddr_training_error()
197 if (0 != phy) { in ddr_training_error()
202 uart_early_put_hex(phy); in ddr_training_error()
247 void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq) in ddr_training_error() argument
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_mode_aarch64.c49 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
52 WRITE_ONCE(*pte, phy); in page_table_entry_set()
56 *pte = phy; in page_table_entry_set()
63 : "r"(&phy) in page_table_entry_set()
162 static void entry_set_ate(u64 *entry, struct tagged_addr phy, unsigned long flags, int const level) in entry_set_ate() argument
165 page_table_entry_set(entry, as_phys_addr_t(phy) | get_mmu_flags(flags) | ENTRY_ACCESS_BIT | ENTRY_IS_ATE_L3); in entry_set_ate()
167 page_table_entry_set(entry, as_phys_addr_t(phy) | get_mmu_flags(flags) | ENTRY_ACCESS_BIT | ENTRY_IS_ATE_L02); in entry_set_ate()
171 static void entry_set_pte(u64 *entry, phys_addr_t phy) in entry_set_pte() argument
173 page_table_entry_set(entry, (phy & PAGE_MASK) | ENTRY_ACCESS_BIT | ENTRY_IS_PTE); in entry_set_pte()
H A Dmali_kbase_mmu_mode_lpae.c45 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
48 WRITE_ONCE(*pte, phy); in page_table_entry_set()
52 *pte = phy; in page_table_entry_set()
59 : "r"(&phy) in page_table_entry_set()
171 static void entry_set_ate(u64 *entry, struct tagged_addr phy, unsigned long flags, int const level) in entry_set_ate() argument
173 page_table_entry_set(entry, as_phys_addr_t(phy) | get_mmu_flags(flags) | ENTRY_IS_ATE); in entry_set_ate()
176 static void entry_set_pte(u64 *entry, phys_addr_t phy) in entry_set_pte() argument
178 page_table_entry_set(entry, (phy & ~0xFFF) | ENTRY_IS_PTE); in entry_set_pte()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_kbase_mmu_mode_aarch64.c40 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
43 *pte = phy; in page_table_entry_set()
60 : [ptemp] "r"(&phy), [pte] "r"(pte), "m"(phy) in page_table_entry_set()
158 static void entry_set_ate(u64 *entry, phys_addr_t phy, unsigned long flags) in entry_set_ate() argument
160 page_table_entry_set(entry, (phy & ~0xFFF) | get_mmu_flags(flags) | ENTRY_ACCESS_BIT | ENTRY_IS_ATE); in entry_set_ate()
163 static void entry_set_pte(u64 *entry, phys_addr_t phy) in entry_set_pte() argument
165 page_table_entry_set(entry, (phy & ~0xFFF) | ENTRY_ACCESS_BIT | ENTRY_IS_PTE); in entry_set_pte()
H A Dmali_kbase_mmu_mode_lpae.c39 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
42 *pte = phy; in page_table_entry_set()
60 : [ptemp] "r"(&phy), [pte] "r"(pte), "m"(phy) in page_table_entry_set()
154 static void entry_set_ate(u64 *entry, phys_addr_t phy, unsigned long flags) in entry_set_ate() argument
156 page_table_entry_set(entry, (phy & ~0xFFF) | get_mmu_flags(flags) | ENTRY_IS_ATE); in entry_set_ate()
159 static void entry_set_pte(u64 *entry, phys_addr_t phy) in entry_set_pte() argument
161 page_table_entry_set(entry, (phy & ~0xFFF) | ENTRY_IS_PTE); in entry_set_pte()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_kbase_mmu_mode_aarch64.c44 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
47 *pte = phy; in page_table_entry_set()
64 : [ptemp] "r" (&phy), [pte] "r" (pte), "m" (phy) in page_table_entry_set()
167 static void entry_set_ate(u64 *entry, phys_addr_t phy, unsigned long flags) in entry_set_ate() argument
169 page_table_entry_set(entry, (phy & ~0xFFF) | in entry_set_ate()
174 static void entry_set_pte(u64 *entry, phys_addr_t phy) in entry_set_pte() argument
176 page_table_entry_set(entry, (phy & ~0xFFF) | in entry_set_pte()
H A Dmali_kbase_mmu_mode_lpae.c43 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
46 *pte = phy; in page_table_entry_set()
64 : [ptemp] "r" (&phy), [pte] "r" (pte), "m" (phy) in page_table_entry_set()
166 static void entry_set_ate(u64 *entry, phys_addr_t phy, unsigned long flags) in entry_set_ate() argument
168 page_table_entry_set(entry, (phy & ~0xFFF) | in entry_set_ate()
173 static void entry_set_pte(u64 *entry, phys_addr_t phy) in entry_set_pte() argument
175 page_table_entry_set(entry, (phy & ~0xFFF) | ENTRY_IS_PTE); in entry_set_pte()
/device/soc/rockchip/common/vendor/drivers/gpu/drm/rockchip/rk628/
H A Drk628_combtxphy.h9 #include <linux/phy/phy.h>
11 int rk628_combtxphy_set_gvi_division_mode(struct phy *phy, u8 mode);
/device/soc/hisilicon/common/platform/hieth-sf/adapter/
H A Dhieth_phy.c35 pstPrivData->phy = (EthPhyAccess *)OsalMemCalloc(sizeof(EthPhyAccess)); in CreateHiethPrivData()
36 if (pstPrivData->phy == NULL) { in CreateHiethPrivData()
40 pstPrivData->phy->initDone = false; in CreateHiethPrivData()
41 pstPrivData->phy->init = NULL; in CreateHiethPrivData()
42 pstPrivData->phy->reset = NULL; in CreateHiethPrivData()
74 OsalMemFree((void *)pstPrivData->phy); in CreateHiethPrivData()
142 if (priv->phy != NULL) { in DeinitHiethDriver()
143 OsalMemFree((void *)priv->phy); in DeinitHiethDriver()
/device/soc/hisilicon/common/platform/hieth-sf/src/
H A Dinterface.c85 linkStatus = MiiphyLink(ld, priv->phy); in PhyStateMachine()
377 duplex = MiiphyDuplex(ld, priv->phy); in HiethLinkStatusChanged()
378 speed = MiiphySpeed(ld, priv->phy); in HiethLinkStatusChanged()
392 switch (priv->phy->phyMode) { in HiethLinkStatusChanged()
400 HDF_LOGE("not supported mode: %d", priv->phy->phyMode); in HiethLinkStatusChanged()
463 priv->phy->phyMode = g_phyModeVal; in HiethHwInit()
464 HDF_LOGE("hisi_eth: User set phy mode=%s", PhyModes(priv->phy->phyMode)); in HiethHwInit()
466 priv->phy->phyMode = ld->phyMode; in HiethHwInit()
467 HDF_LOGE("hisi_eth: User did not set phy mod in HiethHwInit()
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/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_mode_aarch64.c51 static inline void page_table_entry_set(u64 *pte, u64 phy) in page_table_entry_set() argument
53 WRITE_ONCE(*pte, phy); in page_table_entry_set()
144 struct tagged_addr phy, in entry_set_ate()
149 page_table_entry_set(entry, as_phys_addr_t(phy) | in entry_set_ate()
153 page_table_entry_set(entry, as_phys_addr_t(phy) | in entry_set_ate()
192 static void entry_set_pte(u64 *pgd, u64 vpfn, phys_addr_t phy) in entry_set_pte() argument
196 page_table_entry_set(&pgd[vpfn], (phy & PAGE_MASK) | ENTRY_ACCESS_BIT | in entry_set_pte()
143 entry_set_ate(u64 *entry, struct tagged_addr phy, unsigned long flags, int const level) entry_set_ate() argument
/device/soc/rockchip/common/sdk_linux/drivers/pci/controller/
H A Dpcie-rockchip.c19 #include <linux/phy/phy.h>
35 struct phy *phy; in rockchip_pcie_get_phys() local
39 phy = devm_phy_get(dev, "pcie-phy"); in rockchip_pcie_get_phys()
40 if (!IS_ERR(phy)) { in rockchip_pcie_get_phys()
42 rockchip->phys[0] = phy; in rockchip_pcie_get_phys()
43 dev_warn(dev, "legacy phy model is deprecated!\n"); in rockchip_pcie_get_phys()
47 if (PTR_ERR(phy) in rockchip_pcie_get_phys()
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