1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Rockchip PCIE3.0 phy driver
4  *
5  * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <dt-bindings/phy/phy-snps-pcie3.h>
21 
22 /* Register for RK3568 */
23 #define GRF_PCIE30PHY_CON1 0x4
24 #define GRF_PCIE30PHY_CON6 0x18
25 #define GRF_PCIE30PHY_CON9 0x24
26 #define GRF_PCIE30PHY_STATUS0 0x80
27 #define SRAM_INIT_DONE(reg) ((reg)&BIT(14))
28 
29 /* Register for RK3588 */
30 #define PHP_GRF_PCIESEL_CON 0x100
31 #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
32 #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
33 #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
34 #define RK3588_SRAM_INIT_DONE(reg) ((reg)&BIT(0))
35 
36 #define DEBUGER_INDEX_TH 3
37 #define DEBUGER_INDEX_FO 4
38 #define DEBUGER_INDEX_EI 8
39 #define DEBUGER_INDEX_FIF 15
40 #define DEBUGER_INDEX_SIX 16
41 #define DEBUGER_INDEX_TWEF 24
42 #define DEBUGER_INDEX_THIO 31
43 #define SRAM_NODE_VALUE 500
44 
45 struct rockchip_p3phy_ops;
46 
47 struct rockchip_p3phy_priv {
48     const struct rockchip_p3phy_ops *ops;
49     void __iomem *mmio;
50     /* mode: RC, EP */
51     int mode;
52     /* pcie30_phymode: Aggregation, Bifurcation */
53     int pcie30_phymode;
54     struct regmap *phy_grf;
55     struct regmap *pipe_grf;
56     struct reset_control *p30phy;
57     struct phy *phy;
58     struct clk_bulk_data *clks;
59     int num_clks;
60     bool is_bifurcation;
61 };
62 
63 struct rockchip_p3phy_ops {
64     int (*phy_init)(struct rockchip_p3phy_priv *priv);
65 };
66 
rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)67 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
68 {
69     struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
70 
71     /* Acutally We don't care EP/RC mode, but just record it */
72     switch (submode) {
73         case PHY_MODE_PCIE_RC:
74             priv->mode = PHY_MODE_PCIE_RC;
75             break;
76         case PHY_MODE_PCIE_EP:
77             priv->mode = PHY_MODE_PCIE_EP;
78             break;
79         case PHY_MODE_PCIE_BIFURCATION:
80             priv->is_bifurcation = true;
81             break;
82         default:
83             pr_info("%s, invalid mode\n", __func__);
84             return -EINVAL;
85     }
86 
87     return 0;
88 }
89 
rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)90 static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
91 {
92     int ret = 0;
93     u32 reg;
94 
95     /* Deassert PCIe PMA output clamp mode */
96     regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, (0x1 << DEBUGER_INDEX_FIF) | (0x1 << DEBUGER_INDEX_THIO));
97     /* Set bifurcation if needed, and it doesn't care RC/EP */
98     if (priv->is_bifurcation) {
99         regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, 0x1 | (0xf << DEBUGER_INDEX_SIX));
100         regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, (0x1 << DEBUGER_INDEX_FIF) | (0x1 << DEBUGER_INDEX_THIO));
101     }
102 
103     reset_control_deassert(priv->p30phy);
104 
105     ret = regmap_read_poll_timeout(priv->phy_grf, GRF_PCIE30PHY_STATUS0, reg, SRAM_INIT_DONE(reg), 0, SRAM_NODE_VALUE);
106     if (ret) {
107         pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", __func__, reg);
108     }
109     return ret;
110 }
111 
112 static const struct rockchip_p3phy_ops rk3568_ops = {
113     .phy_init = rockchip_p3phy_rk3568_init,
114 };
115 
rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)116 static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
117 {
118     int ret = 0;
119     u32 reg;
120 
121     /* Deassert PCIe PMA output clamp mode */
122     regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x1 << DEBUGER_INDEX_EI) | (0x1 << DEBUGER_INDEX_TWEF));
123 
124     reset_control_deassert(priv->p30phy);
125 
126     ret = regmap_read_poll_timeout(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_STATUS1, reg, RK3588_SRAM_INIT_DONE(reg), 0,
127                                    SRAM_NODE_VALUE);
128     ret |= regmap_read_poll_timeout(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_STATUS1, reg, RK3588_SRAM_INIT_DONE(reg), 0,
129                                     SRAM_NODE_VALUE);
130     if (ret) {
131         pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", __func__, reg);
132     }
133     return ret;
134 }
135 
136 static const struct rockchip_p3phy_ops rk3588_ops = {
137     .phy_init = rockchip_p3phy_rk3588_init,
138 };
139 
rochchip_p3phy_init(struct phy *phy)140 static int rochchip_p3phy_init(struct phy *phy)
141 {
142     struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
143     int ret;
144 
145     ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
146     if (ret) {
147         pr_err("failed to enable PCIe bulk clks %d\n", ret);
148         return ret;
149     }
150 
151     reset_control_assert(priv->p30phy);
152     udelay(1);
153 
154     if (priv->ops->phy_init) {
155         ret = priv->ops->phy_init(priv);
156         if (ret) {
157             clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
158         }
159     };
160 
161     return ret;
162 }
163 
rochchip_p3phy_exit(struct phy *phy)164 static int rochchip_p3phy_exit(struct phy *phy)
165 {
166     struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
167     clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
168     reset_control_assert(priv->p30phy);
169     return 0;
170 }
171 
172 static const struct phy_ops rochchip_p3phy_ops = {
173     .init = rochchip_p3phy_init,
174     .exit = rochchip_p3phy_exit,
175     .set_mode = rockchip_p3phy_set_mode,
176     .owner = THIS_MODULE,
177 };
178 
rockchip_p3phy_probe(struct platform_device *pdev)179 static int rockchip_p3phy_probe(struct platform_device *pdev)
180 {
181     struct phy_provider *phy_provider;
182     struct device *dev = &pdev->dev;
183     struct rockchip_p3phy_priv *priv;
184     struct device_node *np = dev->of_node;
185     struct resource *res;
186     int ret;
187     u32 val, reg;
188 
189     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
190     if (!priv) {
191         return -ENOMEM;
192     }
193 
194     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
195     priv->mmio = devm_ioremap_resource(dev, res);
196     if (IS_ERR(priv->mmio)) {
197         ret = PTR_ERR(priv->mmio);
198         return ret;
199     }
200 
201     priv->ops = of_device_get_match_data(&pdev->dev);
202     if (!priv->ops) {
203         dev_err(&pdev->dev, "no of match data provided\n");
204         return -EINVAL;
205     }
206 
207     priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
208     if (IS_ERR(priv->phy_grf)) {
209         dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
210         return PTR_ERR(priv->phy_grf);
211     }
212 
213     priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
214     if (IS_ERR(priv->pipe_grf)) {
215         dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
216     }
217 
218     ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
219     if (!ret) {
220         priv->pcie30_phymode = val;
221     } else {
222         priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
223     }
224 
225     /* Select correct pcie30_phymode */
226     if (priv->pcie30_phymode > DEBUGER_INDEX_FO) {
227         priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
228     }
229 
230     regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7 << DEBUGER_INDEX_SIX) | priv->pcie30_phymode);
231 
232     /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
233     if (!IS_ERR(priv->pipe_grf)) {
234         reg = priv->pcie30_phymode & DEBUGER_INDEX_TH;
235         if (reg) {
236             regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, (reg << DEBUGER_INDEX_SIX) | reg);
237         }
238     };
239 
240     priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
241     if (IS_ERR(priv->phy)) {
242         dev_err(dev, "failed to create combphy\n");
243         return PTR_ERR(priv->phy);
244     }
245 
246     priv->p30phy = devm_reset_control_get(dev, "phy");
247     if (IS_ERR(priv->p30phy)) {
248         dev_warn(dev, "no phy reset control specified\n");
249         priv->p30phy = NULL;
250     }
251 
252     priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
253     if (priv->num_clks < 1) {
254         return -ENODEV;
255     }
256 
257     dev_set_drvdata(dev, priv);
258     phy_set_drvdata(priv->phy, priv);
259     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
260     return PTR_ERR_OR_ZERO(phy_provider);
261 }
262 
263 static const struct of_device_id rockchip_p3phy_of_match[] = {
264     {.compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops},
265     {.compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops},
266     {},
267 };
268 MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
269 
270 static struct platform_driver rockchip_p3phy_driver = {
271     .probe = rockchip_p3phy_probe,
272     .driver =
273         {
274             .name = "rockchip-snps-pcie3-phy",
275             .of_match_table = rockchip_p3phy_of_match,
276         },
277 };
278 module_platform_driver(rockchip_p3phy_driver);
279 MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
280 MODULE_LICENSE("GPL v2");
281