| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3188-cru-common.h | 23 #define SCLK_UART3 67 macro
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| H A D | rk1808-cru.h | 64 #define SCLK_UART3 63 macro
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| H A D | px30-cru.h | 28 #define SCLK_UART3 26 macro
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| H A D | rk3288-cru.h | 35 #define SCLK_UART3 80 macro
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| H A D | rk3368-cru.h | 33 #define SCLK_UART3 80 macro
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| H A D | rk3568-cru.h | 358 #define SCLK_UART3 295 macro
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| H A D | rk3399-cru.h | 42 #define SCLK_UART3 84 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 64 #define SCLK_UART3 63 macro
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| H A D | rv1126-cru.h | 91 #define SCLK_UART3 24 macro
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| H A D | rk3568-cru.h | 358 #define SCLK_UART3 295 macro
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| H A D | rk3588-cru.h | 194 #define SCLK_UART3 191 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3368.c | 263 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
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| H A D | clk-rk3188.c | 255 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
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| H A D | clk-rk3308.c | 300 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0, RK3308_CLKGATE_CON(2), 8, GFLAGS),
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| H A D | clk-rk3288.c | 217 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
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| H A D | clk-px30.c | 496 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(11), 7, GFLAGS),
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| H A D | clk-rk3399.c | 266 SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(36), 8, 2, MFLAGS, uart_mux_idx);
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 616 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0, RK1808_CLKGATE_CON(12), 3, GFLAGS),
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 907 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0, RK3568_CLKGATE_CON(28), 7, GFLAGS),
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 1230 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
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