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Searched refs:PLL_GPLL (Results 1 - 25 of 27) sorted by relevance

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/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-rk3188.c215 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 7,
225 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 8,
651 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3066_cpuclk_data, in rk3066a_clk_init()
672 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3188_cpuclk_data, in rk3188a_clk_init()
676 if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) { in rk3188a_clk_init()
679 ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]); in rk3188a_clk_init()
H A Dclk-rk3036.c144 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 6,
417 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3036_cpuclk_data, in rk3036_clk_init()
H A Dclk-rk3368.c152 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16), RK3368_PLL_CON(19), 8, 4,
760 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 0x2, clks[PLL_APLLB], clks[PLL_GPLL], &rk3368_cpuclkb_data, in rk3368_clk_init()
763 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 0x2, clks[PLL_APLLL], clks[PLL_GPLL], &rk3368_cpuclkl_data, in rk3368_clk_init()
H A Dclk-rk3328.c179 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, RK3328_PLL_CON(24), RK3328_MODE_CON, 12, 1, 0,
654 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 4, clks[PLL_APLL], clks[PLL_GPLL], &rk3328_cpuclk_data, in rk3328_clk_init()
H A Dclk-rv1108.c148 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), RV1108_PLL_CON(19), 8, 2, 0,
578 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_GPLL], &rv1108_cpuclk_data, in rv1108_clk_init()
H A Dclk-rk3228.c166 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), RK2928_MODE_CON, 12, 9,
557 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_GPLL], &rk3228_cpuclk_data, in rk3228_clk_init()
H A Dclk-rk3288.c180 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8,
759 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3288_cpuclk_data, in rk3288_common_init()
H A Dclk-px30.c165 PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0), PX30_PMU_MODE, 0, 3, 0, px30_pll_rates),
795 rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", 2, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL], in px30_pmu_clk_init()
H A Dclk-rk3399.c226 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32), RK3399_PLL_CON(35), 8, 31, 0,
1233 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", 4, clks[PLL_APLLL], clks[PLL_GPLL], &rk3399_cpuclkl_data, in rk3399_clk_init()
1236 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", 4, clks[PLL_APLLB], clks[PLL_GPLL], &rk3399_cpuclkb_data, in rk3399_clk_init()
H A Dclk-rk3128.c158 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), RK2928_MODE_CON, 12, 3,
/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A Drk3036-cru.h13 #define PLL_GPLL 3 macro
H A Drk3128-cru.h14 #define PLL_GPLL 4 macro
H A Drk3188-cru-common.h14 #define PLL_GPLL 4 macro
H A Drk1808-cru.h10 #define PLL_GPLL 4 macro
H A Dpx30-cru.h184 #define PLL_GPLL 1 macro
H A Drk3288-cru.h14 #define PLL_GPLL 4 macro
H A Drk3368-cru.h14 #define PLL_GPLL 5 macro
H A Drk3568-cru.h73 #define PLL_GPLL 4 macro
H A Drk3399-cru.h15 #define PLL_GPLL 5 macro
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A Drk1808-cru.h10 #define PLL_GPLL 4 macro
H A Drv1126-cru.h13 #define PLL_GPLL 1 macro
H A Drk3568-cru.h73 #define PLL_GPLL 4 macro
H A Drk3588-cru.h19 #define PLL_GPLL 7 macro
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c661 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
2427 3, clks[PLL_LPLL], clks[PLL_GPLL], in rk3588_clk_init()
2431 3, clks[PLL_B0PLL], clks[PLL_GPLL], in rk3588_clk_init()
2435 3, clks[PLL_B1PLL], clks[PLL_GPLL], in rk3588_clk_init()
/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-rk1808.c183 PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK1808_PLL_CON(24), RK1808_MODE_CON, 6, 3, 0, rk1808_pll_rates),
870 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 3, clks[PLL_APLL], clks[PLL_GPLL], &rk1808_cpuclk_data, in rk1808_clk_init()

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