| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 12 #define PLL_DPLL 2 macro
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| H A D | rk3128-cru.h | 12 #define PLL_DPLL 2 macro
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| H A D | rk3188-cru-common.h | 12 #define PLL_DPLL 2 macro
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| H A D | rk1808-cru.h | 8 #define PLL_DPLL 2 macro
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| H A D | px30-cru.h | 8 #define PLL_DPLL 2 macro
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| H A D | rk3288-cru.h | 12 #define PLL_DPLL 2 macro
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| H A D | rk3368-cru.h | 12 #define PLL_DPLL 3 macro
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| H A D | rk3568-cru.h | 71 #define PLL_DPLL 2 macro
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| H A D | rk3399-cru.h | 13 #define PLL_DPLL 3 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 8 #define PLL_DPLL 2 macro
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| H A D | rv1126-cru.h | 67 #define PLL_DPLL 2 macro
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| H A D | rk3568-cru.h | 71 #define PLL_DPLL 2 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 212 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 4, 0, NULL),
222 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 5, 0, NULL),
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| H A D | clk-rk3036.c | 143 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 4, 0, NULL),
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| H A D | clk-rk3128.c | 155 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), RK2928_MODE_CON, 4, 0, 0, NULL),
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| H A D | clk-rk3368.c | 149 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8), RK3368_PLL_CON(11), 8, 2, 0, NULL),
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| H A D | clk-rk3328.c | 176 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3328_PLL_CON(8), RK3328_MODE_CON, 4, 3, 0, NULL),
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| H A D | clk-rv1108.c | 147 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), RV1108_PLL_CON(11), 8, 1, 0, NULL),
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| H A D | clk-rk3228.c | 164 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), RK2928_MODE_CON, 4, 6, 0, NULL),
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| H A D | clk-rk3308.c | 161 PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3308_PLL_CON(8), RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
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| H A D | clk-rk3288.c | 177 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4), RK3288_MODE_CON, 4, 5, 0, NULL),
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| H A D | clk-px30.c | 157 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, PX30_PLL_CON(8), PX30_MODE_CON, 4, 1, 0, NULL),
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| H A D | clk-rk3399.c | 218 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16), RK3399_PLL_CON(19), 8, 31, 0, NULL),
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 179 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK1808_PLL_CON(8), RK1808_MODE_CON, 2, 1, 0, NULL),
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 308 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 0, RK3568_PLL_CON(8), RK3568_MODE_CON0, 2, 1, 0, NULL),
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