| /device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/ |
| H A D | rk3128-cru.h | 13 #define PLL_CPLL 3 macro
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| H A D | rk3188-cru-common.h | 13 #define PLL_CPLL 3 macro
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| H A D | rk1808-cru.h | 9 #define PLL_CPLL 3 macro
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| H A D | px30-cru.h | 9 #define PLL_CPLL 3 macro
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| H A D | rk3288-cru.h | 13 #define PLL_CPLL 3 macro
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| H A D | rk3368-cru.h | 13 #define PLL_CPLL 4 macro
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| H A D | rk3568-cru.h | 72 #define PLL_CPLL 3 macro
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| H A D | rk3399-cru.h | 14 #define PLL_CPLL 4 macro
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| /device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/ |
| H A D | rk1808-cru.h | 9 #define PLL_CPLL 3 macro
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| H A D | rv1126-cru.h | 68 #define PLL_CPLL 3 macro
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| H A D | rk3568-cru.h | 72 #define PLL_CPLL 3 macro
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| H A D | rk3588-cru.h | 18 #define PLL_CPLL 6 macro
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 213 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), RK2928_MODE_CON, 8, 6,
223 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), RK2928_MODE_CON, 8, 7,
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| H A D | clk-rk3128.c | 157 PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), RK2928_MODE_CON, 8, 2, 0, rk3128_pll_rates),
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| H A D | clk-rk3368.c | 150 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12), RK3368_PLL_CON(15), 8, 3,
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| H A D | clk-rk3328.c | 178 PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RK3328_PLL_CON(16), RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
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| H A D | clk-rk3228.c | 165 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), RK2928_MODE_CON, 8, 8, 0, NULL),
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| H A D | clk-rk3399.c | 220 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), RK3399_PLL_CON(27), 8, 31, 0,
223 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24), RK3399_PLL_CON(27), 8, 31,
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| H A D | clk-rk3288.c | 178 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8), RK3288_MODE_CON, 8, 7,
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| H A D | clk-px30.c | 158 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, PX30_PLL_CON(16), PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-rk1808.c | 181 PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK1808_PLL_CON(16), RK1808_MODE_CON, 4, 2, 0, rk1808_pll_rates),
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| /device/soc/rockchip/rk3566/vendor/drivers/clk/ |
| H A D | clk-rk3568.c | 309 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RK3568_PLL_CON(24), RK3568_MODE_CON0, 4, 2, 0,
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-rk3588.c | 658 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
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