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Searched refs:HIWORD_UPDATE (Results 1 - 25 of 39) sorted by relevance

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/device/soc/rockchip/rk3588/kernel/include/linux/mfd/
H A Drk618.h23 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
26 #define LVDS_CON_START_PHASE(x) HIWORD_UPDATE(x, 14, 14)
27 #define LVDS_DCLK_INV HIWORD_UPDATE(1, 13, 13)
28 #define LVDS_CON_CHADS_10PF HIWORD_UPDATE(3, 12, 11)
29 #define LVDS_CON_CHADS_5PF HIWORD_UPDATE(2, 12, 11)
30 #define LVDS_CON_CHADS_7PF HIWORD_UPDATE(1, 12, 11)
31 #define LVDS_CON_CHADS_3PF HIWORD_UPDATE(0, 12, 11)
32 #define LVDS_CON_CHA1TTL_ENABLE HIWORD_UPDATE(1, 10, 10)
33 #define LVDS_CON_CHA1TTL_DISABLE HIWORD_UPDATE(0, 10, 10)
34 #define LVDS_CON_CHA0TTL_ENABLE HIWORD_UPDATE(
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H A Drk630.h18 #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) macro
23 #define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0)
25 #define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2)
27 #define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4)
29 #define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6)
31 #define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8)
33 #define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10)
35 #define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12)
37 #define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14)
40 #define GPIO0B0_SEL(x) HIWORD_UPDATE(
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H A Drk628.h20 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
51 #define SCL_VER_DOWN_MODE(x) HIWORD_UPDATE(x, 8, 8)
52 #define SCL_HOR_DOWN_MODE(x) HIWORD_UPDATE(x, 7, 7)
53 #define SCL_BIC_COE_SEL(x) HIWORD_UPDATE(x, 6, 5)
54 #define SCL_VER_MODE(x) HIWORD_UPDATE(x, 4, 3)
55 #define SCL_HOR_MODE(x) HIWORD_UPDATE(x, 2, 1)
56 #define SCL_EN(x) HIWORD_UPDATE(x, 0, 0)
92 #define SW_YUV2VYU_SWP(x) HIWORD_UPDATE(x, 8, 8)
93 #define SW_R2Y_EN(x) HIWORD_UPDATE(x, 4, 4)
94 #define SW_Y2R_EN(x) HIWORD_UPDATE(
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/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_lvds.c27 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
30 #define PX30_LVDS_SELECT(x) HIWORD_UPDATE(x, 14, 13)
31 #define PX30_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 12, 12)
32 #define PX30_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
33 #define PX30_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6)
34 #define PX30_LVDS_VOP_SEL(x) HIWORD_UPDATE(x, 1, 1)
37 #define RK3126_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 9, 9)
38 #define RK3126_LVDS_MODE_EN(x) HIWORD_UPDATE(x, 6, 6)
39 #define RK3126_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 3, 3)
40 #define RK3126_LVDS_SELECT(x) HIWORD_UPDATE(
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H A Drockchip_rgb.c28 #define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16)) macro
31 #define PX30_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
32 #define PX30_RGB_VOP_SEL(v) HIWORD_UPDATE(v, 2, 2)
35 #define RK1808_RGB_DATA_SYNC_BYPASS(v) HIWORD_UPDATE(v, 3, 3)
38 #define RV1126_LCDC_IO_BYPASS(v) HIWORD_UPDATE(v, 0, 0)
41 #define RK3288_LVDS_LCDC_SEL(x) HIWORD_UPDATE(x, 3, 3)
43 #define RK3288_LVDS_PWRDWN(x) HIWORD_UPDATE(x, 15, 15)
44 #define RK3288_LVDS_CON_ENABLE_2(x) HIWORD_UPDATE(x, 12, 12)
45 #define RK3288_LVDS_CON_ENABLE_1(x) HIWORD_UPDATE(x, 11, 11)
46 #define RK3288_LVDS_CON_CLKINV(x) HIWORD_UPDATE(
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H A Ddw_hdmi-rockchip.c30 #define HIWORD_UPDATE(val, mask) ((val) | ((mask) << 16)) macro
879 val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK); in hdmi_select_link_config()
886 val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); in hdmi_select_link_config()
896 val = HIWORD_UPDATE(RK3588_HDMI21_MASK, RK3588_HDMI21_MASK); in hdmi_select_link_config()
915 val = HIWORD_UPDATE(RK3588_COMPRESS_MODE_MASK | RK3588_COMPRESSED_DATA, in hdmi_select_link_config()
926 val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK); in hdmi_select_link_config()
1280 val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK); in rockchip_hdmi_hardirq()
1282 val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK); in rockchip_hdmi_hardirq()
1305 val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, RK3588_HDMI0_HPD_INT_CLR); in rockchip_hdmi_irq()
1312 val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CL in rockchip_hdmi_irq()
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H A Ddw-mipi-dsi-rockchip.c183 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) macro
1203 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1204 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, PX30_DSI_LCDC_SEL),
1207 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | PX30_DSI_FORCERXMODE | PX30_DSI_FORCETXSTOPMODE),
1219 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1220 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1229 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1230 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1242 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1243 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SE
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/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Dgrf.c15 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) macro
50 {"jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11)},
61 {"jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8)},
72 {"jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8)},
84 {"jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12)},
85 {"pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0)},
96 {"jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12)},
107 {"uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10)},
118 {"jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13)},
129 {"jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(
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/device/soc/rockchip/common/sdk_linux/drivers/soc/rockchip/
H A Dgrf.c15 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) macro
50 {"jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11)},
61 {"jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8)},
72 {"jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8)},
84 {"jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12)},
85 {"pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0)},
96 {"jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12)},
107 {"uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10)},
118 {"jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13)},
129 {"jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(
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/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-naneng-edp.c20 #define HIWORD_UPDATE(x, h, l) ((((x) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) macro
23 #define EDP_PHY_TX_IDLE(x) HIWORD_UPDATE(x, 11, 8)
24 #define EDP_PHY_TX_PD(x) HIWORD_UPDATE(x, 7, 4)
25 #define EDP_PHY_IDDQ_EN(x) HIWORD_UPDATE(x, 1, 1)
26 #define EDP_PHY_PD_PLL(x) HIWORD_UPDATE(x, 0, 0)
28 #define EDP_PHY_PLL_DIV(x) HIWORD_UPDATE(x, 14, 0)
30 #define EDP_PHY_TX_RTERM(x) HIWORD_UPDATE(x, 10, 8)
31 #define EDP_PHY_RATE(x) HIWORD_UPDATE(x, 5, 4)
32 #define EDP_PHY_REF_DIV(x) HIWORD_UPDATE(x, 3, 0)
34 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(
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H A Dphy-rockchip-csi2-dphy-hw.c209 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) macro
229 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_sys_grf_reg()
239 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_grf_reg()
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-edp.c20 #define HIWORD_UPDATE(x, h, l) ((((x) << (l)) & GENMASK((h), (l))) | \ macro
24 #define EDP_PHY_TX_IDLE(x) HIWORD_UPDATE(x, 11, 8)
25 #define EDP_PHY_TX_PD(x) HIWORD_UPDATE(x, 7, 4)
26 #define EDP_PHY_IDDQ_EN(x) HIWORD_UPDATE(x, 1, 1)
27 #define EDP_PHY_PD_PLL(x) HIWORD_UPDATE(x, 0, 0)
29 #define EDP_PHY_PLL_DIV(x) HIWORD_UPDATE(x, 14, 0)
31 #define EDP_PHY_TX_RTERM(x) HIWORD_UPDATE(x, 10, 8)
32 #define EDP_PHY_RATE(x) HIWORD_UPDATE(x, 5, 4)
33 #define EDP_PHY_REF_DIV(x) HIWORD_UPDATE(x, 3, 0)
35 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(
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/device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c34 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) macro
216 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_HOST, RK3288_UOC0_CON3_IDDIG_SET_MASK); in otg_mode_store()
219 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_PERIPHERAL, RK3288_UOC0_CON3_IDDIG_SET_MASK); in otg_mode_store()
222 val = HIWORD_UPDATE(RK3288_UOC0_CON3_IDDIG_SET_OTG, RK3288_UOC0_CON3_IDDIG_SET_MASK); in otg_mode_store()
251 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
312 val = HIWORD_UPDATE(RK3288_UOC0_CON4_BVALID_IRQ_EN | RK3288_UOC0_CON4_BVALID_IRQ_PD, in rk3288_usb_phy_init()
543 val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL, RK3288_UOC0_CON2_SOFT_CON_SEL); in rk3288_chg_detect_work()
545 val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING, in rk3288_chg_detect_work()
549 val = HIWORD_UPDATE(RK3288_UOC0_CON2_DCDENB, RK3288_UOC0_CON2_DCDENB); in rk3288_chg_detect_work()
560 val = HIWORD_UPDATE( in rk3288_chg_detect_work()
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H A Dphy-rockchip-pcie.c26 #define HIWORD_UPDATE(val, mask, shift) (((val) << (shift)) | ((mask) << ((shift) + 16))) macro
103 HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT) | in phy_wr_cfg()
104 HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT)); in phy_wr_cfg()
107 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, PHY_CFG_WR_MASK, PHY_CFG_WR_SHIFT)); in phy_wr_cfg()
110 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, PHY_CFG_WR_MASK, PHY_CFG_WR_SHIFT)); in phy_wr_cfg()
118 HIWORD_UPDATE(addr, PHY_CFG_RD_MASK, PHY_CFG_ADDR_SHIFT)); in phy_rd_cfg()
132 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, PHY_LANE_IDLE_MASK, PHY_LANE_IDLE_A_SHIFT + inst->index)); in rockchip_pcie_phy_power_off()
151 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, PHY_LANE_IDLE_MASK, PHY_LANE_IDLE_A_SHIFT + inst->index)); in rockchip_pcie_phy_power_off()
167 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, PHY_LANE_IDLE_MASK, PHY_LANE_IDLE_A_SHIFT + inst->index)); in rockchip_pcie_phy_power_on()
180 HIWORD_UPDATE(PHY_CFG_PLL_LOC in rockchip_pcie_phy_power_on()
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/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-pll.c513 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, RK3036_PLLCON0_FBDIV_SHIFT) | in rockchip_rk3036_pll_set_params()
514 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, RK3036_PLLCON0_POSTDIV1_SHIFT), in rockchip_rk3036_pll_set_params()
517 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, RK3036_PLLCON1_REFDIV_SHIFT) | in rockchip_rk3036_pll_set_params()
518 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, RK3036_PLLCON1_POSTDIV2_SHIFT) | in rockchip_rk3036_pll_set_params()
519 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, RK3036_PLLCON1_DSMPD_SHIFT), in rockchip_rk3036_pll_set_params()
565 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_enable()
575 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base + RK3036_PLLCON(1)); in rockchip_rk3036_pll_disable()
727 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_set_params()
730 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, RK3066_PLLCON0_NR_SHIFT) | in rockchip_rk3066_pll_set_params()
731 HIWORD_UPDATE(rat in rockchip_rk3066_pll_set_params()
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H A Dclk-cpu.c163 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i], reg_data->div_core_shift[i]), in rockchip_cpuclk_pre_rate_change()
171 writel(HIWORD_UPDATE(reg_data->mux_core_alt, reg_data->mux_core_mask, reg_data->mux_core_shift), in rockchip_cpuclk_pre_rate_change()
204 writel(HIWORD_UPDATE(reg_data->mux_core_main, reg_data->mux_core_mask, reg_data->mux_core_shift), in rockchip_cpuclk_post_rate_change()
209 writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i], reg_data->div_core_shift[i]), in rockchip_cpuclk_post_rate_change()
H A Dclk-rk3188.c121 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, RK3066_DIV_CORE_PERIPH_SHIFT) \
126 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, RK3066_DIV_ACLK_CORE_SHIFT) | \
127 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, RK3066_DIV_ACLK_HCLK_SHIFT) | \
128 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, RK3066_DIV_ACLK_PCLK_SHIFT) | \
129 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, RK3066_DIV_AHB2APB_SHIFT), \
165 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK, RK3188_DIV_ACLK_CORE_SHIFT) \
H A Dclk-rk3288.c102 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, RK3288_DIV_ACLK_CORE_M0_SHIFT) | \
103 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, RK3288_DIV_ACLK_CORE_MP_SHIFT), \
108 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, RK3288_DIV_L2RAM_SHIFT) | \
109 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, RK3288_DIV_ATCLK_SHIFT) | \
110 HIWORD_UPDATE(_pclk_dbg_pre, RK3288_DIV_PCLK_DBGPRE_MASK, RK3288_DIV_PCLK_DBGPRE_SHIFT), \
H A Dclk-rk3036.c93 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, RK3036_DIV_PERI_SHIFT) \
399 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 0xa), reg_base + RK2928_CLKSEL_CON(0xd)); in rk3036_clk_init()
H A Dclk-rk3368.c202 .val = HIWORD_UPDATE((_aclkm), RK3368_DIV_ACLKM_MASK, RK3368_DIV_ACLKM_SHIFT), \
207 .val = HIWORD_UPDATE((_atclk), RK3368_DIV_ATCLK_MASK, RK3368_DIV_ATCLK_SHIFT) | \
208 HIWORD_UPDATE((_pdbg), RK3368_DIV_PCLK_DBG_MASK, RK3368_DIV_PCLK_DBG_SHIFT), \
H A Dclk-rk3128.c92 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, RK3128_DIV_PERI_SHIFT) | \
93 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, RK3128_DIV_ACLK_SHIFT), \
/device/soc/rockchip/common/sdk_linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c208 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) macro
281 #define RK1808_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
282 #define RK1808_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
397 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
398 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
492 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
493 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
621 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
622 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
754 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(va
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/device/board/hihope/rk3568/audio_drivers/dai/include/
H A Drk3568_dai_linux.h188 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) macro
189 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
190 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-rk3588.c127 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
129 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
136 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
143 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK, \
145 HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK, \
152 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK, \
159 .val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
161 HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK, \
168 .val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK, \
170 HIWORD_UPDATE(_divds
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/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A Dclk-rk3568.c122 .val = HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_NPLL_MASK, RK3568_MUX_SCLK_CORE_NPLL_SHIFT) | \
123 HIWORD_UPDATE(_sclk_core, RK3568_MUX_SCLK_CORE_MASK, RK3568_MUX_SCLK_CORE_SHIFT) | \
124 HIWORD_UPDATE(1, RK3568_DIV_SCLK_CORE_MASK, RK3568_DIV_SCLK_CORE_SHIFT), \
130 .val = HIWORD_UPDATE(_aclk_core, RK3568_DIV_ACLK_CORE_MASK, RK3568_DIV_ACLK_CORE_SHIFT), \
136 .val = HIWORD_UPDATE(_atclk_core, RK3568_DIV_ATCLK_CORE_MASK, RK3568_DIV_ATCLK_CORE_SHIFT) | \
137 HIWORD_UPDATE(_gic_core, RK3568_DIV_GICCLK_CORE_MASK, RK3568_DIV_GICCLK_CORE_SHIFT), \
143 .val = HIWORD_UPDATE(_pclk_core, RK3568_DIV_PCLK_CORE_MASK, RK3568_DIV_PCLK_CORE_SHIFT) | \
144 HIWORD_UPDATE(_periph_core, RK3568_DIV_PERIPHCLK_CORE_MASK, RK3568_DIV_PERIPHCLK_CORE_SHIFT), \

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