1root { 2 platform { 3 template codec_controller { 4 match_attr = ""; 5 serviceName = ""; 6 codecDaiName = ""; 7 } 8 controller_0x120c1030 :: codec_controller { 9 match_attr = "hdf_codec_driver"; 10 serviceName = "codec_service_0"; 11 codecDaiName = "codec_dai"; 12 13 idInfo { 14 chipName = "hi3516"; 15 chipIdRegister = 0x113c0000; 16 chipIdSize = 0x1000; 17 } 18 19 regConfig { 20 /* reg, value */ 21 initSeqConfig = [ 22 0x14, 0x04000002, 23 0x18, 0xFD200004, 24 0x1C, 0x00180018, 25 0x20, 0x8F8F0028, 26 0x24, 0x00005C5C, 27 0x28, 0x00130000, 28 0x2c, 0x00303E2E, 29 0x30, 0xFF035AC2, 30 0x34, 0x08000001, 31 0x38, 0x06062424, 32 0x3C, 0x0000C001, 33 0x14, 0x04000002 34 ]; 35 36 /* 37 Mixer 38 reg: register address 39 rreg: register address 40 shift: shift bits 41 rshift: rshift bits 42 min: min value 43 max: max value 44 mask: mask of value 45 invert: enum InvertVal 0-uninvert 1-invert 46 value: value 47 */ 48 ctrlParamsSeqConfig = [ 49 0x2004, 0x2004, 8, 8, 0x28, 0x7F, 0x7F, 0, 0, //"Main Playback Volume" 50 0x3c, 0x3c, 24, 24, 0x0, 0x57, 0x7F, 1, 0, //"Main Capture Volume" 51 0x38, 0x38, 31, 31, 0x0, 0x1, 0x1, 0, 0, //"Playback Mute" 52 0x3c, 0x3c, 31, 31, 0x0, 0x1, 0x1, 0, 0, //"Capture Mute" 53 0x20, 0x20, 16, 16, 0x0, 0xF, 0x1F, 0, 0, //"Mic Left Gain" 54 0x20, 0x20, 24, 24, 0x0, 0xF, 0x1F, 0, 0, //"Mic Right Gain" 55 0x2000, 0x2000, 16, 16, 0x0, 0x7, 0x7, 0, 0, //"Render Channel Mode" 56 0x1000, 0x1000, 16, 16, 0x0, 0x7, 0x7, 0, 0 //"Capture Channel Mode" 57 ]; 58 59 controlsConfig = [ 60 /* 61 "Master Playback Volume", 62 "Master Capture Volume", 63 "Playback Mute", 64 "Capture Mute", 65 "Mic Left Gain", 66 "Mic Right Gain", 67 "External Codec Enable", 68 "Internally Codec Enable", 69 "Render Channel Mode", 70 "Capture Channel Mode" 71 */ 72 73 /*array index, iface, mixer/mux, enable,*/ 74 0, 2, 0, 0, 75 1, 2, 0, 1, 76 2, 2, 0, 1, 77 3, 2, 0, 1, 78 4, 2, 0, 1, 79 5, 2, 0, 1, 80 8, 2, 0, 0, 81 9, 2, 0, 0, 82 ]; 83 84 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 85 daiStartupSeqConfig = [ 86 0x24, 0x24, 11, 11, 0x0, 0x1, 0x1, 0, 0x1 // adc_tune_En09 87 ]; 88 89 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 90 daiParamsSeqConfig = [ 91 0x30, 0x30, 13, 13, 0x0, 0x1F, 0x1F, 0, 0x0, // i2s_frequency 92 0x1C, 0x1C, 6, 6, 0x0, 0x3, 0x3, 0, 0x0, // adc_mode_sel 93 0x30, 0x30, 22, 22, 0x0, 0x3, 0x3, 0, 0x0, // i2s_datawith 94 ]; 95 96 // Mixer: reg, rreg, shift, rshift, min, max, mask, invert, value 97 ctrlSapmParamsSeqConfig = [ 98 0x20, 0x20, 23, 23, 0x0, 0x1, 0x1, 0, 0, // LPGA MIC 0 -- connect MIC 99 0x20, 0x20, 31, 31, 0x0, 0x1, 0x1, 0, 0, // RPGA MIC 0 -- connect MIC 100 0x30, 0x30, 27, 27, 0x0, 0x1, 0x1, 0, 0, // dacl to dacr mixer 101 0x30, 0x30, 26, 26, 0x0, 0x1, 0x1, 0, 0 // dacr to dacl mixer 102 ]; 103 104 /* index = "ADCL", "ADCR", "DACL", "DACR", "LPGA", "RPGA", "SPKL", "SPKR", "MIC"*/ 105 // sapmType, compNameIndex, reg, mask, shift, invert, kcontrolNews, kcontrolsNum 106 sapmComponent = [ 107 10, 0, 0x20, 0x1, 15, 1, 0, 0, // ADCL 108 10, 1, 0x20, 0x1, 14, 1, 0, 0, // ADCR 109 11, 2, 0x14, 0x1, 11, 1, 0, 0, // DACL 110 11, 3, 0x14, 0x1, 12, 1, 0, 0, // DACR 111 17, 4, 0x20, 0x1, 13, 1, 1, 1, // LPGA 112 17, 5, 0x20, 0x1, 12, 1, 2, 1, // RPGA 113 15, 6, 0xFFFF, 0xFFFF, 0, 0, 0, 0, // SPKL 114 15, 7, 0xFFFF, 0xFFFF, 0, 0, 0, 0, // SPKR 115 17, 52, 0xFFFF, 0xFFFF, 0, 0, 3, 1, // SPKL PGA 116 17, 53, 0xFFFF, 0xFFFF, 0, 0, 4, 1, // SPKR PGA 117 13, 40, 0xFFFF, 0xFFFF, 0, 0, 0, 0, // MIC1 118 13, 41, 0xFFFF, 0xFFFF, 0, 0, 0, 0 // MIC2 119 ]; 120 121 /* array index, iface, mixer/mux, enable */ 122 sapmConfig = [ 123 0, 2, 0, 1, 124 1, 2, 0, 1, 125 2, 2, 0, 1, 126 3, 2, 0, 1 127 ]; 128 } 129 } 130 controller_0x120c1031 :: codec_controller { 131 match_attr = "hdf_codec_driver_ex"; 132 serviceName = "codec_service_1"; 133 codecDaiName = "tfa9879_codec_dai"; 134 135 regConfig { 136 /* regAddr: register address 137 regValue: config register value 138 mask: mask of value 139 shift: shift bits 140 max: max value 141 min: min value 142 invert: enum Tfa9879InvertVal 0-uninvert 1-invert 143 */ 144 145 /* reg, value */ 146 /* regAddr, regValue, mask, shift, max, min, invert, opsType */ 147 /* reg, rreg, shift, value, min, max, mask, invert */ 148 resetSeqConfig = [ 149 0x00, 0x0 150 ]; 151 152 /* reg, value */ 153 initSeqConfig = [ 154 0x00, 0x0001, 155 0x01, 0x0a18, 156 0x02, 0x0007, 157 0x03, 0x0a18, 158 0x04, 0x0007, 159 0x05, 0x59DD, 160 0x06, 0xC63E, 161 0x07, 0x651A, 162 0x08, 0xE53E, 163 0x09, 0x4616, 164 0x0A, 0xD33E, 165 0x0B, 0x4DF3, 166 0x0C, 0xEA3E, 167 0x0D, 0x5EE0, 168 0x0E, 0xF93E, 169 0x0F, 0x0008, 170 0x10, 0x92BA, 171 0x11, 0x12A5, 172 0x12, 0x0004, 173 0x13, 0x1031, 174 0x14, 0x0000 175 ]; 176 177 /* reg: register address 178 rreg: register address 179 shift: shift bits 180 rshift: rshift bits 181 min: min value 182 max: max value 183 mask: mask of value 184 invert: enum InvertVal 0-uninvert 1-invert 185 value: value 186 */ 187 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 188 ctrlParamsSeqConfig = [ 189 0x13, 0x13, 0, 0, 0x0, 0xBC, 0xFF, 1, 0x0, // output volume 190 0x14, 0x14, 9, 9, 0x0, 0x1, 0x1, 0, 0x0, // output mute 191 0x01, 0x01, 10, 10, 0x0, 0x3, 0x3, 0, 0x0 // output channel 192 ]; 193 194 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 195 daiStartupSeqConfig = [ 196 0x00, 0x00, 0, 0, 0x0, 0xF, 0xF, 0, 0x9 // work 197 ]; 198 199 /* reg, rreg, shift, rshift, min, max, mask, invert, value */ 200 daiParamsSeqConfig = [ 201 0x01, 0x01, 6, 6, 0x0, 0xF, 0xF, 0, 0x0, // i2s_frequency 202 0x01, 0x01, 3, 3, 0x0, 0x7, 0x7, 0, 0x0, // i2s_format 203 0x01, 0x01, 10, 10, 0x0, 0x3, 0x3, 0, 0x0 // i2s_channel 204 ]; 205 206 /*array index, iface, mixer/mux, enable,*/ 207 controlsConfig = [ 208 /* 209 "Master Playback Volume", 210 "Playback Mute", 211 "Render Channel Mode" 212 */ 213 0, 2, 0, 1, 214 2, 2, 0, 1, 215 8, 2, 0, 1 216 ]; 217 } 218 } 219 } 220} 221