1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses.
8 //
9 // The example below will disassemble a block of code and print it to stdout.
10 //
11 //   NameConverter converter;
12 //   Disassembler d(converter);
13 //   for (byte* pc = begin; pc < end;) {
14 //     v8::base::EmbeddedVector<char, 256> buffer;
15 //     byte* prev_pc = pc;
16 //     pc += d.InstructionDecode(buffer, pc);
17 //     printf("%p    %08x      %s\n",
18 //            prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
19 //   }
20 //
21 // The Disassembler class also has a convenience method to disassemble a block
22 // of code into a FILE*, meaning that the above functionality could also be
23 // achieved by just calling Disassembler::Disassemble(stdout, begin, end);
24 
25 #include <assert.h>
26 #include <stdarg.h>
27 #include <stdio.h>
28 #include <string.h>
29 
30 #if V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
31 
32 #include "src/base/platform/platform.h"
33 #include "src/base/strings.h"
34 #include "src/base/vector.h"
35 #include "src/codegen/macro-assembler.h"
36 #include "src/codegen/ppc/constants-ppc.h"
37 #include "src/codegen/register-configuration.h"
38 #include "src/diagnostics/disasm.h"
39 
40 namespace v8 {
41 namespace internal {
42 
43 //------------------------------------------------------------------------------
44 
45 // Decoder decodes and disassembles instructions into an output buffer.
46 // It uses the converter to convert register names and call destinations into
47 // more informative description.
48 class Decoder {
49  public:
Decoder(const disasm::NameConverter& converter, base::Vector<char> out_buffer)50   Decoder(const disasm::NameConverter& converter, base::Vector<char> out_buffer)
51       : converter_(converter), out_buffer_(out_buffer), out_buffer_pos_(0) {
52     out_buffer_[out_buffer_pos_] = '\0';
53   }
54 
~Decoder()55   ~Decoder() {}
56 
57   Decoder(const Decoder&) = delete;
58   Decoder& operator=(const Decoder&) = delete;
59 
60   // Writes one disassembled instruction into 'buffer' (0-terminated).
61   // Returns the length of the disassembled machine instruction in bytes.
62   int InstructionDecode(byte* instruction);
63 
64   // Prefixed instructions.
65   enum PrefixType { not_prefixed, is_prefixed };
66   // static is used to retain values even with new instances.
67   static PrefixType PrefixStatus;
68   static uint64_t PrefixValue;
69   uint64_t GetPrefixValue();
70   void SetAsPrefixed(uint64_t v);
71   void ResetPrefix();
72   bool IsPrefixed();
73 
74  private:
75   // Bottleneck functions to print into the out_buffer.
76   void PrintChar(const char ch);
77   void Print(const char* str);
78 
79   // Printing of common values.
80   void PrintRegister(int reg);
81   void PrintDRegister(int reg);
82   void PrintVectorRegister(int reg);
83   int FormatFPRegister(Instruction* instr, const char* format);
84   int FormatVectorRegister(Instruction* instr, const char* format);
85   void PrintSoftwareInterrupt(SoftwareInterruptCodes svc);
86   const char* NameOfVectorRegister(int reg) const;
87 
88   // Handle formatting of instructions and their options.
89   int FormatRegister(Instruction* instr, const char* option);
90   int FormatOption(Instruction* instr, const char* option);
91   void Format(Instruction* instr, const char* format);
92   void Unknown(Instruction* instr);
93   void UnknownFormat(Instruction* instr, const char* opcname);
94 
95   void DecodeExtP(Instruction* instr);
96   void DecodeExt0(Instruction* instr);
97   void DecodeExt1(Instruction* instr);
98   void DecodeExt2(Instruction* instr);
99   void DecodeExt3(Instruction* instr);
100   void DecodeExt4(Instruction* instr);
101   void DecodeExt5(Instruction* instr);
102   void DecodeExt6(Instruction* instr);
103 
104   const disasm::NameConverter& converter_;
105   base::Vector<char> out_buffer_;
106   int out_buffer_pos_;
107 };
108 
109 // Define Prefix functions and values.
110 // static
111 Decoder::PrefixType Decoder::PrefixStatus = not_prefixed;
112 uint64_t Decoder::PrefixValue = 0;
113 
GetPrefixValue()114 uint64_t Decoder::GetPrefixValue() { return PrefixValue; }
115 
SetAsPrefixed(uint64_t v)116 void Decoder::SetAsPrefixed(uint64_t v) {
117   PrefixStatus = is_prefixed;
118   PrefixValue = v;
119 }
120 
ResetPrefix()121 void Decoder::ResetPrefix() {
122   PrefixStatus = not_prefixed;
123   PrefixValue = 0;
124 }
125 
IsPrefixed()126 bool Decoder::IsPrefixed() { return PrefixStatus == is_prefixed; }
127 
128 // Support for assertions in the Decoder formatting functions.
129 #define STRING_STARTS_WITH(string, compare_string) \
130   (strncmp(string, compare_string, strlen(compare_string)) == 0)
131 
132 // Append the ch to the output buffer.
PrintChar(const char ch)133 void Decoder::PrintChar(const char ch) { out_buffer_[out_buffer_pos_++] = ch; }
134 
135 // Append the str to the output buffer.
Print(const char* str)136 void Decoder::Print(const char* str) {
137   char cur = *str++;
138   while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
139     PrintChar(cur);
140     cur = *str++;
141   }
142   out_buffer_[out_buffer_pos_] = 0;
143 }
144 
145 // Print the register name according to the active name converter.
PrintRegister(int reg)146 void Decoder::PrintRegister(int reg) {
147   Print(converter_.NameOfCPURegister(reg));
148 }
149 
150 // Print the double FP register name according to the active name converter.
PrintDRegister(int reg)151 void Decoder::PrintDRegister(int reg) {
152   Print(RegisterName(DoubleRegister::from_code(reg)));
153 }
154 
155 // Print the Simd128 register name according to the active name converter.
PrintVectorRegister(int reg)156 void Decoder::PrintVectorRegister(int reg) {
157   Print(RegisterName(Simd128Register::from_code(reg)));
158 }
159 
160 // Print SoftwareInterrupt codes. Factoring this out reduces the complexity of
161 // the FormatOption method.
PrintSoftwareInterrupt(SoftwareInterruptCodes svc)162 void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) {
163   switch (svc) {
164     case kCallRtRedirected:
165       Print("call rt redirected");
166       return;
167     case kBreakpoint:
168       Print("breakpoint");
169       return;
170     default:
171       if (svc >= kStopCode) {
172         out_buffer_pos_ +=
173             base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d - 0x%x",
174                            svc & kStopCodeMask, svc & kStopCodeMask);
175       } else {
176         out_buffer_pos_ +=
177             base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", svc);
178       }
179       return;
180   }
181 }
182 
183 // Handle all register based formatting in this function to reduce the
184 // complexity of FormatOption.
FormatRegister(Instruction* instr, const char* format)185 int Decoder::FormatRegister(Instruction* instr, const char* format) {
186   DCHECK_EQ(format[0], 'r');
187 
188   if ((format[1] == 't') || (format[1] == 's')) {  // 'rt & 'rs register
189     int reg = instr->RTValue();
190     PrintRegister(reg);
191     return 2;
192   } else if (format[1] == 'a') {  // 'ra: RA register
193     int reg = instr->RAValue();
194     PrintRegister(reg);
195     return 2;
196   } else if (format[1] == 'b') {  // 'rb: RB register
197     int reg = instr->RBValue();
198     PrintRegister(reg);
199     return 2;
200   }
201 
202   UNREACHABLE();
203 }
204 
205 // Handle all FP register based formatting in this function to reduce the
206 // complexity of FormatOption.
FormatFPRegister(Instruction* instr, const char* format)207 int Decoder::FormatFPRegister(Instruction* instr, const char* format) {
208   DCHECK(format[0] == 'D' || format[0] == 'X');
209 
210   int retval = 2;
211   int reg = -1;
212   if (format[1] == 't' || format[1] == 's') {
213     reg = instr->RTValue();
214   } else if (format[1] == 'a') {
215     reg = instr->RAValue();
216   } else if (format[1] == 'b') {
217     reg = instr->RBValue();
218   } else if (format[1] == 'c') {
219     reg = instr->RCValue();
220   } else {
221     UNREACHABLE();
222   }
223 
224   PrintDRegister(reg);
225 
226   return retval;
227 }
228 
FormatVectorRegister(Instruction* instr, const char* format)229 int Decoder::FormatVectorRegister(Instruction* instr, const char* format) {
230   int retval = 2;
231   int reg = -1;
232   if (format[1] == 't' || format[1] == 's') {
233     reg = instr->RTValue();
234   } else if (format[1] == 'a') {
235     reg = instr->RAValue();
236   } else if (format[1] == 'b') {
237     reg = instr->RBValue();
238   } else if (format[1] == 'c') {
239     reg = instr->RCValue();
240   } else {
241     UNREACHABLE();
242   }
243 
244   PrintVectorRegister(reg);
245 
246   return retval;
247 }
248 
249 // FormatOption takes a formatting string and interprets it based on
250 // the current instructions. The format string points to the first
251 // character of the option string (the option escape has already been
252 // consumed by the caller.)  FormatOption returns the number of
253 // characters that were consumed from the formatting string.
FormatOption(Instruction* instr, const char* format)254 int Decoder::FormatOption(Instruction* instr, const char* format) {
255   switch (format[0]) {
256     case 'o': {
257       if (instr->Bit(10) == 1) {
258         Print("o");
259       }
260       return 1;
261     }
262     case '.': {
263       if (instr->Bit(0) == 1) {
264         Print(".");
265       } else {
266         Print(" ");  // ensure consistent spacing
267       }
268       return 1;
269     }
270     case 'r': {
271       return FormatRegister(instr, format);
272     }
273     case 'D': {
274       return FormatFPRegister(instr, format);
275     }
276     case 'X': {
277       // Check the TX/SX value, if set then it's a Vector register.
278       if (instr->Bit(0) == 1) {
279         return FormatVectorRegister(instr, format);
280       }
281       // Double (VSX) register.
282       return FormatFPRegister(instr, format);
283     }
284     case 'V': {
285       return FormatVectorRegister(instr, format);
286     }
287     case 'i': {  // int16
288       int64_t value;
289       uint32_t imm_value = instr->Bits(15, 0);
290       if (IsPrefixed()) {
291         uint64_t prefix_value = GetPrefixValue();
292         value = SIGN_EXT_IMM34((prefix_value << 16) | imm_value);
293       } else {
294         value = (static_cast<int64_t>(imm_value) << 48) >> 48;
295       }
296       out_buffer_pos_ +=
297           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%ld", value);
298       return 5;
299     }
300     case 'I': {  // IMM8
301       int8_t value = instr->Bits(18, 11);
302       out_buffer_pos_ +=
303           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
304       return 4;
305     }
306     case 'u': {  // uint16
307       int32_t value = instr->Bits(15, 0);
308       out_buffer_pos_ +=
309           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
310       return 6;
311     }
312     case 'F': {  // FXM
313       uint8_t value = instr->Bits(19, 12);
314       out_buffer_pos_ +=
315           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
316       return 3;
317     }
318     case 'S': {  // SIM
319       int32_t value = static_cast<int32_t>(SIGN_EXT_IMM5(instr->Bits(20, 16)));
320       out_buffer_pos_ +=
321           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
322       return 3;
323     }
324     case 'U': {  // UIM
325       uint8_t value = instr->Bits(19, 16);
326       out_buffer_pos_ +=
327           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
328       return 3;
329     }
330     case 'l': {
331       // Link (LK) Bit 0
332       if (instr->Bit(0) == 1) {
333         Print("l");
334       }
335       return 1;
336     }
337     case 'a': {
338       // Absolute Address Bit 1
339       if (instr->Bit(1) == 1) {
340         Print("a");
341       }
342       return 1;
343     }
344     case 'c': {  // 'cr: condition register of branch instruction
345       int code = instr->Bits(20, 18);
346       if (code != 7) {
347         out_buffer_pos_ +=
348             base::SNPrintF(out_buffer_ + out_buffer_pos_, " cr%d", code);
349       }
350       return 2;
351     }
352     case 't': {  // 'target: target of branch instructions
353       // target26 or target16
354       DCHECK(STRING_STARTS_WITH(format, "target"));
355       if ((format[6] == '2') && (format[7] == '6')) {
356         int off = ((instr->Bits(25, 2)) << 8) >> 6;
357         out_buffer_pos_ += base::SNPrintF(
358             out_buffer_ + out_buffer_pos_, "%+d -> %s", off,
359             converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off));
360         return 8;
361       } else if ((format[6] == '1') && (format[7] == '6')) {
362         int off = ((instr->Bits(15, 2)) << 18) >> 16;
363         out_buffer_pos_ += base::SNPrintF(
364             out_buffer_ + out_buffer_pos_, "%+d -> %s", off,
365             converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off));
366         return 8;
367       }
368       break;
369       case 's': {
370         DCHECK_EQ(format[1], 'h');
371         int32_t value = 0;
372         int32_t opcode = instr->OpcodeValue() << 26;
373         int32_t sh = instr->Bits(15, 11);
374         if (opcode == EXT5 ||
375             (opcode == EXT2 && instr->Bits(10, 2) << 2 == SRADIX)) {
376           // SH Bits 1 and 15-11 (split field)
377           value = (sh | (instr->Bit(1) << 5));
378         } else {
379           // SH Bits 15-11
380           value = (sh << 26) >> 26;
381         }
382         out_buffer_pos_ +=
383             base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
384         return 2;
385       }
386       case 'm': {
387         int32_t value = 0;
388         if (format[1] == 'e') {
389           if (instr->OpcodeValue() << 26 != EXT5) {
390             // ME Bits 10-6
391             value = (instr->Bits(10, 6) << 26) >> 26;
392           } else {
393             // ME Bits 5 and 10-6 (split field)
394             value = (instr->Bits(10, 6) | (instr->Bit(5) << 5));
395           }
396         } else if (format[1] == 'b') {
397           if (instr->OpcodeValue() << 26 != EXT5) {
398             // MB Bits 5-1
399             value = (instr->Bits(5, 1) << 26) >> 26;
400           } else {
401             // MB Bits 5 and 10-6 (split field)
402             value = (instr->Bits(10, 6) | (instr->Bit(5) << 5));
403           }
404         } else {
405           UNREACHABLE();  // bad format
406         }
407         out_buffer_pos_ +=
408             base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
409         return 2;
410       }
411     }
412 #if V8_TARGET_ARCH_PPC64
413     case 'd': {  // ds value for offset
414       int32_t value = SIGN_EXT_IMM16(instr->Bits(15, 0) & ~3);
415       out_buffer_pos_ +=
416           base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
417       return 1;
418     }
419 #endif
420     default: {
421       UNREACHABLE();
422     }
423   }
424 
425   UNREACHABLE();
426 }
427 
428 // Format takes a formatting string for a whole instruction and prints it into
429 // the output buffer. All escaped options are handed to FormatOption to be
430 // parsed further.
Format(Instruction* instr, const char* format)431 void Decoder::Format(Instruction* instr, const char* format) {
432   char cur = *format++;
433   while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
434     if (cur == '\'') {  // Single quote is used as the formatting escape.
435       format += FormatOption(instr, format);
436     } else {
437       out_buffer_[out_buffer_pos_++] = cur;
438     }
439     cur = *format++;
440   }
441   out_buffer_[out_buffer_pos_] = '\0';
442 }
443 
444 // The disassembler may end up decoding data inlined in the code. We do not want
445 // it to crash if the data does not resemble any known instruction.
446 #define VERIFY(condition) \
447   if (!(condition)) {     \
448     Unknown(instr);       \
449     return;               \
450   }
451 
452 // For currently unimplemented decodings the disassembler calls Unknown(instr)
453 // which will just print "unknown" of the instruction bits.
Unknown(Instruction* instr)454 void Decoder::Unknown(Instruction* instr) { Format(instr, "unknown"); }
455 
456 // For currently unimplemented decodings the disassembler calls
457 // UnknownFormat(instr) which will just print opcode name of the
458 // instruction bits.
UnknownFormat(Instruction* instr, const char* name)459 void Decoder::UnknownFormat(Instruction* instr, const char* name) {
460   char buffer[100];
461   snprintf(buffer, sizeof(buffer), "%s (unknown-format)", name);
462   Format(instr, buffer);
463 }
464 
DecodeExtP(Instruction* instr)465 void Decoder::DecodeExtP(Instruction* instr) {
466   switch (EXTP | (instr->BitField(25, 25))) {
467     case PLOAD_STORE_8LS:
468     case PLOAD_STORE_MLS: {
469       // TODO(miladfarca): Decode the R bit.
470       DCHECK_NE(instr->Bit(20), 1);
471       // Read prefix.
472       SetAsPrefixed(instr->Bits(17, 0));
473       // Read suffix (next instruction).
474       Instruction* next_instr =
475           bit_cast<Instruction*>(bit_cast<intptr_t>(instr) + kInstrSize);
476       switch (next_instr->OpcodeBase()) {
477           // Prefixed ADDI.
478         case (ADDI): {
479           if (next_instr->RAValue() == 0) {
480             // This is load immediate prefixed.
481             Format(instr, "pli");
482             Format(next_instr, "     'rt, ");
483           } else {
484             Format(instr, "paddi");
485             Format(next_instr, "   'rt, 'ra, ");
486           }
487           Format(next_instr, "'int34");
488           break;
489         }
490         // Prefixed LBZ.
491         case LBZ: {
492           Format(next_instr, "plbz    'rt, 'int34('ra)");
493           break;
494         }
495           // Prefixed LHZ.
496         case LHZ: {
497           Format(next_instr, "plhz    'rt, 'int34('ra)");
498           break;
499         }
500           // Prefixed LHA.
501         case LHA: {
502           Format(next_instr, "plha    'rt, 'int34('ra)");
503           break;
504         }
505           // Prefixed LWZ.
506         case LWZ: {
507           Format(next_instr, "plwz    'rt, 'int34('ra)");
508           break;
509         }
510           // Prefixed LWA.
511         case PPLWA: {
512           Format(next_instr, "plwa    'rt, 'int34('ra)");
513           break;
514         }
515           // Prefixed LD.
516         case PPLD: {
517           Format(next_instr, "pld    'rt, 'int34('ra)");
518           break;
519         }
520           // Prefixed LFS.
521         case LFS: {
522           Format(next_instr, "plfs    'Dt, 'int34('ra)");
523           break;
524         }
525         // Prefixed LFD.
526         case LFD: {
527           Format(next_instr, "plfd    'Dt, 'int34('ra)");
528           break;
529         }
530         default: {
531           Unknown(instr);
532         }
533       }
534       break;
535     }
536     default: {
537       Unknown(instr);
538     }
539   }
540 }
541 
DecodeExt0(Instruction* instr)542 void Decoder::DecodeExt0(Instruction* instr) {
543   // Some encodings have integers hard coded in the middle, handle those first.
544   switch (EXT0 | (instr->BitField(20, 16)) | (instr->BitField(10, 0))) {
545 #define DECODE_VX_D_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
546   case opcode_name: {                                                   \
547     Format(instr, #name " 'Vt, 'Vb");                                   \
548     return;                                                             \
549   }
550     PPC_VX_OPCODE_D_FORM_LIST(DECODE_VX_D_FORM__INSTRUCTIONS)
551 #undef DECODE_VX_D_FORM__INSTRUCTIONS
552 #define DECODE_VX_F_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
553   case opcode_name: {                                                   \
554     Format(instr, #name " 'rt, 'Vb");                                   \
555     return;                                                             \
556   }
557     PPC_VX_OPCODE_F_FORM_LIST(DECODE_VX_F_FORM__INSTRUCTIONS)
558 #undef DECODE_VX_F_FORM__INSTRUCTIONS
559   }
560   // Some encodings are 5-0 bits, handle those first
561   switch (EXT0 | (instr->BitField(5, 0))) {
562 #define DECODE_VA_A_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
563   case opcode_name: {                                                   \
564     Format(instr, #name " 'Vt, 'Va, 'Vb, 'Vc");                         \
565     return;                                                             \
566   }
567     PPC_VA_OPCODE_A_FORM_LIST(DECODE_VA_A_FORM__INSTRUCTIONS)
568 #undef DECODE_VA_A_FORM__INSTRUCTIONS
569   }
570   switch (EXT0 | (instr->BitField(9, 0))) {
571 // TODO(miladfarca): Fix RC indicator.
572 #define DECODE_VC_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
573   case opcode_name: {                                                 \
574     Format(instr, #name " 'Vt, 'Va, 'Vb");                            \
575     return;                                                           \
576   }
577     PPC_VC_OPCODE_LIST(DECODE_VC_FORM__INSTRUCTIONS)
578 #undef DECODE_VC_FORM__INSTRUCTIONS
579   }
580   switch (EXT0 | (instr->BitField(10, 0))) {
581 #define DECODE_VX_A_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
582   case opcode_name: {                                                   \
583     Format(instr, #name " 'Vt, 'Vb, 'UIM");                             \
584     return;                                                             \
585   }
586     PPC_VX_OPCODE_A_FORM_LIST(DECODE_VX_A_FORM__INSTRUCTIONS)
587 #undef DECODE_VX_A_FORM__INSTRUCTIONS
588 #define DECODE_VX_B_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
589   case opcode_name: {                                                   \
590     Format(instr, #name " 'Vt, 'Va, 'Vb");                              \
591     return;                                                             \
592   }
593     PPC_VX_OPCODE_B_FORM_LIST(DECODE_VX_B_FORM__INSTRUCTIONS)
594 #undef DECODE_VX_B_FORM__INSTRUCTIONS
595 #define DECODE_VX_C_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
596   case opcode_name: {                                                   \
597     Format(instr, #name " 'Vt, 'Vb");                                   \
598     return;                                                             \
599   }
600     PPC_VX_OPCODE_C_FORM_LIST(DECODE_VX_C_FORM__INSTRUCTIONS)
601 #undef DECODE_VX_C_FORM__INSTRUCTIONS
602 #define DECODE_VX_E_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
603   case opcode_name: {                                                   \
604     Format(instr, #name " 'Vt, 'SIM");                                  \
605     return;                                                             \
606   }
607     PPC_VX_OPCODE_E_FORM_LIST(DECODE_VX_E_FORM__INSTRUCTIONS)
608 #undef DECODE_VX_E_FORM__INSTRUCTIONS
609 #define DECODE_VX_G_FORM__INSTRUCTIONS(name, opcode_name, opcode_value) \
610   case opcode_name: {                                                   \
611     Format(instr, #name " 'Vt, 'rb, 'UIM");                             \
612     return;                                                             \
613   }
614     PPC_VX_OPCODE_G_FORM_LIST(DECODE_VX_G_FORM__INSTRUCTIONS)
615 #undef DECODE_VX_G_FORM__INSTRUCTIONS
616   }
617 }
618 
DecodeExt1(Instruction* instr)619 void Decoder::DecodeExt1(Instruction* instr) {
620   switch (EXT1 | (instr->BitField(10, 1))) {
621     case MCRF: {
622       UnknownFormat(instr, "mcrf");  // not used by V8
623       break;
624     }
625     case BCLRX: {
626       int bo = instr->BitField(25, 21);
627       int bi = instr->Bits(20, 16);
628       CRBit cond = static_cast<CRBit>(bi & (CRWIDTH - 1));
629       switch (bo) {
630         case DCBNZF: {
631           UnknownFormat(instr, "bclrx-dcbnzf");
632           break;
633         }
634         case DCBEZF: {
635           UnknownFormat(instr, "bclrx-dcbezf");
636           break;
637         }
638         case BF: {
639           switch (cond) {
640             case CR_EQ:
641               Format(instr, "bnelr'l'cr");
642               break;
643             case CR_GT:
644               Format(instr, "blelr'l'cr");
645               break;
646             case CR_LT:
647               Format(instr, "bgelr'l'cr");
648               break;
649             case CR_SO:
650               Format(instr, "bnsolr'l'cr");
651               break;
652           }
653           break;
654         }
655         case DCBNZT: {
656           UnknownFormat(instr, "bclrx-dcbbzt");
657           break;
658         }
659         case DCBEZT: {
660           UnknownFormat(instr, "bclrx-dcbnezt");
661           break;
662         }
663         case BT: {
664           switch (cond) {
665             case CR_EQ:
666               Format(instr, "beqlr'l'cr");
667               break;
668             case CR_GT:
669               Format(instr, "bgtlr'l'cr");
670               break;
671             case CR_LT:
672               Format(instr, "bltlr'l'cr");
673               break;
674             case CR_SO:
675               Format(instr, "bsolr'l'cr");
676               break;
677           }
678           break;
679         }
680         case DCBNZ: {
681           UnknownFormat(instr, "bclrx-dcbnz");
682           break;
683         }
684         case DCBEZ: {
685           UnknownFormat(instr, "bclrx-dcbez");  // not used by V8
686           break;
687         }
688         case BA: {
689           Format(instr, "blr'l");
690           break;
691         }
692       }
693       break;
694     }
695     case BCCTRX: {
696       switch (instr->BitField(25, 21)) {
697         case DCBNZF: {
698           UnknownFormat(instr, "bcctrx-dcbnzf");
699           break;
700         }
701         case DCBEZF: {
702           UnknownFormat(instr, "bcctrx-dcbezf");
703           break;
704         }
705         case BF: {
706           UnknownFormat(instr, "bcctrx-bf");
707           break;
708         }
709         case DCBNZT: {
710           UnknownFormat(instr, "bcctrx-dcbnzt");
711           break;
712         }
713         case DCBEZT: {
714           UnknownFormat(instr, "bcctrx-dcbezf");
715           break;
716         }
717         case BT: {
718           UnknownFormat(instr, "bcctrx-bt");
719           break;
720         }
721         case DCBNZ: {
722           UnknownFormat(instr, "bcctrx-dcbnz");
723           break;
724         }
725         case DCBEZ: {
726           UnknownFormat(instr, "bcctrx-dcbez");
727           break;
728         }
729         case BA: {
730           if (instr->Bit(0) == 1) {
731             Format(instr, "bctrl");
732           } else {
733             Format(instr, "bctr");
734           }
735           break;
736         }
737         default: {
738           UNREACHABLE();
739         }
740       }
741       break;
742     }
743     case CRNOR: {
744       Format(instr, "crnor (stuff)");
745       break;
746     }
747     case RFI: {
748       Format(instr, "rfi (stuff)");
749       break;
750     }
751     case CRANDC: {
752       Format(instr, "crandc (stuff)");
753       break;
754     }
755     case ISYNC: {
756       Format(instr, "isync (stuff)");
757       break;
758     }
759     case CRXOR: {
760       Format(instr, "crxor (stuff)");
761       break;
762     }
763     case CRNAND: {
764       UnknownFormat(instr, "crnand");
765       break;
766     }
767     case CRAND: {
768       UnknownFormat(instr, "crand");
769       break;
770     }
771     case CREQV: {
772       UnknownFormat(instr, "creqv");
773       break;
774     }
775     case CRORC: {
776       UnknownFormat(instr, "crorc");
777       break;
778     }
779     case CROR: {
780       UnknownFormat(instr, "cror");
781       break;
782     }
783     default: {
784       Unknown(instr);  // not used by V8
785     }
786   }
787 }
788 
DecodeExt2(Instruction* instr)789 void Decoder::DecodeExt2(Instruction* instr) {
790   // Some encodings are 10-1 bits, handle those first
791   switch (EXT2 | (instr->BitField(10, 1))) {
792     case LVX: {
793       Format(instr, "lvx     'Vt, 'ra, 'rb");
794       return;
795     }
796     case STVX: {
797       Format(instr, "stvx    'Vs, 'ra, 'rb");
798       return;
799     }
800     case LXVD: {
801       Format(instr, "lxvd    'Xt, 'ra, 'rb");
802       return;
803     }
804     case LXVX: {
805       Format(instr, "lxvx    'Xt, 'ra, 'rb");
806       return;
807     }
808     case LXSDX: {
809       Format(instr, "lxsdx    'Xt, 'ra, 'rb");
810       return;
811     }
812     case LXSIBZX: {
813       Format(instr, "lxsibzx  'Xt, 'ra, 'rb");
814       return;
815     }
816     case LXSIHZX: {
817       Format(instr, "lxsihzx  'Xt, 'ra, 'rb");
818       return;
819     }
820     case LXSIWZX: {
821       Format(instr, "lxsiwzx  'Xt, 'ra, 'rb");
822       return;
823     }
824     case STXVD: {
825       Format(instr, "stxvd   'Xs, 'ra, 'rb");
826       return;
827     }
828     case STXVX: {
829       Format(instr, "stxvx   'Xs, 'ra, 'rb");
830       return;
831     }
832     case STXSDX: {
833       Format(instr, "stxsdx  'Xs, 'ra, 'rb");
834       return;
835     }
836     case STXSIBX: {
837       Format(instr, "stxsibx 'Xs, 'ra, 'rb");
838       return;
839     }
840     case STXSIHX: {
841       Format(instr, "stxsihx 'Xs, 'ra, 'rb");
842       return;
843     }
844     case STXSIWX: {
845       Format(instr, "stxsiwx 'Xs, 'ra, 'rb");
846       return;
847     }
848     case SRWX: {
849       Format(instr, "srw'.    'ra, 'rs, 'rb");
850       return;
851     }
852 #if V8_TARGET_ARCH_PPC64
853     case SRDX: {
854       Format(instr, "srd'.    'ra, 'rs, 'rb");
855       return;
856     }
857 #endif
858     case SRAW: {
859       Format(instr, "sraw'.   'ra, 'rs, 'rb");
860       return;
861     }
862 #if V8_TARGET_ARCH_PPC64
863     case SRAD: {
864       Format(instr, "srad'.   'ra, 'rs, 'rb");
865       return;
866     }
867 #endif
868     case SYNC: {
869       Format(instr, "sync");
870       return;
871     }
872     case MODSW: {
873       Format(instr, "modsw  'rt, 'ra, 'rb");
874       return;
875     }
876     case MODUW: {
877       Format(instr, "moduw  'rt, 'ra, 'rb");
878       return;
879     }
880 #if V8_TARGET_ARCH_PPC64
881     case MODSD: {
882       Format(instr, "modsd  'rt, 'ra, 'rb");
883       return;
884     }
885     case MODUD: {
886       Format(instr, "modud  'rt, 'ra, 'rb");
887       return;
888     }
889 #endif
890     case SRAWIX: {
891       Format(instr, "srawi'.  'ra,'rs,'sh");
892       return;
893     }
894     case EXTSH: {
895       Format(instr, "extsh'.  'ra, 'rs");
896       return;
897     }
898 #if V8_TARGET_ARCH_PPC64
899     case EXTSW: {
900       Format(instr, "extsw'.  'ra, 'rs");
901       return;
902     }
903 #endif
904     case EXTSB: {
905       Format(instr, "extsb'.  'ra, 'rs");
906       return;
907     }
908     case LFSX: {
909       Format(instr, "lfsx    'Dt, 'ra, 'rb");
910       return;
911     }
912     case LFSUX: {
913       Format(instr, "lfsux   'Dt, 'ra, 'rb");
914       return;
915     }
916     case LFDX: {
917       Format(instr, "lfdx    'Dt, 'ra, 'rb");
918       return;
919     }
920     case LFDUX: {
921       Format(instr, "lfdux   'Dt, 'ra, 'rb");
922       return;
923     }
924     case STFSX: {
925       Format(instr, "stfsx    'rs, 'ra, 'rb");
926       return;
927     }
928     case STFSUX: {
929       Format(instr, "stfsux   'rs, 'ra, 'rb");
930       return;
931     }
932     case STFDX: {
933       Format(instr, "stfdx    'rs, 'ra, 'rb");
934       return;
935     }
936     case STFDUX: {
937       Format(instr, "stfdux   'rs, 'ra, 'rb");
938       return;
939     }
940     case POPCNTW: {
941       Format(instr, "popcntw  'ra, 'rs");
942       return;
943     }
944 #if V8_TARGET_ARCH_PPC64
945     case POPCNTD: {
946       Format(instr, "popcntd  'ra, 'rs");
947       return;
948     }
949 #endif
950   }
951 
952   switch (EXT2 | (instr->BitField(10, 2))) {
953     case SRADIX: {
954       Format(instr, "sradi'.  'ra,'rs,'sh");
955       return;
956     }
957   }
958 
959   switch (EXT2 | (instr->BitField(10, 0))) {
960     case STBCX: {
961       Format(instr, "stbcx   'rs, 'ra, 'rb");
962       return;
963     }
964     case STHCX: {
965       Format(instr, "sthcx   'rs, 'ra, 'rb");
966       return;
967     }
968     case STWCX: {
969       Format(instr, "stwcx   'rs, 'ra, 'rb");
970       return;
971     }
972     case STDCX: {
973       Format(instr, "stdcx   'rs, 'ra, 'rb");
974       return;
975     }
976   }
977 
978   // ?? are all of these xo_form?
979   switch (EXT2 | (instr->BitField(10, 1))) {
980     case CMP: {
981 #if V8_TARGET_ARCH_PPC64
982       if (instr->Bit(21)) {
983 #endif
984         Format(instr, "cmp     'ra, 'rb");
985 #if V8_TARGET_ARCH_PPC64
986       } else {
987         Format(instr, "cmpw    'ra, 'rb");
988       }
989 #endif
990       return;
991     }
992     case SLWX: {
993       Format(instr, "slw'.   'ra, 'rs, 'rb");
994       return;
995     }
996 #if V8_TARGET_ARCH_PPC64
997     case SLDX: {
998       Format(instr, "sld'.   'ra, 'rs, 'rb");
999       return;
1000     }
1001 #endif
1002     case SUBFCX: {
1003       Format(instr, "subfc'. 'rt, 'ra, 'rb");
1004       return;
1005     }
1006     case SUBFEX: {
1007       Format(instr, "subfe'. 'rt, 'ra, 'rb");
1008       return;
1009     }
1010     case ADDCX: {
1011       Format(instr, "addc'.   'rt, 'ra, 'rb");
1012       return;
1013     }
1014     case ADDEX: {
1015       Format(instr, "adde'.   'rt, 'ra, 'rb");
1016       return;
1017     }
1018     case CNTLZWX: {
1019       Format(instr, "cntlzw'. 'ra, 'rs");
1020       return;
1021     }
1022     case CNTLZDX: {
1023       Format(instr, "cntlzd'. 'ra, 'rs");
1024       return;
1025     }
1026     case CNTTZWX: {
1027       Format(instr, "cnttzw'. 'ra, 'rs");
1028       return;
1029     }
1030     case CNTTZDX: {
1031       Format(instr, "cnttzd'. 'ra, 'rs");
1032       return;
1033     }
1034     case BRH: {
1035       Format(instr, "brh     'ra, 'rs");
1036       return;
1037     }
1038     case BRW: {
1039       Format(instr, "brw     'ra, 'rs");
1040       return;
1041     }
1042     case BRD: {
1043       Format(instr, "brd     'ra, 'rs");
1044       return;
1045     }
1046     case ANDX: {
1047       Format(instr, "and'.    'ra, 'rs, 'rb");
1048       return;
1049     }
1050     case ANDCX: {
1051       Format(instr, "andc'.   'ra, 'rs, 'rb");
1052       return;
1053     }
1054     case CMPL: {
1055 #if V8_TARGET_ARCH_PPC64
1056       if (instr->Bit(21)) {
1057 #endif
1058         Format(instr, "cmpl    'ra, 'rb");
1059 #if V8_TARGET_ARCH_PPC64
1060       } else {
1061         Format(instr, "cmplw   'ra, 'rb");
1062       }
1063 #endif
1064       return;
1065     }
1066     case NEGX: {
1067       Format(instr, "neg'.    'rt, 'ra");
1068       return;
1069     }
1070     case NORX: {
1071       Format(instr, "nor'.    'rt, 'ra, 'rb");
1072       return;
1073     }
1074     case SUBFX: {
1075       Format(instr, "subf'.   'rt, 'ra, 'rb");
1076       return;
1077     }
1078     case MULHWX: {
1079       Format(instr, "mulhw'o'.  'rt, 'ra, 'rb");
1080       return;
1081     }
1082     case ADDZEX: {
1083       Format(instr, "addze'.   'rt, 'ra");
1084       return;
1085     }
1086     case MULLW: {
1087       Format(instr, "mullw'o'.  'rt, 'ra, 'rb");
1088       return;
1089     }
1090 #if V8_TARGET_ARCH_PPC64
1091     case MULLD: {
1092       Format(instr, "mulld'o'.  'rt, 'ra, 'rb");
1093       return;
1094     }
1095 #endif
1096     case DIVW: {
1097       Format(instr, "divw'o'.   'rt, 'ra, 'rb");
1098       return;
1099     }
1100     case DIVWU: {
1101       Format(instr, "divwu'o'.  'rt, 'ra, 'rb");
1102       return;
1103     }
1104 #if V8_TARGET_ARCH_PPC64
1105     case DIVD: {
1106       Format(instr, "divd'o'.   'rt, 'ra, 'rb");
1107       return;
1108     }
1109 #endif
1110     case ADDX: {
1111       Format(instr, "add'o     'rt, 'ra, 'rb");
1112       return;
1113     }
1114     case XORX: {
1115       Format(instr, "xor'.    'ra, 'rs, 'rb");
1116       return;
1117     }
1118     case ORX: {
1119       if (instr->RTValue() == instr->RBValue()) {
1120         Format(instr, "mr      'ra, 'rb");
1121       } else {
1122         Format(instr, "or      'ra, 'rs, 'rb");
1123       }
1124       return;
1125     }
1126     case MFSPR: {
1127       int spr = instr->Bits(20, 11);
1128       if (256 == spr) {
1129         Format(instr, "mflr    'rt");
1130       } else {
1131         Format(instr, "mfspr   'rt ??");
1132       }
1133       return;
1134     }
1135     case MTSPR: {
1136       int spr = instr->Bits(20, 11);
1137       if (256 == spr) {
1138         Format(instr, "mtlr    'rt");
1139       } else if (288 == spr) {
1140         Format(instr, "mtctr   'rt");
1141       } else {
1142         Format(instr, "mtspr   'rt ??");
1143       }
1144       return;
1145     }
1146     case MFCR: {
1147       Format(instr, "mfcr    'rt");
1148       return;
1149     }
1150     case STWX: {
1151       Format(instr, "stwx    'rs, 'ra, 'rb");
1152       return;
1153     }
1154     case STWUX: {
1155       Format(instr, "stwux   'rs, 'ra, 'rb");
1156       return;
1157     }
1158     case STBX: {
1159       Format(instr, "stbx    'rs, 'ra, 'rb");
1160       return;
1161     }
1162     case STBUX: {
1163       Format(instr, "stbux   'rs, 'ra, 'rb");
1164       return;
1165     }
1166     case STHX: {
1167       Format(instr, "sthx    'rs, 'ra, 'rb");
1168       return;
1169     }
1170     case STHUX: {
1171       Format(instr, "sthux   'rs, 'ra, 'rb");
1172       return;
1173     }
1174     case LWZX: {
1175       Format(instr, "lwzx    'rt, 'ra, 'rb");
1176       return;
1177     }
1178     case LWZUX: {
1179       Format(instr, "lwzux   'rt, 'ra, 'rb");
1180       return;
1181     }
1182     case LWAX: {
1183       Format(instr, "lwax    'rt, 'ra, 'rb");
1184       return;
1185     }
1186     case LBZX: {
1187       Format(instr, "lbzx    'rt, 'ra, 'rb");
1188       return;
1189     }
1190     case LBZUX: {
1191       Format(instr, "lbzux   'rt, 'ra, 'rb");
1192       return;
1193     }
1194     case LHZX: {
1195       Format(instr, "lhzx    'rt, 'ra, 'rb");
1196       return;
1197     }
1198     case LHZUX: {
1199       Format(instr, "lhzux   'rt, 'ra, 'rb");
1200       return;
1201     }
1202     case LHAX: {
1203       Format(instr, "lhax    'rt, 'ra, 'rb");
1204       return;
1205     }
1206     case LBARX: {
1207       Format(instr, "lbarx   'rt, 'ra, 'rb");
1208       return;
1209     }
1210     case LHARX: {
1211       Format(instr, "lharx   'rt, 'ra, 'rb");
1212       return;
1213     }
1214     case LWARX: {
1215       Format(instr, "lwarx   'rt, 'ra, 'rb");
1216       return;
1217     }
1218 #if V8_TARGET_ARCH_PPC64
1219     case LDX: {
1220       Format(instr, "ldx     'rt, 'ra, 'rb");
1221       return;
1222     }
1223     case LDUX: {
1224       Format(instr, "ldux    'rt, 'ra, 'rb");
1225       return;
1226     }
1227     case LDARX: {
1228       Format(instr, "ldarx   'rt, 'ra, 'rb");
1229       return;
1230     }
1231     case STDX: {
1232       Format(instr, "stdx    'rt, 'ra, 'rb");
1233       return;
1234     }
1235     case STDUX: {
1236       Format(instr, "stdux   'rt, 'ra, 'rb");
1237       return;
1238     }
1239     case MFVSRD: {
1240       Format(instr, "mfvsrd  'ra, 'Xs");
1241       return;
1242     }
1243     case MFVSRWZ: {
1244       Format(instr, "mffprwz 'ra, 'Dt");
1245       return;
1246     }
1247     case MTVSRD: {
1248       Format(instr, "mtvsrd  'Xt, 'ra");
1249       return;
1250     }
1251     case MTVSRWA: {
1252       Format(instr, "mtfprwa 'Dt, 'ra");
1253       return;
1254     }
1255     case MTVSRWZ: {
1256       Format(instr, "mtfprwz 'Dt, 'ra");
1257       return;
1258     }
1259     case MTVSRDD: {
1260       Format(instr, "mtvsrdd 'Xt, 'ra, 'rb");
1261       return;
1262     }
1263     case LDBRX: {
1264       Format(instr, "ldbrx   'rt, 'ra, 'rb");
1265       return;
1266     }
1267     case LHBRX: {
1268       Format(instr, "lhbrx   'rt, 'ra, 'rb");
1269       return;
1270     }
1271     case LWBRX: {
1272       Format(instr, "lwbrx   'rt, 'ra, 'rb");
1273       return;
1274     }
1275     case STDBRX: {
1276       Format(instr, "stdbrx  'rs, 'ra, 'rb");
1277       return;
1278     }
1279     case STWBRX: {
1280       Format(instr, "stwbrx  'rs, 'ra, 'rb");
1281       return;
1282     }
1283     case STHBRX: {
1284       Format(instr, "sthbrx  'rs, 'ra, 'rb");
1285       return;
1286     }
1287     case MTCRF: {
1288       Format(instr, "mtcrf   'FXM, 'rs");
1289       return;
1290     }
1291 #endif
1292   }
1293 
1294   switch (EXT2 | (instr->BitField(5, 1))) {
1295     case ISEL: {
1296       Format(instr, "isel    'rt, 'ra, 'rb");
1297       return;
1298     }
1299     default: {
1300       Unknown(instr);  // not used by V8
1301     }
1302   }
1303 }
1304 
DecodeExt3(Instruction* instr)1305 void Decoder::DecodeExt3(Instruction* instr) {
1306   switch (EXT3 | (instr->BitField(10, 1))) {
1307     case FCFID: {
1308       Format(instr, "fcfids'. 'Dt, 'Db");
1309       break;
1310     }
1311     case FCFIDU: {
1312       Format(instr, "fcfidus'.'Dt, 'Db");
1313       break;
1314     }
1315     default: {
1316       Unknown(instr);  // not used by V8
1317     }
1318   }
1319 }
1320 
DecodeExt4(Instruction* instr)1321 void Decoder::DecodeExt4(Instruction* instr) {
1322   switch (EXT4 | (instr->BitField(5, 1))) {
1323     case FDIV: {
1324       Format(instr, "fdiv'.   'Dt, 'Da, 'Db");
1325       return;
1326     }
1327     case FSUB: {
1328       Format(instr, "fsub'.   'Dt, 'Da, 'Db");
1329       return;
1330     }
1331     case FADD: {
1332       Format(instr, "fadd'.   'Dt, 'Da, 'Db");
1333       return;
1334     }
1335     case FSQRT: {
1336       Format(instr, "fsqrt'.  'Dt, 'Db");
1337       return;
1338     }
1339     case FSEL: {
1340       Format(instr, "fsel'.   'Dt, 'Da, 'Dc, 'Db");
1341       return;
1342     }
1343     case FMUL: {
1344       Format(instr, "fmul'.   'Dt, 'Da, 'Dc");
1345       return;
1346     }
1347     case FMSUB: {
1348       Format(instr, "fmsub'.  'Dt, 'Da, 'Dc, 'Db");
1349       return;
1350     }
1351     case FMADD: {
1352       Format(instr, "fmadd'.  'Dt, 'Da, 'Dc, 'Db");
1353       return;
1354     }
1355   }
1356 
1357   switch (EXT4 | (instr->BitField(10, 1))) {
1358     case FCMPU: {
1359       Format(instr, "fcmpu   'Da, 'Db");
1360       break;
1361     }
1362     case FRSP: {
1363       Format(instr, "frsp'.   'Dt, 'Db");
1364       break;
1365     }
1366     case FCFID: {
1367       Format(instr, "fcfid'.  'Dt, 'Db");
1368       break;
1369     }
1370     case FCFIDU: {
1371       Format(instr, "fcfidu'. 'Dt, 'Db");
1372       break;
1373     }
1374     case FCTID: {
1375       Format(instr, "fctid   'Dt, 'Db");
1376       break;
1377     }
1378     case FCTIDZ: {
1379       Format(instr, "fctidz  'Dt, 'Db");
1380       break;
1381     }
1382     case FCTIDU: {
1383       Format(instr, "fctidu  'Dt, 'Db");
1384       break;
1385     }
1386     case FCTIDUZ: {
1387       Format(instr, "fctiduz 'Dt, 'Db");
1388       break;
1389     }
1390     case FCTIW: {
1391       Format(instr, "fctiw'. 'Dt, 'Db");
1392       break;
1393     }
1394     case FCTIWZ: {
1395       Format(instr, "fctiwz'. 'Dt, 'Db");
1396       break;
1397     }
1398     case FCTIWUZ: {
1399       Format(instr, "fctiwuz 'Dt, 'Db");
1400       break;
1401     }
1402     case FMR: {
1403       Format(instr, "fmr'.    'Dt, 'Db");
1404       break;
1405     }
1406     case MTFSFI: {
1407       Format(instr, "mtfsfi'.  ?,?");
1408       break;
1409     }
1410     case MFFS: {
1411       Format(instr, "mffs'.   'Dt");
1412       break;
1413     }
1414     case MTFSF: {
1415       Format(instr, "mtfsf'.  'Db ?,?,?");
1416       break;
1417     }
1418     case FABS: {
1419       Format(instr, "fabs'.   'Dt, 'Db");
1420       break;
1421     }
1422     case FRIN: {
1423       Format(instr, "frin.   'Dt, 'Db");
1424       break;
1425     }
1426     case FRIZ: {
1427       Format(instr, "friz.   'Dt, 'Db");
1428       break;
1429     }
1430     case FRIP: {
1431       Format(instr, "frip.   'Dt, 'Db");
1432       break;
1433     }
1434     case FRIM: {
1435       Format(instr, "frim.   'Dt, 'Db");
1436       break;
1437     }
1438     case FNEG: {
1439       Format(instr, "fneg'.   'Dt, 'Db");
1440       break;
1441     }
1442     case FCPSGN: {
1443       Format(instr, "fcpsgn'.   'Dt, 'Da, 'Db");
1444       break;
1445     }
1446     case MCRFS: {
1447       Format(instr, "mcrfs   ?,?");
1448       break;
1449     }
1450     case MTFSB0: {
1451       Format(instr, "mtfsb0'. ?");
1452       break;
1453     }
1454     case MTFSB1: {
1455       Format(instr, "mtfsb1'. ?");
1456       break;
1457     }
1458     default: {
1459       Unknown(instr);  // not used by V8
1460     }
1461   }
1462 }
1463 
DecodeExt5(Instruction* instr)1464 void Decoder::DecodeExt5(Instruction* instr) {
1465   switch (EXT5 | (instr->BitField(4, 2))) {
1466     case RLDICL: {
1467       Format(instr, "rldicl'. 'ra, 'rs, 'sh, 'mb");
1468       return;
1469     }
1470     case RLDICR: {
1471       Format(instr, "rldicr'. 'ra, 'rs, 'sh, 'me");
1472       return;
1473     }
1474     case RLDIC: {
1475       Format(instr, "rldic'.  'ra, 'rs, 'sh, 'mb");
1476       return;
1477     }
1478     case RLDIMI: {
1479       Format(instr, "rldimi'. 'ra, 'rs, 'sh, 'mb");
1480       return;
1481     }
1482   }
1483   switch (EXT5 | (instr->BitField(4, 1))) {
1484     case RLDCL: {
1485       Format(instr, "rldcl'.  'ra, 'rs, 'sb, 'mb");
1486       return;
1487     }
1488   }
1489   Unknown(instr);  // not used by V8
1490 }
1491 
DecodeExt6(Instruction* instr)1492 void Decoder::DecodeExt6(Instruction* instr) {
1493   switch (EXT6 | (instr->BitField(10, 1))) {
1494     case XXSPLTIB: {
1495       Format(instr, "xxspltib  'Xt, 'IMM8");
1496       return;
1497     }
1498   }
1499   switch (EXT6 | (instr->BitField(10, 3))) {
1500 #define DECODE_XX3_VECTOR_INSTRUCTIONS(name, opcode_name, opcode_value) \
1501   case opcode_name: {                                                   \
1502     Format(instr, #name " 'Xt, 'Xa, 'Xb");                              \
1503     return;                                                             \
1504   }
1505     PPC_XX3_OPCODE_VECTOR_LIST(DECODE_XX3_VECTOR_INSTRUCTIONS)
1506 #undef DECODE_XX3_VECTOR_INSTRUCTIONS
1507 #define DECODE_XX3_SCALAR_INSTRUCTIONS(name, opcode_name, opcode_value) \
1508   case opcode_name: {                                                   \
1509     Format(instr, #name " 'Dt, 'Da, 'Db");                              \
1510     return;                                                             \
1511   }
1512     PPC_XX3_OPCODE_SCALAR_LIST(DECODE_XX3_SCALAR_INSTRUCTIONS)
1513 #undef DECODE_XX3_SCALAR_INSTRUCTIONS
1514   }
1515   // Some encodings have integers hard coded in the middle, handle those first.
1516   switch (EXT6 | (instr->BitField(20, 16)) | (instr->BitField(10, 2))) {
1517 #define DECODE_XX2_B_INSTRUCTIONS(name, opcode_name, opcode_value) \
1518   case opcode_name: {                                              \
1519     Format(instr, #name " 'Xt, 'Xb");                              \
1520     return;                                                        \
1521   }
1522     PPC_XX2_OPCODE_B_FORM_LIST(DECODE_XX2_B_INSTRUCTIONS)
1523 #undef DECODE_XX2_B_INSTRUCTIONS
1524   }
1525   switch (EXT6 | (instr->BitField(10, 2))) {
1526 #define DECODE_XX2_VECTOR_A_INSTRUCTIONS(name, opcode_name, opcode_value) \
1527   case opcode_name: {                                                     \
1528     Format(instr, #name " 'Xt, 'Xb");                                     \
1529     return;                                                               \
1530   }
1531     PPC_XX2_OPCODE_VECTOR_A_FORM_LIST(DECODE_XX2_VECTOR_A_INSTRUCTIONS)
1532 #undef DECODE_XX2_VECTOR_A_INSTRUCTIONS
1533 #define DECODE_XX2_SCALAR_A_INSTRUCTIONS(name, opcode_name, opcode_value) \
1534   case opcode_name: {                                                     \
1535     Format(instr, #name " 'Dt, 'Db");                                     \
1536     return;                                                               \
1537   }
1538     PPC_XX2_OPCODE_SCALAR_A_FORM_LIST(DECODE_XX2_SCALAR_A_INSTRUCTIONS)
1539 #undef DECODE_XX2_SCALAR_A_INSTRUCTIONS
1540   }
1541   Unknown(instr);  // not used by V8
1542 }
1543 
1544 #undef VERIFY
1545 
1546 // Disassemble the instruction at *instr_ptr into the output buffer.
InstructionDecode(byte* instr_ptr)1547 int Decoder::InstructionDecode(byte* instr_ptr) {
1548   Instruction* instr = Instruction::At(instr_ptr);
1549 
1550   uint32_t opcode = instr->OpcodeValue() << 26;
1551   // Print raw instruction bytes.
1552   if (opcode != EXTP) {
1553     out_buffer_pos_ += base::SNPrintF(out_buffer_ + out_buffer_pos_,
1554                                       "%08x       ", instr->InstructionBits());
1555   } else {
1556     // Prefixed instructions have a 4-byte prefix and a 4-byte suffix. Print
1557     // both on the same line.
1558     Instruction* next_instr =
1559         bit_cast<Instruction*>(bit_cast<intptr_t>(instr) + kInstrSize);
1560     out_buffer_pos_ +=
1561         base::SNPrintF(out_buffer_ + out_buffer_pos_, "%08x|%08x ",
1562                        instr->InstructionBits(), next_instr->InstructionBits());
1563   }
1564 
1565   if (ABI_USES_FUNCTION_DESCRIPTORS && instr->InstructionBits() == 0) {
1566     // The first field will be identified as a jump table entry.  We
1567     // emit the rest of the structure as zero, so just skip past them.
1568     Format(instr, "constant");
1569     return kInstrSize;
1570   }
1571 
1572   switch (opcode) {
1573     case TWI: {
1574       PrintSoftwareInterrupt(instr->SvcValue());
1575       break;
1576     }
1577     case MULLI: {
1578       UnknownFormat(instr, "mulli");
1579       break;
1580     }
1581     case SUBFIC: {
1582       Format(instr, "subfic  'rt, 'ra, 'int16");
1583       break;
1584     }
1585     case CMPLI: {
1586 #if V8_TARGET_ARCH_PPC64
1587       if (instr->Bit(21)) {
1588 #endif
1589         Format(instr, "cmpli   'ra, 'uint16");
1590 #if V8_TARGET_ARCH_PPC64
1591       } else {
1592         Format(instr, "cmplwi  'ra, 'uint16");
1593       }
1594 #endif
1595       break;
1596     }
1597     case CMPI: {
1598 #if V8_TARGET_ARCH_PPC64
1599       if (instr->Bit(21)) {
1600 #endif
1601         Format(instr, "cmpi    'ra, 'int16");
1602 #if V8_TARGET_ARCH_PPC64
1603       } else {
1604         Format(instr, "cmpwi   'ra, 'int16");
1605       }
1606 #endif
1607       break;
1608     }
1609     case ADDIC: {
1610       Format(instr, "addic   'rt, 'ra, 'int16");
1611       break;
1612     }
1613     case ADDICx: {
1614       UnknownFormat(instr, "addicx");
1615       break;
1616     }
1617     case ADDI: {
1618       if (instr->RAValue() == 0) {
1619         // this is load immediate
1620         Format(instr, "li      'rt, 'int16");
1621       } else {
1622         Format(instr, "addi    'rt, 'ra, 'int16");
1623       }
1624       break;
1625     }
1626     case ADDIS: {
1627       if (instr->RAValue() == 0) {
1628         Format(instr, "lis     'rt, 'int16");
1629       } else {
1630         Format(instr, "addis   'rt, 'ra, 'int16");
1631       }
1632       break;
1633     }
1634     case BCX: {
1635       int bo = instr->Bits(25, 21) << 21;
1636       int bi = instr->Bits(20, 16);
1637       CRBit cond = static_cast<CRBit>(bi & (CRWIDTH - 1));
1638       switch (bo) {
1639         case BT: {  // Branch if condition true
1640           switch (cond) {
1641             case CR_EQ:
1642               Format(instr, "beq'l'a'cr 'target16");
1643               break;
1644             case CR_GT:
1645               Format(instr, "bgt'l'a'cr 'target16");
1646               break;
1647             case CR_LT:
1648               Format(instr, "blt'l'a'cr 'target16");
1649               break;
1650             case CR_SO:
1651               Format(instr, "bso'l'a'cr 'target16");
1652               break;
1653           }
1654           break;
1655         }
1656         case BF: {  // Branch if condition false
1657           switch (cond) {
1658             case CR_EQ:
1659               Format(instr, "bne'l'a'cr 'target16");
1660               break;
1661             case CR_GT:
1662               Format(instr, "ble'l'a'cr 'target16");
1663               break;
1664             case CR_LT:
1665               Format(instr, "bge'l'a'cr 'target16");
1666               break;
1667             case CR_SO:
1668               Format(instr, "bnso'l'a'cr 'target16");
1669               break;
1670           }
1671           break;
1672         }
1673         case DCBNZ: {  // Decrement CTR; branch if CTR != 0
1674           Format(instr, "bdnz'l'a 'target16");
1675           break;
1676         }
1677         default:
1678           Format(instr, "bc'l'a'cr 'target16");
1679           break;
1680       }
1681       break;
1682     }
1683     case SC: {
1684       UnknownFormat(instr, "sc");
1685       break;
1686     }
1687     case BX: {
1688       Format(instr, "b'l'a 'target26");
1689       break;
1690     }
1691     case EXTP: {
1692       DecodeExtP(instr);
1693       break;
1694     }
1695     case EXT0: {
1696       DecodeExt0(instr);
1697       break;
1698     }
1699     case EXT1: {
1700       DecodeExt1(instr);
1701       break;
1702     }
1703     case RLWIMIX: {
1704       Format(instr, "rlwimi'. 'ra, 'rs, 'sh, 'me, 'mb");
1705       break;
1706     }
1707     case RLWINMX: {
1708       Format(instr, "rlwinm'. 'ra, 'rs, 'sh, 'me, 'mb");
1709       break;
1710     }
1711     case RLWNMX: {
1712       Format(instr, "rlwnm'.  'ra, 'rs, 'rb, 'me, 'mb");
1713       break;
1714     }
1715     case ORI: {
1716       Format(instr, "ori     'ra, 'rs, 'uint16");
1717       break;
1718     }
1719     case ORIS: {
1720       Format(instr, "oris    'ra, 'rs, 'uint16");
1721       break;
1722     }
1723     case XORI: {
1724       Format(instr, "xori    'ra, 'rs, 'uint16");
1725       break;
1726     }
1727     case XORIS: {
1728       Format(instr, "xoris   'ra, 'rs, 'uint16");
1729       break;
1730     }
1731     case ANDIx: {
1732       Format(instr, "andi.   'ra, 'rs, 'uint16");
1733       break;
1734     }
1735     case ANDISx: {
1736       Format(instr, "andis.  'ra, 'rs, 'uint16");
1737       break;
1738     }
1739     case EXT2: {
1740       DecodeExt2(instr);
1741       break;
1742     }
1743     case LWZ: {
1744       Format(instr, "lwz     'rt, 'int16('ra)");
1745       break;
1746     }
1747     case LWZU: {
1748       Format(instr, "lwzu    'rt, 'int16('ra)");
1749       break;
1750     }
1751     case LBZ: {
1752       Format(instr, "lbz     'rt, 'int16('ra)");
1753       break;
1754     }
1755     case LBZU: {
1756       Format(instr, "lbzu    'rt, 'int16('ra)");
1757       break;
1758     }
1759     case STW: {
1760       Format(instr, "stw     'rs, 'int16('ra)");
1761       break;
1762     }
1763     case STWU: {
1764       Format(instr, "stwu    'rs, 'int16('ra)");
1765       break;
1766     }
1767     case STB: {
1768       Format(instr, "stb     'rs, 'int16('ra)");
1769       break;
1770     }
1771     case STBU: {
1772       Format(instr, "stbu    'rs, 'int16('ra)");
1773       break;
1774     }
1775     case LHZ: {
1776       Format(instr, "lhz     'rt, 'int16('ra)");
1777       break;
1778     }
1779     case LHZU: {
1780       Format(instr, "lhzu    'rt, 'int16('ra)");
1781       break;
1782     }
1783     case LHA: {
1784       Format(instr, "lha     'rt, 'int16('ra)");
1785       break;
1786     }
1787     case LHAU: {
1788       Format(instr, "lhau    'rt, 'int16('ra)");
1789       break;
1790     }
1791     case STH: {
1792       Format(instr, "sth 'rs, 'int16('ra)");
1793       break;
1794     }
1795     case STHU: {
1796       Format(instr, "sthu 'rs, 'int16('ra)");
1797       break;
1798     }
1799     case LMW: {
1800       UnknownFormat(instr, "lmw");
1801       break;
1802     }
1803     case STMW: {
1804       UnknownFormat(instr, "stmw");
1805       break;
1806     }
1807     case LFS: {
1808       Format(instr, "lfs     'Dt, 'int16('ra)");
1809       break;
1810     }
1811     case LFSU: {
1812       Format(instr, "lfsu    'Dt, 'int16('ra)");
1813       break;
1814     }
1815     case LFD: {
1816       Format(instr, "lfd     'Dt, 'int16('ra)");
1817       break;
1818     }
1819     case LFDU: {
1820       Format(instr, "lfdu    'Dt, 'int16('ra)");
1821       break;
1822     }
1823     case STFS: {
1824       Format(instr, "stfs    'Dt, 'int16('ra)");
1825       break;
1826     }
1827     case STFSU: {
1828       Format(instr, "stfsu   'Dt, 'int16('ra)");
1829       break;
1830     }
1831     case STFD: {
1832       Format(instr, "stfd    'Dt, 'int16('ra)");
1833       break;
1834     }
1835     case STFDU: {
1836       Format(instr, "stfdu   'Dt, 'int16('ra)");
1837       break;
1838     }
1839     case EXT3: {
1840       DecodeExt3(instr);
1841       break;
1842     }
1843     case EXT4: {
1844       DecodeExt4(instr);
1845       break;
1846     }
1847     case EXT5: {
1848       DecodeExt5(instr);
1849       break;
1850     }
1851     case EXT6: {
1852       DecodeExt6(instr);
1853       break;
1854     }
1855 #if V8_TARGET_ARCH_PPC64
1856     case LD: {
1857       switch (instr->Bits(1, 0)) {
1858         case 0:
1859           Format(instr, "ld      'rt, 'd('ra)");
1860           break;
1861         case 1:
1862           Format(instr, "ldu     'rt, 'd('ra)");
1863           break;
1864         case 2:
1865           Format(instr, "lwa     'rt, 'd('ra)");
1866           break;
1867       }
1868       break;
1869     }
1870     case STD: {  // could be STD or STDU
1871       if (instr->Bit(0) == 0) {
1872         Format(instr, "std     'rs, 'd('ra)");
1873       } else {
1874         Format(instr, "stdu    'rs, 'd('ra)");
1875       }
1876       break;
1877     }
1878 #endif
1879     default: {
1880       Unknown(instr);
1881       break;
1882     }
1883   }
1884 
1885   if (IsPrefixed()) {
1886     // The next instruction (suffix) should have already been decoded as part of
1887     // prefix decoding.
1888     ResetPrefix();
1889     return 2 * kInstrSize;
1890   }
1891 
1892   return kInstrSize;
1893 }
1894 }  // namespace internal
1895 }  // namespace v8
1896 
1897 //------------------------------------------------------------------------------
1898 
1899 namespace disasm {
1900 
NameOfAddress(byte* addr) const1901 const char* NameConverter::NameOfAddress(byte* addr) const {
1902   v8::base::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr));
1903   return tmp_buffer_.begin();
1904 }
1905 
NameOfConstant(byte* addr) const1906 const char* NameConverter::NameOfConstant(byte* addr) const {
1907   return NameOfAddress(addr);
1908 }
1909 
NameOfCPURegister(int reg) const1910 const char* NameConverter::NameOfCPURegister(int reg) const {
1911   return RegisterName(i::Register::from_code(reg));
1912 }
1913 
NameOfByteCPURegister(int reg) const1914 const char* NameConverter::NameOfByteCPURegister(int reg) const {
1915   UNREACHABLE();  // PPC does not have the concept of a byte register
1916 }
1917 
NameOfXMMRegister(int reg) const1918 const char* NameConverter::NameOfXMMRegister(int reg) const {
1919   UNREACHABLE();  // PPC does not have any XMM registers
1920 }
1921 
NameInCode(byte* addr) const1922 const char* NameConverter::NameInCode(byte* addr) const {
1923   // The default name converter is called for unknown code. So we will not try
1924   // to access any memory.
1925   return "";
1926 }
1927 
1928 //------------------------------------------------------------------------------
1929 
InstructionDecode(v8::base::Vector<char> buffer, byte* instruction)1930 int Disassembler::InstructionDecode(v8::base::Vector<char> buffer,
1931                                     byte* instruction) {
1932   v8::internal::Decoder d(converter_, buffer);
1933   return d.InstructionDecode(instruction);
1934 }
1935 
1936 // The PPC assembler does not currently use constant pools.
ConstantPoolSizeAt(byte* instruction)1937 int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; }
1938 
Disassemble(FILE* f, byte* begin, byte* end, UnimplementedOpcodeAction unimplemented_action)1939 void Disassembler::Disassemble(FILE* f, byte* begin, byte* end,
1940                                UnimplementedOpcodeAction unimplemented_action) {
1941   NameConverter converter;
1942   Disassembler d(converter, unimplemented_action);
1943   for (byte* pc = begin; pc < end;) {
1944     v8::base::EmbeddedVector<char, 128> buffer;
1945     buffer[0] = '\0';
1946     byte* prev_pc = pc;
1947     pc += d.InstructionDecode(buffer, pc);
1948     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
1949                          *reinterpret_cast<int32_t*>(prev_pc), buffer.begin());
1950   }
1951 }
1952 
1953 #undef STRING_STARTS_WITH
1954 
1955 }  // namespace disasm
1956 
1957 #endif  // V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
1958