1 // Copyright 2006-2009 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 // CPU specific code for arm independent of OS goes here.
6 #ifdef __arm__
7 #ifdef __QNXNTO__
8 #include <sys/mman.h> // for cache flushing.
9 #undef MAP_TYPE
10 #elif V8_OS_FREEBSD
11 #include <machine/sysarch.h> // for cache flushing
12 #include <sys/types.h>
13 #elif V8_OS_STARBOARD
14 #define __ARM_NR_cacheflush 0x0f0002
15 #else
16 #include <sys/syscall.h> // for cache flushing.
17 #endif
18 #endif
19
20 #if V8_TARGET_ARCH_ARM
21
22 #include "src/codegen/cpu-features.h"
23
24 namespace v8 {
25 namespace internal {
26
27 // The inlining of this seems to trigger an LTO bug that clobbers a register,
28 // see https://crbug.com/952759 and https://bugs.llvm.org/show_bug.cgi?id=41575.
FlushICache(void* start, size_t size)29 V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
30 #if !defined(USE_SIMULATOR)
31 #if V8_OS_QNX
32 msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
33 #elif V8_OS_FREEBSD
34 struct arm_sync_icache_args args = {
35 .addr = reinterpret_cast<uintptr_t>(start), .len = size};
36 sysarch(ARM_SYNC_ICACHE, reinterpret_cast<void*>(&args));
37 #else
38 register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start);
39 register uint32_t end asm("r1") = beg + size;
40 register uint32_t flg asm("r2") = 0;
41
42 asm volatile(
43 // This assembly works for both ARM and Thumb targets.
44
45 // Preserve r7; it is callee-saved, and GCC uses it as a frame pointer for
46 // Thumb targets.
47 " push {r7}\n"
48 // r0 = beg
49 // r1 = end
50 // r2 = flags (0)
51 " ldr r7, =%c[scno]\n" // r7 = syscall number
52 " svc 0\n"
53
54 " pop {r7}\n"
55 :
56 : "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
57 : "memory");
58 #endif
59 #endif // !USE_SIMULATOR
60 }
61
62 } // namespace internal
63 } // namespace v8
64
65 #endif // V8_TARGET_ARCH_ARM
66