1 /* 2 * Copyright © 2022 Imagination Technologies Ltd. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef PVR_JOB_CONTEXT_H 25 #define PVR_JOB_CONTEXT_H 26 27 #include "pvr_private.h" 28 #include "pvr_types.h" 29 #include "pvr_winsys.h" 30 31 /* Support PDS code/data loading/storing to the 'B' shared register state 32 * buffers. 33 */ 34 #define ROGUE_NUM_SHADER_STATE_BUFFERS 2U 35 36 /* TODO: Add reset framework support. */ 37 struct pvr_reset_cmd { 38 }; 39 40 struct pvr_compute_ctx; 41 42 struct rogue_sr_programs { 43 struct pvr_bo *store_load_state_bo; 44 45 struct { 46 uint8_t unified_size; 47 48 struct pvr_bo *store_program_bo; 49 50 struct pvr_bo *load_program_bo; 51 } usc; 52 53 struct { 54 struct pvr_pds_upload store_program; 55 struct pvr_pds_upload load_program; 56 } pds; 57 }; 58 59 struct pvr_render_ctx { 60 struct pvr_device *device; 61 62 struct pvr_winsys_render_ctx *ws_ctx; 63 64 /* Buffer to hold the VDM call stack */ 65 struct pvr_bo *vdm_callstack_bo; 66 67 struct pvr_render_ctx_switch { 68 /* Buffer to hold the VDM context resume control stream. */ 69 struct pvr_bo *vdm_state_bo; 70 71 struct pvr_bo *geom_state_bo; 72 73 struct pvr_render_ctx_programs { 74 /* Context switch persistent state programs. */ 75 struct rogue_pt_programs { 76 /* Buffer used to hold the persistent state. */ 77 struct pvr_bo *store_resume_state_bo; 78 79 /* PDS program to store out the persistent state in 80 * 'store_resume_state_bo'. 81 */ 82 struct pvr_pds_upload pds_store_program; 83 84 /* PDS program to load in the persistent state in 85 * 'store_resume_state_bo'. 86 */ 87 struct pvr_pds_upload pds_resume_program; 88 } pt; 89 90 /* Context switch shared register programs. */ 91 struct rogue_sr_programs sr; 92 93 } programs[ROGUE_NUM_SHADER_STATE_BUFFERS]; 94 } ctx_switch; 95 96 /* Reset framework. */ 97 struct pvr_reset_cmd reset_cmd; 98 }; 99 100 /****************************************************************************** 101 Compute context 102 ******************************************************************************/ 103 104 struct pvr_compute_ctx { 105 struct pvr_device *device; 106 107 struct pvr_winsys_compute_ctx *ws_ctx; 108 109 struct pvr_compute_ctx_switch { 110 struct pvr_bo *compute_state_bo; 111 112 struct rogue_sr_programs sr[ROGUE_NUM_SHADER_STATE_BUFFERS]; 113 114 struct pvr_pds_upload sr_fence_terminate_program; 115 } ctx_switch; 116 117 /* Reset framework. */ 118 struct pvr_reset_cmd reset_cmd; 119 }; 120 121 /****************************************************************************** 122 Transfer context 123 ******************************************************************************/ 124 125 /* TODO: Can we move these to pds code headers? */ 126 /* Maximum number of DMAs in the PDS TexState/Uniform program. */ 127 #define PVR_TRANSFER_MAX_UNIFORM_DMA 1U 128 #define PVR_TRANSFER_MAX_TEXSTATE_DMA 2U 129 130 #if (PVR_TRANSFER_MAX_TEXSTATE_DMA >= PVR_PDS_MAX_NUM_DMA_KICKS) || \ 131 (PVR_TRANSFER_MAX_UNIFORM_DMA >= PVR_PDS_MAX_NUM_DMA_KICKS) 132 # error \ 133 "Transfer queue can not support more DMA kicks than supported by PDS codegen." 134 #endif 135 136 struct pvr_transfer_ctx { 137 struct pvr_device *device; 138 139 /* Reset framework. */ 140 struct pvr_reset_cmd reset_cmd; 141 142 struct pvr_winsys_transfer_ctx *ws_ctx; 143 144 /* Multiple on-chip render targets (MRT). */ 145 pvr_dev_addr_t transfer_mrts[PVR_TRANSFER_MAX_RENDER_TARGETS]; 146 struct pvr_bo *usc_eot_bo; 147 148 struct pvr_pds_upload pds_unitex_code[PVR_TRANSFER_MAX_TEXSTATE_DMA] 149 [PVR_TRANSFER_MAX_UNIFORM_DMA]; 150 }; 151 152 /****************************************************************************** 153 Function prototypes 154 ******************************************************************************/ 155 156 VkResult pvr_render_ctx_create(struct pvr_device *device, 157 enum pvr_winsys_ctx_priority priority, 158 struct pvr_render_ctx **const ctx_out); 159 void pvr_render_ctx_destroy(struct pvr_render_ctx *ctx); 160 161 VkResult pvr_compute_ctx_create(struct pvr_device *const device, 162 enum pvr_winsys_ctx_priority priority, 163 struct pvr_compute_ctx **const ctx_out); 164 void pvr_compute_ctx_destroy(struct pvr_compute_ctx *ctx); 165 166 VkResult pvr_transfer_ctx_create(struct pvr_device *const device, 167 enum pvr_winsys_ctx_priority priority, 168 struct pvr_transfer_ctx **const ctx_out); 169 void pvr_transfer_ctx_destroy(struct pvr_transfer_ctx *const ctx); 170 171 #endif /* PVR_JOB_CONTEXT_H */ 172