1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8 9<!-- these might be same as a5xx --> 10<enum name="a6xx_tile_mode"> 11 <value name="TILE6_LINEAR" value="0"/> 12 <value name="TILE6_2" value="2"/> 13 <value name="TILE6_3" value="3"/> 14</enum> 15 16<enum name="a6xx_format"> 17 <value value="0x02" name="FMT6_A8_UNORM"/> 18 <value value="0x03" name="FMT6_8_UNORM"/> 19 <value value="0x04" name="FMT6_8_SNORM"/> 20 <value value="0x05" name="FMT6_8_UINT"/> 21 <value value="0x06" name="FMT6_8_SINT"/> 22 23 <value value="0x08" name="FMT6_4_4_4_4_UNORM"/> 24 <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/> 25 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> 26 <value value="0x0e" name="FMT6_5_6_5_UNORM"/> 27 28 <value value="0x0f" name="FMT6_8_8_UNORM"/> 29 <value value="0x10" name="FMT6_8_8_SNORM"/> 30 <value value="0x11" name="FMT6_8_8_UINT"/> 31 <value value="0x12" name="FMT6_8_8_SINT"/> 32 <value value="0x13" name="FMT6_L8_A8_UNORM"/> 33 34 <value value="0x15" name="FMT6_16_UNORM"/> 35 <value value="0x16" name="FMT6_16_SNORM"/> 36 <value value="0x17" name="FMT6_16_FLOAT"/> 37 <value value="0x18" name="FMT6_16_UINT"/> 38 <value value="0x19" name="FMT6_16_SINT"/> 39 40 <value value="0x21" name="FMT6_8_8_8_UNORM"/> 41 <value value="0x22" name="FMT6_8_8_8_SNORM"/> 42 <value value="0x23" name="FMT6_8_8_8_UINT"/> 43 <value value="0x24" name="FMT6_8_8_8_SINT"/> 44 45 <value value="0x30" name="FMT6_8_8_8_8_UNORM"/> 46 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> 47 <value value="0x32" name="FMT6_8_8_8_8_SNORM"/> 48 <value value="0x33" name="FMT6_8_8_8_8_UINT"/> 49 <value value="0x34" name="FMT6_8_8_8_8_SINT"/> 50 51 <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/> 52 53 <value value="0x36" name="FMT6_10_10_10_2_UNORM"/> 54 <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/> 55 <value value="0x39" name="FMT6_10_10_10_2_SNORM"/> 56 <value value="0x3a" name="FMT6_10_10_10_2_UINT"/> 57 <value value="0x3b" name="FMT6_10_10_10_2_SINT"/> 58 59 <value value="0x42" name="FMT6_11_11_10_FLOAT"/> 60 61 <value value="0x43" name="FMT6_16_16_UNORM"/> 62 <value value="0x44" name="FMT6_16_16_SNORM"/> 63 <value value="0x45" name="FMT6_16_16_FLOAT"/> 64 <value value="0x46" name="FMT6_16_16_UINT"/> 65 <value value="0x47" name="FMT6_16_16_SINT"/> 66 67 <value value="0x48" name="FMT6_32_UNORM"/> 68 <value value="0x49" name="FMT6_32_SNORM"/> 69 <value value="0x4a" name="FMT6_32_FLOAT"/> 70 <value value="0x4b" name="FMT6_32_UINT"/> 71 <value value="0x4c" name="FMT6_32_SINT"/> 72 <value value="0x4d" name="FMT6_32_FIXED"/> 73 74 <value value="0x58" name="FMT6_16_16_16_UNORM"/> 75 <value value="0x59" name="FMT6_16_16_16_SNORM"/> 76 <value value="0x5a" name="FMT6_16_16_16_FLOAT"/> 77 <value value="0x5b" name="FMT6_16_16_16_UINT"/> 78 <value value="0x5c" name="FMT6_16_16_16_SINT"/> 79 80 <value value="0x60" name="FMT6_16_16_16_16_UNORM"/> 81 <value value="0x61" name="FMT6_16_16_16_16_SNORM"/> 82 <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/> 83 <value value="0x63" name="FMT6_16_16_16_16_UINT"/> 84 <value value="0x64" name="FMT6_16_16_16_16_SINT"/> 85 86 <value value="0x65" name="FMT6_32_32_UNORM"/> 87 <value value="0x66" name="FMT6_32_32_SNORM"/> 88 <value value="0x67" name="FMT6_32_32_FLOAT"/> 89 <value value="0x68" name="FMT6_32_32_UINT"/> 90 <value value="0x69" name="FMT6_32_32_SINT"/> 91 <value value="0x6a" name="FMT6_32_32_FIXED"/> 92 93 <value value="0x70" name="FMT6_32_32_32_UNORM"/> 94 <value value="0x71" name="FMT6_32_32_32_SNORM"/> 95 <value value="0x72" name="FMT6_32_32_32_UINT"/> 96 <value value="0x73" name="FMT6_32_32_32_SINT"/> 97 <value value="0x74" name="FMT6_32_32_32_FLOAT"/> 98 <value value="0x75" name="FMT6_32_32_32_FIXED"/> 99 100 <value value="0x80" name="FMT6_32_32_32_32_UNORM"/> 101 <value value="0x81" name="FMT6_32_32_32_32_SNORM"/> 102 <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/> 103 <value value="0x83" name="FMT6_32_32_32_32_UINT"/> 104 <value value="0x84" name="FMT6_32_32_32_32_SINT"/> 105 <value value="0x85" name="FMT6_32_32_32_32_FIXED"/> 106 107 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY --> 108 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV --> 109 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 --> 110 <value value="0x8f" name="FMT6_NV21"/> 111 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 --> 112 113 <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> 114 115 <!-- Note: tiling/UBWC for these may be different from equivalent formats 116 For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM 117 --> 118 <value value="0x94" name="FMT6_NV12_Y"/> 119 <value value="0x95" name="FMT6_NV12_UV"/> 120 <value value="0x96" name="FMT6_NV12_VU"/> 121 <value value="0x97" name="FMT6_NV12_4R"/> 122 <value value="0x98" name="FMT6_NV12_4R_Y"/> 123 <value value="0x99" name="FMT6_NV12_4R_UV"/> 124 <value value="0x9a" name="FMT6_P010"/> 125 <value value="0x9b" name="FMT6_P010_Y"/> 126 <value value="0x9c" name="FMT6_P010_UV"/> 127 <value value="0x9d" name="FMT6_TP10"/> 128 <value value="0x9e" name="FMT6_TP10_Y"/> 129 <value value="0x9f" name="FMT6_TP10_UV"/> 130 131 <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/> 132 133 <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/> 134 <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/> 135 <value value="0xad" name="FMT6_ETC2_R11_UNORM"/> 136 <value value="0xae" name="FMT6_ETC2_R11_SNORM"/> 137 <value value="0xaf" name="FMT6_ETC1"/> 138 <value value="0xb0" name="FMT6_ETC2_RGB8"/> 139 <value value="0xb1" name="FMT6_ETC2_RGBA8"/> 140 <value value="0xb2" name="FMT6_ETC2_RGB8A1"/> 141 <value value="0xb3" name="FMT6_DXT1"/> 142 <value value="0xb4" name="FMT6_DXT3"/> 143 <value value="0xb5" name="FMT6_DXT5"/> 144 <value value="0xb7" name="FMT6_RGTC1_UNORM"/> 145 <value value="0xb8" name="FMT6_RGTC1_SNORM"/> 146 <value value="0xbb" name="FMT6_RGTC2_UNORM"/> 147 <value value="0xbc" name="FMT6_RGTC2_SNORM"/> 148 <value value="0xbe" name="FMT6_BPTC_UFLOAT"/> 149 <value value="0xbf" name="FMT6_BPTC_FLOAT"/> 150 <value value="0xc0" name="FMT6_BPTC"/> 151 <value value="0xc1" name="FMT6_ASTC_4x4"/> 152 <value value="0xc2" name="FMT6_ASTC_5x4"/> 153 <value value="0xc3" name="FMT6_ASTC_5x5"/> 154 <value value="0xc4" name="FMT6_ASTC_6x5"/> 155 <value value="0xc5" name="FMT6_ASTC_6x6"/> 156 <value value="0xc6" name="FMT6_ASTC_8x5"/> 157 <value value="0xc7" name="FMT6_ASTC_8x6"/> 158 <value value="0xc8" name="FMT6_ASTC_8x8"/> 159 <value value="0xc9" name="FMT6_ASTC_10x5"/> 160 <value value="0xca" name="FMT6_ASTC_10x6"/> 161 <value value="0xcb" name="FMT6_ASTC_10x8"/> 162 <value value="0xcc" name="FMT6_ASTC_10x10"/> 163 <value value="0xcd" name="FMT6_ASTC_12x10"/> 164 <value value="0xce" name="FMT6_ASTC_12x12"/> 165 166 <!-- for sampling stencil (integer, 2nd channel), not available on a630 --> 167 <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/> 168 169 <!-- Not a hw enum, used internally in driver --> 170 <value value="0xff" name="FMT6_NONE"/> 171 172</enum> 173 174<!-- probably same as a5xx --> 175<enum name="a6xx_polygon_mode"> 176 <value name="POLYMODE6_POINTS" value="1"/> 177 <value name="POLYMODE6_LINES" value="2"/> 178 <value name="POLYMODE6_TRIANGLES" value="3"/> 179</enum> 180 181<enum name="a6xx_depth_format"> 182 <value name="DEPTH6_NONE" value="0"/> 183 <value name="DEPTH6_16" value="1"/> 184 <value name="DEPTH6_24_8" value="2"/> 185 <value name="DEPTH6_32" value="4"/> 186</enum> 187 188<bitset name="a6x_cp_protect" inline="yes"> 189 <bitfield name="BASE_ADDR" low="0" high="17"/> 190 <bitfield name="MASK_LEN" low="18" high="30"/> 191 <bitfield name="READ" pos="31" type="boolean"/> 192</bitset> 193 194<enum name="a6xx_shader_id"> 195 <value value="0x9" name="A6XX_TP0_TMO_DATA"/> 196 <value value="0xa" name="A6XX_TP0_SMO_DATA"/> 197 <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> 198 <value value="0x19" name="A6XX_TP1_TMO_DATA"/> 199 <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> 200 <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> 201 <value value="0x29" name="A6XX_SP_INST_DATA"/> 202 <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> 203 <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> 204 <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> 205 <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> 206 <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> 207 <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> 208 <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> 209 <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> 210 <value value="0x32" name="A6XX_SP_UAV_DATA"/> 211 <value value="0x33" name="A6XX_SP_INST_TAG"/> 212 <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> 213 <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> 214 <value value="0x36" name="A6XX_SP_SMO_TAG"/> 215 <value value="0x37" name="A6XX_SP_STATE_DATA"/> 216 <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> 217 <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> 218 <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 219 <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 220 <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 221 <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 222 <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> 223 <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> 224 <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> 225 <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> 226 <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> 227 <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> 228 <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> 229 <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> 230 <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 231 <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 232 <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> 233 <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> 234 <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> 235 <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> 236 <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> 237 <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> 238</enum> 239 240<enum name="a6xx_debugbus_id"> 241 <value value="0x1" name="A6XX_DBGBUS_CP"/> 242 <value value="0x2" name="A6XX_DBGBUS_RBBM"/> 243 <value value="0x3" name="A6XX_DBGBUS_VBIF"/> 244 <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> 245 <value value="0x5" name="A6XX_DBGBUS_UCHE"/> 246 <value value="0x6" name="A6XX_DBGBUS_DPM"/> 247 <value value="0x7" name="A6XX_DBGBUS_TESS"/> 248 <value value="0x8" name="A6XX_DBGBUS_PC"/> 249 <value value="0x9" name="A6XX_DBGBUS_VFDP"/> 250 <value value="0xa" name="A6XX_DBGBUS_VPC"/> 251 <value value="0xb" name="A6XX_DBGBUS_TSE"/> 252 <value value="0xc" name="A6XX_DBGBUS_RAS"/> 253 <value value="0xd" name="A6XX_DBGBUS_VSC"/> 254 <value value="0xe" name="A6XX_DBGBUS_COM"/> 255 <value value="0x10" name="A6XX_DBGBUS_LRZ"/> 256 <value value="0x11" name="A6XX_DBGBUS_A2D"/> 257 <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> 258 <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> 259 <value value="0x14" name="A6XX_DBGBUS_RBP"/> 260 <value value="0x15" name="A6XX_DBGBUS_DCS"/> 261 <value value="0x16" name="A6XX_DBGBUS_DBGC"/> 262 <value value="0x17" name="A6XX_DBGBUS_CX"/> 263 <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> 264 <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> 265 <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> 266 <value value="0x1d" name="A6XX_DBGBUS_GPC"/> 267 <value value="0x1e" name="A6XX_DBGBUS_LARC"/> 268 <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> 269 <value value="0x20" name="A6XX_DBGBUS_RB_0"/> 270 <value value="0x21" name="A6XX_DBGBUS_RB_1"/> 271 <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> 272 <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> 273 <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> 274 <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> 275 <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> 276 <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> 277 <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> 278 <value value="0x40" name="A6XX_DBGBUS_SP_0"/> 279 <value value="0x41" name="A6XX_DBGBUS_SP_1"/> 280 <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> 281 <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> 282 <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> 283 <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> 284</enum> 285 286<enum name="a6xx_cp_perfcounter_select"> 287 <value value="0" name="PERF_CP_ALWAYS_COUNT"/> 288 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> 289 <value value="2" name="PERF_CP_BUSY_CYCLES"/> 290 <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> 291 <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> 292 <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 293 <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 294 <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 295 <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> 296 <value value="9" name="PERF_CP_MODE_SWITCH"/> 297 <value value="10" name="PERF_CP_ZPASS_DONE"/> 298 <value value="11" name="PERF_CP_CONTEXT_DONE"/> 299 <value value="12" name="PERF_CP_CACHE_FLUSH"/> 300 <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> 301 <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> 302 <value value="15" name="PERF_CP_SQE_IDLE"/> 303 <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> 304 <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> 305 <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> 306 <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> 307 <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> 308 <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> 309 <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> 310 <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> 311 <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> 312 <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> 313 <value value="26" name="PERF_CP_SQE_T4_EXEC"/> 314 <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> 315 <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> 316 <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> 317 <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 318 <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> 319 <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> 320 <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> 321 <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 322 <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 323 <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> 324 <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 325 <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 326 <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> 327 <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> 328 <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> 329 <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> 330 <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> 331 <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> 332 <value value="45" name="PERF_CP_PM4_DATA"/> 333 <value value="46" name="PERF_CP_PM4_HEADERS"/> 334 <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> 335 <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> 336 <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> 337</enum> 338 339<enum name="a6xx_rbbm_perfcounter_select"> 340 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> 341 <value value="1" name="PERF_RBBM_ALWAYS_ON"/> 342 <value value="2" name="PERF_RBBM_TSE_BUSY"/> 343 <value value="3" name="PERF_RBBM_RAS_BUSY"/> 344 <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> 345 <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> 346 <value value="6" name="PERF_RBBM_STATUS_MASKED"/> 347 <value value="7" name="PERF_RBBM_COM_BUSY"/> 348 <value value="8" name="PERF_RBBM_DCOM_BUSY"/> 349 <value value="9" name="PERF_RBBM_VBIF_BUSY"/> 350 <value value="10" name="PERF_RBBM_VSC_BUSY"/> 351 <value value="11" name="PERF_RBBM_TESS_BUSY"/> 352 <value value="12" name="PERF_RBBM_UCHE_BUSY"/> 353 <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> 354</enum> 355 356<enum name="a6xx_pc_perfcounter_select"> 357 <value value="0" name="PERF_PC_BUSY_CYCLES"/> 358 <value value="1" name="PERF_PC_WORKING_CYCLES"/> 359 <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> 360 <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> 361 <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> 362 <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> 363 <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> 364 <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> 365 <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> 366 <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> 367 <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 368 <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 369 <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 370 <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> 371 <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> 372 <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> 373 <value value="16" name="PERF_PC_INSTANCES"/> 374 <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> 375 <value value="18" name="PERF_PC_DEAD_PRIM"/> 376 <value value="19" name="PERF_PC_LIVE_PRIM"/> 377 <value value="20" name="PERF_PC_VERTEX_HITS"/> 378 <value value="21" name="PERF_PC_IA_VERTICES"/> 379 <value value="22" name="PERF_PC_IA_PRIMITIVES"/> 380 <value value="23" name="PERF_PC_GS_PRIMITIVES"/> 381 <value value="24" name="PERF_PC_HS_INVOCATIONS"/> 382 <value value="25" name="PERF_PC_DS_INVOCATIONS"/> 383 <value value="26" name="PERF_PC_VS_INVOCATIONS"/> 384 <value value="27" name="PERF_PC_GS_INVOCATIONS"/> 385 <value value="28" name="PERF_PC_DS_PRIMITIVES"/> 386 <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> 387 <value value="30" name="PERF_PC_3D_DRAWCALLS"/> 388 <value value="31" name="PERF_PC_2D_DRAWCALLS"/> 389 <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 390 <value value="33" name="PERF_TESS_BUSY_CYCLES"/> 391 <value value="34" name="PERF_TESS_WORKING_CYCLES"/> 392 <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> 393 <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> 394 <value value="37" name="PERF_PC_TSE_TRANSACTION"/> 395 <value value="38" name="PERF_PC_TSE_VERTEX"/> 396 <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> 397 <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> 398 <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> 399</enum> 400 401<enum name="a6xx_vfd_perfcounter_select"> 402 <value value="0" name="PERF_VFD_BUSY_CYCLES"/> 403 <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> 404 <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 405 <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> 406 <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> 407 <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> 408 <value value="6" name="PERF_VFD_RBUFFER_FULL"/> 409 <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> 410 <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 411 <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> 412 <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> 413 <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> 414 <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> 415 <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> 416 <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> 417 <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> 418 <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> 419 <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> 420 <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> 421 <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 422 <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 423 <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> 424 <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> 425</enum> 426 427<enum name="a6xx_hlsq_perfcounter_select"> 428 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> 429 <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> 430 <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 431 <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 432 <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 433 <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> 434 <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> 435 <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> 436 <value value="8" name="PERF_HLSQ_QUADS"/> 437 <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> 438 <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> 439 <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 440 <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 441 <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 442 <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 443 <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 444 <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 445 <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 446 <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> 447 <value value="19" name="PERF_HLSQ_PIXELS"/> 448 <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 449</enum> 450 451<enum name="a6xx_vpc_perfcounter_select"> 452 <value value="0" name="PERF_VPC_BUSY_CYCLES"/> 453 <value value="1" name="PERF_VPC_WORKING_CYCLES"/> 454 <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> 455 <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> 456 <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 457 <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> 458 <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> 459 <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> 460 <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> 461 <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> 462 <value value="10" name="PERF_VPC_SP_COMPONENTS"/> 463 <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 464 <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 465 <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 466 <value value="14" name="PERF_VPC_LM_TRANSACTION"/> 467 <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> 468 <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> 469 <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> 470 <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> 471 <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> 472 <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> 473 <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> 474 <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> 475 <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> 476 <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 477 <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> 478 <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> 479 <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> 480</enum> 481 482<enum name="a6xx_tse_perfcounter_select"> 483 <value value="0" name="PERF_TSE_BUSY_CYCLES"/> 484 <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> 485 <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> 486 <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 487 <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 488 <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> 489 <value value="6" name="PERF_TSE_INPUT_PRIM"/> 490 <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> 491 <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> 492 <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> 493 <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> 494 <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> 495 <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> 496 <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> 497 <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 498 <value value="15" name="PERF_TSE_CINVOCATION"/> 499 <value value="16" name="PERF_TSE_CPRIMITIVES"/> 500 <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> 501 <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> 502 <value value="19" name="PERF_TSE_CLIP_PLANES"/> 503</enum> 504 505<enum name="a6xx_ras_perfcounter_select"> 506 <value value="0" name="PERF_RAS_BUSY_CYCLES"/> 507 <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 508 <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> 509 <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> 510 <value value="4" name="PERF_RAS_SUPER_TILES"/> 511 <value value="5" name="PERF_RAS_8X4_TILES"/> 512 <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> 513 <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 514 <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> 515 <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> 516 <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 517 <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 518 <value value="12" name="PERF_RAS_BLOCKS"/> 519</enum> 520 521<enum name="a6xx_uche_perfcounter_select"> 522 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> 523 <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> 524 <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> 525 <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 526 <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> 527 <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> 528 <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 529 <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 530 <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> 531 <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> 532 <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> 533 <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> 534 <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> 535 <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> 536 <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> 537 <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> 538 <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> 539 <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> 540 <value value="18" name="PERF_UCHE_EVICTS"/> 541 <value value="19" name="PERF_UCHE_BANK_REQ0"/> 542 <value value="20" name="PERF_UCHE_BANK_REQ1"/> 543 <value value="21" name="PERF_UCHE_BANK_REQ2"/> 544 <value value="22" name="PERF_UCHE_BANK_REQ3"/> 545 <value value="23" name="PERF_UCHE_BANK_REQ4"/> 546 <value value="24" name="PERF_UCHE_BANK_REQ5"/> 547 <value value="25" name="PERF_UCHE_BANK_REQ6"/> 548 <value value="26" name="PERF_UCHE_BANK_REQ7"/> 549 <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> 550 <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> 551 <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> 552 <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> 553 <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> 554 <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> 555 <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 556 <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 557 <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> 558 <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> 559 <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> 560 <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> 561 <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> 562</enum> 563 564<enum name="a6xx_tp_perfcounter_select"> 565 <value value="0" name="PERF_TP_BUSY_CYCLES"/> 566 <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> 567 <value value="2" name="PERF_TP_LATENCY_CYCLES"/> 568 <value value="3" name="PERF_TP_LATENCY_TRANS"/> 569 <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> 570 <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> 571 <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> 572 <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> 573 <value value="8" name="PERF_TP_SP_TP_TRANS"/> 574 <value value="9" name="PERF_TP_TP_SP_TRANS"/> 575 <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> 576 <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> 577 <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> 578 <value value="13" name="PERF_TP_QUADS_RECEIVED"/> 579 <value value="14" name="PERF_TP_QUADS_OFFSET"/> 580 <value value="15" name="PERF_TP_QUADS_SHADOW"/> 581 <value value="16" name="PERF_TP_QUADS_ARRAY"/> 582 <value value="17" name="PERF_TP_QUADS_GRADIENT"/> 583 <value value="18" name="PERF_TP_QUADS_1D"/> 584 <value value="19" name="PERF_TP_QUADS_2D"/> 585 <value value="20" name="PERF_TP_QUADS_BUFFER"/> 586 <value value="21" name="PERF_TP_QUADS_3D"/> 587 <value value="22" name="PERF_TP_QUADS_CUBE"/> 588 <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 589 <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 590 <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> 591 <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 592 <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> 593 <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> 594 <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 595 <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> 596 <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> 597 <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> 598 <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> 599 <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 600 <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 601 <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 602 <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 603 <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> 604 <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> 605 <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> 606 <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> 607 <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> 608 <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> 609 <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> 610 <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 611 <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 612 <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 613 <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> 614 <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> 615 <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 616 <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 617 <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> 618 <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> 619 <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 620 <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> 621 <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> 622</enum> 623 624<enum name="a6xx_sp_perfcounter_select"> 625 <value value="0" name="PERF_SP_BUSY_CYCLES"/> 626 <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> 627 <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> 628 <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> 629 <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> 630 <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> 631 <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> 632 <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> 633 <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> 634 <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> 635 <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> 636 <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> 637 <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> 638 <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 639 <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> 640 <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> 641 <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> 642 <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> 643 <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> 644 <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> 645 <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> 646 <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> 647 <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> 648 <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> 649 <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 650 <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 651 <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> 652 <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> 653 <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> 654 <value value="29" name="PERF_SP_LM_ATOMICS"/> 655 <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> 656 <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> 657 <value value="32" name="PERF_SP_GM_ATOMICS"/> 658 <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 659 <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 660 <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 661 <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 662 <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 663 <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 664 <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 665 <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 666 <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 667 <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 668 <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> 669 <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> 670 <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> 671 <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> 672 <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> 673 <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> 674 <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> 675 <value value="50" name="PERF_SP_PIXELS_KILLED"/> 676 <value value="51" name="PERF_SP_ICL1_REQUESTS"/> 677 <value value="52" name="PERF_SP_ICL1_MISSES"/> 678 <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> 679 <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> 680 <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> 681 <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> 682 <value value="57" name="PERF_SP_GPR_READ"/> 683 <value value="58" name="PERF_SP_GPR_WRITE"/> 684 <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 685 <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 686 <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> 687 <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 688 <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 689 <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 690 <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> 691 <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> 692 <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> 693 <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 694 <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> 695 <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> 696 <value value="71" name="PERF_SP_WORKING_EU"/> 697 <value value="72" name="PERF_SP_ANY_EU_WORKING"/> 698 <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> 699 <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 700 <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> 701 <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 702 <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> 703 <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 704 <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> 705 <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> 706 <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> 707 <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 708 <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 709 <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> 710</enum> 711 712<enum name="a6xx_rb_perfcounter_select"> 713 <value value="0" name="PERF_RB_BUSY_CYCLES"/> 714 <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> 715 <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 716 <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 717 <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 718 <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> 719 <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 720 <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> 721 <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> 722 <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 723 <value value="10" name="PERF_RB_Z_WORKLOAD"/> 724 <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> 725 <value value="12" name="PERF_RB_Z_READ"/> 726 <value value="13" name="PERF_RB_Z_WRITE"/> 727 <value value="14" name="PERF_RB_C_READ"/> 728 <value value="15" name="PERF_RB_C_WRITE"/> 729 <value value="16" name="PERF_RB_TOTAL_PASS"/> 730 <value value="17" name="PERF_RB_Z_PASS"/> 731 <value value="18" name="PERF_RB_Z_FAIL"/> 732 <value value="19" name="PERF_RB_S_FAIL"/> 733 <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> 734 <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> 735 <value value="22" name="PERF_RB_PS_INVOCATIONS"/> 736 <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> 737 <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> 738 <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> 739 <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> 740 <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> 741 <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> 742 <value value="29" name="PERF_RB_3D_PIXELS"/> 743 <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> 744 <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> 745 <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> 746 <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> 747 <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 748 <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 749 <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 750 <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 751 <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> 752 <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> 753 <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 754 <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 755 <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> 756 <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> 757 <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> 758 <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> 759 <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> 760 <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> 761</enum> 762 763<enum name="a6xx_vsc_perfcounter_select"> 764 <value value="0" name="PERF_VSC_BUSY_CYCLES"/> 765 <value value="1" name="PERF_VSC_WORKING_CYCLES"/> 766 <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> 767 <value value="3" name="PERF_VSC_EOT_NUM"/> 768 <value value="4" name="PERF_VSC_INPUT_TILES"/> 769</enum> 770 771<enum name="a6xx_ccu_perfcounter_select"> 772 <value value="0" name="PERF_CCU_BUSY_CYCLES"/> 773 <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 774 <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 775 <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> 776 <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> 777 <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> 778 <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> 779 <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> 780 <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> 781 <value value="9" name="PERF_CCU_GMEM_READ"/> 782 <value value="10" name="PERF_CCU_GMEM_WRITE"/> 783 <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> 784 <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> 785 <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> 786 <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> 787 <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> 788 <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> 789 <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> 790 <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> 791 <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> 792 <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> 793 <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> 794 <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> 795 <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> 796 <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> 797 <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> 798 <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> 799 <value value="27" name="PERF_CCU_2D_RD_REQ"/> 800 <value value="28" name="PERF_CCU_2D_WR_REQ"/> 801</enum> 802 803<enum name="a6xx_lrz_perfcounter_select"> 804 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> 805 <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> 806 <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> 807 <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> 808 <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> 809 <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 810 <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> 811 <value value="7" name="PERF_LRZ_LRZ_READ"/> 812 <value value="8" name="PERF_LRZ_LRZ_WRITE"/> 813 <value value="9" name="PERF_LRZ_READ_LATENCY"/> 814 <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> 815 <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 816 <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 817 <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 818 <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> 819 <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> 820 <value value="16" name="PERF_LRZ_TILE_KILLED"/> 821 <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> 822 <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 823 <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> 824 <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> 825 <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> 826 <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> 827 <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> 828 <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 829 <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 830 <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> 831 <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> 832</enum> 833 834<enum name="a6xx_cmp_perfcounter_select"> 835 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> 836 <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 837 <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 838 <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 839 <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 840 <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> 841 <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 842 <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> 843 <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> 844 <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> 845 <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> 846 <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 847 <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 848 <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 849 <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 850 <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 851 <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 852 <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 853 <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 854 <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 855 <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 856 <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 857 <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 858 <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 859 <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 860 <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> 861 <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> 862 <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> 863 <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> 864 <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> 865 <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 866 <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 867 <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> 868 <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 869 <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 870 <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 871 <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 872 <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> 873 <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> 874 <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> 875</enum> 876 877<!-- 878Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the 879component type/size, so I think it relates to internal format used for 880blending? The one exception is that 16b unorm and 32b float use the 881same value... maybe 16b unorm is uncommon enough that it was just easier 882to upconvert to 32b float internally? 883 884 8b unorm: 10 (sometimes 0, is the high bit part of something else?) 88516b unorm: 4 886 88732b int: 7 88816b int: 6 889 8b int: 5 890 89132b float: 4 89216b float: 3 893 --> 894<enum name="a6xx_2d_ifmt"> 895 <value value="0x10" name="R2D_UNORM8"/> 896 <value value="0x7" name="R2D_INT32"/> 897 <value value="0x6" name="R2D_INT16"/> 898 <value value="0x5" name="R2D_INT8"/> 899 <value value="0x4" name="R2D_FLOAT32"/> 900 <value value="0x3" name="R2D_FLOAT16"/> 901 <value value="0x1" name="R2D_UNORM8_SRGB"/> 902 <value value="0x0" name="R2D_RAW"/> 903</enum> 904 905<enum name="a6xx_ztest_mode"> 906 <doc>Allow early z-test and early-lrz (if applicable)</doc> 907 <value value="0x0" name="A6XX_EARLY_Z"/> 908 <doc>Disable early z-test and early-lrz test (if applicable)</doc> 909 <value value="0x1" name="A6XX_LATE_Z"/> 910 <doc> 911 A special mode that allows early-lrz test but disables 912 early-z test. Which might sound a bit funny, since 913 lrz-test happens before z-test. But as long as a couple 914 conditions are maintained this allows using lrz-test in 915 cases where fragment shader has kill/discard: 916 917 1) Disable lrz-write in cases where it is uncertain during 918 binning pass that a fragment will pass. Ie. if frag 919 shader has-kill, writes-z, or alpha/stencil test is 920 enabled. (For correctness, lrz-write must be disabled 921 when blend is enabled.) This is analogous to how a 922 z-prepass works. 923 924 2) Disable lrz-write and test if a depth-test direction 925 reversal is detected. Due to condition (1), the contents 926 of the lrz buffer are a conservative estimation of the 927 depth buffer during the draw pass. Meaning that geometry 928 that we know for certain will not be visible will not pass 929 lrz-test. But geometry which may be (or contributes to 930 blend) will pass the lrz-test. 931 932 This allows us to keep early-lrz-test in cases where the frag 933 shader does not write-z (ie. we know the z-value before FS) 934 and does not have side-effects (image/ssbo writes, etc), but 935 does have kill/discard. Which turns out to be a common 936 enough case that it is useful to keep early-lrz test against 937 the conservative lrz buffer to discard fragments that we 938 know will definitely not be visible. 939 </doc> 940 <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/> 941</enum> 942 943<domain name="A6XX" width="32"> 944 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no"> 945 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> 946 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/> 947 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/> 948 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/> 949 <bitfield name="CP_SW" pos="8" type="boolean"/> 950 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/> 951 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/> 952 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/> 953 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/> 954 <bitfield name="CP_IB2" pos="13" type="boolean"/> 955 <bitfield name="CP_IB1" pos="14" type="boolean"/> 956 <bitfield name="CP_RB" pos="15" type="boolean"/> 957 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/> 958 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/> 959 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/> 960 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/> 961 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/> 962 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/> 963 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/> 964 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/> 965 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/> 966 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/> 967 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/> 968 </bitset> 969 970 <bitset name="A6XX_CP_INT"> 971 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/> 972 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/> 973 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/> 974 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/> 975 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/> 976 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/> 977 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/> 978 </bitset> 979 980 <reg64 offset="0x0800" name="CP_RB_BASE"/> 981 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 982 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 983 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 984 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 985 <reg32 offset="0x0808" name="CP_SQE_CNTL"/> 986 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS"> 987 <bitfield name="IFPC" pos="0" type="boolean"/> 988 </reg32> 989 <reg32 offset="0x0821" name="CP_HW_FAULT"/> 990 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/> 991 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/> 992 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/> 993 <reg32 offset="0x0840" name="CP_MISC_CNTL"/> 994 <reg32 offset="0x0844" name="CP_APRIV_CNTL"/> 995 <!-- all the threshold values seem to be in units of quad-dwords: --> 996 <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"> 997 <doc> 998 b0..7 seems to contain the size of buffered by not yet processed 999 RB level cmdstream.. it's possible that it is a low threshold 1000 and b8..15 is a high threshold? 1001 1002 b16..23 identifies where IB1 data starts (and RB data ends?) 1003 1004 b24..31 identifies where IB2 data starts (and IB1 data ends) 1005 </doc> 1006 <bitfield name="RB_LO" low="0" high="7" shr="2"/> 1007 <bitfield name="RB_HI" low="8" high="15" shr="2"/> 1008 <bitfield name="IB1_START" low="16" high="23" shr="2"/> 1009 <bitfield name="IB2_START" low="24" high="31" shr="2"/> 1010 </reg32> 1011 <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"> 1012 <doc> 1013 low bits identify where CP_SET_DRAW_STATE stateobj 1014 processing starts (and IB2 data ends). I'm guessing 1015 b8 is part of this since (from downstream kgsl): 1016 1017 /* ROQ sizes are twice as big on a640/a680 than on a630 */ 1018 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { 1019 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1020 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); 1021 } ... 1022 </doc> 1023 <bitfield name="SDS_START" low="0" high="8" shr="2"/> 1024 <!-- total ROQ size: --> 1025 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/> 1026 </reg32> 1027 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/> 1028 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/> 1029 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1030 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/> 1031 <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/> 1032 1033 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8"> 1034 <reg32 offset="0x0" name="REG" type="uint"/> 1035 </array> 1036 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32"> 1037 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 1038 </array> 1039 1040 <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> 1041 <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> 1042 <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> 1043 <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> 1044 <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/> 1045 <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> 1046 <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/> 1047 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> 1048 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> 1049 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> 1050 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/> 1051 <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/> 1052 <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/> 1053 <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/> 1054 <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/> 1055 <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/> 1056 <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/> 1057 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/> 1058 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/> 1059 <reg64 offset="0x0928" name="CP_IB1_BASE"/> 1060 <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/> 1061 <reg64 offset="0x092B" name="CP_IB2_BASE"/> 1062 <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/> 1063 <!-- SDS == CP_SET_DRAW_STATE: --> 1064 <reg64 offset="0x092e" name="CP_SDS_BASE"/> 1065 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/> 1066 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware --> 1067 <reg64 offset="0x0931" name="CP_MRB_BASE"/> 1068 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/> 1069 <!-- 1070 VSD == Visibility Stream Decode 1071 This is used by CP to read the draw stream and skip empty draws 1072 --> 1073 <reg64 offset="0x0934" name="CP_VSD_BASE"/> 1074 <reg32 offset="0x0946" name="CP_MRB_DWORDS"/> 1075 <reg32 offset="0x0947" name="CP_VSD_DWORDS"/> 1076 <!-- 1077 There are probably similar registers for RB and SDS, teasing out SDS will 1078 take a slightly better test case.. 1079 --> 1080 <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT"> 1081 <doc>number of remaining dwords incl current dword being consumed?</doc> 1082 <bitfield name="REM" low="16" high="31"/> 1083 </reg32> 1084 <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT"> 1085 <doc>number of remaining dwords incl current dword being consumed?</doc> 1086 <bitfield name="REM" low="16" high="31"/> 1087 </reg32> 1088 <reg32 offset="0x094c" name="CP_MRQ_MRB_STAT"> 1089 <doc>number of dwords that have already been read but haven't been consumed by $addr</doc> 1090 <bitfield name="REM" low="16" high="31"/> 1091 </reg32> 1092 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/> 1093 <reg32 offset="0x098D" name="CP_AHB_CNTL"/> 1094 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/> 1095 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/> 1096 <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/> 1097 <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/> 1098 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1099 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/> 1100 <reg32 offset="0x0210" name="RBBM_STATUS"> 1101 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 1102 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 1103 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/> 1104 <bitfield pos="20" name="VSC_BUSY" type="boolean"/> 1105 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/> 1106 <bitfield pos="18" name="SP_BUSY" type="boolean"/> 1107 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/> 1108 <bitfield pos="16" name="VPC_BUSY" type="boolean"/> 1109 <bitfield pos="15" name="VFD_BUSY" type="boolean"/> 1110 <bitfield pos="14" name="TESS_BUSY" type="boolean"/> 1111 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/> 1112 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/> 1113 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/> 1114 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/> 1115 <bitfield pos="9" name="A2D_BUSY" type="boolean"/> 1116 <bitfield pos="8" name="CCU_BUSY" type="boolean"/> 1117 <bitfield pos="7" name="RB_BUSY" type="boolean"/> 1118 <bitfield pos="6" name="RAS_BUSY" type="boolean"/> 1119 <bitfield pos="5" name="TSE_BUSY" type="boolean"/> 1120 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/> 1121 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 1122 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 1123 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 1124 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 1125 </reg32> 1126 <reg32 offset="0x0213" name="RBBM_STATUS3"> 1127 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 1128 </reg32> 1129 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/> 1130 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14"/> 1131 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/> 1132 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8"/> 1133 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8"/> 1134 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/> 1135 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6"/> 1136 <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/> 1137 <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4"/> 1138 <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/> 1139 <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/> 1140 <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12"/> 1141 <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/> 1142 <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/> 1143 <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/> 1144 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/> 1145 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/> 1146 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/> 1147 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/> 1148 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/> 1149 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/> 1150 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/> 1151 <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> 1152 <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> 1153 <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/> 1154 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> 1155 <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/> 1156 <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/> 1157 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> 1158 1159 <!--- 1160 This block of registers aren't tied to perf counters. They 1161 count various geometry stats, for example number of 1162 vertices in, number of primnitives assembled etc. 1163 --> 1164 1165 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in --> 1166 <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/> 1167 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out --> 1168 <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/> 1169 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in --> 1170 <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/> 1171 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out --> 1172 <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/> 1173 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in --> 1174 <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/> 1175 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out --> 1176 <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/> 1177 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in --> 1178 <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/> 1179 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out --> 1180 <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/> 1181 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out --> 1182 <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/> 1183 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in --> 1184 <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/> 1185 <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/> 1186 <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/> 1187 1188 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 1189 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 1190 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 1191 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> 1192 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1193 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/> 1194 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/> 1195 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD"> 1196 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/> 1197 </reg32> 1198 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> 1199 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/> 1200 <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/> 1201 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/> 1202 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/> 1203 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/> 1204 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/> 1205 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/> 1206 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/> 1207 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/> 1208 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/> 1209 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/> 1210 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/> 1211 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/> 1212 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/> 1213 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/> 1214 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/> 1215 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/> 1216 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/> 1217 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/> 1218 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/> 1219 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/> 1220 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/> 1221 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/> 1222 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/> 1223 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/> 1224 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/> 1225 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/> 1226 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/> 1227 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/> 1228 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/> 1229 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/> 1230 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/> 1231 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/> 1232 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/> 1233 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/> 1234 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/> 1235 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/> 1236 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/> 1237 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/> 1238 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/> 1239 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/> 1240 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/> 1241 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/> 1242 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/> 1243 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/> 1244 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/> 1245 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/> 1246 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/> 1247 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/> 1248 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/> 1249 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/> 1250 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/> 1251 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/> 1252 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/> 1253 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/> 1254 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/> 1255 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/> 1256 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/> 1257 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/> 1258 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/> 1259 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/> 1260 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/> 1261 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/> 1262 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/> 1263 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/> 1264 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/> 1265 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/> 1266 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/> 1267 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/> 1268 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/> 1269 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/> 1270 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/> 1271 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/> 1272 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/> 1273 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/> 1274 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/> 1275 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/> 1276 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/> 1277 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/> 1278 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/> 1279 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/> 1280 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/> 1281 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/> 1282 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/> 1283 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/> 1284 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/> 1285 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/> 1286 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/> 1287 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/> 1288 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/> 1289 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/> 1290 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/> 1291 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> 1292 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> 1293 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> 1294 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/> 1295 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/> 1296 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/> 1297 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/> 1298 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/> 1299 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/> 1300 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/> 1301 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/> 1302 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/> 1303 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/> 1304 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/> 1305 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/> 1306 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/> 1307 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/> 1308 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/> 1309 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/> 1310 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/> 1311 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/> 1312 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/> 1313 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/> 1314 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/> 1315 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/> 1316 1317 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 1318 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 1319 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 1320 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D"> 1321 <bitfield high="7" low="0" name="PING_INDEX"/> 1322 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 1323 </reg32> 1324 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 1325 <bitfield high="5" low="0" name="TRACEEN"/> 1326 <bitfield high="14" low="12" name="GRANU"/> 1327 <bitfield high="31" low="28" name="SEGT"/> 1328 </reg32> 1329 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> 1330 <bitfield high="27" low="24" name="ENABLE"/> 1331 </reg32> 1332 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> 1333 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> 1334 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> 1335 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/> 1336 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/> 1337 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/> 1338 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/> 1339 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/> 1340 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"> 1341 <bitfield high="3" low="0" name="BYTEL0"/> 1342 <bitfield high="7" low="4" name="BYTEL1"/> 1343 <bitfield high="11" low="8" name="BYTEL2"/> 1344 <bitfield high="15" low="12" name="BYTEL3"/> 1345 <bitfield high="19" low="16" name="BYTEL4"/> 1346 <bitfield high="23" low="20" name="BYTEL5"/> 1347 <bitfield high="27" low="24" name="BYTEL6"/> 1348 <bitfield high="31" low="28" name="BYTEL7"/> 1349 </reg32> 1350 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"> 1351 <bitfield high="3" low="0" name="BYTEL8"/> 1352 <bitfield high="7" low="4" name="BYTEL9"/> 1353 <bitfield high="11" low="8" name="BYTEL10"/> 1354 <bitfield high="15" low="12" name="BYTEL11"/> 1355 <bitfield high="19" low="16" name="BYTEL12"/> 1356 <bitfield high="23" low="20" name="BYTEL13"/> 1357 <bitfield high="27" low="24" name="BYTEL14"/> 1358 <bitfield high="31" low="28" name="BYTEL15"/> 1359 </reg32> 1360 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 1361 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 1362 <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 1363 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> 1364 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> 1365 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1366 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> 1367 <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/> 1368 <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/> 1369 <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/> 1370 <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/> 1371 <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/> 1372 <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/> 1373 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> 1374 <reg32 offset="0x0E19" name="UCHE_CLIENT_PF"> 1375 <bitfield high="7" low="0" name="PERFSEL"/> 1376 </reg32> 1377 <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/> 1378 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/> 1379 1380 <reg32 offset="0x3000" name="VBIF_VERSION"/> 1381 <reg32 offset="0x3001" name="VBIF_CLKON"> 1382 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/> 1383 </reg32> 1384 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/> 1385 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/> 1386 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> 1387 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> 1388 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> 1389 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"> 1390 <bitfield low="0" high="3" name="DATA_SEL"/> 1391 </reg32> 1392 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> 1393 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"> 1394 <bitfield low="0" high="8" name="DATA_SEL"/> 1395 </reg32> 1396 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> 1397 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/> 1398 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/> 1399 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/> 1400 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/> 1401 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> 1402 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> 1403 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> 1404 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> 1405 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> 1406 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> 1407 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> 1408 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> 1409 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> 1410 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> 1411 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> 1412 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> 1413 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> 1414 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> 1415 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> 1416 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> 1417 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> 1418 1419 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 1420 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 1421 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> 1422 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/> 1423 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/> 1424 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 1425 <reg32 offset="0x3c45" name="GBIF_HALT"/> 1426 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 1427 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 1428 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 1429 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/> 1430 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/> 1431 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/> 1432 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/> 1433 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/> 1434 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/> 1435 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/> 1436 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/> 1437 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/> 1438 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/> 1439 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/> 1440 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/> 1441 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/> 1442 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/> 1443 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/> 1444 1445 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> 1446 <reg32 offset="0x0c02" name="VSC_BIN_SIZE"> 1447 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> 1448 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> 1449 </reg32> 1450 <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/> 1451 <reg32 offset="0x0c06" name="VSC_BIN_COUNT"> 1452 <bitfield name="NX" low="1" high="10" type="uint"/> 1453 <bitfield name="NY" low="11" high="20" type="uint"/> 1454 </reg32> 1455 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32"> 1456 <reg32 offset="0x0" name="REG"> 1457 <doc> 1458 Configures the mapping between VSC_PIPE buffer and 1459 bin, X/Y specify the bin index in the horiz/vert 1460 direction (0,0 is upper left, 0,1 is leftmost bin 1461 on second row, and so on). W/H specify the number 1462 of bins assigned to this VSC_PIPE in the horiz/vert 1463 dimension. 1464 </doc> 1465 <bitfield name="X" low="0" high="9" type="uint"/> 1466 <bitfield name="Y" low="10" high="19" type="uint"/> 1467 <bitfield name="W" low="20" high="25" type="uint"/> 1468 <bitfield name="H" low="26" high="31" type="uint"/> 1469 </reg32> 1470 </array> 1471 <!-- 1472 HW binning primitive & draw streams, which enable draws and primitives 1473 within a draw to be skipped in the main tile pass. See: 1474 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format 1475 1476 Compared to a5xx and earlier, we just program the address of the first 1477 stream and hw adds (pipe_num * VSC_*_STRM_PITCH) 1478 1479 LIMIT is set to PITCH - 64, to make room for a bit of overflow 1480 --> 1481 <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/> 1482 <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/> 1483 <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/> 1484 <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/> 1485 <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/> 1486 <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/> 1487 1488 <array offset="0x0c38" name="VSC_STATE" stride="1" length="32"> 1489 <doc> 1490 Seems to be a bitmap of which tiles mapped to the VSC 1491 pipe contain geometry. 1492 1493 I suppose we can connect a maximum of 32 tiles to a 1494 single VSC pipe. 1495 </doc> 1496 <reg32 offset="0x0" name="REG"/> 1497 </array> 1498 1499 <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32"> 1500 <doc> 1501 Has the size of data written to corresponding VSC_PRIM_STRM 1502 buffer. 1503 </doc> 1504 <reg32 offset="0x0" name="REG"/> 1505 </array> 1506 1507 <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32"> 1508 <doc> 1509 Has the size of data written to corresponding VSC pipe, ie. 1510 same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI 1511 </doc> 1512 <reg32 offset="0x0" name="REG"/> 1513 </array> 1514 1515 <!-- always 0x03200000 ? --> 1516 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/> 1517 1518 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 --> 1519 <bitset name="a6xx_reg_xy" inline="yes"> 1520 <bitfield name="X" low="0" high="13" type="uint"/> 1521 <bitfield name="Y" low="16" high="29" type="uint"/> 1522 </bitset> 1523 1524 <reg32 offset="0x8000" name="GRAS_CL_CNTL"> 1525 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 1526 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 1527 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> 1528 <!-- set with depthClampEnable, not clear what it does --> 1529 <bitfield name="UNK5" pos="5" type="boolean"/> 1530 <!-- controls near z clip behavior (set for vulkan) --> 1531 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> 1532 <!-- guess based on a3xx and meaning of bits 8 and 9 1533 if the guess is right then this is related to point sprite clipping --> 1534 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 1535 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 1536 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 1537 </reg32> 1538 1539 <bitset name="a6xx_gras_xs_cl_cntl" inline="yes"> 1540 <bitfield name="CLIP_MASK" low="0" high="7"/> 1541 <bitfield name="CULL_MASK" low="8" high="15"/> 1542 </bitset> 1543 <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/> 1544 <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/> 1545 <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/> 1546 <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/> 1547 1548 <reg32 offset="0x8005" name="GRAS_CNTL"> 1549 <!-- see also RB_RENDER_CONTROL0 --> 1550 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 1551 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 1552 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 1553 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 1554 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 1555 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 1556 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 1557 </reg32> 1558 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ"> 1559 <bitfield name="HORZ" low="0" high="8" type="uint"/> 1560 <bitfield name="VERT" low="10" high="18" type="uint"/> 1561 </reg32> 1562 <!-- 0x8006-0x800f invalid --> 1563 <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16"> 1564 <reg32 offset="0" name="XOFFSET" type="float"/> 1565 <reg32 offset="1" name="XSCALE" type="float"/> 1566 <reg32 offset="2" name="YOFFSET" type="float"/> 1567 <reg32 offset="3" name="YSCALE" type="float"/> 1568 <reg32 offset="4" name="ZOFFSET" type="float"/> 1569 <reg32 offset="5" name="ZSCALE" type="float"/> 1570 </array> 1571 <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16"> 1572 <reg32 offset="0" name="MIN" type="float"/> 1573 <reg32 offset="1" name="MAX" type="float"/> 1574 </array> 1575 1576 <reg32 offset="0x8090" name="GRAS_SU_CNTL"> 1577 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 1578 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 1579 <bitfield name="FRONT_CW" pos="2" type="boolean"/> 1580 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> 1581 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> 1582 <bitfield name="UNK12" pos="12"/> 1583 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 1584 <bitfield name="UNK15" low="15" high="16"/> 1585 <!-- 1586 This is set by the blob when multiview is enabled, but doesn't seem 1587 to do anything. 1588 --> 1589 <bitfield name="UNK17" pos="17" type="boolean"/> 1590 <bitfield name="MULTIVIEW_ENABLE" pos="18" type="boolean"/> 1591 <bitfield name="UNK19" low="19" high="22"/> 1592 </reg32> 1593 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX"> 1594 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 1595 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 1596 </reg32> 1597 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/> 1598 <!-- 0x8093 invalid --> 1599 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL"> 1600 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 1601 </reg32> 1602 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/> 1603 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/> 1604 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/> 1605 <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 1606 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO"> 1607 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1608 <bitfield name="UNK3" pos="3"/> 1609 </reg32> 1610 1611 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"> 1612 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 1613 <bitfield name="SHIFTAMOUNT" low="1" high="2"/> 1614 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 1615 <bitfield name="UNK4" low="4" high="5"/> 1616 </reg32> 1617 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 1618 <bitfield name="UNK0" pos="0" type="boolean"/> 1619 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> 1620 </reg32> 1621 1622 <bitset name="a6xx_gras_layer_cntl" inline="yes"> 1623 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 1624 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 1625 </bitset> 1626 <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/> 1627 <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/> 1628 <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/> 1629 <!-- 0x809e/0x809f invalid --> 1630 1631 <enum name="a6xx_sequenced_thread_dist"> 1632 <value value="0x0" name="DIST_SCREEN_COORD"/> 1633 <value value="0x1" name="DIST_ALL_TO_RB0"/> 1634 </enum> 1635 1636 <enum name="a6xx_single_prim_mode"> 1637 <value value="0x0" name="NO_FLUSH"/> 1638 <doc> 1639 In addition to FLUSH_PER_OVERLAP, guarantee that UCHE 1640 and CCU don't get out of sync when fetching the previous 1641 value for the current pixel. With NO_FLUSH, there's the 1642 possibility that the flags for the current pixel are 1643 flushed before the data or vice-versa, leading to 1644 texture fetches via UCHE getting out of sync values. 1645 This mode should eliminate that. It's used in bypass 1646 mode for coherent blending 1647 (GL_KHR_blend_equation_advanced_coherent) as well as 1648 non-coherent blending. 1649 </doc> 1650 <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/> 1651 <doc> 1652 Invalidate UCHE and wait for any pending work to finish 1653 if there was possibly an overlapping primitive prior to 1654 the current one. This is similar to a combination of 1655 GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and 1656 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for 1657 coherent blending 1658 (GL_KHR_blend_equation_advanced_coherent). 1659 </doc> 1660 <value value="0x3" name="FLUSH_PER_OVERLAP"/> 1661 </enum> 1662 1663 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE --> 1664 <enum name="a6xx_raster_mode"> 1665 <value value="0x0" name="TYPE_TILED"/> 1666 <value value="0x1" name="TYPE_WRITER"/> 1667 </enum> 1668 1669 <!-- I'm guessing this is the same as a3xx --> 1670 <enum name="a6xx_raster_direction"> 1671 <value value="0x0" name="LR_TB"/> 1672 <value value="0x1" name="RL_TB"/> 1673 <value value="0x2" name="LR_BT"/> 1674 <value value="0x3" name="RB_BT"/> 1675 </enum> 1676 1677 <reg32 offset="0x80a0" name="GRAS_SC_CNTL"> 1678 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/> 1679 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 1680 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> 1681 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/> 1682 <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/> 1683 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set --> 1684 <bitfield name="UNK9" low="9" high="11"/> 1685 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1686 </reg32> 1687 1688 <enum name="a6xx_render_mode"> 1689 <value value="0x0" name="RENDERING_PASS"/> 1690 <value value="0x1" name="BINNING_PASS"/> 1691 </enum> 1692 1693 <enum name="a6xx_buffers_location"> 1694 <value value="0" name="BUFFERS_IN_GMEM"/> 1695 <value value="3" name="BUFFERS_IN_SYSMEM"/> 1696 </enum> 1697 1698 <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL"> 1699 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1700 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1701 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1702 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1703 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/> 1704 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/> 1705 <bitfield name="UNK27" pos="27"/> 1706 </reg32> 1707 1708 <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL"> 1709 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1710 <bitfield name="UNK2" pos="2"/> 1711 <bitfield name="UNK3" pos="3"/> 1712 </reg32> 1713 <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL"> 1714 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1715 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1716 </reg32> 1717 1718 <bitset name="a6xx_sample_config" inline="yes"> 1719 <bitfield name="UNK0" pos="0"/> 1720 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> 1721 </bitset> 1722 1723 <bitset name="a6xx_sample_locations" inline="yes"> 1724 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> 1725 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> 1726 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> 1727 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/> 1728 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/> 1729 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/> 1730 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/> 1731 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1732 </bitset> 1733 1734 <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/> 1735 <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/> 1736 <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/> 1737 <!-- 0x80a7-0x80ae invalid --> 1738 <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/> 1739 1740 <bitset name="a6xx_scissor_xy" inline="yes"> 1741 <bitfield name="X" low="0" high="15" type="uint"/> 1742 <bitfield name="Y" low="16" high="31" type="uint"/> 1743 </bitset> 1744 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16"> 1745 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1746 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1747 </array> 1748 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16"> 1749 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1750 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1751 </array> 1752 1753 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/> 1754 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/> 1755 <!-- 0x80f2-0x80ff invalid --> 1756 1757 <enum name="a6xx_lrz_dir_status"> 1758 <value value="0x1" name="LRZ_DIR_LE"/> 1759 <value value="0x2" name="LRZ_DIR_GE"/> 1760 <value value="0x3" name="LRZ_DIR_INVALID"/> 1761 </enum> 1762 1763 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL"> 1764 <bitfield name="ENABLE" pos="0" type="boolean"/> 1765 <doc>LRZ write also disabled for blend/etc.</doc> 1766 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> 1767 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> 1768 <bitfield name="GREATER" pos="2" type="boolean"/> 1769 <doc> 1770 Clears the LRZ block being touched to: 1771 - 0.0 if GREATER 1772 - 1.0 if LESS 1773 </doc> 1774 <bitfield name="FC_ENABLE" pos="3" type="boolean"/> 1775 <!-- set when depth-test + depth-write enabled --> 1776 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/> 1777 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> 1778 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> 1779 <doc> 1780 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into 1781 buffer, in case of mismatched direction writes 0 (disables LRZ). 1782 </doc> 1783 <bitfield name="DIR_WRITE" pos="8" type="boolean"/> 1784 <doc> 1785 Disable LRZ based on previous direction and the current one. 1786 If DIR_WRITE is not enabled - there is no write to direction buffer. 1787 </doc> 1788 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean"/> 1789 </reg32> 1790 1791 <enum name="a6xx_fragcoord_sample_mode"> 1792 <value value="0" name="FRAGCOORD_CENTER"/> 1793 <value value="3" name="FRAGCOORD_SAMPLE"/> 1794 </enum> 1795 1796 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2"> 1797 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 1798 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 1799 </reg32> 1800 1801 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0"> 1802 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1803 </reg32> 1804 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/> 1805 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH"> 1806 <!-- TODO: fix the shr fields --> 1807 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 1808 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/> 1809 </reg32> 1810 1811 <!-- 1812 The LRZ "fast clear" buffer is initialized to zero's by blob, and 1813 read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears 1814 to store 1b/block. It appears that '0' means block has original 1815 depth clear value, and '1' means that the corresponding block in 1816 LRZ has been modified. Ignoring alignment/padding, the size is 1817 given by the formula: 1818 1819 // calculate LRZ size from depth size: 1820 if (nr_samples == 4) { 1821 width *= 2; 1822 height *= 2; 1823 } else if (nr_samples == 2) { 1824 height *= 2; 1825 } 1826 1827 lrz_width = div_round_up(width, 8); 1828 lrz_heigh = div_round_up(height, 8); 1829 1830 // calculate # of blocks: 1831 nblocksx = div_round_up(lrz_width, 16); 1832 nblocksy = div_round_up(lrz_height, 4); 1833 1834 // fast-clear buffer is 1bit/block: 1835 fc_sz = div_round_up(nblocksx * nblocksy, 8); 1836 1837 In practice the blob seems to switch off FC_ENABLE once the size 1838 increases beyond 1 page. Not sure if that is an actual limit or 1839 not. 1840 --> 1841 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/> 1842 <!-- 0x8108 invalid --> 1843 <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL"> 1844 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1845 </reg32> 1846 <!-- 1847 LRZ buffer represents a single array layer + mip level, and there is 1848 a single buffer per depth image. Thus to reuse LRZ between renderpasses 1849 it is necessary to track the depth view used in the past renderpass, which 1850 GRAS_LRZ_DEPTH_VIEW is for. 1851 GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to 1852 the value stored in the LRZ buffer, if not - LRZ is disabled. 1853 --> 1854 <reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW"> 1855 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> 1856 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> 1857 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> 1858 </reg32> 1859 1860 <!-- 0x810b-0x810f invalid --> 1861 1862 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/> 1863 1864 <!-- 0x8111-0x83ff invalid --> 1865 1866 <enum name="a6xx_rotation"> 1867 <value value="0x0" name="ROTATE_0"/> 1868 <value value="0x1" name="ROTATE_90"/> 1869 <value value="0x2" name="ROTATE_180"/> 1870 <value value="0x3" name="ROTATE_270"/> 1871 <value value="0x4" name="ROTATE_HFLIP"/> 1872 <value value="0x5" name="ROTATE_VFLIP"/> 1873 </enum> 1874 1875 <bitset name="a6xx_2d_blit_cntl" inline="yes"> 1876 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 1877 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 1878 <bitfield name="UNK4" low="4" high="6"/> 1879 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/> 1880 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/> 1881 <bitfield name="SCISSOR" pos="16" type="boolean"/> 1882 <bitfield name="UNK17" low="17" high="18"/> 1883 <!-- required when blitting D24S8/D24X8 --> 1884 <bitfield name="D24S8" pos="19" type="boolean"/> 1885 <!-- some sort of channel mask, disabled channels are set to zero ? --> 1886 <bitfield name="MASK" low="20" high="23"/> 1887 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> 1888 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 1889 </bitset> 1890 1891 <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/> 1892 <!-- note: the low 8 bits for src coords are valid, probably fixed point 1893 it would be a bit weird though, since we subtract 1 from BR coords 1894 apparently signed, gallium driver uses negative coords and it works? 1895 --> 1896 <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/> 1897 <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/> 1898 <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/> 1899 <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/> 1900 <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/> 1901 <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/> 1902 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 1903 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 1904 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 1905 <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/> 1906 <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/> 1907 <!-- 0x840c-0x85ff invalid --> 1908 1909 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 1910 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL"> 1911 <bitfield name="UNK7" pos="7" type="boolean"/> 1912 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/> 1913 </reg32> 1914 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 1915 <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/> 1916 <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/> 1917 <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/> 1918 1919 <!-- note 0x8620-0x87ff are not all invalid 1920 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) 1921 --> 1922 1923 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 1924 <reg32 offset="0x8800" name="RB_BIN_CONTROL"> 1925 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1926 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1927 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1928 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1929 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/> 1930 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/> 1931 </reg32> 1932 1933 <reg32 offset="0x8801" name="RB_RENDER_CNTL"> 1934 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> 1935 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 1936 <!-- set during binning pass: --> 1937 <bitfield name="BINNING" pos="7" type="boolean"/> 1938 <bitfield name="UNK8" low="8" high="10"/> 1939 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 1940 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 1941 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 1942 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 1943 <!-- bit seems to be set whenever depth buffer enabled: --> 1944 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> 1945 <!-- bitmask of MRTs using UBWC flag buffer: --> 1946 <bitfield name="FLAG_MRTS" low="16" high="23"/> 1947 </reg32> 1948 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL"> 1949 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1950 <bitfield name="UNK2" pos="2"/> 1951 <bitfield name="UNK3" pos="3"/> 1952 </reg32> 1953 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL"> 1954 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1955 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1956 </reg32> 1957 1958 <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/> 1959 <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/> 1960 <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/> 1961 <!-- 0x8807-0x8808 invalid --> 1962 <!-- 1963 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 1964 name comes from kernel and is probably right) 1965 --> 1966 <reg32 offset="0x8809" name="RB_RENDER_CONTROL0"> 1967 <!-- see also GRAS_CNTL --> 1968 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 1969 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 1970 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 1971 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 1972 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 1973 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 1974 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 1975 <bitfield name="UNK10" pos="10" type="boolean"/> 1976 </reg32> 1977 <reg32 offset="0x880a" name="RB_RENDER_CONTROL1"> 1978 <!-- enable bits for various FS sysvalue regs: --> 1979 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> 1980 <bitfield name="UNK1" pos="1" type="boolean"/> 1981 <bitfield name="FACENESS" pos="2" type="boolean"/> 1982 <bitfield name="SAMPLEID" pos="3" type="boolean"/> 1983 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/> 1984 <bitfield name="CENTERRHW" pos="6" type="boolean"/> 1985 <bitfield name="LINELENGTHEN" pos="7" type="boolean"/> 1986 <bitfield name="FOVEATION" pos="8" type="boolean"/> 1987 </reg32> 1988 1989 <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0"> 1990 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 1991 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> 1992 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> 1993 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> 1994 </reg32> 1995 <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1"> 1996 <bitfield name="MRT" low="0" high="3" type="uint"/> 1997 </reg32> 1998 <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS"> 1999 <bitfield name="RT0" low="0" high="3"/> 2000 <bitfield name="RT1" low="4" high="7"/> 2001 <bitfield name="RT2" low="8" high="11"/> 2002 <bitfield name="RT3" low="12" high="15"/> 2003 <bitfield name="RT4" low="16" high="19"/> 2004 <bitfield name="RT5" low="20" high="23"/> 2005 <bitfield name="RT6" low="24" high="27"/> 2006 <bitfield name="RT7" low="28" high="31"/> 2007 </reg32> 2008 <reg32 offset="0x880e" name="RB_DITHER_CNTL"> 2009 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 2010 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 2011 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 2012 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 2013 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 2014 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 2015 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/> 2016 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 2017 </reg32> 2018 <reg32 offset="0x880f" name="RB_SRGB_CNTL"> 2019 <!-- Same as SP_SRGB_CNTL --> 2020 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 2021 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 2022 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 2023 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 2024 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 2025 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 2026 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 2027 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 2028 </reg32> 2029 2030 <reg32 offset="0x8810" name="RB_SAMPLE_CNTL"> 2031 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2032 </reg32> 2033 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/> 2034 <!-- 0x8812-0x8817 invalid --> 2035 <!-- always 0x0 ? --> 2036 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/> 2037 <!-- 0x8819-0x881e all 32 bits --> 2038 <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/> 2039 <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/> 2040 <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/> 2041 <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/> 2042 <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/> 2043 <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/> 2044 <!-- 0x881f invalid --> 2045 <array offset="0x8820" name="RB_MRT" stride="8" length="8"> 2046 <reg32 offset="0x0" name="CONTROL"> 2047 <bitfield name="BLEND" pos="0" type="boolean"/> 2048 <bitfield name="BLEND2" pos="1" type="boolean"/> 2049 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> 2050 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> 2051 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> 2052 </reg32> 2053 <reg32 offset="0x1" name="BLEND_CONTROL"> 2054 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> 2055 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> 2056 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> 2057 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> 2058 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> 2059 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> 2060 </reg32> 2061 <reg32 offset="0x2" name="BUF_INFO"> 2062 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2063 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2064 <bitfield name="UNK10" pos="10"/> 2065 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2066 </reg32> 2067 <!-- 2068 at least in gmem, things seem to be aligned to pitch of 64.. 2069 maybe an artifact of tiled format used in gmem? 2070 --> 2071 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/> 2072 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/> 2073 <!-- 2074 Compared to a5xx and before, we configure both a GMEM base and 2075 external base. Not sure if this is to facilitate GMEM save/ 2076 restore for context switch, or just to simplify state setup to 2077 not have to care about GMEM vs BYPASS mode. 2078 --> 2079 <!-- maybe something in low bits since alignment of 1 doesn't make sense? --> 2080 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/> 2081 2082 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> 2083 </array> 2084 2085 <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/> 2086 <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/> 2087 <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/> 2088 <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/> 2089 <reg32 offset="0x8864" name="RB_ALPHA_CONTROL"> 2090 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> 2091 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 2092 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> 2093 </reg32> 2094 <reg32 offset="0x8865" name="RB_BLEND_CNTL"> 2095 <!-- per-mrt enable bit --> 2096 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 2097 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> 2098 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 2099 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 2100 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/> 2101 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 2102 </reg32> 2103 <!-- 0x8866-0x886f invalid --> 2104 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL"> 2105 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 2106 </reg32> 2107 2108 <reg32 offset="0x8871" name="RB_DEPTH_CNTL"> 2109 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 2110 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> 2111 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> 2112 <bitfield name="Z_CLIP_DISABLE" pos="5" type="boolean"/> 2113 <doc> 2114 Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER 2115 also set when Z_BOUNDS_ENABLE is set 2116 </doc> 2117 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 2118 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 2119 </reg32> 2120 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 2121 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO"> 2122 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 2123 <bitfield name="UNK3" low="3" high="4"/> 2124 </reg32> 2125 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/> 2126 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/> 2127 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/> 2128 <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/> 2129 2130 <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/> 2131 <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/> 2132 <!-- 0x887a-0x887f invalid --> 2133 <reg32 offset="0x8880" name="RB_STENCIL_CONTROL"> 2134 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 2135 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> 2136 <!-- 2137 set for stencil operations that require read from stencil 2138 buffer, but not for example for stencil clear (which does 2139 not require read).. so guessing this is analogous to 2140 READ_DEST_ENABLE for color buffer.. 2141 --> 2142 <bitfield name="STENCIL_READ" pos="2" type="boolean"/> 2143 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> 2144 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> 2145 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> 2146 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> 2147 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> 2148 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> 2149 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 2150 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 2151 </reg32> 2152 <reg32 offset="0x8881" name="RB_STENCIL_INFO"> 2153 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2154 <bitfield name="UNK1" pos="1" type="boolean"/> 2155 </reg32> 2156 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/> 2157 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/> 2158 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/> 2159 <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/> 2160 <reg32 offset="0x8887" name="RB_STENCILREF"> 2161 <bitfield name="REF" low="0" high="7"/> 2162 <bitfield name="BFREF" low="8" high="15"/> 2163 </reg32> 2164 <reg32 offset="0x8888" name="RB_STENCILMASK"> 2165 <bitfield name="MASK" low="0" high="7"/> 2166 <bitfield name="BFMASK" low="8" high="15"/> 2167 </reg32> 2168 <reg32 offset="0x8889" name="RB_STENCILWRMASK"> 2169 <bitfield name="WRMASK" low="0" high="7"/> 2170 <bitfield name="BFWRMASK" low="8" high="15"/> 2171 </reg32> 2172 <!-- 0x888a-0x888f invalid --> 2173 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/> 2174 <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL"> 2175 <bitfield name="DISABLE" pos="0" type="boolean"/> 2176 <bitfield name="COPY" pos="1" type="boolean"/> 2177 </reg32> 2178 <!-- 0x8892-0x8897 invalid --> 2179 <reg32 offset="0x8898" name="RB_LRZ_CNTL"> 2180 <bitfield name="ENABLE" pos="0" type="boolean"/> 2181 </reg32> 2182 <!-- 0x8899-0x88bf invalid --> 2183 <!-- clamps depth value for depth test/write --> 2184 <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/> 2185 <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/> 2186 <!-- 0x88c2-0x88cf invalid--> 2187 <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"> 2188 <bitfield name="UNK0" low="0" high="12"/> 2189 <bitfield name="UNK16" low="16" high="26"/> 2190 </reg32> 2191 <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/> 2192 <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/> 2193 <!-- weird to duplicate other regs from same block?? --> 2194 <reg32 offset="0x88d3" name="RB_BIN_CONTROL2"> 2195 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2196 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2197 </reg32> 2198 <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/> 2199 <reg32 offset="0x88d5" name="RB_MSAA_CNTL"> 2200 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2201 </reg32> 2202 <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/> 2203 <!-- s/DST_FORMAT/DST_INFO/ probably: --> 2204 <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO"> 2205 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 2206 <bitfield name="FLAGS" pos="2" type="boolean"/> 2207 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2208 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> 2209 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/> 2210 <bitfield name="UNK15" pos="15" type="boolean"/> 2211 </reg32> 2212 <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/> 2213 <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/> 2214 <!-- array-pitch is size of layer --> 2215 <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/> 2216 <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/> 2217 <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH"> 2218 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2219 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 2220 </reg32> 2221 2222 <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/> 2223 <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/> 2224 <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/> 2225 <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/> 2226 2227 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> 2228 <reg32 offset="0x88e3" name="RB_BLIT_INFO"> 2229 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? --> 2230 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? --> 2231 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> 2232 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> 2233 <doc> 2234 For clearing depth/stencil 2235 1 - depth 2236 2 - stencil 2237 3 - depth+stencil 2238 For clearing color buffer: 2239 then probably a component mask, I always see 0xf 2240 </doc> 2241 <bitfield name="CLEAR_MASK" low="4" high="7"/> 2242 <!-- set when this is the last resolve on a650+ --> 2243 <bitfield name="LAST" low="8" high="9"/> 2244 <!-- 2245 a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 2246 a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise. 2247 2248 We believe this is related to concurrent resolves 2249 --> 2250 <bitfield name="BUFFER_ID" low="12" high="15"/> 2251 </reg32> 2252 <!-- 0x88e4-0x88ef invalid --> 2253 <!-- always 0x0 ? --> 2254 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/> 2255 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 2256 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/> 2257 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH"> 2258 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2259 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> 2260 </reg32> 2261 <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/> 2262 <!-- 0x88f5-0x88ff invalid --> 2263 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/> 2264 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH"> 2265 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/> 2266 <!-- TODO: actually part of array pitch --> 2267 <bitfield name="UNK8" low="8" high="10"/> 2268 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 2269 </reg32> 2270 <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8"> 2271 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 2272 <reg32 offset="2" name="PITCH"> 2273 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2274 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 2275 </reg32> 2276 </array> 2277 <!-- 0x891b-0x8926 invalid --> 2278 <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/> 2279 <!-- 0x8929-0x89ff invalid --> 2280 2281 <!-- TODO: there are some registers in the 0x8a00-0x8bff range --> 2282 2283 <!-- 2284 These show up in a6xx gen3+ but so far haven't found an example of 2285 blob writing non-zero: 2286 --> 2287 <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00"/> 2288 <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10"/> 2289 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20"/> 2290 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30"/> 2291 2292 <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/> 2293 <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/> 2294 2295 <bitset name="a6xx_2d_surf_info" inline="yes"> 2296 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2297 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2298 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 2299 <bitfield name="FLAGS" pos="12" type="boolean"/> 2300 <bitfield name="SRGB" pos="13" type="boolean"/> 2301 <!-- the rest is only for src --> 2302 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 2303 <bitfield name="FILTER" pos="16" type="boolean"/> 2304 <bitfield name="UNK17" pos="17" type="boolean"/> 2305 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/> 2306 <bitfield name="UNK19" pos="19" type="boolean"/> 2307 <bitfield name="UNK20" pos="20" type="boolean"/> 2308 <bitfield name="UNK21" pos="21" type="boolean"/> 2309 <bitfield name="UNK22" pos="22" type="boolean"/> 2310 <bitfield name="UNK23" low="23" high="26"/> 2311 <bitfield name="UNK28" pos="28" type="boolean"/> 2312 </bitset> 2313 2314 <!-- 0x8c02-0x8c16 invalid --> 2315 <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) --> 2316 <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/> 2317 <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/> 2318 <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/> 2319 <!-- this is a guess but seems likely (for NV12/IYUV): --> 2320 <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64"/> 2321 <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/> 2322 <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/> 2323 2324 <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/> 2325 <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/> 2326 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 2327 <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64"/> 2328 <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint"/> 2329 2330 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> 2331 <!-- unlike a5xx, these are per channel values rather than packed --> 2332 <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/> 2333 <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/> 2334 <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/> 2335 <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/> 2336 <!-- 0x8c34-0x8dff invalid --> 2337 2338 <!-- always 0x1 ? either doesn't exist for a650 or write-only: --> 2339 <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/> 2340 <!-- 0x8e00-0x8e03 invalid --> 2341 <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff --> 2342 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 2343 <!-- 0x8e06 invalid --> 2344 <reg32 offset="0x8e07" name="RB_CCU_CNTL"> 2345 <!-- GMEM offset of CCU color cache 2346 for GMEM rendering, we set it to GMEM size minus the minimum 2347 CCU color cache size. CCU color cache will be needed in some 2348 resolve cases, and in those cases we need to reserve the end 2349 of GMEM for color cache. 2350 --> 2351 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2352 <!-- GMEM offset of CCU depth cache --> 2353 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2354 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path --> 2355 <!-- concurrent resolves are apparently a 2-bit enum on a650+ --> 2356 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 2357 <!--TODO: valid mask 0xfffffc1f --> 2358 </reg32> 2359 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"> 2360 <bitfield name="MODE" pos="0" type="boolean"/> 2361 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 2362 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 2363 <bitfield name="AMSBC" pos="4" type="boolean"/> 2364 <bitfield name="UPPER_BIT" pos="10" type="uint"/> 2365 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/> 2366 <bitfield name="UNK12" low="12" high="13"/> 2367 </reg32> 2368 <!-- 0x8e09-0x8e0f invalid --> 2369 <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 2370 <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 2371 <!-- 0x8e1d-0x8e1f invalid --> 2372 <!-- 0x8e20-0x8e25 more perfcntr sel? --> 2373 <!-- 0x8e26-0x8e27 invalid --> 2374 <reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/> 2375 <!-- 0x8e29-0x8e2b invalid --> 2376 <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/> 2377 <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/> 2378 <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> 2379 <!-- 0x8e3e-0x8e4f invalid --> 2380 <!-- GMEM save/restore for preemption: --> 2381 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/> 2382 <!-- address for GMEM save/restore? --> 2383 <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/> 2384 <!-- 0x8e53-0x8e7f invalid --> 2385 <!-- 0x8e80-0x8e83 are valid --> 2386 <!-- 0x8e84-0x90ff invalid --> 2387 2388 <!-- 0x9000-0x90ff invalid --> 2389 2390 <reg32 offset="0x9100" name="VPC_GS_PARAM"> 2391 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/> 2392 </reg32> 2393 2394 <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes"> 2395 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/> 2396 <!-- there can be up to 8 total clip/cull distance outputs, 2397 but apparenly VPC can only deal with vec4, so when there are 2398 more than 4 outputs a second location needs to be programmed 2399 --> 2400 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 2401 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 2402 </bitset> 2403 <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/> 2404 <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/> 2405 <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl"/> 2406 2407 <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes"> 2408 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> 2409 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> 2410 </bitset> 2411 2412 <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/> 2413 <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/> 2414 <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/> 2415 2416 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"> 2417 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused --> 2418 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 2419 <bitfield name="UNK2" pos="2" type="boolean"/> 2420 </reg32> 2421 <reg32 offset="0x9108" name="VPC_POLYGON_MODE"> 2422 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2423 </reg32> 2424 <!-- 0x9109-0x91ff invalid --> 2425 <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8"> 2426 <reg32 offset="0x0" name="MODE"/> 2427 </array> 2428 <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8"> 2429 <reg32 offset="0x0" name="MODE"/> 2430 </array> 2431 2432 <!-- always 0x0 --> 2433 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31"/> 2434 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31"/> 2435 2436 <array offset="0x9212" name="VPC_VAR" stride="1" length="4"> 2437 <!-- one bit per varying component: --> 2438 <reg32 offset="0" name="DISABLE"/> 2439 </array> 2440 2441 <reg32 offset="0x9216" name="VPC_SO_CNTL"> 2442 <!-- 2443 Choose which DWORD to write to. There is an array of 2444 (4 * 64) DWORD's, dumped in the devcoredump at 2445 HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a 2446 (VPC location, stream) pair like so: 2447 2448 location 0, stream 0 2449 location 2, stream 0 2450 ... 2451 location 126, stream 0 2452 location 0, stream 1 2453 location 2, stream 1 2454 ... 2455 location 126, stream 1 2456 location 0, stream 2 2457 ... 2458 2459 When EmitStreamVertex(N) happens, the HW goes to DWORD 2460 64 * N and then "executes" the next 64 DWORD's. 2461 2462 This field is auto-incremented when VPC_SO_PROG is 2463 written to. 2464 --> 2465 <bitfield name="ADDR" low="0" high="7" type="hex"/> 2466 <!-- clear all A_EN and B_EN bits for all DWORD's --> 2467 <bitfield name="RESET" pos="16" type="boolean"/> 2468 </reg32> 2469 <!-- special register, write multiple times to load SO program (not readable) --> 2470 <reg32 offset="0x9217" name="VPC_SO_PROG"> 2471 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 2472 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 2473 <bitfield name="A_EN" pos="11" type="boolean"/> 2474 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 2475 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 2476 <bitfield name="B_EN" pos="23" type="boolean"/> 2477 </reg32> 2478 2479 <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/> 2480 2481 <array offset="0x921a" name="VPC_SO" stride="7" length="4"> 2482 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 2483 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 2484 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 2485 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 2486 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 2487 </array> 2488 2489 <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT"> 2490 <bitfield name="INVERT" pos="0" type="boolean"/> 2491 </reg32> 2492 <!-- 0x9237-0x92ff invalid --> 2493 <!-- always 0x0 ? --> 2494 <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2"/> 2495 2496 <bitset name="a6xx_vpc_xs_pack" inline="yes"> 2497 <doc> 2498 num of varyings plus four for gl_Position (plus one if gl_PointSize) 2499 plus # of transform-feedback (streamout) varyings if using the 2500 hw streamout (rather than stg instructions in shader) 2501 </doc> 2502 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 2503 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> 2504 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> 2505 <bitfield name="EXTRAPOS" low="24" high="27" type="uint"> 2506 <doc> 2507 The number of extra copies of POSITION, i.e. 2508 number of views minus one when multi-position 2509 output is enabled, otherwise 0. 2510 </doc> 2511 </bitfield> 2512 </bitset> 2513 <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/> 2514 <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/> 2515 <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack"/> 2516 2517 <reg32 offset="0x9304" name="VPC_CNTL_0"> 2518 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 2519 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 2520 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> 2521 <bitfield name="VARYING" pos="16" type="boolean"/> 2522 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint"> 2523 <doc> 2524 This VPC location will be overwritten with 2525 ViewID when multiview is enabled. It's used when 2526 fragment shaders read ViewID. It's only 2527 strictly required for multi-position output, 2528 where the same VS invocation is used for all the 2529 views at once, but it can be used when multi-pos 2530 output is disabled too, to avoid having to pass 2531 ViewID through the VS. 2532 </doc> 2533 </bitfield> 2534 </reg32> 2535 2536 <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL"> 2537 <!-- 2538 It's offset by 1, and 0 means "disabled" 2539 --> 2540 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/> 2541 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/> 2542 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 2543 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 2544 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2545 </reg32> 2546 <reg32 offset="0x9306" name="VPC_SO_DISABLE"> 2547 <bitfield name="DISABLE" pos="0" type="boolean"/> 2548 </reg32> 2549 <!-- 0x9307-0x95ff invalid --> 2550 2551 <!-- TODO: 0x9600-0x97ff range --> 2552 <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 2553 <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 2554 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? --> 2555 <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/> 2556 <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6"/> 2557 <!-- 0x960a-0x9623 invalid --> 2558 <!-- TODO: regs from 0x9624-0x963a --> 2559 <!-- 0x963b-0x97ff invalid --> 2560 2561 <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/> 2562 2563 <!-- always 0x0 ? --> 2564 <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE"> 2565 <bitfield name="SIZE" low="0" high="10" type="uint"/> 2566 <bitfield name="UNK13" pos="13"/> 2567 </reg32> 2568 2569 <enum name="a6xx_tess_spacing"> 2570 <value value="0x0" name="TESS_EQUAL"/> 2571 <value value="0x2" name="TESS_FRACTIONAL_ODD"/> 2572 <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> 2573 </enum> 2574 <enum name="a6xx_tess_output"> 2575 <value value="0x0" name="TESS_POINTS"/> 2576 <value value="0x1" name="TESS_LINES"/> 2577 <value value="0x2" name="TESS_CW_TRIS"/> 2578 <value value="0x3" name="TESS_CCW_TRIS"/> 2579 </enum> 2580 <reg32 offset="0x9802" name="PC_TESS_CNTL"> 2581 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 2582 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 2583 </reg32> 2584 2585 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/> 2586 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/> 2587 2588 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2"/> 2589 2590 <!-- probably a mirror of VFD_CONTROL_6 --> 2591 <reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/> 2592 2593 <!-- New in a6xx gen3+ --> 2594 <reg32 offset="0x9808" name="PC_SO_STREAM_CNTL"> 2595 <bitfield name="STREAM_ENABLE" pos="15" type="boolean"/> 2596 </reg32> 2597 2598 <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL"> 2599 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 2600 </reg32> 2601 <!-- 0x980b-0x983f invalid --> 2602 2603 <!-- 0x9840 - 0x9842 are not readable --> 2604 <reg32 offset="0x9840" name="PC_DRAW_CMD"> 2605 <bitfield name="STATE_ID" low="0" high="7"/> 2606 </reg32> 2607 2608 <reg32 offset="0x9841" name="PC_DISPATCH_CMD"> 2609 <bitfield name="STATE_ID" low="0" high="7"/> 2610 </reg32> 2611 2612 <reg32 offset="0x9842" name="PC_EVENT_CMD"> 2613 <!-- I think only the low bit is actually used? --> 2614 <bitfield name="STATE_ID" low="16" high="23"/> 2615 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 2616 </reg32> 2617 2618 <!-- 2619 0x9880 written in a lot of places by SQE, same value gets written 2620 to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after 2621 that 2622 --> 2623 <reg32 offset="0x9880" name="PC_MARKER"/> 2624 2625 <!-- 0x9843-0x997f invalid --> 2626 2627 <reg32 offset="0x9981" name="PC_POLYGON_MODE"> 2628 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2629 </reg32> 2630 2631 <reg32 offset="0x9980" name="PC_RASTER_CNTL"> 2632 <!-- which stream to send to GRAS --> 2633 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2634 <!-- discard primitives before rasterization --> 2635 <bitfield name="DISCARD" pos="2" type="boolean"/> 2636 </reg32> 2637 2638 <!-- 0x9982-0x9aff invalid --> 2639 2640 <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0"> 2641 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 2642 <!-- maybe? b1 seems always set, so just assume it is for now: --> 2643 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> 2644 <bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/> 2645 <bitfield name="UNK3" pos="3" type="boolean"/> 2646 </reg32> 2647 2648 <bitset name="a6xx_xs_out_cntl" inline="yes"> 2649 <doc> 2650 num of varyings plus four for gl_Position (plus one if gl_PointSize) 2651 plus # of transform-feedback (streamout) varyings if using the 2652 hw streamout (rather than stg instructions in shader) 2653 </doc> 2654 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 2655 <bitfield name="PSIZE" pos="8" type="boolean"/> 2656 <bitfield name="LAYER" pos="9" type="boolean"/> 2657 <bitfield name="VIEW" pos="10" type="boolean"/> 2658 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit --> 2659 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 2660 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 2661 </bitset> 2662 2663 <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/> 2664 <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/> 2665 <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2666 <reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl"/> 2667 <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/> 2668 2669 <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5"> 2670 <doc> 2671 geometry shader 2672 </doc> 2673 <!-- TODO: first 16 bits are valid so something is wrong or missing here --> 2674 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/> 2675 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/> 2676 <bitfield name="LINELENGTHEN" pos="15" type="boolean"/> 2677 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/> 2678 <bitfield name="UNK18" pos="18"/> 2679 </reg32> 2680 2681 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6"> 2682 <doc> 2683 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC 2684 </doc> 2685 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 2686 </reg32> 2687 2688 <bitset name="a6xx_multiview_cntl" inline="yes"> 2689 <bitfield name="ENABLE" pos="0" type="boolean"/> 2690 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> 2691 <doc> 2692 Multi-position output lets the last geometry 2693 stage shader write multiple copies of 2694 gl_Position. If disabled then the VS is run once 2695 for each view, and ViewID is passed as a 2696 register to the VS. 2697 </doc> 2698 </bitfield> 2699 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 2700 </bitset> 2701 2702 <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/> 2703 <!-- mask of enabled views, doesn't exist on A630 --> 2704 <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15"/> 2705 <!-- 0x9b09-0x9bff invalid --> 2706 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 2707 <!-- special register (but note first 8 bits can be written/read) --> 2708 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 2709 <bitfield name="STATE_ID" low="8" high="15"/> 2710 </reg32> 2711 <!-- 0x9c01-0x9dff invalid --> 2712 <!-- TODO: 0x9e00-0xa000 range incomplete --> 2713 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 2714 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2715 <reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/> 2716 <reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/> 2717 <reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/> 2718 <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/> 2719 2720 <reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx"> 2721 <doc> 2722 Possibly not really "initiating" the draw but the layout is similar 2723 to VGT_DRAW_INITIATOR on older gens 2724 </doc> 2725 </reg32> 2726 <reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/> 2727 <reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/> 2728 2729 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 2730 <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL"> 2731 <bitfield name="UNK0" low="0" high="15"/> 2732 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 2733 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 2734 </reg32> 2735 <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/> 2736 <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/> 2737 2738 <reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE"> 2739 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 2740 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 2741 </reg32> 2742 2743 <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8"/> 2744 2745 <!-- always 0x0 --> 2746 <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/> 2747 2748 <reg32 offset="0xa000" name="VFD_CONTROL_0"> 2749 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> 2750 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> 2751 </reg32> 2752 <reg32 offset="0xa001" name="VFD_CONTROL_1"> 2753 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> 2754 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> 2755 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> 2756 <!-- only used for VS in non-multi-position-output case --> 2757 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> 2758 </reg32> 2759 <reg32 offset="0xa002" name="VFD_CONTROL_2"> 2760 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> 2761 <doc> 2762 This is the ID of the current patch within the 2763 subdraw, used to calculate the offset of the 2764 patch within the HS->DS buffers. When a draw is 2765 split into multiple subdraws then this differs 2766 from gl_PrimitiveID on the second, third, etc. 2767 subdraws. 2768 </doc> 2769 </bitfield> 2770 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> 2771 </reg32> 2772 <reg32 offset="0xa003" name="VFD_CONTROL_3"> 2773 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> 2774 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> 2775 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> 2776 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> 2777 </reg32> 2778 <reg32 offset="0xa004" name="VFD_CONTROL_4"> 2779 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/> 2780 </reg32> 2781 <reg32 offset="0xa005" name="VFD_CONTROL_5"> 2782 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> 2783 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/> 2784 </reg32> 2785 <reg32 offset="0xa006" name="VFD_CONTROL_6"> 2786 <!-- 2787 True if gl_PrimitiveID is read via the FS and there is 2788 no matching write from the GS, and therefore it needs to 2789 be passed through via fixed-function logic. 2790 --> 2791 <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/> 2792 </reg32> 2793 2794 <reg32 offset="0xa007" name="VFD_MODE_CNTL"> 2795 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> 2796 </reg32> 2797 2798 <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl"/> 2799 <reg32 offset="0xa009" name="VFD_ADD_OFFSET"> 2800 <!-- add VFD_INDEX_OFFSET to REGID4VTX --> 2801 <bitfield name="VERTEX" pos="0" type="boolean"/> 2802 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> 2803 <bitfield name="INSTANCE" pos="1" type="boolean"/> 2804 </reg32> 2805 2806 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/> 2807 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/> 2808 <array offset="0xa010" name="VFD_FETCH" stride="4" length="32"> 2809 <reg64 offset="0x0" name="BASE" type="address" align="1"/> 2810 <reg32 offset="0x2" name="SIZE" type="uint"/> 2811 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> 2812 </array> 2813 <array offset="0xa090" name="VFD_DECODE" stride="2" length="32"> 2814 <reg32 offset="0x0" name="INSTR"> 2815 <!-- IDX and byte OFFSET into VFD_FETCH --> 2816 <bitfield name="IDX" low="0" high="4" type="uint"/> 2817 <bitfield name="OFFSET" low="5" high="16"/> 2818 <bitfield name="INSTANCED" pos="17" type="boolean"/> 2819 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/> 2820 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> 2821 <bitfield name="UNK30" pos="30" type="boolean"/> 2822 <bitfield name="FLOAT" pos="31" type="boolean"/> 2823 </reg32> 2824 <reg32 offset="0x1" name="STEP_RATE" type="uint"/> 2825 </array> 2826 <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32"> 2827 <reg32 offset="0x0" name="INSTR"> 2828 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> 2829 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> 2830 </reg32> 2831 </array> 2832 2833 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2"/> 2834 2835 <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2836 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8"/> 2837 2838 <!-- 2839 Note: this seems to always be paired with another bit in another 2840 block. 2841 --> 2842 <enum name="a6xx_threadsize"> 2843 <value value="0" name="THREAD64"/> 2844 <value value="1" name="THREAD128"/> 2845 </enum> 2846 2847 <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes"> 2848 <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> 2849 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> 2850 <!-- 2851 When b31 set we just see FULLREGFOOTPRINT set. The pattern of 2852 used registers is a bit odd too: 2853 - used (half): 0-15 68-179 (cnt=128, max=179) 2854 - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127> 2855 whereas we usually see a (mostly) contiguous range of regs used. But if 2856 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)), 2857 then: 2858 - used (merged): 0-191 (cnt=192, max=191) 2859 So I think if b31 is set, then the half precision registers overlap 2860 the full precision registers. (Which seems like a pretty sensible 2861 feature, actually I'm not sure when you *wouldn't* want to use that, 2862 since it gives register allocation more flexibility) 2863 --> 2864 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/> 2865 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/> 2866 <!-- could it be a low bit of branchstack? --> 2867 <bitfield name="UNK13" pos="13" type="boolean"/> 2868 <!-- seems to be nesting level for flow control:.. --> 2869 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/> 2870 </bitset> 2871 2872 <bitset name="a6xx_sp_xs_config" inline="yes"> 2873 <!-- 2874 Each of these are set if the given resource type is used 2875 with the Vulkan/bindless binding model. 2876 --> 2877 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> 2878 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> 2879 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/> 2880 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> 2881 2882 <bitfield name="ENABLED" pos="8" type="boolean"/> 2883 <!-- 2884 number of textures and samplers.. these might be swapped, with GL I 2885 always see the same value for both. 2886 --> 2887 <bitfield name="NTEX" low="9" high="16" type="uint"/> 2888 <bitfield name="NSAMP" low="17" high="21" type="uint"/> 2889 <bitfield name="NIBO" low="22" high="28" type="uint"/> 2890 </bitset> 2891 2892 <bitset name="a6xx_sp_xs_prim_cntl" inline="yes"> 2893 <!-- # of VS outputs including pos/psize --> 2894 <bitfield name="OUT" low="0" high="5" type="uint"/> 2895 <!-- FLAGS_REGID only for GS --> 2896 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 2897 </bitset> 2898 2899 <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"> 2900 <!-- 2901 This field actually controls all geometry stages. TCS, TES, and 2902 GS must have the same mergedregs setting as VS. 2903 --> 2904 <bitfield name="MERGEDREGS" pos="20" type="boolean"/> 2905 <!-- 2906 Creates a separate preamble-only thread? 2907 2908 Early preamble has the following limitations: 2909 - Only shared, a1, and consts regs could be used 2910 (accessing other regs would result in GPU fault); 2911 - No cat5/cat6, only stc/ldc variants are working; 2912 - Values writen to shared regs are not accessible by the rest 2913 of the shader; 2914 - Instructions before shps are also considered to be a part of 2915 early preamble; 2916 2917 Note, for all shaders from d3d11 games blob produced preambles 2918 compatible with early preamble mode. 2919 --> 2920 <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/> 2921 </reg32> 2922 <!-- bitmask of true/false conditions for VS brac.N instructions, 2923 bit N corresponds to brac.N --> 2924 <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/> 2925 <!-- # of VS outputs including pos/psize --> 2926 <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/> 2927 <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16"> 2928 <reg32 offset="0x0" name="REG"> 2929 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2930 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 2931 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 2932 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 2933 </reg32> 2934 </array> 2935 <!-- 2936 Starting with a5xx, position/psize outputs from shader end up in the 2937 SP_VS_OUT map, with highest OUTLOCn position. (Generally they are 2938 the last entries too, except when gl_PointCoord is used, blob inserts 2939 an extra varying after, but with a lower OUTLOC position. If present, 2940 psize is last, preceded by position. 2941 --> 2942 <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8"> 2943 <reg32 offset="0x0" name="REG"> 2944 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2945 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 2946 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 2947 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 2948 </reg32> 2949 </array> 2950 2951 <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes"> 2952 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9"> 2953 <doc>The size of memory that ldp/stp can address.</doc> 2954 </bitfield> 2955 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31"> 2956 <doc> 2957 Seems to be the same as a3xx. The maximum stack 2958 size in units of 4 calls, so a call depth of 7 2959 would result in a value of 2. 2960 TODO: What's the actual size per call, i.e. the 2961 size of the PC? a3xx docs say it's 16 bits 2962 there, but the length register now takes 28 bits 2963 so it's probably been bumped to 32 bits. 2964 </doc> 2965 </bitfield> 2966 </bitset> 2967 2968 <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes"> 2969 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/> 2970 <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean"> 2971 <doc> 2972 There are four indices used to compute the 2973 private memory location for an access: 2974 2975 - stp/ldp offset 2976 - fiber id 2977 - wavefront id (a swizzled version of what "getwid" returns) 2978 - SP ID (the same as what "getspid" returns) 2979 2980 The stride for the SP ID is always set by 2981 TOTALPVTMEMSIZE. In the per-wave layout, the 2982 indices are used in this order: 2983 2984 - offset % 4 (offset within dword) 2985 - fiber id 2986 - offset / 4 2987 - wavefront id 2988 - SP ID 2989 2990 and the stride for the wavefront ID is 2991 MEMSIZEPERITEM, multiplied by 128 (fibers per 2992 wavefront). In the per-fiber layout, the indices 2993 are used in this order: 2994 2995 - offset 2996 - fiber id % 4 2997 - wavefront id 2998 - fiber id / 4 2999 - SP ID 3000 3001 and the stride for the fiber id/wavefront id 3002 combo is MEMSIZEPERITEM. 3003 3004 Note: Accesses of more than 1 dword do not work 3005 with per-fiber layout. The blob will fall back 3006 to per-wave instead. 3007 </doc> 3008 </bitfield> 3009 </bitset> 3010 3011 <bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes"> 3012 <doc> 3013 This seems to be be the equivalent of HWSTACKOFFSET in 3014 a3xx. The ldp/stp offset formula above isn't affected by 3015 HWSTACKSIZEPERTHREAD at all, so the HW return address 3016 stack seems to be after all the normal per-SP private 3017 memory. 3018 </doc> 3019 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 3020 </bitset> 3021 3022 <reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint"/> 3023 <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32"/> 3024 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/> 3025 <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/> 3026 <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/> 3027 <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint"/> 3028 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/> 3029 <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint"/> 3030 <reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/> 3031 3032 <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"> 3033 <!-- There is no mergedregs bit, that comes from the VS. --> 3034 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3035 </reg32> 3036 <!-- 3037 Total size of local storage in dwords divided by the wave size. 3038 The maximum value is 64. With the wave size being always 64 for HS, 3039 the maximum size of local storage should be: 3040 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k 3041 --> 3042 <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint"/> 3043 <reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex"/> 3044 3045 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3046 <reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint"/> 3047 <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32"/> 3048 <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/> 3049 <reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/> 3050 <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/> 3051 <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint"/> 3052 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/> 3053 <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint"/> 3054 <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/> 3055 3056 <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"> 3057 <!-- There is no mergedregs bit, that comes from the VS. --> 3058 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3059 </reg32> 3060 <reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/> 3061 3062 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3063 <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/> 3064 <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16"> 3065 <reg32 offset="0x0" name="REG"> 3066 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3067 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3068 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3069 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3070 </reg32> 3071 </array> 3072 <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8"> 3073 <reg32 offset="0x0" name="REG"> 3074 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3075 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3076 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3077 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3078 </reg32> 3079 </array> 3080 3081 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3082 <reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint"/> 3083 <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32"/> 3084 <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/> 3085 <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/> 3086 <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/> 3087 <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint"/> 3088 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/> 3089 <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint"/> 3090 <reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/> 3091 3092 <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"> 3093 <!-- There is no mergedregs bit, that comes from the VS. --> 3094 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3095 </reg32> 3096 <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint"> 3097 <doc> 3098 Normally the size of the output of the last stage in 3099 dwords. It should be programmed as follows: 3100 3101 size less than 63 - size 3102 size of 63 (?) or 64 - 63 3103 size greater than 64 - 64 3104 3105 What to program when the size is 61-63 is a guess, but 3106 both the blob and ir3 align the size to 4 dword's so it 3107 doesn't matter in practice. 3108 </doc> 3109 </reg32> 3110 <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex"/> 3111 3112 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3113 <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl"/> 3114 <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16"> 3115 <reg32 offset="0x0" name="REG"> 3116 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3117 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3118 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3119 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3120 </reg32> 3121 </array> 3122 3123 <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8"> 3124 <reg32 offset="0x0" name="REG"> 3125 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3126 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3127 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3128 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3129 </reg32> 3130 </array> 3131 3132 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3133 <reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint"/> 3134 <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32"/> 3135 <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/> 3136 <reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/> 3137 <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/> 3138 <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint"/> 3139 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/> 3140 <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint"/> 3141 <reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/> 3142 3143 <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16"/> 3144 <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16"/> 3145 <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16"/> 3146 <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16"/> 3147 <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64"/> 3148 <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64"/> 3149 <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64"/> 3150 <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64"/> 3151 3152 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> 3153 3154 <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"> 3155 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 3156 <bitfield name="UNK21" pos="21" type="boolean"/> 3157 <bitfield name="VARYING" pos="22" type="boolean"/> 3158 <bitfield name="DIFF_FINE" pos="23" type="boolean"/> 3159 <!-- note: vk blob uses bit24 --> 3160 <bitfield name="UNK24" pos="24" type="boolean"/> 3161 <bitfield name="UNK25" pos="25" type="boolean"/> 3162 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/> 3163 <bitfield name="UNK27" pos="27" type="boolean"/> 3164 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> 3165 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 3166 </reg32> 3167 <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/> 3168 <reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint"/> 3169 <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32"/> 3170 <reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/> 3171 <reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/> 3172 <reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/> 3173 3174 <reg32 offset="0xa989" name="SP_BLEND_CNTL"> 3175 <!-- per-mrt enable bit --> 3176 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 3177 <bitfield name="UNK8" pos="8" type="boolean"/> 3178 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 3179 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 3180 </reg32> 3181 <reg32 offset="0xa98a" name="SP_SRGB_CNTL"> 3182 <!-- Same as RB_SRGB_CNTL --> 3183 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 3184 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 3185 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 3186 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 3187 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 3188 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 3189 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 3190 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 3191 </reg32> 3192 <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS"> 3193 <bitfield name="RT0" low="0" high="3"/> 3194 <bitfield name="RT1" low="4" high="7"/> 3195 <bitfield name="RT2" low="8" high="11"/> 3196 <bitfield name="RT3" low="12" high="15"/> 3197 <bitfield name="RT4" low="16" high="19"/> 3198 <bitfield name="RT5" low="20" high="23"/> 3199 <bitfield name="RT6" low="24" high="27"/> 3200 <bitfield name="RT7" low="28" high="31"/> 3201 </reg32> 3202 <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0"> 3203 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 3204 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> 3205 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> 3206 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> 3207 </reg32> 3208 <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1"> 3209 <bitfield name="MRT" low="0" high="3" type="uint"/> 3210 </reg32> 3211 3212 <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8"> 3213 <doc>per MRT</doc> 3214 <reg32 offset="0x0" name="REG"> 3215 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> 3216 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> 3217 </reg32> 3218 </array> 3219 3220 <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8"> 3221 <reg32 offset="0" name="REG"> 3222 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 3223 <bitfield name="COLOR_SINT" pos="8" type="boolean"/> 3224 <bitfield name="COLOR_UINT" pos="9" type="boolean"/> 3225 <bitfield name="UNK10" pos="10" type="boolean"/> 3226 </reg32> 3227 </array> 3228 3229 <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL"> 3230 <!-- unknown bits 0x7fc0 always set --> 3231 <bitfield name="COUNT" low="0" high="2" type="uint"/> 3232 <!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? --> 3233 <bitfield name="UNK3" pos="3" type="boolean"/> 3234 <bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/> 3235 <bitfield name="UNK12" low="12" high="14"/> 3236 </reg32> 3237 <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4"> 3238 <reg32 offset="0" name="CMD"> 3239 <bitfield name="SRC" low="0" high="6" type="uint"/> 3240 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> 3241 <bitfield name="TEX_ID" low="11" high="15" type="uint"/> 3242 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/> 3243 <bitfield name="WRMASK" low="22" high="25" type="hex"/> 3244 <bitfield name="HALF" pos="26" type="boolean"/> 3245 <!-- 3246 CMD seems always 0x4?? 3d, textureProj, textureLod seem to 3247 skip pre-fetch.. TODO test texelFetch 3248 CMD is 0x6 when the Vulkan mode is enabled, and 3249 TEX_ID/SAMP_ID refer to the descriptor sets while the 3250 indices come from SP_FS_BINDLESS_PREFETCH[n] 3251 --> 3252 <bitfield name="CMD" low="27" high="31"/> 3253 </reg32> 3254 </array> 3255 <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4"> 3256 <reg32 offset="0" name="CMD"> 3257 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> 3258 <bitfield name="TEX_ID" low="16" high="31" type="uint"/> 3259 </reg32> 3260 </array> 3261 <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint"/> 3262 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" /> <!-- always 0x0 ? --> 3263 <reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/> 3264 3265 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 3266 3267 3268 3269 3270 <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"> 3271 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 3272 <!-- seems to make SP use less concurrent threads when possible? --> 3273 <bitfield name="UNK21" pos="21" type="boolean"/> 3274 <!-- has a small impact on performance, not clear what it does --> 3275 <bitfield name="UNK22" pos="22" type="boolean"/> 3276 <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/> 3277 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 3278 </reg32> 3279 3280 <!-- set for compute shaders --> 3281 <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1"> 3282 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> 3283 <doc> 3284 If 0 - all 32k of shared storage is enabled, otherwise 3285 (SHARED_SIZE + 1) * 1k is enabled. 3286 The ldl/stl offset seems to be rewritten to 0 when it is beyond 3287 this limit. This is different from ldlw/stlw, which wraps at 3288 64k (and has 36k of storage on A640 - reads between 36k-64k 3289 always return 0) 3290 </doc> 3291 </bitfield> 3292 <bitfield name="UNK5" pos="5" type="boolean"/> 3293 <!-- always 1 ? --> 3294 <bitfield name="UNK6" pos="6" type="boolean"/> 3295 </reg32> 3296 <reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex"/> 3297 <reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint"/> 3298 <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32"/> 3299 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/> 3300 <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32"/> 3301 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/> 3302 <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint"/> 3303 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/> 3304 <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint"/> 3305 <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset"/> 3306 3307 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 --> 3308 <reg32 offset="0xa9c2" name="SP_CS_CNTL_0"> 3309 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 3310 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 3311 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 3312 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 3313 </reg32> 3314 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 --> 3315 <reg32 offset="0xa9c3" name="SP_CS_CNTL_1"> 3316 <!-- gl_LocalInvocationIndex --> 3317 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 3318 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 3319 one of those 6 "SP cores" --> 3320 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 3321 <!-- Must match SP_CS_CTRL --> 3322 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 3323 <!-- 1 thread per wave (ignored if bit9 set) --> 3324 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 3325 </reg32> 3326 3327 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> 3328 3329 <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16"/> 3330 <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16"/> 3331 <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64"/> 3332 <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64"/> 3333 3334 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5"> 3335 <!-- TODO: probably align=64 with 6 flags bits in the low bits ? --> 3336 <reg64 offset="0" name="ADDR" type="address"/> 3337 </array> 3338 3339 <!-- 3340 IBO state for compute shader: 3341 --> 3342 <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/> 3343 <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/> 3344 3345 <!-- 3346 This enum is probably similar in purpose to SNORMMODE on a3xx, 3347 minus the snorm stuff, i.e. it controls what happens with an 3348 out-of-bounds isam/isamm. GL and Vulkan robustness require us to 3349 return 0 on out-of-bound textureFetch(). 3350 --> 3351 <enum name="a6xx_isam_mode"> 3352 <value value="0x2" name="ISAMMODE_GL"/> 3353 </enum> 3354 3355 <reg32 offset="0xab00" name="SP_MODE_CONTROL"> 3356 <!-- 3357 When set, half register loads from the constant file will 3358 load a 32-bit value (so hc0.y loads the same value as c0.y) 3359 and implicitly convert it to 16b (f2f16, or u2u16, based on 3360 operand type). When unset, half register loads from the 3361 constant file will load 16 bits from the packed constant 3362 file (so hc0.y loads the top 16 bits of the value of c0.x) 3363 --> 3364 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/> 3365 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/> 3366 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS --> 3367 </reg32> 3368 3369 <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/> 3370 <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint"/> 3371 3372 <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5"> 3373 <!-- TODO: probably align=64 with 6 flags bits in the low bits? --> 3374 <reg64 offset="0" name="ADDR" type="address"/> 3375 </array> 3376 3377 <!-- 3378 Combined IBO state for 3d pipe, used for Image and SSBO write/atomic 3379 instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders. 3380 --> 3381 <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16"/> 3382 <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint"/> 3383 3384 <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT"> 3385 <bitfield name="NORM" pos="0" type="boolean"/> 3386 <bitfield name="SINT" pos="1" type="boolean"/> 3387 <bitfield name="UINT" pos="2" type="boolean"/> 3388 <!-- looks like HW only cares about the base type of this format, 3389 which matches the ifmt? --> 3390 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> 3391 <!-- set when ifmt is R2D_UNORM8_SRGB --> 3392 <bitfield name="SRGB" pos="11" type="boolean"/> 3393 <!-- some sort of channel mask, not sure what it is for --> 3394 <bitfield name="MASK" low="12" high="15"/> 3395 </reg32> 3396 3397 <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/> 3398 <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 3399 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"> 3400 <!-- TODO: valid bits 0x3c3f, see kernel --> 3401 </reg32> 3402 <reg32 offset="0xae03" name="SP_CHICKEN_BITS"/> 3403 <reg32 offset="0xae04" name="SP_FLOAT_CNTL"> 3404 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 3405 </reg32> 3406 3407 <reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE"> 3408 <!-- some perfcntrs are affected by a per-stage enable bit 3409 (PERF_SP_ALU_WORKING_CYCLES for example) 3410 TODO: verify position of HS/DS/GS bits --> 3411 <bitfield name="VS" pos="0" type="boolean"/> 3412 <bitfield name="HS" pos="1" type="boolean"/> 3413 <bitfield name="DS" pos="2" type="boolean"/> 3414 <bitfield name="GS" pos="3" type="boolean"/> 3415 <bitfield name="FS" pos="4" type="boolean"/> 3416 <bitfield name="CS" pos="5" type="boolean"/> 3417 </reg32> 3418 <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/> 3419 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) --> 3420 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range --> 3421 <reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3422 3423 <!-- 3424 The downstream kernel calls the debug cluster of registers 3425 "a6xx_sp_ps_tp_cluster" but this actually specifies the border 3426 color base for compute shaders. 3427 --> 3428 <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/> 3429 <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2"/> 3430 <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23"/> 3431 3432 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 3433 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 3434 3435 <!-- could be all the stuff below here is actually TPL1?? --> 3436 3437 <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL"> 3438 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 3439 <bitfield name="UNK2" low="2" high="3"/> 3440 </reg32> 3441 <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL"> 3442 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 3443 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 3444 </reg32> 3445 3446 <!-- looks to work in the same way as a5xx: --> 3447 <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/> 3448 <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/> 3449 <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/> 3450 <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/> 3451 <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy"/> 3452 <reg32 offset="0xb309" name="SP_TP_MODE_CNTL"> 3453 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 3454 <bitfield name="UNK3" low="2" high="7"/> 3455 </reg32> 3456 3457 <!-- 3458 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either 3459 badly named or the functionality moved in a6xx. But downstream kernel 3460 calls this "a6xx_sp_ps_tp_2d_cluster" 3461 --> 3462 <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info"/> 3463 <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE"> 3464 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3465 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3466 </reg32> 3467 <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16"/> 3468 <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH"> 3469 <bitfield name="UNK0" low="0" high="8"/> 3470 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 3471 </reg32> 3472 3473 <!-- planes for NV12, etc. (TODO: not tested) --> 3474 <reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16"/> 3475 <reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint"/> 3476 <reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16"/> 3477 3478 <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16"/> 3479 <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/> 3480 3481 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31"/> 3482 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31"/> 3483 <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30"/> 3484 <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29"/> 3485 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy"/> 3486 3487 <!-- always 0x100000 or 0x1000000? --> 3488 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25"/> 3489 <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3490 <reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint"/> 3491 <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"> 3492 <bitfield name="MODE" pos="0" type="boolean"/> 3493 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 3494 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 3495 <bitfield name="UPPER_BIT" pos="4" type="uint"/> 3496 <bitfield name="UNK6" low="6" high="7"/> 3497 </reg32> 3498 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint"/> <!-- always 0x0 or 0x44 ? --> 3499 <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29"/> 3500 <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29"/> 3501 <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29"/> 3502 <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29"/> 3503 <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29"/> 3504 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/> 3505 3506 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 3507 3508 <bitset name="a6xx_hlsq_xs_cntl" inline="yes"> 3509 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> 3510 <bitfield name="ENABLED" pos="8" type="boolean"/> 3511 </bitset> 3512 3513 <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/> 3514 <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/> 3515 <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/> 3516 <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/> 3517 3518 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/> 3519 <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/> 3520 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> 3521 3522 <reg32 offset="0xb980" name="HLSQ_FS_CNTL_0"> 3523 <!-- must match SP_FS_CTRL --> 3524 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> 3525 <bitfield name="VARYINGS" pos="1" type="boolean"/> 3526 <bitfield name="UNK2" low="2" high="11"/> 3527 </reg32> 3528 <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean"/> <!-- never used by blob --> 3529 3530 <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2"> 3531 <!-- TODO: have test cases with either 0x3 or 0x7 --> 3532 </reg32> 3533 <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG"> 3534 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 3535 <!-- SAMPLEID is loaded into a half-precision register: --> 3536 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 3537 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 3538 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 3539 </reg32> 3540 <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG"> 3541 <!-- register loaded with position (bary.f) --> 3542 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> 3543 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> 3544 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> 3545 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> 3546 </reg32> 3547 <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG"> 3548 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> 3549 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> 3550 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> 3551 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> 3552 </reg32> 3553 <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG"> 3554 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> 3555 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> 3556 </reg32> 3557 <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/> 3558 3559 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 3560 <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0"> 3561 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 3562 <!-- localsize is value minus one: --> 3563 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3564 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3565 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 3566 </reg32> 3567 <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1"> 3568 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 3569 </reg32> 3570 <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2"> 3571 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 3572 </reg32> 3573 <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3"> 3574 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 3575 </reg32> 3576 <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4"> 3577 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 3578 </reg32> 3579 <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5"> 3580 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 3581 </reg32> 3582 <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6"> 3583 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 3584 </reg32> 3585 <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0"> 3586 <!-- these are all vec3. first 3 need to be high regs 3587 WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0) 3588 WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID 3589 --> 3590 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 3591 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 3592 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 3593 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 3594 </reg32> 3595 <reg32 offset="0xb998" name="HLSQ_CS_CNTL_1"> 3596 <!-- gl_LocalInvocationIndex --> 3597 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 3598 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 3599 one of those 6 "SP cores" --> 3600 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 3601 <!-- Must match SP_CS_CTRL --> 3602 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 3603 <!-- 1 thread per wave (ignored if bit9 set) --> 3604 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 3605 </reg32> 3606 <!--note: vulkan blob doesn't use these --> 3607 <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/> 3608 <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/> 3609 <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/> 3610 3611 <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/> 3612 <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/> 3613 <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/> 3614 3615 <!-- mirror of SP_CS_BINDLESS_BASE --> 3616 <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5"> 3617 <!-- 64 alignment, 2 low bits for unknown flags (always 0x3 when enabled?) --> 3618 <reg64 offset="0" name="ADDR" type="waddress"/> 3619 </array> 3620 3621 <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? --> 3622 <reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0"> 3623 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> 3624 <bitfield name="UNK5" pos="5" type="boolean"/> 3625 <!-- always 1 ? --> 3626 <bitfield name="UNK6" pos="6" type="boolean"/> 3627 </reg32> 3628 3629 <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD"> 3630 <bitfield name="STATE_ID" low="0" high="7"/> 3631 </reg32> 3632 3633 <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD"> 3634 <bitfield name="STATE_ID" low="0" high="7"/> 3635 </reg32> 3636 3637 <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD"> 3638 <!-- I think only the low bit is actually used? --> 3639 <bitfield name="STATE_ID" low="16" high="23"/> 3640 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3641 </reg32> 3642 3643 <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD"> 3644 <doc> 3645 This register clears pending loads queued up by 3646 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 3647 CP_LOAD_STATE6. 3648 </doc> 3649 3650 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 3651 <bitfield name="VS_STATE" pos="0" type="boolean"/> 3652 <bitfield name="HS_STATE" pos="1" type="boolean"/> 3653 <bitfield name="DS_STATE" pos="2" type="boolean"/> 3654 <bitfield name="GS_STATE" pos="3" type="boolean"/> 3655 <bitfield name="FS_STATE" pos="4" type="boolean"/> 3656 <bitfield name="CS_STATE" pos="5" type="boolean"/> 3657 3658 <bitfield name="CS_IBO" pos="6" type="boolean"/> 3659 <bitfield name="GFX_IBO" pos="7" type="boolean"/> 3660 3661 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> 3662 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> 3663 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/> 3664 3665 <!-- SS6_BINDLESS: one bit per bindless base --> 3666 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/> 3667 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> 3668 </reg32> 3669 3670 <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/> 3671 3672 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS"> 3673 <doc> 3674 Shared constants are intended to be used for Vulkan push 3675 constants. When enabled, 8 vec4's are reserved in the FS 3676 const pool and 16 in the geometry const pool although 3677 only 8 are actually used (why?) and they are mapped to 3678 c504-c511 in each stage. Both VS and FS shared consts 3679 are written using ST6_CONSTANTS/SB6_IBO, so that both 3680 the geometry and FS shared consts can be written at once 3681 by using CP_LOAD_STATE6 rather than 3682 CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition 3683 DST_OFF and NUM_UNIT are in units of dwords instead of 3684 vec4's. 3685 3686 There is also a separate shared constant pool for CS, 3687 which is loaded through CP_LOAD_STATE6_FRAG with 3688 ST6_UBO/ST6_IBO. However the only real difference for CS 3689 is the dword units. 3690 </doc> 3691 <bitfield name="ENABLE" pos="0" type="boolean"/> 3692 </reg32> 3693 3694 <!-- mirror of SP_BINDLESS_BASE --> 3695 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5"> 3696 <!-- align 64 with two LSB for unknown flags (always 0x3 enabled) --> 3697 <reg64 offset="0" name="ADDR" type="address"/> 3698 </array> 3699 3700 <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD"> 3701 <bitfield name="STATE_ID" low="8" high="15"/> 3702 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3703 </reg32> 3704 3705 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/> <!-- all bits valid except bit 29 --> 3706 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6"/> 3707 <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/> 3708 <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3709 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/> 3710 <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 3711 3712 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 --> 3713 <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3714 3715 <!-- 3716 These special registers signal the beginning/end of an event 3717 sequence. The sequence used internally for an event looks like: 3718 - write EVENT_CMD pipe register 3719 - write CP_EVENT_START 3720 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD 3721 - write PC_EVENT_CMD with event or PC_DRAW_CMD 3722 - write HLSQ_EVENT_CMD(CONTEXT_DONE) 3723 - write PC_EVENT_CMD(CONTEXT_DONE) 3724 - write CP_EVENT_END 3725 Writing to CP_EVENT_END seems to actually trigger the context roll 3726 --> 3727 <reg32 offset="0xd600" name="CP_EVENT_START"> 3728 <bitfield name="STATE_ID" low="0" high="7"/> 3729 </reg32> 3730 <reg32 offset="0xd601" name="CP_EVENT_END"> 3731 <bitfield name="STATE_ID" low="0" high="7"/> 3732 </reg32> 3733 <reg32 offset="0xd700" name="CP_2D_EVENT_START"> 3734 <bitfield name="STATE_ID" low="0" high="7"/> 3735 </reg32> 3736 <reg32 offset="0xd701" name="CP_2D_EVENT_END"> 3737 <bitfield name="STATE_ID" low="0" high="7"/> 3738 </reg32> 3739</domain> 3740 3741<!-- Seems basically the same as a5xx, maybe move to common.xml.. --> 3742<domain name="A6XX_TEX_SAMP" width="32"> 3743 <doc>Texture sampler dwords</doc> 3744 <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 3745 <value name="A6XX_TEX_NEAREST" value="0"/> 3746 <value name="A6XX_TEX_LINEAR" value="1"/> 3747 <value name="A6XX_TEX_ANISO" value="2"/> 3748 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 3749 </enum> 3750 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 3751 <value name="A6XX_TEX_REPEAT" value="0"/> 3752 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 3753 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 3754 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 3755 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 3756 </enum> 3757 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 3758 <value name="A6XX_TEX_ANISO_1" value="0"/> 3759 <value name="A6XX_TEX_ANISO_2" value="1"/> 3760 <value name="A6XX_TEX_ANISO_4" value="2"/> 3761 <value name="A6XX_TEX_ANISO_8" value="3"/> 3762 <value name="A6XX_TEX_ANISO_16" value="4"/> 3763 </enum> 3764 <enum name="a6xx_reduction_mode"> 3765 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 3766 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 3767 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 3768 </enum> 3769 3770 <reg32 offset="0" name="0"> 3771 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> 3772 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> 3773 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> 3774 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> 3775 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> 3776 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> 3777 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> 3778 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> 3779 </reg32> 3780 <reg32 offset="1" name="1"> 3781 <bitfield name="CLAMPENABLE" pos="0" type="boolean"> 3782 <doc> 3783 clamp result to [0, 1] if the format is unorm or 3784 [-1, 1] if the format is snorm, *after* 3785 filtering. Has no effect for other formats. 3786 </doc> 3787 </bitfield> 3788 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> 3789 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> 3790 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> 3791 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> 3792 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> 3793 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> 3794 </reg32> 3795 <reg32 offset="2" name="2"> 3796 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/> 3797 <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/> 3798 <bitfield name="BCOLOR" low="7" high="31"/> 3799 </reg32> 3800 <reg32 offset="3" name="3"/> 3801</domain> 3802 3803<domain name="A6XX_TEX_CONST" width="32"> 3804 <doc>Texture constant dwords</doc> 3805 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 3806 <value name="A6XX_TEX_X" value="0"/> 3807 <value name="A6XX_TEX_Y" value="1"/> 3808 <value name="A6XX_TEX_Z" value="2"/> 3809 <value name="A6XX_TEX_W" value="3"/> 3810 <value name="A6XX_TEX_ZERO" value="4"/> 3811 <value name="A6XX_TEX_ONE" value="5"/> 3812 </enum> 3813 <enum name="a6xx_tex_type"> <!-- same as a4xx? --> 3814 <value name="A6XX_TEX_1D" value="0"/> 3815 <value name="A6XX_TEX_2D" value="1"/> 3816 <value name="A6XX_TEX_CUBE" value="2"/> 3817 <value name="A6XX_TEX_3D" value="3"/> 3818 <value name="A6XX_TEX_BUFFER" value="4"/> 3819 </enum> 3820 <reg32 offset="0" name="0"> 3821 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 3822 <bitfield name="SRGB" pos="2" type="boolean"/> 3823 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> 3824 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> 3825 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> 3826 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> 3827 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> 3828 <!-- overlaps with MIPLVLS --> 3829 <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/> 3830 <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/> 3831 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> 3832 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/> 3833 <!-- 3834 Why is the swap needed in addition to SWIZ_*? The swap 3835 is performed before border color replacement, while the 3836 swizzle is applied after after it. 3837 --> 3838 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> 3839 </reg32> 3840 <reg32 offset="1" name="1"> 3841 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3842 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3843 </reg32> 3844 <reg32 offset="2" name="2"> 3845 <!-- 3846 b4 and b31 set for buffer/ssbo case, in which case low 15 bits 3847 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT 3848 3849 b31 is probably the 'BUFFER' bit.. it is the one that changes 3850 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071 3851 --> 3852 <bitfield name="BUFFER" pos="4" type="boolean"/> 3853 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) --> 3854 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/> 3855 <doc>Pitch in bytes (so actually stride)</doc> 3856 <bitfield name="PITCH" low="7" high="28" type="uint"/> 3857 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 3858 </reg32> 3859 <reg32 offset="3" name="3"> 3860 <!-- 3861 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and 3862 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the 3863 layer size at the point that it stops being reduced moving to 3864 higher (smaller) mipmap levels 3865 --> 3866 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/> 3867 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> 3868 <!-- 3869 by default levels with w < 16 are linear 3870 TILE_ALL makes all levels have tiling 3871 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) 3872 --> 3873 <bitfield name="TILE_ALL" pos="27" type="boolean"/> 3874 <bitfield name="FLAG" pos="28" type="boolean"/> 3875 </reg32> 3876 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled) 3877 the address of the non-flag base buffer is determined automatically, 3878 and must follow the flag buffer 3879 --> 3880 <reg32 offset="4" name="4"> 3881 <bitfield name="BASE_LO" low="5" high="31" shr="5"/> 3882 </reg32> 3883 <reg32 offset="5" name="5"> 3884 <bitfield name="BASE_HI" low="0" high="16"/> 3885 <bitfield name="DEPTH" low="17" high="29" type="uint"/> 3886 </reg32> 3887 <reg32 offset="6" name="6"> 3888 <!-- overlaps with PLANE_PITCH --> 3889 <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/> 3890 <!-- pitch for plane 2 / plane 3 --> 3891 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/> 3892 </reg32> 3893 <!-- 7/8 is plane 2 address for planar formats --> 3894 <reg32 offset="7" name="7"> 3895 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> 3896 </reg32> 3897 <reg32 offset="8" name="8"> 3898 <bitfield name="FLAG_HI" low="0" high="16"/> 3899 </reg32> 3900 <!-- 9/10 is plane 3 address for planar formats --> 3901 <reg32 offset="9" name="9"> 3902 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> 3903 </reg32> 3904 <reg32 offset="10" name="10"> 3905 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> 3906 <!-- log2 size of the first level, required for mipmapping --> 3907 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> 3908 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> 3909 </reg32> 3910 <reg32 offset="11" name="11"/> 3911 <reg32 offset="12" name="12"/> 3912 <reg32 offset="13" name="13"/> 3913 <reg32 offset="14" name="14"/> 3914 <reg32 offset="15" name="15"/> 3915</domain> 3916 3917<domain name="A6XX_UBO" width="32"> 3918 <reg32 offset="0" name="0"> 3919 <bitfield name="BASE_LO" low="0" high="31"/> 3920 </reg32> 3921 <reg32 offset="1" name="1"> 3922 <bitfield name="BASE_HI" low="0" high="16"/> 3923 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units --> 3924 </reg32> 3925</domain> 3926 3927<domain name="A6XX_PDC" width="32"> 3928 <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> 3929 <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> 3930 <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/> 3931 <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/> 3932 <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/> 3933 <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/> 3934 <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/> 3935 <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/> 3936 <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/> 3937 <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/> 3938 <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/> 3939 <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/> 3940 <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/> 3941 <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/> 3942 <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/> 3943 <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/> 3944 <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/> 3945 <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/> 3946 <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/> 3947 <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/> 3948 <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/> 3949 <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/> 3950 <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/> 3951 <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/> 3952 <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/> 3953 <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/> 3954</domain> 3955 3956<domain name="A6XX_PDC_GPU_SEQ" width="32"> 3957 <reg32 offset="0x0" name="MEM_0"/> 3958</domain> 3959 3960<domain name="A6XX_CX_DBGC" width="32"> 3961 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A"> 3962 <bitfield high="7" low="0" name="PING_INDEX"/> 3963 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 3964 </reg32> 3965 <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/> 3966 <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/> 3967 <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/> 3968 <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT"> 3969 <bitfield high="5" low="0" name="TRACEEN"/> 3970 <bitfield high="14" low="12" name="GRANU"/> 3971 <bitfield high="31" low="28" name="SEGT"/> 3972 </reg32> 3973 <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM"> 3974 <bitfield high="27" low="24" name="ENABLE"/> 3975 </reg32> 3976 <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/> 3977 <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/> 3978 <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/> 3979 <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/> 3980 <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/> 3981 <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/> 3982 <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/> 3983 <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/> 3984 <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0"> 3985 <bitfield high="3" low="0" name="BYTEL0"/> 3986 <bitfield high="7" low="4" name="BYTEL1"/> 3987 <bitfield high="11" low="8" name="BYTEL2"/> 3988 <bitfield high="15" low="12" name="BYTEL3"/> 3989 <bitfield high="19" low="16" name="BYTEL4"/> 3990 <bitfield high="23" low="20" name="BYTEL5"/> 3991 <bitfield high="27" low="24" name="BYTEL6"/> 3992 <bitfield high="31" low="28" name="BYTEL7"/> 3993 </reg32> 3994 <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1"> 3995 <bitfield high="3" low="0" name="BYTEL8"/> 3996 <bitfield high="7" low="4" name="BYTEL9"/> 3997 <bitfield high="11" low="8" name="BYTEL10"/> 3998 <bitfield high="15" low="12" name="BYTEL11"/> 3999 <bitfield high="19" low="16" name="BYTEL12"/> 4000 <bitfield high="23" low="20" name="BYTEL13"/> 4001 <bitfield high="27" low="24" name="BYTEL14"/> 4002 <bitfield high="31" low="28" name="BYTEL15"/> 4003 </reg32> 4004 4005 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 4006 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 4007</domain> 4008 4009<domain name="A6XX_CX_MISC" width="32"> 4010 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> 4011 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> 4012</domain> 4013 4014</database> 4015