1# 2# Copyright (C) 2018 Red Hat 3# Copyright (C) 2014 Intel Corporation 4# 5# Permission is hereby granted, free of charge, to any person obtaining a 6# copy of this software and associated documentation files (the "Software"), 7# to deal in the Software without restriction, including without limitation 8# the rights to use, copy, modify, merge, publish, distribute, sublicense, 9# and/or sell copies of the Software, and to permit persons to whom the 10# Software is furnished to do so, subject to the following conditions: 11# 12# The above copyright notice and this permission notice (including the next 13# paragraph) shall be included in all copies or substantial portions of the 14# Software. 15# 16# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22# IN THE SOFTWARE. 23# 24 25# This file defines all the available intrinsics in one place. 26# 27# The Intrinsic class corresponds one-to-one with nir_intrinsic_info 28# structure. 29 30src0 = ('src', 0) 31src1 = ('src', 1) 32src2 = ('src', 2) 33src3 = ('src', 3) 34src4 = ('src', 4) 35 36class Index(object): 37 def __init__(self, c_data_type, name): 38 self.c_data_type = c_data_type 39 self.name = name 40 41class Intrinsic(object): 42 """Class that represents all the information about an intrinsic opcode. 43 NOTE: this must be kept in sync with nir_intrinsic_info. 44 """ 45 def __init__(self, name, src_components, dest_components, 46 indices, flags, sysval, bit_sizes): 47 """Parameters: 48 49 - name: the intrinsic name 50 - src_components: list of the number of components per src, 0 means 51 vectorized instruction with number of components given in the 52 num_components field in nir_intrinsic_instr. 53 - dest_components: number of destination components, -1 means no 54 dest, 0 means number of components given in num_components field 55 in nir_intrinsic_instr. 56 - indices: list of constant indicies 57 - flags: list of semantic flags 58 - sysval: is this a system-value intrinsic 59 - bit_sizes: allowed dest bit_sizes or the source it must match 60 """ 61 assert isinstance(name, str) 62 assert isinstance(src_components, list) 63 if src_components: 64 assert isinstance(src_components[0], int) 65 assert isinstance(dest_components, int) 66 assert isinstance(indices, list) 67 if indices: 68 assert isinstance(indices[0], Index) 69 assert isinstance(flags, list) 70 if flags: 71 assert isinstance(flags[0], str) 72 assert isinstance(sysval, bool) 73 if isinstance(bit_sizes, list): 74 assert not bit_sizes or isinstance(bit_sizes[0], int) 75 else: 76 assert isinstance(bit_sizes, tuple) 77 assert bit_sizes[0] == 'src' 78 assert isinstance(bit_sizes[1], int) 79 80 self.name = name 81 self.num_srcs = len(src_components) 82 self.src_components = src_components 83 self.has_dest = (dest_components >= 0) 84 self.dest_components = dest_components 85 self.num_indices = len(indices) 86 self.indices = indices 87 self.flags = flags 88 self.sysval = sysval 89 self.bit_sizes = bit_sizes if isinstance(bit_sizes, list) else [] 90 self.bit_size_src = bit_sizes[1] if isinstance(bit_sizes, tuple) else -1 91 92# 93# Possible flags: 94# 95 96CAN_ELIMINATE = "NIR_INTRINSIC_CAN_ELIMINATE" 97CAN_REORDER = "NIR_INTRINSIC_CAN_REORDER" 98 99INTR_INDICES = [] 100INTR_OPCODES = {} 101 102def index(c_data_type, name): 103 idx = Index(c_data_type, name) 104 INTR_INDICES.append(idx) 105 globals()[name.upper()] = idx 106 107# Defines a new NIR intrinsic. By default, the intrinsic will have no sources 108# and no destination. 109# 110# You can set dest_comp=n to enable a destination for the intrinsic, in which 111# case it will have that many components, or =0 for "as many components as the 112# NIR destination value." 113# 114# Set src_comp=n to enable sources for the intruction. It can be an array of 115# component counts, or (for convenience) a scalar component count if there's 116# only one source. If a component count is 0, it will be as many components as 117# the intrinsic has based on the dest_comp. 118def intrinsic(name, src_comp=[], dest_comp=-1, indices=[], 119 flags=[], sysval=False, bit_sizes=[]): 120 assert name not in INTR_OPCODES 121 INTR_OPCODES[name] = Intrinsic(name, src_comp, dest_comp, 122 indices, flags, sysval, bit_sizes) 123 124# 125# Possible indices: 126# 127 128# Generally instructions that take a offset src argument, can encode 129# a constant 'base' value which is added to the offset. 130index("int", "base") 131 132# For store instructions, a writemask for the store. 133index("unsigned", "write_mask") 134 135# The stream-id for GS emit_vertex/end_primitive intrinsics. 136index("unsigned", "stream_id") 137 138# The clip-plane id for load_user_clip_plane intrinsic. 139index("unsigned", "ucp_id") 140 141# The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative 142# to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't 143# have the implicit addition of a base to the offset. 144# 145# If the [range_base, range] is [0, ~0], then we don't know the possible 146# range of the access. 147index("unsigned", "range_base") 148 149# The amount of data, starting from BASE or RANGE_BASE, that this 150# instruction may access. This is used to provide bounds if the offset is 151# not constant. 152index("unsigned", "range") 153 154# The Vulkan descriptor set for vulkan_resource_index intrinsic. 155index("unsigned", "desc_set") 156 157# The Vulkan descriptor set binding for vulkan_resource_index intrinsic. 158index("unsigned", "binding") 159 160# Component offset 161index("unsigned", "component") 162 163# Column index for matrix system values 164index("unsigned", "column") 165 166# Interpolation mode (only meaningful for FS inputs) 167index("unsigned", "interp_mode") 168 169# A binary nir_op to use when performing a reduction or scan operation 170index("unsigned", "reduction_op") 171 172# Cluster size for reduction operations 173index("unsigned", "cluster_size") 174 175# Parameter index for a load_param intrinsic 176index("unsigned", "param_idx") 177 178# Image dimensionality for image intrinsics 179index("enum glsl_sampler_dim", "image_dim") 180 181# Non-zero if we are accessing an array image 182index("bool", "image_array") 183 184# Image format for image intrinsics 185index("enum pipe_format", "format") 186 187# Access qualifiers for image and memory access intrinsics. ACCESS_RESTRICT is 188# not set at the intrinsic if the NIR was created from SPIR-V. 189index("enum gl_access_qualifier", "access") 190 191# call index for split raytracing shaders 192index("unsigned", "call_idx") 193 194# The stack size increment/decrement for split raytracing shaders 195index("unsigned", "stack_size") 196 197# Alignment for offsets and addresses 198# 199# These two parameters, specify an alignment in terms of a multiplier and 200# an offset. The multiplier is always a power of two. The offset or 201# address parameter X of the intrinsic is guaranteed to satisfy the 202# following: 203# 204# (X - align_offset) % align_mul == 0 205# 206# For constant offset values, align_mul will be NIR_ALIGN_MUL_MAX and the 207# align_offset will be modulo that. 208index("unsigned", "align_mul") 209index("unsigned", "align_offset") 210 211# The Vulkan descriptor type for a vulkan_resource_[re]index intrinsic. 212index("unsigned", "desc_type") 213 214# The nir_alu_type of input data to a store or conversion 215index("nir_alu_type", "src_type") 216 217# The nir_alu_type of the data output from a load or conversion 218index("nir_alu_type", "dest_type") 219 220# The swizzle mask for quad_swizzle_amd & masked_swizzle_amd 221index("unsigned", "swizzle_mask") 222 223# Whether the load_buffer_amd/store_buffer_amd is swizzled 224index("bool", "is_swizzled") 225 226# The SLC ("system level coherent") bit of load_buffer_amd/store_buffer_amd 227index("bool", "slc_amd") 228 229# Offsets for load_shared2_amd/store_shared2_amd 230index("uint8_t", "offset0") 231index("uint8_t", "offset1") 232 233# If true, both offsets have an additional stride of 64 dwords (ie. they are multiplied by 256 bytes 234# in hardware, instead of 4). 235index("bool", "st64") 236 237# When set, range analysis will use it for nir_unsigned_upper_bound 238index("unsigned", "arg_upper_bound_u32_amd") 239 240# Separate source/dest access flags for copies 241index("enum gl_access_qualifier", "dst_access") 242index("enum gl_access_qualifier", "src_access") 243 244# Driver location of attribute 245index("unsigned", "driver_location") 246 247# Ordering and visibility of a memory operation 248index("nir_memory_semantics", "memory_semantics") 249 250# Modes affected by a memory operation 251index("nir_variable_mode", "memory_modes") 252 253# Scope of a memory operation 254index("nir_scope", "memory_scope") 255 256# Scope of a control barrier 257index("nir_scope", "execution_scope") 258 259# Semantics of an IO instruction 260index("struct nir_io_semantics", "io_semantics") 261 262# Transform feedback info 263index("struct nir_io_xfb", "io_xfb") 264index("struct nir_io_xfb", "io_xfb2") 265 266# Rounding mode for conversions 267index("nir_rounding_mode", "rounding_mode") 268 269# Whether or not to saturate in conversions 270index("unsigned", "saturate") 271 272# Whether or not trace_ray_intel is synchronous 273index("bool", "synchronous") 274 275intrinsic("nop", flags=[CAN_ELIMINATE]) 276 277intrinsic("convert_alu_types", dest_comp=0, src_comp=[0], 278 indices=[SRC_TYPE, DEST_TYPE, ROUNDING_MODE, SATURATE], 279 flags=[CAN_ELIMINATE, CAN_REORDER]) 280 281intrinsic("load_param", dest_comp=0, indices=[PARAM_IDX], flags=[CAN_ELIMINATE]) 282 283intrinsic("load_deref", dest_comp=0, src_comp=[-1], 284 indices=[ACCESS], flags=[CAN_ELIMINATE]) 285intrinsic("store_deref", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 286intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS]) 287intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS]) 288 289# Interpolation of input. The interp_deref_at* intrinsics are similar to the 290# load_var intrinsic acting on a shader input except that they interpolate the 291# input differently. The at_sample, at_offset and at_vertex intrinsics take an 292# additional source that is an integer sample id, a vec2 position offset, or a 293# vertex ID respectively. 294 295intrinsic("interp_deref_at_centroid", dest_comp=0, src_comp=[1], 296 flags=[ CAN_ELIMINATE, CAN_REORDER]) 297intrinsic("interp_deref_at_sample", src_comp=[1, 1], dest_comp=0, 298 flags=[CAN_ELIMINATE, CAN_REORDER]) 299intrinsic("interp_deref_at_offset", src_comp=[1, 2], dest_comp=0, 300 flags=[CAN_ELIMINATE, CAN_REORDER]) 301intrinsic("interp_deref_at_vertex", src_comp=[1, 1], dest_comp=0, 302 flags=[CAN_ELIMINATE, CAN_REORDER]) 303 304# Gets the length of an unsized array at the end of a buffer 305intrinsic("deref_buffer_array_length", src_comp=[-1], dest_comp=1, 306 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 307 308# Ask the driver for the size of a given SSBO. It takes the buffer index 309# as source. 310intrinsic("get_ssbo_size", src_comp=[-1], dest_comp=1, bit_sizes=[32], 311 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 312intrinsic("get_ubo_size", src_comp=[-1], dest_comp=1, 313 flags=[CAN_ELIMINATE, CAN_REORDER]) 314 315# Intrinsics which provide a run-time mode-check. Unlike the compile-time 316# mode checks, a pointer can only have exactly one mode at runtime. 317intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1, 318 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 319intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1, 320 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 321 322intrinsic("is_sparse_texels_resident", dest_comp=1, src_comp=[1], bit_sizes=[1,32], 323 flags=[CAN_ELIMINATE, CAN_REORDER]) 324# result code is resident only if both inputs are resident 325intrinsic("sparse_residency_code_and", dest_comp=1, src_comp=[1, 1], bit_sizes=[32], 326 flags=[CAN_ELIMINATE, CAN_REORDER]) 327 328# a barrier is an intrinsic with no inputs/outputs but which can't be moved 329# around/optimized in general 330def barrier(name): 331 intrinsic(name) 332 333barrier("discard") 334 335# Demote fragment shader invocation to a helper invocation. Any stores to 336# memory after this instruction are suppressed and the fragment does not write 337# outputs to the framebuffer. Unlike discard, demote needs to ensure that 338# derivatives will still work for invocations that were not demoted. 339# 340# As specified by SPV_EXT_demote_to_helper_invocation. 341barrier("demote") 342intrinsic("is_helper_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 343 344# SpvOpTerminateInvocation from SPIR-V. Essentially a discard "for real". 345barrier("terminate") 346 347# A workgroup-level control barrier. Any thread which hits this barrier will 348# pause until all threads within the current workgroup have also hit the 349# barrier. For compute shaders, the workgroup is defined as the local group. 350# For tessellation control shaders, the workgroup is defined as the current 351# patch. This intrinsic does not imply any sort of memory barrier. 352barrier("control_barrier") 353 354# Memory barrier with semantics analogous to the memoryBarrier() GLSL 355# intrinsic. 356barrier("memory_barrier") 357 358# Control/Memory barrier with explicit scope. Follows the semantics of SPIR-V 359# OpMemoryBarrier and OpControlBarrier, used to implement Vulkan Memory Model. 360# Storage that the barrier applies is represented using NIR variable modes. 361# For an OpMemoryBarrier, set EXECUTION_SCOPE to NIR_SCOPE_NONE. 362intrinsic("scoped_barrier", 363 indices=[EXECUTION_SCOPE, MEMORY_SCOPE, MEMORY_SEMANTICS, MEMORY_MODES]) 364 365# Shader clock intrinsic with semantics analogous to the clock2x32ARB() 366# GLSL intrinsic. 367# The latter can be used as code motion barrier, which is currently not 368# feasible with NIR. 369intrinsic("shader_clock", dest_comp=2, bit_sizes=[32], flags=[CAN_ELIMINATE], 370 indices=[MEMORY_SCOPE]) 371 372# Shader ballot intrinsics with semantics analogous to the 373# 374# ballotARB() 375# readInvocationARB() 376# readFirstInvocationARB() 377# 378# GLSL functions from ARB_shader_ballot. 379intrinsic("ballot", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 380intrinsic("read_invocation", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 381intrinsic("read_first_invocation", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 382 383# Returns the value of the first source for the lane where the second source is 384# true. The second source must be true for exactly one lane. 385intrinsic("read_invocation_cond_ir3", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 386 387# Additional SPIR-V ballot intrinsics 388# 389# These correspond to the SPIR-V opcodes 390# 391# OpGroupNonUniformElect 392# OpSubgroupFirstInvocationKHR 393intrinsic("elect", dest_comp=1, flags=[CAN_ELIMINATE]) 394intrinsic("first_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 395intrinsic("last_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 396 397# Memory barrier with semantics analogous to the compute shader 398# groupMemoryBarrier(), memoryBarrierAtomicCounter(), memoryBarrierBuffer(), 399# memoryBarrierImage() and memoryBarrierShared() GLSL intrinsics. 400barrier("group_memory_barrier") 401barrier("memory_barrier_atomic_counter") 402barrier("memory_barrier_buffer") 403barrier("memory_barrier_image") 404barrier("memory_barrier_shared") 405barrier("begin_invocation_interlock") 406barrier("end_invocation_interlock") 407 408# Memory barrier for synchronizing TCS patch outputs 409barrier("memory_barrier_tcs_patch") 410 411# A conditional discard/demote/terminate, with a single boolean source. 412intrinsic("discard_if", src_comp=[1]) 413intrinsic("demote_if", src_comp=[1]) 414intrinsic("terminate_if", src_comp=[1]) 415 416# ARB_shader_group_vote intrinsics 417intrinsic("vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 418intrinsic("vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 419intrinsic("vote_feq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 420intrinsic("vote_ieq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 421 422# Ballot ALU operations from SPIR-V. 423# 424# These operations work like their ALU counterparts except that the operate 425# on a uvec4 which is treated as a 128bit integer. Also, they are, in 426# general, free to ignore any bits which are above the subgroup size. 427intrinsic("ballot_bitfield_extract", src_comp=[4, 1], dest_comp=1, flags=[CAN_ELIMINATE]) 428intrinsic("ballot_bit_count_reduce", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 429intrinsic("ballot_bit_count_inclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 430intrinsic("ballot_bit_count_exclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 431intrinsic("ballot_find_lsb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 432intrinsic("ballot_find_msb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 433 434# Shuffle operations from SPIR-V. 435intrinsic("shuffle", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 436intrinsic("shuffle_xor", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 437intrinsic("shuffle_up", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 438intrinsic("shuffle_down", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 439 440# Quad operations from SPIR-V. 441intrinsic("quad_broadcast", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 442intrinsic("quad_swap_horizontal", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 443intrinsic("quad_swap_vertical", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 444intrinsic("quad_swap_diagonal", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 445 446intrinsic("reduce", src_comp=[0], dest_comp=0, bit_sizes=src0, 447 indices=[REDUCTION_OP, CLUSTER_SIZE], flags=[CAN_ELIMINATE]) 448intrinsic("inclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 449 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 450intrinsic("exclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 451 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 452 453# AMD shader ballot operations 454intrinsic("quad_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 455 indices=[SWIZZLE_MASK], flags=[CAN_ELIMINATE]) 456intrinsic("masked_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 457 indices=[SWIZZLE_MASK], flags=[CAN_ELIMINATE]) 458intrinsic("write_invocation_amd", src_comp=[0, 0, 1], dest_comp=0, bit_sizes=src0, 459 flags=[CAN_ELIMINATE]) 460# src = [ mask, addition ] 461intrinsic("mbcnt_amd", src_comp=[1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 462# Compiled to v_perm_b32. src = [ in_bytes_hi, in_bytes_lo, selector ] 463intrinsic("byte_permute_amd", src_comp=[1, 1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 464# Compiled to v_permlane16_b32. src = [ value, lanesel_lo, lanesel_hi ] 465intrinsic("lane_permute_16_amd", src_comp=[1, 1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 466 467# Basic Geometry Shader intrinsics. 468# 469# emit_vertex implements GLSL's EmitStreamVertex() built-in. It takes a single 470# index, which is the stream ID to write to. 471# 472# end_primitive implements GLSL's EndPrimitive() built-in. 473intrinsic("emit_vertex", indices=[STREAM_ID]) 474intrinsic("end_primitive", indices=[STREAM_ID]) 475 476# Geometry Shader intrinsics with a vertex count. 477# 478# Alternatively, drivers may implement these intrinsics, and use 479# nir_lower_gs_intrinsics() to convert from the basic intrinsics. 480# 481# These contain two additional unsigned integer sources: 482# 1. The total number of vertices emitted so far. 483# 2. The number of vertices emitted for the current primitive 484# so far if we're counting, otherwise undef. 485intrinsic("emit_vertex_with_counter", src_comp=[1, 1], indices=[STREAM_ID]) 486intrinsic("end_primitive_with_counter", src_comp=[1, 1], indices=[STREAM_ID]) 487# Contains the final total vertex and primitive counts in the current GS thread. 488intrinsic("set_vertex_and_primitive_count", src_comp=[1, 1], indices=[STREAM_ID]) 489 490# Launches mesh shader workgroups from a task shader, with explicit task_payload. 491# Rules: 492# - This is a terminating instruction. 493# - May only occur in workgroup-uniform control flow. 494# - Dispatch sizes may be divergent (in which case the values 495# from the first invocation are used). 496# Meaning of indices: 497# - BASE: address of the task_payload variable used. 498# - RANGE: size of the task_payload variable used. 499# 500# src[] = {vec(x, y, z)} 501intrinsic("launch_mesh_workgroups", src_comp=[3], indices=[BASE, RANGE]) 502 503# Trace a ray through an acceleration structure 504# 505# This instruction has a lot of parameters: 506# 0. Acceleration Structure 507# 1. Ray Flags 508# 2. Cull Mask 509# 3. SBT Offset 510# 4. SBT Stride 511# 5. Miss shader index 512# 6. Ray Origin 513# 7. Ray Tmin 514# 8. Ray Direction 515# 9. Ray Tmax 516# 10. Payload 517intrinsic("trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1]) 518# src[] = { hit_t, hit_kind } 519intrinsic("report_ray_intersection", src_comp=[1, 1], dest_comp=1) 520intrinsic("ignore_ray_intersection") 521intrinsic("accept_ray_intersection") # Not in SPIR-V; useful for lowering 522intrinsic("terminate_ray") 523# src[] = { sbt_index, payload } 524intrinsic("execute_callable", src_comp=[1, -1]) 525 526# Initialize a ray query 527# 528# 0. Ray Query 529# 1. Acceleration Structure 530# 2. Ray Flags 531# 3. Cull Mask 532# 4. Ray Origin 533# 5. Ray Tmin 534# 6. Ray Direction 535# 7. Ray Tmax 536intrinsic("rq_initialize", src_comp=[-1, -1, 1, 1, 3, 1, 3, 1]) 537# src[] = { query } 538intrinsic("rq_terminate", src_comp=[-1]) 539# src[] = { query } 540intrinsic("rq_proceed", src_comp=[-1], dest_comp=1) 541# src[] = { query, hit } 542intrinsic("rq_generate_intersection", src_comp=[-1, 1]) 543# src[] = { query } 544intrinsic("rq_confirm_intersection", src_comp=[-1]) 545# src[] = { query, committed } BASE=nir_ray_query_value 546intrinsic("rq_load", src_comp=[-1, 1], dest_comp=0, indices=[BASE,COLUMN]) 547 548# Driver independent raytracing helpers 549 550# rt_resume is a helper that that be the first instruction accesing the 551# stack/scratch in a resume shader for a raytracing pipeline. It includes the 552# resume index (for nir_lower_shader_calls_internal reasons) and the stack size 553# of the variables spilled during the call. The stack size can be use to e.g. 554# adjust a stack pointer. 555intrinsic("rt_resume", indices=[CALL_IDX, STACK_SIZE]) 556 557# Lowered version of execute_callabe that includes the index of the resume 558# shader, and the amount of scratch space needed for this call (.ie. how much 559# to increase a stack pointer by). 560# src[] = { sbt_index, payload } 561intrinsic("rt_execute_callable", src_comp=[1, -1], indices=[CALL_IDX,STACK_SIZE]) 562 563# Lowered version of trace_ray in a similar vein to rt_execute_callable. 564# src same as trace_ray 565intrinsic("rt_trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1], 566 indices=[CALL_IDX, STACK_SIZE]) 567 568 569# Atomic counters 570# 571# The *_deref variants take an atomic_uint nir_variable, while the other, 572# lowered, variants take a buffer index and register offset. The buffer index 573# is always constant, as there's no way to declare an array of atomic counter 574# buffers. 575# 576# The register offset may be non-constant but must by dynamically uniform 577# ("Atomic counters aggregated into arrays within a shader can only be indexed 578# with dynamically uniform integral expressions, otherwise results are 579# undefined.") 580def atomic(name, flags=[]): 581 intrinsic(name + "_deref", src_comp=[-1], dest_comp=1, flags=flags) 582 intrinsic(name, src_comp=[1], dest_comp=1, indices=[BASE], flags=flags) 583 584def atomic2(name): 585 intrinsic(name + "_deref", src_comp=[-1, 1], dest_comp=1) 586 intrinsic(name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 587 588def atomic3(name): 589 intrinsic(name + "_deref", src_comp=[-1, 1, 1], dest_comp=1) 590 intrinsic(name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 591 592atomic("atomic_counter_inc") 593atomic("atomic_counter_pre_dec") 594atomic("atomic_counter_post_dec") 595atomic("atomic_counter_read", flags=[CAN_ELIMINATE]) 596atomic2("atomic_counter_add") 597atomic2("atomic_counter_min") 598atomic2("atomic_counter_max") 599atomic2("atomic_counter_and") 600atomic2("atomic_counter_or") 601atomic2("atomic_counter_xor") 602atomic2("atomic_counter_exchange") 603atomic3("atomic_counter_comp_swap") 604 605# Image load, store and atomic intrinsics. 606# 607# All image intrinsics come in three versions. One which take an image target 608# passed as a deref chain as the first source, one which takes an index as the 609# first source, and one which takes a bindless handle as the first source. 610# In the first version, the image variable contains the memory and layout 611# qualifiers that influence the semantics of the intrinsic. In the second and 612# third, the image format and access qualifiers are provided as constant 613# indices. Up through GLSL ES 3.10, the image index source may only be a 614# constant array access. GLSL ES 3.20 and GLSL 4.00 allow dynamically uniform 615# indexing. 616# 617# All image intrinsics take a four-coordinate vector and a sample index as 618# 2nd and 3rd sources, determining the location within the image that will be 619# accessed by the intrinsic. Components not applicable to the image target 620# in use are undefined. Image store takes an additional four-component 621# argument with the value to be written, and image atomic operations take 622# either one or two additional scalar arguments with the same meaning as in 623# the ARB_shader_image_load_store specification. 624def image(name, src_comp=[], extra_indices=[], **kwargs): 625 intrinsic("image_deref_" + name, src_comp=[-1] + src_comp, 626 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 627 intrinsic("image_" + name, src_comp=[1] + src_comp, 628 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 629 intrinsic("bindless_image_" + name, src_comp=[-1] + src_comp, 630 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 631 632image("load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 633image("sparse_load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 634image("store", src_comp=[4, 1, 0, 1], extra_indices=[SRC_TYPE]) 635image("atomic_add", src_comp=[4, 1, 1], dest_comp=1) 636image("atomic_imin", src_comp=[4, 1, 1], dest_comp=1) 637image("atomic_umin", src_comp=[4, 1, 1], dest_comp=1) 638image("atomic_imax", src_comp=[4, 1, 1], dest_comp=1) 639image("atomic_umax", src_comp=[4, 1, 1], dest_comp=1) 640image("atomic_and", src_comp=[4, 1, 1], dest_comp=1) 641image("atomic_or", src_comp=[4, 1, 1], dest_comp=1) 642image("atomic_xor", src_comp=[4, 1, 1], dest_comp=1) 643image("atomic_exchange", src_comp=[4, 1, 1], dest_comp=1) 644image("atomic_comp_swap", src_comp=[4, 1, 1, 1], dest_comp=1) 645image("atomic_fadd", src_comp=[4, 1, 1], dest_comp=1) 646image("atomic_fmin", src_comp=[4, 1, 1], dest_comp=1) 647image("atomic_fmax", src_comp=[4, 1, 1], dest_comp=1) 648image("size", dest_comp=0, src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 649image("samples", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 650image("atomic_inc_wrap", src_comp=[4, 1, 1], dest_comp=1) 651image("atomic_dec_wrap", src_comp=[4, 1, 1], dest_comp=1) 652# CL-specific format queries 653image("format", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 654image("order", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 655 656# Vulkan descriptor set intrinsics 657# 658# The Vulkan API uses a different binding model from GL. In the Vulkan 659# API, all external resources are represented by a tuple: 660# 661# (descriptor set, binding, array index) 662# 663# where the array index is the only thing allowed to be indirect. The 664# vulkan_surface_index intrinsic takes the descriptor set and binding as 665# its first two indices and the array index as its source. The third 666# index is a nir_variable_mode in case that's useful to the backend. 667# 668# The intended usage is that the shader will call vulkan_surface_index to 669# get an index and then pass that as the buffer index ubo/ssbo calls. 670# 671# The vulkan_resource_reindex intrinsic takes a resource index in src0 672# (the result of a vulkan_resource_index or vulkan_resource_reindex) which 673# corresponds to the tuple (set, binding, index) and computes an index 674# corresponding to tuple (set, binding, idx + src1). 675intrinsic("vulkan_resource_index", src_comp=[1], dest_comp=0, 676 indices=[DESC_SET, BINDING, DESC_TYPE], 677 flags=[CAN_ELIMINATE, CAN_REORDER]) 678intrinsic("vulkan_resource_reindex", src_comp=[0, 1], dest_comp=0, 679 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 680intrinsic("load_vulkan_descriptor", src_comp=[-1], dest_comp=0, 681 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 682 683# atomic intrinsics 684# 685# All of these atomic memory operations read a value from memory, compute a new 686# value using one of the operations below, write the new value to memory, and 687# return the original value read. 688# 689# All variable operations take 2 sources except CompSwap that takes 3. These 690# sources represent: 691# 692# 0: A deref to the memory on which to perform the atomic 693# 1: The data parameter to the atomic function (i.e. the value to add 694# in shared_atomic_add, etc). 695# 2: For CompSwap only: the second data parameter. 696# 697# All SSBO operations take 3 sources except CompSwap that takes 4. These 698# sources represent: 699# 700# 0: The SSBO buffer index (dynamically uniform in GLSL, possibly non-uniform 701# with VK_EXT_descriptor_indexing). 702# 1: The offset into the SSBO buffer of the variable that the atomic 703# operation will operate on. 704# 2: The data parameter to the atomic function (i.e. the value to add 705# in ssbo_atomic_add, etc). 706# 3: For CompSwap only: the second data parameter. 707# 708# All shared (and task payload) variable operations take 2 sources 709# except CompSwap that takes 3. 710# These sources represent: 711# 712# 0: The offset into the shared variable storage region that the atomic 713# operation will operate on. 714# 1: The data parameter to the atomic function (i.e. the value to add 715# in shared_atomic_add, etc). 716# 2: For CompSwap only: the second data parameter. 717# 718# All global operations take 2 sources except CompSwap that takes 3. These 719# sources represent: 720# 721# 0: The memory address that the atomic operation will operate on. 722# 1: The data parameter to the atomic function (i.e. the value to add 723# in shared_atomic_add, etc). 724# 2: For CompSwap only: the second data parameter. 725# 726# The 2x32 global variants use a vec2 for the memory address where component X 727# has the low 32-bit and component Y has the high 32-bit. 728# 729# IR3 global operations take 32b vec2 as memory address. IR3 doesn't support 730# float atomics. 731 732def memory_atomic_data1(name): 733 intrinsic("deref_atomic_" + name, src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 734 intrinsic("ssbo_atomic_" + name, src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 735 intrinsic("shared_atomic_" + name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 736 intrinsic("task_payload_atomic_" + name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 737 intrinsic("global_atomic_" + name, src_comp=[1, 1], dest_comp=1, indices=[]) 738 intrinsic("global_atomic_" + name + "_2x32", src_comp=[2, 1], dest_comp=1, indices=[]) 739 intrinsic("global_atomic_" + name + "_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 740 if not name.startswith('f'): 741 intrinsic("global_atomic_" + name + "_ir3", src_comp=[2, 1], dest_comp=1, indices=[BASE]) 742 743def memory_atomic_data2(name): 744 intrinsic("deref_atomic_" + name, src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 745 intrinsic("ssbo_atomic_" + name, src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 746 intrinsic("shared_atomic_" + name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 747 intrinsic("task_payload_atomic_" + name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 748 intrinsic("global_atomic_" + name, src_comp=[1, 1, 1], dest_comp=1, indices=[]) 749 intrinsic("global_atomic_" + name + "_2x32", src_comp=[2, 1, 1], dest_comp=1, indices=[]) 750 intrinsic("global_atomic_" + name + "_amd", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[BASE]) 751 if not name.startswith('f'): 752 intrinsic("global_atomic_" + name + "_ir3", src_comp=[2, 1, 1], dest_comp=1, indices=[BASE]) 753 754memory_atomic_data1("add") 755memory_atomic_data1("imin") 756memory_atomic_data1("umin") 757memory_atomic_data1("imax") 758memory_atomic_data1("umax") 759memory_atomic_data1("and") 760memory_atomic_data1("or") 761memory_atomic_data1("xor") 762memory_atomic_data1("exchange") 763memory_atomic_data1("fadd") 764memory_atomic_data1("fmin") 765memory_atomic_data1("fmax") 766memory_atomic_data2("comp_swap") 767memory_atomic_data2("fcomp_swap") 768 769def system_value(name, dest_comp, indices=[], bit_sizes=[32]): 770 intrinsic("load_" + name, [], dest_comp, indices, 771 flags=[CAN_ELIMINATE, CAN_REORDER], sysval=True, 772 bit_sizes=bit_sizes) 773 774system_value("frag_coord", 4) 775system_value("point_coord", 2) 776system_value("line_coord", 1) 777system_value("front_face", 1, bit_sizes=[1, 32]) 778system_value("vertex_id", 1) 779system_value("vertex_id_zero_base", 1) 780system_value("first_vertex", 1) 781system_value("is_indexed_draw", 1) 782system_value("base_vertex", 1) 783system_value("instance_id", 1) 784system_value("base_instance", 1) 785system_value("draw_id", 1) 786system_value("sample_id", 1) 787# sample_id_no_per_sample is like sample_id but does not imply per- 788# sample shading. See the lower_helper_invocation option. 789system_value("sample_id_no_per_sample", 1) 790system_value("sample_pos", 2) 791# sample_pos_or_center is like sample_pos but does not imply per-sample 792# shading. When per-sample dispatch is not enabled, it returns (0.5, 0.5). 793system_value("sample_pos_or_center", 2) 794system_value("sample_mask_in", 1) 795system_value("primitive_id", 1) 796system_value("invocation_id", 1) 797system_value("tess_coord", 3) 798system_value("tess_level_outer", 4) 799system_value("tess_level_inner", 2) 800system_value("tess_level_outer_default", 4) 801system_value("tess_level_inner_default", 2) 802system_value("patch_vertices_in", 1) 803system_value("local_invocation_id", 3) 804system_value("local_invocation_index", 1) 805# zero_base indicates it starts from 0 for the current dispatch 806# non-zero_base indicates the base is included 807system_value("workgroup_id", 3, bit_sizes=[32, 64]) 808system_value("workgroup_id_zero_base", 3) 809# The workgroup_index is intended for situations when a 3 dimensional 810# workgroup_id is not available on the HW, but a 1 dimensional index is. 811system_value("workgroup_index", 1) 812system_value("base_workgroup_id", 3, bit_sizes=[32, 64]) 813system_value("user_clip_plane", 4, indices=[UCP_ID]) 814system_value("num_workgroups", 3, bit_sizes=[32, 64]) 815system_value("num_vertices", 1) 816system_value("helper_invocation", 1, bit_sizes=[1, 32]) 817system_value("layer_id", 1) 818system_value("view_index", 1) 819system_value("subgroup_size", 1) 820system_value("subgroup_invocation", 1) 821system_value("subgroup_eq_mask", 0, bit_sizes=[32, 64]) 822system_value("subgroup_ge_mask", 0, bit_sizes=[32, 64]) 823system_value("subgroup_gt_mask", 0, bit_sizes=[32, 64]) 824system_value("subgroup_le_mask", 0, bit_sizes=[32, 64]) 825system_value("subgroup_lt_mask", 0, bit_sizes=[32, 64]) 826system_value("num_subgroups", 1) 827system_value("subgroup_id", 1) 828system_value("workgroup_size", 3) 829# note: the definition of global_invocation_id_zero_base is based on 830# (workgroup_id * workgroup_size) + local_invocation_id. 831# it is *not* based on workgroup_id_zero_base, meaning the work group 832# base is already accounted for, and the global base is additive on top of that 833system_value("global_invocation_id", 3, bit_sizes=[32, 64]) 834system_value("global_invocation_id_zero_base", 3, bit_sizes=[32, 64]) 835system_value("base_global_invocation_id", 3, bit_sizes=[32, 64]) 836system_value("global_invocation_index", 1, bit_sizes=[32, 64]) 837system_value("work_dim", 1) 838system_value("line_width", 1) 839system_value("aa_line_width", 1) 840# BASE=0 for global/shader, BASE=1 for local/function 841system_value("scratch_base_ptr", 0, bit_sizes=[32,64], indices=[BASE]) 842system_value("constant_base_ptr", 0, bit_sizes=[32,64]) 843system_value("shared_base_ptr", 0, bit_sizes=[32,64]) 844system_value("global_base_ptr", 0, bit_sizes=[32,64]) 845# Address of a transform feedback buffer, indexed by BASE 846system_value("xfb_address", 1, bit_sizes=[32,64], indices=[BASE]) 847 848# System values for ray tracing. 849system_value("ray_launch_id", 3) 850system_value("ray_launch_size", 3) 851system_value("ray_world_origin", 3) 852system_value("ray_world_direction", 3) 853system_value("ray_object_origin", 3) 854system_value("ray_object_direction", 3) 855system_value("ray_t_min", 1) 856system_value("ray_t_max", 1) 857system_value("ray_object_to_world", 3, indices=[COLUMN]) 858system_value("ray_world_to_object", 3, indices=[COLUMN]) 859system_value("ray_hit_kind", 1) 860system_value("ray_flags", 1) 861system_value("ray_geometry_index", 1) 862system_value("ray_instance_custom_index", 1) 863system_value("shader_record_ptr", 1, bit_sizes=[64]) 864system_value("cull_mask", 1) 865 866# Driver-specific viewport scale/offset parameters. 867# 868# VC4 and V3D need to emit a scaled version of the position in the vertex 869# shaders for binning, and having system values lets us move the math for that 870# into NIR. 871# 872# Panfrost needs to implement all coordinate transformation in the 873# vertex shader; system values allow us to share this routine in NIR. 874# 875# RADV uses these for NGG primitive culling. 876system_value("viewport_x_scale", 1) 877system_value("viewport_y_scale", 1) 878system_value("viewport_z_scale", 1) 879system_value("viewport_x_offset", 1) 880system_value("viewport_y_offset", 1) 881system_value("viewport_z_offset", 1) 882system_value("viewport_scale", 3) 883system_value("viewport_offset", 3) 884 885# Blend constant color values. Float values are clamped. Vectored versions are 886# provided as well for driver convenience 887 888system_value("blend_const_color_r_float", 1) 889system_value("blend_const_color_g_float", 1) 890system_value("blend_const_color_b_float", 1) 891system_value("blend_const_color_a_float", 1) 892system_value("blend_const_color_rgba", 4) 893system_value("blend_const_color_rgba8888_unorm", 1) 894system_value("blend_const_color_aaaa8888_unorm", 1) 895 896# System values for gl_Color, for radeonsi which interpolates these in the 897# shader prolog to handle two-sided color without recompiles and therefore 898# doesn't handle these in the main shader part like normal varyings. 899system_value("color0", 4) 900system_value("color1", 4) 901 902# System value for internal compute shaders in radeonsi. 903system_value("user_data_amd", 4) 904 905# Barycentric coordinate intrinsics. 906# 907# These set up the barycentric coordinates for a particular interpolation. 908# The first four are for the simple cases: pixel, centroid, per-sample 909# (at gl_SampleID), or pull model (1/W, 1/I, 1/J) at the pixel center. The next 910# two handle interpolating at a specified sample location, or interpolating 911# with a vec2 offset, 912# 913# The interp_mode index should be either the INTERP_MODE_SMOOTH or 914# INTERP_MODE_NOPERSPECTIVE enum values. 915# 916# The vec2 value produced by these intrinsics is intended for use as the 917# barycoord source of a load_interpolated_input intrinsic. 918 919def barycentric(name, dst_comp, src_comp=[]): 920 intrinsic("load_barycentric_" + name, src_comp=src_comp, dest_comp=dst_comp, 921 indices=[INTERP_MODE], flags=[CAN_ELIMINATE, CAN_REORDER]) 922 923# no sources. 924barycentric("pixel", 2) 925barycentric("centroid", 2) 926barycentric("sample", 2) 927barycentric("model", 3) 928# src[] = { sample_id }. 929barycentric("at_sample", 2, [1]) 930# src[] = { offset.xy }. 931barycentric("at_offset", 2, [2]) 932 933# Load sample position: 934# 935# Takes a sample # and returns a sample position. Used for lowering 936# interpolateAtSample() to interpolateAtOffset() 937intrinsic("load_sample_pos_from_id", src_comp=[1], dest_comp=2, 938 flags=[CAN_ELIMINATE, CAN_REORDER]) 939 940intrinsic("load_persp_center_rhw_ir3", dest_comp=1, 941 flags=[CAN_ELIMINATE, CAN_REORDER]) 942 943# Load texture scaling values: 944# 945# Takes a sampler # and returns 1/size values for multiplying to normalize 946# texture coordinates. Used for lowering rect textures. 947intrinsic("load_texture_rect_scaling", src_comp=[1], dest_comp=2, 948 flags=[CAN_ELIMINATE, CAN_REORDER]) 949 950# Fragment shader input interpolation delta intrinsic. 951# 952# For hw where fragment shader input interpolation is handled in shader, the 953# load_fs_input_interp deltas intrinsics can be used to load the input deltas 954# used for interpolation as follows: 955# 956# vec3 iid = load_fs_input_interp_deltas(varying_slot) 957# vec2 bary = load_barycentric_*(...) 958# float result = iid.x + iid.y * bary.y + iid.z * bary.x 959 960intrinsic("load_fs_input_interp_deltas", src_comp=[1], dest_comp=3, 961 indices=[BASE, COMPONENT, IO_SEMANTICS], flags=[CAN_ELIMINATE, CAN_REORDER]) 962 963# Load operations pull data from some piece of GPU memory. All load 964# operations operate in terms of offsets into some piece of theoretical 965# memory. Loads from externally visible memory (UBO and SSBO) simply take a 966# byte offset as a source. Loads from opaque memory (uniforms, inputs, etc.) 967# take a base+offset pair where the nir_intrinsic_base() gives the location 968# of the start of the variable being loaded and and the offset source is a 969# offset into that variable. 970# 971# Uniform load operations have a nir_intrinsic_range() index that specifies the 972# range (starting at base) of the data from which we are loading. If 973# range == 0, then the range is unknown. 974# 975# UBO load operations have a nir_intrinsic_range_base() and 976# nir_intrinsic_range() that specify the byte range [range_base, 977# range_base+range] of the UBO that the src offset access must lie within. 978# 979# Some load operations such as UBO/SSBO load and per_vertex loads take an 980# additional source to specify which UBO/SSBO/vertex to load from. 981# 982# The exact address type depends on the lowering pass that generates the 983# load/store intrinsics. Typically, this is vec4 units for things such as 984# varying slots and float units for fragment shader inputs. UBO and SSBO 985# offsets are always in bytes. 986 987def load(name, src_comp, indices=[], flags=[]): 988 intrinsic("load_" + name, src_comp, dest_comp=0, indices=indices, 989 flags=flags) 990 991# src[] = { offset }. 992load("uniform", [1], [BASE, RANGE, DEST_TYPE], [CAN_ELIMINATE, CAN_REORDER]) 993# src[] = { buffer_index, offset }. 994load("ubo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE, CAN_REORDER]) 995# src[] = { buffer_index, offset in vec4 units }. base is also in vec4 units. 996load("ubo_vec4", [-1, 1], [ACCESS, BASE, COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER]) 997# src[] = { offset }. 998load("input", [1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 999# src[] = { vertex_id, offset }. 1000load("input_vertex", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1001# src[] = { vertex, offset }. 1002load("per_vertex_input", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1003# src[] = { barycoord, offset }. 1004load("interpolated_input", [2, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1005 1006# src[] = { buffer_index, offset }. 1007load("ssbo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1008# src[] = { buffer_index } 1009load("ssbo_address", [1], [], [CAN_ELIMINATE, CAN_REORDER]) 1010# src[] = { offset }. 1011load("output", [1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 1012# src[] = { vertex, offset }. 1013load("per_vertex_output", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1014# src[] = { primitive, offset }. 1015load("per_primitive_output", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1016# src[] = { offset }. 1017load("shared", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1018# src[] = { offset }. 1019load("task_payload", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1020# src[] = { offset }. 1021load("push_constant", [1], [BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 1022# src[] = { offset }. 1023load("constant", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], 1024 [CAN_ELIMINATE, CAN_REORDER]) 1025# src[] = { address }. 1026load("global", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1027# src[] = { address }. 1028load("global_2x32", [2], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1029# src[] = { address }. 1030load("global_constant", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1031 [CAN_ELIMINATE, CAN_REORDER]) 1032# src[] = { base_address, offset }. 1033load("global_constant_offset", [1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1034 [CAN_ELIMINATE, CAN_REORDER]) 1035# src[] = { base_address, offset, bound }. 1036load("global_constant_bounded", [1, 1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1037 [CAN_ELIMINATE, CAN_REORDER]) 1038# src[] = { address }. 1039load("kernel_input", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 1040# src[] = { offset }. 1041load("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1042 1043# Stores work the same way as loads, except now the first source is the value 1044# to store and the second (and possibly third) source specify where to store 1045# the value. SSBO and shared memory stores also have a 1046# nir_intrinsic_write_mask() 1047 1048def store(name, srcs, indices=[], flags=[]): 1049 intrinsic("store_" + name, [0] + srcs, indices=indices, flags=flags) 1050 1051# src[] = { value, offset }. 1052store("output", [1], [BASE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS, IO_XFB, IO_XFB2]) 1053# src[] = { value, vertex, offset }. 1054store("per_vertex_output", [1, 1], [BASE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1055# src[] = { value, primitive, offset }. 1056store("per_primitive_output", [1, 1], [BASE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1057# src[] = { value, block_index, offset } 1058store("ssbo", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1059# src[] = { value, offset }. 1060store("shared", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1061# src[] = { value, offset }. 1062store("task_payload", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1063# src[] = { value, address }. 1064store("global", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1065# src[] = { value, address }. 1066store("global_2x32", [2], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1067# src[] = { value, offset }. 1068store("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 1069 1070# A bit field to implement SPIRV FragmentShadingRateKHR 1071# bit | name | description 1072# 0 | Vertical2Pixels | Fragment invocation covers 2 pixels vertically 1073# 1 | Vertical4Pixels | Fragment invocation covers 4 pixels vertically 1074# 2 | Horizontal2Pixels | Fragment invocation covers 2 pixels horizontally 1075# 3 | Horizontal4Pixels | Fragment invocation covers 4 pixels horizontally 1076intrinsic("load_frag_shading_rate", dest_comp=1, bit_sizes=[32], 1077 flags=[CAN_ELIMINATE, CAN_REORDER]) 1078 1079# OpenCL printf instruction 1080# First source is a deref to the format string 1081# Second source is a deref to a struct containing the args 1082# Dest is success or failure 1083intrinsic("printf", src_comp=[1, 1], dest_comp=1, bit_sizes=[32]) 1084# Since most drivers will want to lower to just dumping args 1085# in a buffer, nir_lower_printf will do that, but requires 1086# the driver to at least provide a base location 1087system_value("printf_buffer_address", 1, bit_sizes=[32,64]) 1088 1089# Mesh shading MultiView intrinsics 1090system_value("mesh_view_count", 1) 1091load("mesh_view_indices", [1], [BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 1092 1093# Used to pass values from the preamble to the main shader. 1094# This should use something similar to Vulkan push constants and load_preamble 1095# should be relatively cheap. 1096# For now we only support accesses with a constant offset. 1097load("preamble", [], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1098store("preamble", [], indices=[BASE]) 1099 1100# IR3-specific version of most SSBO intrinsics. The only different 1101# compare to the originals is that they add an extra source to hold 1102# the dword-offset, which is needed by the backend code apart from 1103# the byte-offset already provided by NIR in one of the sources. 1104# 1105# NIR lowering pass 'ir3_nir_lower_io_offset' will replace the 1106# original SSBO intrinsics by these, placing the computed 1107# dword-offset always in the last source. 1108# 1109# The float versions are not handled because those are not supported 1110# by the backend. 1111store("ssbo_ir3", [1, 1, 1], 1112 indices=[WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1113load("ssbo_ir3", [1, 1, 1], 1114 indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1115intrinsic("ssbo_atomic_add_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1116intrinsic("ssbo_atomic_imin_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1117intrinsic("ssbo_atomic_umin_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1118intrinsic("ssbo_atomic_imax_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1119intrinsic("ssbo_atomic_umax_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1120intrinsic("ssbo_atomic_and_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1121intrinsic("ssbo_atomic_or_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1122intrinsic("ssbo_atomic_xor_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1123intrinsic("ssbo_atomic_exchange_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1124intrinsic("ssbo_atomic_comp_swap_ir3", src_comp=[1, 1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1125 1126# System values for freedreno geometry shaders. 1127system_value("vs_primitive_stride_ir3", 1) 1128system_value("vs_vertex_stride_ir3", 1) 1129system_value("gs_header_ir3", 1) 1130system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) 1131 1132# System values for freedreno tessellation shaders. 1133system_value("hs_patch_stride_ir3", 1) 1134system_value("tess_factor_base_ir3", 2) 1135system_value("tess_param_base_ir3", 2) 1136system_value("tcs_header_ir3", 1) 1137system_value("rel_patch_id_ir3", 1) 1138 1139# System values for freedreno compute shaders. 1140system_value("subgroup_id_shift_ir3", 1) 1141 1142# IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end 1143# the shader when src0 is false and is used to narrow down the TCS shader to 1144# just thread 0 before writing out tessellation levels. 1145intrinsic("cond_end_ir3", src_comp=[1]) 1146# end_patch_ir3 is used just before thread 0 exist the TCS and presumably 1147# signals the TE that the patch is complete and can be tessellated. 1148intrinsic("end_patch_ir3") 1149 1150# IR3-specific load/store intrinsics. These access a buffer used to pass data 1151# between geometry stages - perhaps it's explicit access to the vertex cache. 1152 1153# src[] = { value, offset }. 1154store("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET]) 1155# src[] = { offset }. 1156load("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1157 1158# IR3-specific load/store global intrinsics. They take a 64-bit base address 1159# and a 32-bit offset. The hardware will add the base and the offset, which 1160# saves us from doing 64-bit math on the base address. 1161 1162# src[] = { value, address(vec2 of hi+lo uint32_t), offset }. 1163# const_index[] = { write_mask, align_mul, align_offset } 1164store("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1165# src[] = { address(vec2 of hi+lo uint32_t), offset }. 1166# const_index[] = { access, align_mul, align_offset } 1167load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1168 1169# IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but 1170# without the binding because the hardware expects a single flattened index 1171# rather than a (binding, index) pair. We may also want to use this with GL. 1172# Note that this doesn't actually turn into a HW instruction. 1173intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET], flags=[CAN_ELIMINATE, CAN_REORDER]) 1174 1175# IR3-specific intrinsics for shader preamble. These are meant to be used like 1176# this: 1177# 1178# if (preamble_start()) { 1179# if (subgroupElect()) { 1180# // preamble 1181# ... 1182# preamble_end(); 1183# } 1184# } 1185# // main shader 1186# ... 1187 1188intrinsic("preamble_start_ir3", [], dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1189 1190barrier("preamble_end_ir3") 1191 1192# IR3-specific intrinsic for stc. Should be used in the shader preamble. 1193store("uniform_ir3", [], indices=[BASE]) 1194 1195# IR3-specific intrinsic for ldc.k. Copies UBO to constant file. 1196# base is the const file base in components, range is the amount to copy in 1197# vec4's. 1198intrinsic("copy_ubo_to_uniform_ir3", [1, 1], indices=[BASE, RANGE]) 1199 1200# DXIL specific intrinsics 1201# src[] = { value, mask, index, offset }. 1202intrinsic("store_ssbo_masked_dxil", [1, 1, 1, 1]) 1203# src[] = { value, index }. 1204intrinsic("store_shared_dxil", [1, 1]) 1205# src[] = { value, mask, index }. 1206intrinsic("store_shared_masked_dxil", [1, 1, 1]) 1207# src[] = { value, index }. 1208intrinsic("store_scratch_dxil", [1, 1]) 1209# src[] = { index }. 1210load("shared_dxil", [1], [], [CAN_ELIMINATE]) 1211# src[] = { index }. 1212load("scratch_dxil", [1], [], [CAN_ELIMINATE]) 1213# src[] = { deref_var, offset } 1214load("ptr_dxil", [1, 1], [], []) 1215# src[] = { index, 16-byte-based-offset } 1216load("ubo_dxil", [1, 1], [], [CAN_ELIMINATE, CAN_REORDER]) 1217 1218# DXIL Shared atomic intrinsics 1219# 1220# All of the shared variable atomic memory operations read a value from 1221# memory, compute a new value using one of the operations below, write the 1222# new value to memory, and return the original value read. 1223# 1224# All operations take 2 sources: 1225# 1226# 0: The index in the i32 array for by the shared memory region 1227# 1: The data parameter to the atomic function (i.e. the value to add 1228# in shared_atomic_add, etc). 1229intrinsic("shared_atomic_add_dxil", src_comp=[1, 1], dest_comp=1) 1230intrinsic("shared_atomic_imin_dxil", src_comp=[1, 1], dest_comp=1) 1231intrinsic("shared_atomic_umin_dxil", src_comp=[1, 1], dest_comp=1) 1232intrinsic("shared_atomic_imax_dxil", src_comp=[1, 1], dest_comp=1) 1233intrinsic("shared_atomic_umax_dxil", src_comp=[1, 1], dest_comp=1) 1234intrinsic("shared_atomic_and_dxil", src_comp=[1, 1], dest_comp=1) 1235intrinsic("shared_atomic_or_dxil", src_comp=[1, 1], dest_comp=1) 1236intrinsic("shared_atomic_xor_dxil", src_comp=[1, 1], dest_comp=1) 1237intrinsic("shared_atomic_exchange_dxil", src_comp=[1, 1], dest_comp=1) 1238intrinsic("shared_atomic_comp_swap_dxil", src_comp=[1, 1, 1], dest_comp=1) 1239 1240# Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined 1241# within a blend shader to read/write the raw value from the tile buffer, 1242# without applying any format conversion in the process. If the shader needs 1243# usable pixel values, it must apply format conversions itself. 1244# 1245# These definitions are generic, but they are explicitly vendored to prevent 1246# other drivers from using them, as their semantics is defined in terms of the 1247# Midgard/Bifrost hardware tile buffer and may not line up with anything sane. 1248# One notable divergence is sRGB, which is asymmetric: raw_input_pan requires 1249# an sRGB->linear conversion, but linear values should be written to 1250# raw_output_pan and the hardware handles linear->sRGB. 1251 1252# src[] = { value } 1253store("raw_output_pan", [], []) 1254store("combined_output_pan", [1, 1, 1, 4], [BASE, COMPONENT, SRC_TYPE, DEST_TYPE]) 1255load("raw_output_pan", [1], [BASE], [CAN_ELIMINATE, CAN_REORDER]) 1256 1257# Loads the sampler paramaters <min_lod, max_lod, lod_bias> 1258# src[] = { sampler_index } 1259load("sampler_lod_parameters_pan", [1], flags=[CAN_ELIMINATE, CAN_REORDER]) 1260 1261# Loads the sample position array on Bifrost, in a packed Arm-specific format 1262system_value("sample_positions_pan", 1, bit_sizes=[64]) 1263 1264# R600 specific instrincs 1265# 1266# location where the tesselation data is stored in LDS 1267system_value("tcs_in_param_base_r600", 4) 1268system_value("tcs_out_param_base_r600", 4) 1269system_value("tcs_rel_patch_id_r600", 1) 1270system_value("tcs_tess_factor_base_r600", 1) 1271 1272# the tess coords come as xy only, z has to be calculated 1273system_value("tess_coord_r600", 2) 1274 1275# load as many components as needed giving per-component addresses 1276intrinsic("load_local_shared_r600", src_comp=[0], dest_comp=0, indices = [], flags = [CAN_ELIMINATE]) 1277 1278store("local_shared_r600", [1], [WRITE_MASK]) 1279store("tf_r600", []) 1280 1281# AMD GCN/RDNA specific intrinsics 1282 1283# src[] = { descriptor, base address, scalar offset } 1284intrinsic("load_buffer_amd", src_comp=[4, 1, 1], dest_comp=0, indices=[BASE, IS_SWIZZLED, SLC_AMD, MEMORY_MODES], flags=[CAN_ELIMINATE]) 1285# src[] = { store value, descriptor, base address, scalar offset } 1286intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1], indices=[BASE, WRITE_MASK, IS_SWIZZLED, SLC_AMD, MEMORY_MODES]) 1287 1288# src[] = { address, unsigned 32-bit offset }. 1289load("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1290# src[] = { value, address, unsigned 32-bit offset }. 1291store("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 1292 1293# Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} 1294intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 1295 1296# Descriptor where TCS outputs are stored for TES 1297system_value("ring_tess_offchip_amd", 4) 1298system_value("ring_tess_offchip_offset_amd", 1) 1299# Descriptor where TCS outputs are stored for the HW tessellator 1300system_value("ring_tess_factors_amd", 4) 1301system_value("ring_tess_factors_offset_amd", 1) 1302# Descriptor where ES outputs are stored for GS to read on GFX6-8 1303system_value("ring_esgs_amd", 4) 1304system_value("ring_es2gs_offset_amd", 1) 1305# Address of the task shader draw ring (used for VARYING_SLOT_TASK_COUNT) 1306system_value("ring_task_draw_amd", 4) 1307# Address of the task shader payload ring (used for all other outputs) 1308system_value("ring_task_payload_amd", 4) 1309# Address of the mesh shader scratch ring (used for excess mesh shader outputs) 1310system_value("ring_mesh_scratch_amd", 4) 1311system_value("ring_mesh_scratch_offset_amd", 1) 1312# Pointer into the draw and payload rings 1313system_value("task_ring_entry_amd", 1) 1314# Pointer into the draw and payload rings 1315system_value("task_ib_addr", 2) 1316system_value("task_ib_stride", 1) 1317 1318# Number of patches processed by each TCS workgroup 1319system_value("tcs_num_patches_amd", 1) 1320# Relative tessellation patch ID within the current workgroup 1321system_value("tess_rel_patch_id_amd", 1) 1322# Vertex offsets used for GS per-vertex inputs 1323system_value("gs_vertex_offset_amd", 1, [BASE]) 1324 1325# AMD merged shader intrinsics 1326 1327# Whether the current invocation has an input vertex / primitive to process (also known as "ES thread" or "GS thread"). 1328# Not safe to reorder because it changes after overwrite_subgroup_num_vertices_and_primitives_amd. 1329# Also, the generated code is more optimal if they are not CSE'd. 1330intrinsic("has_input_vertex_amd", src_comp=[], dest_comp=1, bit_sizes=[1], indices=[]) 1331intrinsic("has_input_primitive_amd", src_comp=[], dest_comp=1, bit_sizes=[1], indices=[]) 1332 1333# AMD NGG intrinsics 1334 1335# Number of initial input vertices in the current workgroup. 1336system_value("workgroup_num_input_vertices_amd", 1) 1337# Number of initial input primitives in the current workgroup. 1338system_value("workgroup_num_input_primitives_amd", 1) 1339# For NGG passthrough mode only. Pre-packed argument for export_primitive_amd. 1340system_value("packed_passthrough_primitive_amd", 1) 1341# Whether NGG GS should execute shader query. 1342system_value("shader_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1343# Whether the shader should cull front facing triangles. 1344intrinsic("load_cull_front_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1345# Whether the shader should cull back facing triangles. 1346intrinsic("load_cull_back_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1347# True if face culling should use CCW (false if CW). 1348intrinsic("load_cull_ccw_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1349# Whether the shader should cull small primitives that are not visible in a pixel. 1350intrinsic("load_cull_small_primitives_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1351# Whether any culling setting is enabled in the shader. 1352intrinsic("load_cull_any_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1353# Small primitive culling precision 1354intrinsic("load_cull_small_prim_precision_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1355# Initial edge flags in a Vertex Shader, packed into the format the HW needs for primitive export. 1356intrinsic("load_initial_edgeflags_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[]) 1357# Exports the current invocation's vertex. This is a placeholder where all vertex attribute export instructions should be emitted. 1358intrinsic("export_vertex_amd", src_comp=[], indices=[]) 1359# Exports the current invocation's primitive. src[] = {packed_primitive_data}. 1360intrinsic("export_primitive_amd", src_comp=[1], indices=[]) 1361# Allocates export space for vertices and primitives. src[] = {num_vertices, num_primitives}. 1362intrinsic("alloc_vertices_and_primitives_amd", src_comp=[1, 1], indices=[]) 1363# Overwrites VS input registers, for use with vertex compaction after culling. src = {vertex_id, instance_id}. 1364intrinsic("overwrite_vs_arguments_amd", src_comp=[1, 1], indices=[]) 1365# Overwrites TES input registers, for use with vertex compaction after culling. src = {tes_u, tes_v, rel_patch_id, patch_id}. 1366intrinsic("overwrite_tes_arguments_amd", src_comp=[1, 1, 1, 1], indices=[]) 1367 1368# The address of the sbt descriptors. 1369system_value("sbt_base_amd", 1, bit_sizes=[64]) 1370 1371# 1. HW descriptor 1372# 2. BVH node(64-bit pointer as 2x32 ...) 1373# 3. ray extent 1374# 4. ray origin 1375# 5. ray direction 1376# 6. inverse ray direction (componentwise 1.0/ray direction) 1377intrinsic("bvh64_intersect_ray_amd", [4, 2, 1, 3, 3, 3], 4, flags=[CAN_ELIMINATE, CAN_REORDER]) 1378 1379# Return of a callable in raytracing pipelines 1380intrinsic("rt_return_amd") 1381 1382# offset into scratch for the input callable data in a raytracing pipeline. 1383system_value("rt_arg_scratch_offset_amd", 1) 1384 1385# Whether to call the anyhit shader for an intersection in an intersection shader. 1386system_value("intersection_opaque_amd", 1, bit_sizes=[1]) 1387 1388# Used for indirect ray tracing. 1389system_value("ray_launch_size_addr_amd", 1, bit_sizes=[64]) 1390 1391# Load forced VRS rates. 1392intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1393 1394intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER]) 1395intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], indices=[BASE, ARG_UPPER_BOUND_U32_AMD], flags=[CAN_ELIMINATE, CAN_REORDER]) 1396 1397# src[] = { 64-bit base address, 32-bit offset }. 1398intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32], 1399 indices=[ALIGN_MUL, ALIGN_OFFSET], 1400 flags=[CAN_ELIMINATE, CAN_REORDER]) 1401 1402# src[] = { offset }. 1403intrinsic("load_shared2_amd", [1], dest_comp=2, indices=[OFFSET0, OFFSET1, ST64], flags=[CAN_ELIMINATE]) 1404 1405# src[] = { value, offset }. 1406intrinsic("store_shared2_amd", [2, 1], indices=[OFFSET0, OFFSET1, ST64]) 1407 1408# Vertex stride in LS-HS buffer 1409system_value("lshs_vertex_stride_amd", 1) 1410 1411# Per patch data offset in HS VRAM output buffer 1412system_value("hs_out_patch_data_offset_amd", 1) 1413 1414# V3D-specific instrinc for tile buffer color reads. 1415# 1416# The hardware requires that we read the samples and components of a pixel 1417# in order, so we cannot eliminate or remove any loads in a sequence. 1418# 1419# src[] = { render_target } 1420# BASE = sample index 1421load("tlb_color_v3d", [1], [BASE, COMPONENT], []) 1422 1423# V3D-specific instrinc for per-sample tile buffer color writes. 1424# 1425# The driver backend needs to identify per-sample color writes and emit 1426# specific code for them. 1427# 1428# src[] = { value, render_target } 1429# BASE = sample index 1430store("tlb_sample_color_v3d", [1], [BASE, COMPONENT, SRC_TYPE], []) 1431 1432# V3D-specific intrinsic to load the number of layers attached to 1433# the target framebuffer 1434intrinsic("load_fb_layers_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1435 1436# Logical complement of load_front_face, mapping to an AGX system value 1437system_value("back_face_agx", 1, bit_sizes=[1, 32]) 1438 1439# Intel-specific query for loading from the brw_image_param struct passed 1440# into the shader as a uniform. The variable is a deref to the image 1441# variable. The const index specifies which of the six parameters to load. 1442intrinsic("image_deref_load_param_intel", src_comp=[1], dest_comp=0, 1443 indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1444image("load_raw_intel", src_comp=[1], dest_comp=0, 1445 flags=[CAN_ELIMINATE]) 1446image("store_raw_intel", src_comp=[1, 0]) 1447 1448# Intrinsic to load a block of at least 32B of constant data from a 64-bit 1449# global memory address. The memory address must be uniform and 32B-aligned. 1450# The second source is a predicate which indicates whether or not to actually 1451# do the load. 1452# src[] = { address, predicate }. 1453intrinsic("load_global_const_block_intel", src_comp=[1, 1], dest_comp=0, 1454 bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1455 1456# Number of data items being operated on for a SIMD program. 1457system_value("simd_width_intel", 1) 1458 1459# Load a relocatable 32-bit value 1460intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], 1461 indices=[PARAM_IDX], flags=[CAN_ELIMINATE, CAN_REORDER]) 1462 1463# 64-bit global address for a Vulkan descriptor set 1464# src[0] = { set } 1465intrinsic("load_desc_set_address_intel", dest_comp=1, bit_sizes=[64], 1466 src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 1467 1468# OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL from SPV_INTEL_subgroups. 1469intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1], 1470 indices=[ACCESS], flags=[CAN_ELIMINATE]) 1471intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 1472 1473# src[] = { address }. 1474load("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1475 1476# src[] = { buffer_index, offset }. 1477load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1478 1479# src[] = { offset }. 1480load("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1481 1482# src[] = { value, address }. 1483store("global_block_intel", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1484 1485# src[] = { value, block_index, offset } 1486store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1487 1488# src[] = { value, offset }. 1489store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1490 1491# Intrinsics for Intel mesh shading 1492system_value("mesh_inline_data_intel", 1, [ALIGN_OFFSET], bit_sizes=[32, 64]) 1493 1494# Intrinsics for Intel bindless thread dispatch 1495# BASE=brw_topoloy_id 1496system_value("topology_id_intel", 1, indices=[BASE]) 1497system_value("btd_stack_id_intel", 1) 1498system_value("btd_global_arg_addr_intel", 1, bit_sizes=[64]) 1499system_value("btd_local_arg_addr_intel", 1, bit_sizes=[64]) 1500system_value("btd_resume_sbt_addr_intel", 1, bit_sizes=[64]) 1501# src[] = { global_arg_addr, btd_record } 1502intrinsic("btd_spawn_intel", src_comp=[1, 1]) 1503# RANGE=stack_size 1504intrinsic("btd_stack_push_intel", indices=[STACK_SIZE]) 1505# src[] = { } 1506intrinsic("btd_retire_intel") 1507 1508# Intel-specific ray-tracing intrinsic 1509# src[] = { globals, level, operation } SYNCHRONOUS=synchronous 1510intrinsic("trace_ray_intel", src_comp=[1, 1, 1], indices=[SYNCHRONOUS]) 1511 1512# System values used for ray-tracing on Intel 1513system_value("ray_base_mem_addr_intel", 1, bit_sizes=[64]) 1514system_value("ray_hw_stack_size_intel", 1) 1515system_value("ray_sw_stack_size_intel", 1) 1516system_value("ray_num_dss_rt_stacks_intel", 1) 1517system_value("ray_hit_sbt_addr_intel", 1, bit_sizes=[64]) 1518system_value("ray_hit_sbt_stride_intel", 1, bit_sizes=[16]) 1519system_value("ray_miss_sbt_addr_intel", 1, bit_sizes=[64]) 1520system_value("ray_miss_sbt_stride_intel", 1, bit_sizes=[16]) 1521system_value("callable_sbt_addr_intel", 1, bit_sizes=[64]) 1522system_value("callable_sbt_stride_intel", 1, bit_sizes=[16]) 1523system_value("leaf_opaque_intel", 1, bit_sizes=[1]) 1524system_value("leaf_procedural_intel", 1, bit_sizes=[1]) 1525# Values : 1526# 0: AnyHit 1527# 1: ClosestHit 1528# 2: Miss 1529# 3: Intersection 1530system_value("btd_shader_type_intel", 1) 1531system_value("ray_query_global_intel", 1, bit_sizes=[64]) 1532 1533# In order to deal with flipped render targets, gl_PointCoord may be flipped 1534# in the shader requiring a shader key or extra instructions or it may be 1535# flipped in hardware based on a state bit. This version of gl_PointCoord 1536# is defined to be whatever thing the hardware can easily give you, so long as 1537# it's in normalized coordinates in the range [0, 1] across the point. 1538intrinsic("load_point_coord_maybe_flipped", dest_comp=2, bit_sizes=[32]) 1539