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"VGT_STAGES_HS_EN": { 962 "entries": [ 963 {"name": "HS_STAGE_OFF", "value": 0}, 964 {"name": "HS_STAGE_ON", "value": 1} 965 ] 966 }, 967 "VGT_STAGES_LS_EN": { 968 "entries": [ 969 {"name": "LS_STAGE_OFF", "value": 0}, 970 {"name": "LS_STAGE_ON", "value": 1}, 971 {"name": "CS_STAGE_ON", "value": 2}, 972 {"name": "RESERVED_LS", "value": 3} 973 ] 974 }, 975 "VGT_STAGES_VS_EN": { 976 "entries": [ 977 {"name": "VS_STAGE_REAL", "value": 0}, 978 {"name": "VS_STAGE_DS", "value": 1}, 979 {"name": "VS_STAGE_COPY_SHADER", "value": 2}, 980 {"name": "RESERVED_VS", "value": 3} 981 ] 982 }, 983 "VGT_TESS_PARTITION": { 984 "entries": [ 985 {"name": "PART_INTEGER", "value": 0}, 986 {"name": "PART_POW2", "value": 1}, 987 {"name": "PART_FRAC_ODD", "value": 2}, 988 {"name": "PART_FRAC_EVEN", "value": 3} 989 ] 990 }, 991 "VGT_TESS_TOPOLOGY": { 992 "entries": [ 993 {"name": "OUTPUT_POINT", "value": 0}, 994 {"name": "OUTPUT_LINE", "value": 1}, 995 {"name": "OUTPUT_TRIANGLE_CW", "value": 2}, 996 {"name": "OUTPUT_TRIANGLE_CCW", "value": 3} 997 ] 998 }, 999 "VGT_TESS_TYPE": { 1000 "entries": [ 1001 {"name": "TESS_ISOLINE", "value": 0}, 1002 {"name": "TESS_TRIANGLE", "value": 1}, 1003 {"name": "TESS_QUAD", "value": 2} 1004 ] 1005 }, 1006 "ZFormat": { 1007 "entries": [ 1008 {"name": "Z_INVALID", "value": 0}, 1009 {"name": "Z_16", "value": 1}, 1010 {"name": "Z_24", "value": 2}, 1011 {"name": "Z_32_FLOAT", "value": 3} 1012 ] 1013 }, 1014 "ZLimitSumm": { 1015 "entries": [ 1016 {"name": "FORCE_SUMM_OFF", "value": 0}, 1017 {"name": "FORCE_SUMM_MINZ", "value": 1}, 1018 {"name": "FORCE_SUMM_MAXZ", "value": 2}, 1019 {"name": "FORCE_SUMM_BOTH", "value": 3} 1020 ] 1021 }, 1022 "ZOrder": { 1023 "entries": [ 1024 {"name": "LATE_Z", "value": 0}, 1025 {"name": "EARLY_Z_THEN_LATE_Z", "value": 1}, 1026 {"name": "RE_Z", "value": 2}, 1027 {"name": "EARLY_Z_THEN_RE_Z", "value": 3} 1028 ] 1029 } 1030 }, 1031 "register_mappings": [ 1032 { 1033 "chips": ["gfx6"], 1034 "map": {"at": 68, "to": "mm"}, 1035 "name": "SQ_WAVE_MODE", 1036 "type_ref": "SQ_WAVE_MODE" 1037 }, 1038 { 1039 "chips": ["gfx6"], 1040 "map": {"at": 72, "to": "mm"}, 1041 "name": "SQ_WAVE_STATUS", 1042 "type_ref": "SQ_WAVE_STATUS" 1043 }, 1044 { 1045 "chips": ["gfx6"], 1046 "map": {"at": 76, "to": "mm"}, 1047 "name": "SQ_WAVE_TRAPSTS", 1048 "type_ref": "SQ_WAVE_TRAPSTS" 1049 }, 1050 { 1051 "chips": ["gfx6"], 1052 "map": {"at": 80, "to": "mm"}, 1053 "name": "SQ_WAVE_HW_ID", 1054 "type_ref": "SQ_WAVE_HW_ID" 1055 }, 1056 { 1057 "chips": ["gfx6"], 1058 "map": {"at": 84, "to": "mm"}, 1059 "name": "SQ_WAVE_GPR_ALLOC", 1060 "type_ref": "SQ_WAVE_GPR_ALLOC" 1061 }, 1062 { 1063 "chips": ["gfx6"], 1064 "map": {"at": 88, "to": "mm"}, 1065 "name": "SQ_WAVE_LDS_ALLOC", 1066 "type_ref": "SQ_WAVE_LDS_ALLOC" 1067 }, 1068 { 1069 "chips": ["gfx6"], 1070 "map": {"at": 92, "to": "mm"}, 1071 "name": "SQ_WAVE_IB_STS", 1072 "type_ref": "SQ_WAVE_IB_STS" 1073 }, 1074 { 1075 "chips": ["gfx6"], 1076 "map": {"at": 96, "to": "mm"}, 1077 "name": "SQ_WAVE_PC_LO" 1078 }, 1079 { 1080 "chips": ["gfx6"], 1081 "map": {"at": 100, "to": "mm"}, 1082 "name": "SQ_WAVE_PC_HI", 1083 "type_ref": "SQ_WAVE_PC_HI" 1084 }, 1085 { 1086 "chips": ["gfx6"], 1087 "map": {"at": 104, "to": "mm"}, 1088 "name": "SQ_WAVE_INST_DW0" 1089 }, 1090 { 1091 "chips": ["gfx6"], 1092 "map": {"at": 108, "to": "mm"}, 1093 "name": "SQ_WAVE_INST_DW1" 1094 }, 1095 { 1096 "chips": ["gfx6"], 1097 "map": {"at": 112, "to": "mm"}, 1098 "name": "SQ_WAVE_IB_DBG0", 1099 "type_ref": "SQ_WAVE_IB_DBG0" 1100 }, 1101 { 1102 "chips": ["gfx6"], 1103 "map": {"at": 2480, "to": "mm"}, 1104 "name": "SQ_WAVE_TBA_LO" 1105 }, 1106 { 1107 "chips": ["gfx6"], 1108 "map": {"at": 2484, "to": "mm"}, 1109 "name": "SQ_WAVE_TBA_HI", 1110 "type_ref": "SQ_WAVE_TBA_HI" 1111 }, 1112 { 1113 "chips": ["gfx6"], 1114 "map": {"at": 2488, "to": "mm"}, 1115 "name": "SQ_WAVE_TMA_LO" 1116 }, 1117 { 1118 "chips": ["gfx6"], 1119 "map": {"at": 2492, "to": "mm"}, 1120 "name": "SQ_WAVE_TMA_HI", 1121 "type_ref": "SQ_WAVE_TBA_HI" 1122 }, 1123 { 1124 "chips": ["gfx6"], 1125 "map": {"at": 2496, "to": "mm"}, 1126 "name": "SQ_WAVE_TTMP0" 1127 }, 1128 { 1129 "chips": ["gfx6"], 1130 "map": {"at": 2500, "to": "mm"}, 1131 "name": "SQ_WAVE_TTMP1" 1132 }, 1133 { 1134 "chips": ["gfx6"], 1135 "map": {"at": 2504, "to": "mm"}, 1136 "name": "SQ_WAVE_TTMP2" 1137 }, 1138 { 1139 "chips": ["gfx6"], 1140 "map": {"at": 2508, "to": "mm"}, 1141 "name": "SQ_WAVE_TTMP3" 1142 }, 1143 { 1144 "chips": ["gfx6"], 1145 "map": {"at": 2512, "to": "mm"}, 1146 "name": "SQ_WAVE_TTMP4" 1147 }, 1148 { 1149 "chips": ["gfx6"], 1150 "map": {"at": 2516, "to": "mm"}, 1151 "name": "SQ_WAVE_TTMP5" 1152 }, 1153 { 1154 "chips": ["gfx6"], 1155 "map": {"at": 2520, "to": "mm"}, 1156 "name": "SQ_WAVE_TTMP6" 1157 }, 1158 { 1159 "chips": ["gfx6"], 1160 "map": {"at": 2524, "to": "mm"}, 1161 "name": "SQ_WAVE_TTMP7" 1162 }, 1163 { 1164 "chips": ["gfx6"], 1165 "map": {"at": 2528, "to": "mm"}, 1166 "name": "SQ_WAVE_TTMP8" 1167 }, 1168 { 1169 "chips": ["gfx6"], 1170 "map": {"at": 2532, "to": "mm"}, 1171 "name": "SQ_WAVE_TTMP9" 1172 }, 1173 { 1174 "chips": ["gfx6"], 1175 "map": {"at": 2536, "to": "mm"}, 1176 "name": "SQ_WAVE_TTMP10" 1177 }, 1178 { 1179 "chips": ["gfx6"], 1180 "map": {"at": 2540, "to": "mm"}, 1181 "name": "SQ_WAVE_TTMP11" 1182 }, 1183 { 1184 "chips": ["gfx6"], 1185 "map": {"at": 2544, "to": "mm"}, 1186 "name": "SQ_WAVE_M0" 1187 }, 1188 { 1189 "chips": ["gfx6"], 1190 "map": {"at": 2552, "to": "mm"}, 1191 "name": "SQ_WAVE_EXEC_LO" 1192 }, 1193 { 1194 "chips": ["gfx6"], 1195 "map": {"at": 2556, "to": "mm"}, 1196 "name": "SQ_WAVE_EXEC_HI" 1197 }, 1198 { 1199 "chips": ["gfx6"], 1200 "map": {"at": 32768, "to": "mm"}, 1201 "name": "GRBM_CNTL", 1202 "type_ref": "GRBM_CNTL" 1203 }, 1204 { 1205 "chips": ["gfx6"], 1206 "map": {"at": 32772, "to": "mm"}, 1207 "name": "GRBM_SKEW_CNTL", 1208 "type_ref": "GRBM_SKEW_CNTL" 1209 }, 1210 { 1211 "chips": ["gfx6"], 1212 "map": {"at": 32776, "to": "mm"}, 1213 "name": "GRBM_STATUS2", 1214 "type_ref": "GRBM_STATUS2" 1215 }, 1216 { 1217 "chips": ["gfx6"], 1218 "map": {"at": 32780, "to": "mm"}, 1219 "name": "GRBM_PWR_CNTL", 1220 "type_ref": "GRBM_PWR_CNTL" 1221 }, 1222 { 1223 "chips": ["gfx6"], 1224 "map": {"at": 32784, "to": "mm"}, 1225 "name": "GRBM_STATUS", 1226 "type_ref": "GRBM_STATUS" 1227 }, 1228 { 1229 "chips": ["gfx6"], 1230 "map": {"at": 32788, "to": "mm"}, 1231 "name": "GRBM_STATUS_SE0", 1232 "type_ref": "GRBM_STATUS_SE0" 1233 }, 1234 { 1235 "chips": ["gfx6"], 1236 "map": {"at": 32792, "to": "mm"}, 1237 "name": "GRBM_STATUS_SE1", 1238 "type_ref": "GRBM_STATUS_SE0" 1239 }, 1240 { 1241 "chips": ["gfx6"], 1242 "map": {"at": 32800, "to": "mm"}, 1243 "name": "GRBM_SOFT_RESET", 1244 "type_ref": "GRBM_SOFT_RESET" 1245 }, 1246 { 1247 "chips": ["gfx6"], 1248 "map": {"at": 32804, "to": "mm"}, 1249 "name": "GRBM_DEBUG_CNTL", 1250 "type_ref": "GRBM_DEBUG_CNTL" 1251 }, 1252 { 1253 "chips": ["gfx6"], 1254 "map": {"at": 32808, "to": "mm"}, 1255 "name": "GRBM_DEBUG_DATA" 1256 }, 1257 { 1258 "chips": ["gfx6"], 1259 "map": {"at": 32812, "to": "mm"}, 1260 "name": "GRBM_GFX_INDEX", 1261 "type_ref": "GRBM_GFX_INDEX" 1262 }, 1263 { 1264 "chips": ["gfx6"], 1265 "map": {"at": 32816, "to": "mm"}, 1266 "name": "GRBM_GFX_CLKEN_CNTL", 1267 "type_ref": "GRBM_GFX_CLKEN_CNTL" 1268 }, 1269 { 1270 "chips": ["gfx6"], 1271 "map": {"at": 32820, "to": "mm"}, 1272 "name": "GRBM_WAIT_IDLE_CLOCKS", 1273 "type_ref": "GRBM_WAIT_IDLE_CLOCKS" 1274 }, 1275 { 1276 "chips": ["gfx6"], 1277 "map": {"at": 32848, "to": "mm"}, 1278 "name": "GRBM_DEBUG", 1279 "type_ref": "GRBM_DEBUG" 1280 }, 1281 { 1282 "chips": ["gfx6"], 1283 "map": {"at": 32852, "to": "mm"}, 1284 "name": "GRBM_DEBUG_SNAPSHOT", 1285 "type_ref": "GRBM_DEBUG_SNAPSHOT" 1286 }, 1287 { 1288 "chips": ["gfx6"], 1289 "map": {"at": 32856, "to": "mm"}, 1290 "name": "GRBM_READ_ERROR", 1291 "type_ref": "GRBM_READ_ERROR" 1292 }, 1293 { 1294 "chips": ["gfx6"], 1295 "map": {"at": 32864, "to": "mm"}, 1296 "name": "GRBM_INT_CNTL", 1297 "type_ref": "GRBM_INT_CNTL" 1298 }, 1299 { 1300 "chips": ["gfx6"], 1301 "map": {"at": 32880, "to": "mm"}, 1302 "name": "GRBM_PERFCOUNTER0_SELECT", 1303 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 1304 }, 1305 { 1306 "chips": ["gfx6"], 1307 "map": {"at": 32884, "to": "mm"}, 1308 "name": "GRBM_PERFCOUNTER1_SELECT", 1309 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 1310 }, 1311 { 1312 "chips": ["gfx6"], 1313 "map": {"at": 32888, "to": "mm"}, 1314 "name": "GRBM_PERFCOUNTER0_LO" 1315 }, 1316 { 1317 "chips": ["gfx6"], 1318 "map": {"at": 32892, "to": "mm"}, 1319 "name": "GRBM_PERFCOUNTER0_HI" 1320 }, 1321 { 1322 "chips": ["gfx6"], 1323 "map": {"at": 32896, "to": "mm"}, 1324 "name": "GRBM_PERFCOUNTER1_LO" 1325 }, 1326 { 1327 "chips": ["gfx6"], 1328 "map": {"at": 32900, "to": "mm"}, 1329 "name": "GRBM_PERFCOUNTER1_HI" 1330 }, 1331 { 1332 "chips": ["gfx6"], 1333 "map": {"at": 32920, "to": "mm"}, 1334 "name": "GRBM_SE0_PERFCOUNTER_SELECT", 1335 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 1336 }, 1337 { 1338 "chips": ["gfx6"], 1339 "map": {"at": 32924, "to": "mm"}, 1340 "name": "GRBM_SE1_PERFCOUNTER_SELECT", 1341 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 1342 }, 1343 { 1344 "chips": ["gfx6"], 1345 "map": {"at": 32936, "to": "mm"}, 1346 "name": "GRBM_SE0_PERFCOUNTER_LO" 1347 }, 1348 { 1349 "chips": ["gfx6"], 1350 "map": {"at": 32940, "to": "mm"}, 1351 "name": "GRBM_SE0_PERFCOUNTER_HI" 1352 }, 1353 { 1354 "chips": ["gfx6"], 1355 "map": {"at": 32944, "to": "mm"}, 1356 "name": "GRBM_SE1_PERFCOUNTER_LO" 1357 }, 1358 { 1359 "chips": ["gfx6"], 1360 "map": {"at": 32948, "to": "mm"}, 1361 "name": "GRBM_SE1_PERFCOUNTER_HI" 1362 }, 1363 { 1364 "chips": ["gfx6"], 1365 "map": {"at": 33008, "to": "mm"}, 1366 "name": "DEBUG_INDEX", 1367 "type_ref": "DEBUG_INDEX" 1368 }, 1369 { 1370 "chips": ["gfx6"], 1371 "map": {"at": 33012, "to": "mm"}, 1372 "name": "DEBUG_DATA" 1373 }, 1374 { 1375 "chips": ["gfx6"], 1376 "map": {"at": 33020, "to": "mm"}, 1377 "name": "GRBM_NOWHERE" 1378 }, 1379 { 1380 "chips": ["gfx6"], 1381 "map": {"at": 33024, "to": "mm"}, 1382 "name": "GRBM_SCRATCH_REG0" 1383 }, 1384 { 1385 "chips": ["gfx6"], 1386 "map": {"at": 33028, "to": "mm"}, 1387 "name": "GRBM_SCRATCH_REG1" 1388 }, 1389 { 1390 "chips": ["gfx6"], 1391 "map": {"at": 33032, "to": "mm"}, 1392 "name": "GRBM_SCRATCH_REG2" 1393 }, 1394 { 1395 "chips": ["gfx6"], 1396 "map": {"at": 33036, "to": "mm"}, 1397 "name": "GRBM_SCRATCH_REG3" 1398 }, 1399 { 1400 "chips": ["gfx6"], 1401 "map": {"at": 33040, "to": "mm"}, 1402 "name": "GRBM_SCRATCH_REG4" 1403 }, 1404 { 1405 "chips": ["gfx6"], 1406 "map": {"at": 33044, "to": "mm"}, 1407 "name": "GRBM_SCRATCH_REG5" 1408 }, 1409 { 1410 "chips": ["gfx6"], 1411 "map": {"at": 33048, "to": "mm"}, 1412 "name": "GRBM_SCRATCH_REG6" 1413 }, 1414 { 1415 "chips": ["gfx6"], 1416 "map": {"at": 33052, "to": "mm"}, 1417 "name": "GRBM_SCRATCH_REG7" 1418 }, 1419 { 1420 "chips": ["gfx6"], 1421 "map": {"at": 33536, "to": "mm"}, 1422 "name": "SQ_INTERRUPT_WORD_AUTO", 1423 "type_ref": "SQ_INTERRUPT_WORD_AUTO" 1424 }, 1425 { 1426 "chips": ["gfx6"], 1427 "map": {"at": 33792, "to": "mm"}, 1428 "name": "CP_EOP_DONE_ADDR_LO", 1429 "type_ref": "CP_EOP_DONE_ADDR_LO" 1430 }, 1431 { 1432 "chips": ["gfx6"], 1433 "map": {"at": 33796, "to": "mm"}, 1434 "name": "CP_EOP_DONE_ADDR_HI", 1435 "type_ref": "CP_EOP_DONE_ADDR_HI" 1436 }, 1437 { 1438 "chips": ["gfx6"], 1439 "map": {"at": 33800, "to": "mm"}, 1440 "name": "CP_EOP_DONE_DATA_LO" 1441 }, 1442 { 1443 "chips": ["gfx6"], 1444 "map": {"at": 33804, "to": "mm"}, 1445 "name": "CP_EOP_DONE_DATA_HI" 1446 }, 1447 { 1448 "chips": ["gfx6"], 1449 "map": {"at": 33808, "to": "mm"}, 1450 "name": "CP_EOP_LAST_FENCE_LO" 1451 }, 1452 { 1453 "chips": ["gfx6"], 1454 "map": {"at": 33812, "to": "mm"}, 1455 "name": "CP_EOP_LAST_FENCE_HI" 1456 }, 1457 { 1458 "chips": ["gfx6"], 1459 "map": {"at": 33816, "to": "mm"}, 1460 "name": "CP_STREAM_OUT_ADDR_LO", 1461 "type_ref": "CP_STREAM_OUT_ADDR_LO" 1462 }, 1463 { 1464 "chips": ["gfx6"], 1465 "map": {"at": 33820, "to": "mm"}, 1466 "name": "CP_STREAM_OUT_ADDR_HI" 1467 }, 1468 { 1469 "chips": ["gfx6"], 1470 "map": {"at": 33824, "to": "mm"}, 1471 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO" 1472 }, 1473 { 1474 "chips": ["gfx6"], 1475 "map": {"at": 33828, "to": "mm"}, 1476 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI" 1477 }, 1478 { 1479 "chips": ["gfx6"], 1480 "map": {"at": 33832, "to": "mm"}, 1481 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO" 1482 }, 1483 { 1484 "chips": ["gfx6"], 1485 "map": {"at": 33836, "to": "mm"}, 1486 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI" 1487 }, 1488 { 1489 "chips": ["gfx6"], 1490 "map": {"at": 33840, "to": "mm"}, 1491 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO" 1492 }, 1493 { 1494 "chips": ["gfx6"], 1495 "map": {"at": 33844, "to": "mm"}, 1496 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI" 1497 }, 1498 { 1499 "chips": ["gfx6"], 1500 "map": {"at": 33848, "to": "mm"}, 1501 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO" 1502 }, 1503 { 1504 "chips": ["gfx6"], 1505 "map": {"at": 33852, "to": "mm"}, 1506 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI" 1507 }, 1508 { 1509 "chips": ["gfx6"], 1510 "map": {"at": 33856, "to": "mm"}, 1511 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO" 1512 }, 1513 { 1514 "chips": ["gfx6"], 1515 "map": {"at": 33860, "to": "mm"}, 1516 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI" 1517 }, 1518 { 1519 "chips": ["gfx6"], 1520 "map": {"at": 33864, "to": "mm"}, 1521 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO" 1522 }, 1523 { 1524 "chips": ["gfx6"], 1525 "map": {"at": 33868, "to": "mm"}, 1526 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI" 1527 }, 1528 { 1529 "chips": ["gfx6"], 1530 "map": {"at": 33872, "to": "mm"}, 1531 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO" 1532 }, 1533 { 1534 "chips": ["gfx6"], 1535 "map": {"at": 33876, "to": "mm"}, 1536 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI" 1537 }, 1538 { 1539 "chips": ["gfx6"], 1540 "map": {"at": 33880, "to": "mm"}, 1541 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO" 1542 }, 1543 { 1544 "chips": ["gfx6"], 1545 "map": {"at": 33884, "to": "mm"}, 1546 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI" 1547 }, 1548 { 1549 "chips": ["gfx6"], 1550 "map": {"at": 33888, "to": "mm"}, 1551 "name": "CP_PIPE_STATS_ADDR_LO", 1552 "type_ref": "CP_PIPE_STATS_ADDR_LO" 1553 }, 1554 { 1555 "chips": ["gfx6"], 1556 "map": {"at": 33892, "to": "mm"}, 1557 "name": "CP_PIPE_STATS_ADDR_HI" 1558 }, 1559 { 1560 "chips": ["gfx6"], 1561 "map": {"at": 33896, "to": "mm"}, 1562 "name": "CP_VGT_IAVERT_COUNT_LO" 1563 }, 1564 { 1565 "chips": ["gfx6"], 1566 "map": {"at": 33900, "to": "mm"}, 1567 "name": "CP_VGT_IAVERT_COUNT_HI" 1568 }, 1569 { 1570 "chips": ["gfx6"], 1571 "map": {"at": 33904, "to": "mm"}, 1572 "name": "CP_VGT_IAPRIM_COUNT_LO" 1573 }, 1574 { 1575 "chips": ["gfx6"], 1576 "map": {"at": 33908, "to": "mm"}, 1577 "name": "CP_VGT_IAPRIM_COUNT_HI" 1578 }, 1579 { 1580 "chips": ["gfx6"], 1581 "map": {"at": 33912, "to": "mm"}, 1582 "name": "CP_VGT_GSPRIM_COUNT_LO" 1583 }, 1584 { 1585 "chips": ["gfx6"], 1586 "map": {"at": 33916, "to": "mm"}, 1587 "name": "CP_VGT_GSPRIM_COUNT_HI" 1588 }, 1589 { 1590 "chips": ["gfx6"], 1591 "map": {"at": 33920, "to": "mm"}, 1592 "name": "CP_VGT_VSINVOC_COUNT_LO" 1593 }, 1594 { 1595 "chips": ["gfx6"], 1596 "map": {"at": 33924, "to": "mm"}, 1597 "name": "CP_VGT_VSINVOC_COUNT_HI" 1598 }, 1599 { 1600 "chips": ["gfx6"], 1601 "map": {"at": 33928, "to": "mm"}, 1602 "name": "CP_VGT_GSINVOC_COUNT_LO" 1603 }, 1604 { 1605 "chips": ["gfx6"], 1606 "map": {"at": 33932, "to": "mm"}, 1607 "name": "CP_VGT_GSINVOC_COUNT_HI" 1608 }, 1609 { 1610 "chips": ["gfx6"], 1611 "map": {"at": 33936, "to": "mm"}, 1612 "name": "CP_VGT_HSINVOC_COUNT_LO" 1613 }, 1614 { 1615 "chips": ["gfx6"], 1616 "map": {"at": 33940, "to": "mm"}, 1617 "name": "CP_VGT_HSINVOC_COUNT_HI" 1618 }, 1619 { 1620 "chips": ["gfx6"], 1621 "map": {"at": 33944, "to": "mm"}, 1622 "name": "CP_VGT_DSINVOC_COUNT_LO" 1623 }, 1624 { 1625 "chips": ["gfx6"], 1626 "map": {"at": 33948, "to": "mm"}, 1627 "name": "CP_VGT_DSINVOC_COUNT_HI" 1628 }, 1629 { 1630 "chips": ["gfx6"], 1631 "map": {"at": 33952, "to": "mm"}, 1632 "name": "CP_PA_CINVOC_COUNT_LO" 1633 }, 1634 { 1635 "chips": ["gfx6"], 1636 "map": {"at": 33956, "to": "mm"}, 1637 "name": "CP_PA_CINVOC_COUNT_HI" 1638 }, 1639 { 1640 "chips": ["gfx6"], 1641 "map": {"at": 33960, "to": "mm"}, 1642 "name": "CP_PA_CPRIM_COUNT_LO" 1643 }, 1644 { 1645 "chips": ["gfx6"], 1646 "map": {"at": 33964, "to": "mm"}, 1647 "name": "CP_PA_CPRIM_COUNT_HI" 1648 }, 1649 { 1650 "chips": ["gfx6"], 1651 "map": {"at": 33968, "to": "mm"}, 1652 "name": "CP_SC_PSINVOC_COUNT0_LO" 1653 }, 1654 { 1655 "chips": ["gfx6"], 1656 "map": {"at": 33972, "to": "mm"}, 1657 "name": "CP_SC_PSINVOC_COUNT0_HI" 1658 }, 1659 { 1660 "chips": ["gfx6"], 1661 "map": {"at": 33976, "to": "mm"}, 1662 "name": "CP_SC_PSINVOC_COUNT1_LO" 1663 }, 1664 { 1665 "chips": ["gfx6"], 1666 "map": {"at": 33980, "to": "mm"}, 1667 "name": "CP_SC_PSINVOC_COUNT1_HI" 1668 }, 1669 { 1670 "chips": ["gfx6"], 1671 "map": {"at": 33984, "to": "mm"}, 1672 "name": "CP_VGT_CSINVOC_COUNT_LO" 1673 }, 1674 { 1675 "chips": ["gfx6"], 1676 "map": {"at": 33988, "to": "mm"}, 1677 "name": "CP_VGT_CSINVOC_COUNT_HI" 1678 }, 1679 { 1680 "chips": ["gfx6"], 1681 "map": {"at": 34044, "to": "mm"}, 1682 "name": "CP_STRMOUT_CNTL", 1683 "type_ref": "CP_STRMOUT_CNTL" 1684 }, 1685 { 1686 "chips": ["gfx6"], 1687 "map": {"at": 34048, "to": "mm"}, 1688 "name": "SCRATCH_REG0" 1689 }, 1690 { 1691 "chips": ["gfx6"], 1692 "map": {"at": 34052, "to": "mm"}, 1693 "name": "SCRATCH_REG1" 1694 }, 1695 { 1696 "chips": ["gfx6"], 1697 "map": {"at": 34056, "to": "mm"}, 1698 "name": "SCRATCH_REG2" 1699 }, 1700 { 1701 "chips": ["gfx6"], 1702 "map": {"at": 34060, "to": "mm"}, 1703 "name": "SCRATCH_REG3" 1704 }, 1705 { 1706 "chips": ["gfx6"], 1707 "map": {"at": 34064, "to": "mm"}, 1708 "name": "SCRATCH_REG4" 1709 }, 1710 { 1711 "chips": ["gfx6"], 1712 "map": {"at": 34068, "to": "mm"}, 1713 "name": "SCRATCH_REG5" 1714 }, 1715 { 1716 "chips": ["gfx6"], 1717 "map": {"at": 34072, "to": "mm"}, 1718 "name": "SCRATCH_REG6" 1719 }, 1720 { 1721 "chips": ["gfx6"], 1722 "map": {"at": 34076, "to": "mm"}, 1723 "name": "SCRATCH_REG7" 1724 }, 1725 { 1726 "chips": ["gfx6"], 1727 "map": {"at": 34112, "to": "mm"}, 1728 "name": "SCRATCH_UMSK", 1729 "type_ref": "SCRATCH_UMSK" 1730 }, 1731 { 1732 "chips": ["gfx6"], 1733 "map": {"at": 34116, "to": "mm"}, 1734 "name": "SCRATCH_ADDR" 1735 }, 1736 { 1737 "chips": ["gfx6"], 1738 "map": {"at": 34144, "to": "mm"}, 1739 "name": "CP_APPEND_ADDR_LO", 1740 "type_ref": "CP_APPEND_ADDR_LO" 1741 }, 1742 { 1743 "chips": ["gfx6"], 1744 "map": {"at": 34148, "to": "mm"}, 1745 "name": "CP_APPEND_ADDR_HI", 1746 "type_ref": "CP_APPEND_ADDR_HI" 1747 }, 1748 { 1749 "chips": ["gfx6"], 1750 "map": {"at": 34152, "to": "mm"}, 1751 "name": "CP_APPEND_DATA" 1752 }, 1753 { 1754 "chips": ["gfx6"], 1755 "map": {"at": 34156, "to": "mm"}, 1756 "name": "CP_APPEND_LAST_CS_FENCE" 1757 }, 1758 { 1759 "chips": ["gfx6"], 1760 "map": {"at": 34160, "to": "mm"}, 1761 "name": "CP_APPEND_LAST_PS_FENCE" 1762 }, 1763 { 1764 "chips": ["gfx6"], 1765 "map": {"at": 34164, "to": "mm"}, 1766 "name": "CP_ATOMIC_PREOP_LO" 1767 }, 1768 { 1769 "chips": ["gfx6"], 1770 "map": {"at": 34168, "to": "mm"}, 1771 "name": "CP_ATOMIC_PREOP_HI" 1772 }, 1773 { 1774 "chips": ["gfx6"], 1775 "map": {"at": 34172, "to": "mm"}, 1776 "name": "CP_GDS_ATOMIC0_PREOP_LO" 1777 }, 1778 { 1779 "chips": ["gfx6"], 1780 "map": {"at": 34176, "to": "mm"}, 1781 "name": "CP_GDS_ATOMIC0_PREOP_HI" 1782 }, 1783 { 1784 "chips": ["gfx6"], 1785 "map": {"at": 34180, "to": "mm"}, 1786 "name": "CP_GDS_ATOMIC1_PREOP_LO" 1787 }, 1788 { 1789 "chips": ["gfx6"], 1790 "map": {"at": 34184, "to": "mm"}, 1791 "name": "CP_GDS_ATOMIC1_PREOP_HI" 1792 }, 1793 { 1794 "chips": ["gfx6"], 1795 "map": {"at": 34212, "to": "mm"}, 1796 "name": "CP_ME_MC_WADDR_LO", 1797 "type_ref": "CP_ME_MC_WADDR_LO" 1798 }, 1799 { 1800 "chips": ["gfx6"], 1801 "map": {"at": 34216, "to": "mm"}, 1802 "name": "CP_ME_MC_WADDR_HI", 1803 "type_ref": "CP_ME_MC_WADDR_HI" 1804 }, 1805 { 1806 "chips": ["gfx6"], 1807 "map": {"at": 34220, "to": "mm"}, 1808 "name": "CP_ME_MC_WDATA_LO" 1809 }, 1810 { 1811 "chips": ["gfx6"], 1812 "map": {"at": 34224, "to": "mm"}, 1813 "name": "CP_ME_MC_WDATA_HI" 1814 }, 1815 { 1816 "chips": ["gfx6"], 1817 "map": {"at": 34228, "to": "mm"}, 1818 "name": "CP_ME_MC_RADDR_LO", 1819 "type_ref": "CP_ME_MC_RADDR_LO" 1820 }, 1821 { 1822 "chips": ["gfx6"], 1823 "map": {"at": 34232, "to": "mm"}, 1824 "name": "CP_ME_MC_RADDR_HI", 1825 "type_ref": "CP_ME_MC_RADDR_HI" 1826 }, 1827 { 1828 "chips": ["gfx6"], 1829 "map": {"at": 34236, "to": "mm"}, 1830 "name": "CP_SEM_WAIT_TIMER" 1831 }, 1832 { 1833 "chips": ["gfx6"], 1834 "map": {"at": 34240, "to": "mm"}, 1835 "name": "CP_SIG_SEM_ADDR_LO", 1836 "type_ref": "CP_SIG_SEM_ADDR_LO" 1837 }, 1838 { 1839 "chips": ["gfx6"], 1840 "map": {"at": 34244, "to": "mm"}, 1841 "name": "CP_SIG_SEM_ADDR_HI", 1842 "type_ref": "CP_SIG_SEM_ADDR_HI" 1843 }, 1844 { 1845 "chips": ["gfx6"], 1846 "map": {"at": 34256, "to": "mm"}, 1847 "name": "CP_WAIT_REG_MEM_TIMEOUT" 1848 }, 1849 { 1850 "chips": ["gfx6"], 1851 "map": {"at": 34260, "to": "mm"}, 1852 "name": "CP_WAIT_SEM_ADDR_LO", 1853 "type_ref": "CP_SIG_SEM_ADDR_LO" 1854 }, 1855 { 1856 "chips": ["gfx6"], 1857 "map": {"at": 34264, "to": "mm"}, 1858 "name": "CP_WAIT_SEM_ADDR_HI", 1859 "type_ref": "CP_SIG_SEM_ADDR_HI" 1860 }, 1861 { 1862 "chips": ["gfx6"], 1863 "map": {"at": 34284, "to": "mm"}, 1864 "name": "CP_COHER_START_DELAY", 1865 "type_ref": "CP_COHER_START_DELAY" 1866 }, 1867 { 1868 "chips": ["gfx6"], 1869 "map": {"at": 34288, "to": "mm"}, 1870 "name": "CP_COHER_CNTL", 1871 "type_ref": "CP_COHER_CNTL" 1872 }, 1873 { 1874 "chips": ["gfx6"], 1875 "map": {"at": 34292, "to": "mm"}, 1876 "name": "CP_COHER_SIZE" 1877 }, 1878 { 1879 "chips": ["gfx6"], 1880 "map": {"at": 34296, "to": "mm"}, 1881 "name": "CP_COHER_BASE" 1882 }, 1883 { 1884 "chips": ["gfx6"], 1885 "map": {"at": 34300, "to": "mm"}, 1886 "name": "CP_COHER_STATUS", 1887 "type_ref": "CP_COHER_STATUS" 1888 }, 1889 { 1890 "chips": ["gfx6"], 1891 "map": {"at": 34304, "to": "mm"}, 1892 "name": "CP_DMA_ME_SRC_ADDR" 1893 }, 1894 { 1895 "chips": ["gfx6"], 1896 "map": {"at": 34308, "to": "mm"}, 1897 "name": "CP_DMA_ME_SRC_ADDR_HI", 1898 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 1899 }, 1900 { 1901 "chips": ["gfx6"], 1902 "map": {"at": 34312, "to": "mm"}, 1903 "name": "CP_DMA_ME_DST_ADDR" 1904 }, 1905 { 1906 "chips": ["gfx6"], 1907 "map": {"at": 34316, "to": "mm"}, 1908 "name": "CP_DMA_ME_DST_ADDR_HI", 1909 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 1910 }, 1911 { 1912 "chips": ["gfx6"], 1913 "map": {"at": 34320, "to": "mm"}, 1914 "name": "CP_DMA_ME_COMMAND", 1915 "type_ref": "CP_DMA_ME_COMMAND" 1916 }, 1917 { 1918 "chips": ["gfx6"], 1919 "map": {"at": 34324, "to": "mm"}, 1920 "name": "CP_DMA_PFP_SRC_ADDR" 1921 }, 1922 { 1923 "chips": ["gfx6"], 1924 "map": {"at": 34328, "to": "mm"}, 1925 "name": "CP_DMA_PFP_SRC_ADDR_HI", 1926 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 1927 }, 1928 { 1929 "chips": ["gfx6"], 1930 "map": {"at": 34332, "to": "mm"}, 1931 "name": "CP_DMA_PFP_DST_ADDR" 1932 }, 1933 { 1934 "chips": ["gfx6"], 1935 "map": {"at": 34336, "to": "mm"}, 1936 "name": "CP_DMA_PFP_DST_ADDR_HI", 1937 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 1938 }, 1939 { 1940 "chips": ["gfx6"], 1941 "map": {"at": 34340, "to": "mm"}, 1942 "name": "CP_DMA_PFP_COMMAND", 1943 "type_ref": "CP_DMA_ME_COMMAND" 1944 }, 1945 { 1946 "chips": ["gfx6"], 1947 "map": {"at": 34344, "to": "mm"}, 1948 "name": "CP_DMA_CNTL", 1949 "type_ref": "CP_DMA_CNTL" 1950 }, 1951 { 1952 "chips": ["gfx6"], 1953 "map": {"at": 34348, "to": "mm"}, 1954 "name": "CP_DMA_READ_TAGS", 1955 "type_ref": "CP_DMA_READ_TAGS" 1956 }, 1957 { 1958 "chips": ["gfx6"], 1959 "map": {"at": 34356, "to": "mm"}, 1960 "name": "CP_PFP_IB_CONTROL", 1961 "type_ref": "CP_PFP_IB_CONTROL" 1962 }, 1963 { 1964 "chips": ["gfx6"], 1965 "map": {"at": 34360, "to": "mm"}, 1966 "name": "CP_PFP_LOAD_CONTROL", 1967 "type_ref": "CP_PFP_LOAD_CONTROL" 1968 }, 1969 { 1970 "chips": ["gfx6"], 1971 "map": {"at": 34364, "to": "mm"}, 1972 "name": "CP_SCRATCH_INDEX", 1973 "type_ref": "CP_SCRATCH_INDEX" 1974 }, 1975 { 1976 "chips": ["gfx6"], 1977 "map": {"at": 34368, "to": "mm"}, 1978 "name": "CP_SCRATCH_DATA" 1979 }, 1980 { 1981 "chips": ["gfx6"], 1982 "map": {"at": 34372, "to": "mm"}, 1983 "name": "CP_RB_OFFSET", 1984 "type_ref": "CP_RB_OFFSET" 1985 }, 1986 { 1987 "chips": ["gfx6"], 1988 "map": {"at": 34376, "to": "mm"}, 1989 "name": "CP_IB1_OFFSET", 1990 "type_ref": "CP_IB1_OFFSET" 1991 }, 1992 { 1993 "chips": ["gfx6"], 1994 "map": {"at": 34380, "to": "mm"}, 1995 "name": "CP_IB2_OFFSET", 1996 "type_ref": "CP_IB2_OFFSET" 1997 }, 1998 { 1999 "chips": ["gfx6"], 2000 "map": {"at": 34384, "to": "mm"}, 2001 "name": "CP_IB1_PREAMBLE_BEGIN", 2002 "type_ref": "CP_IB1_PREAMBLE_BEGIN" 2003 }, 2004 { 2005 "chips": ["gfx6"], 2006 "map": {"at": 34388, "to": "mm"}, 2007 "name": "CP_IB1_PREAMBLE_END", 2008 "type_ref": "CP_IB1_PREAMBLE_END" 2009 }, 2010 { 2011 "chips": ["gfx6"], 2012 "map": {"at": 34392, "to": "mm"}, 2013 "name": "CP_IB2_PREAMBLE_BEGIN", 2014 "type_ref": "CP_IB2_PREAMBLE_BEGIN" 2015 }, 2016 { 2017 "chips": ["gfx6"], 2018 "map": {"at": 34396, "to": "mm"}, 2019 "name": "CP_IB2_PREAMBLE_END", 2020 "type_ref": "CP_IB2_PREAMBLE_END" 2021 }, 2022 { 2023 "chips": ["gfx6"], 2024 "map": {"at": 34416, "to": "mm"}, 2025 "name": "CP_STALLED_STAT3", 2026 "type_ref": "CP_STALLED_STAT3" 2027 }, 2028 { 2029 "chips": ["gfx6"], 2030 "map": {"at": 34420, "to": "mm"}, 2031 "name": "CP_STALLED_STAT1", 2032 "type_ref": "CP_STALLED_STAT1" 2033 }, 2034 { 2035 "chips": ["gfx6"], 2036 "map": {"at": 34424, "to": "mm"}, 2037 "name": "CP_STALLED_STAT2", 2038 "type_ref": "CP_STALLED_STAT2" 2039 }, 2040 { 2041 "chips": ["gfx6"], 2042 "map": {"at": 34428, "to": "mm"}, 2043 "name": "CP_BUSY_STAT", 2044 "type_ref": "CP_BUSY_STAT" 2045 }, 2046 { 2047 "chips": ["gfx6"], 2048 "map": {"at": 34432, "to": "mm"}, 2049 "name": "CP_STAT", 2050 "type_ref": "CP_STAT" 2051 }, 2052 { 2053 "chips": ["gfx6"], 2054 "map": {"at": 34436, "to": "mm"}, 2055 "name": "CP_ME_HEADER_DUMP" 2056 }, 2057 { 2058 "chips": ["gfx6"], 2059 "map": {"at": 34440, "to": "mm"}, 2060 "name": "CP_PFP_HEADER_DUMP" 2061 }, 2062 { 2063 "chips": ["gfx6"], 2064 "map": {"at": 34444, "to": "mm"}, 2065 "name": "CP_GRBM_FREE_COUNT", 2066 "type_ref": "CP_GRBM_FREE_COUNT" 2067 }, 2068 { 2069 "chips": ["gfx6"], 2070 "map": {"at": 34448, "to": "mm"}, 2071 "name": "CP_CE_HEADER_DUMP" 2072 }, 2073 { 2074 "chips": ["gfx6"], 2075 "map": {"at": 34460, "to": "mm"}, 2076 "name": "CP_MC_PACK_DELAY_CNT", 2077 "type_ref": "CP_MC_PACK_DELAY_CNT" 2078 }, 2079 { 2080 "chips": ["gfx6"], 2081 "map": {"at": 34512, "to": "mm"}, 2082 "name": "CP_CSF_STAT", 2083 "type_ref": "CP_CSF_STAT" 2084 }, 2085 { 2086 "chips": ["gfx6"], 2087 "map": {"at": 34516, "to": "mm"}, 2088 "name": "CP_CSF_CNTL", 2089 "type_ref": "CP_CSF_CNTL" 2090 }, 2091 { 2092 "chips": ["gfx6"], 2093 "map": {"at": 34520, "to": "mm"}, 2094 "name": "CP_ME_CNTL", 2095 "type_ref": "CP_ME_CNTL" 2096 }, 2097 { 2098 "chips": ["gfx6"], 2099 "map": {"at": 34528, "to": "mm"}, 2100 "name": "CP_CNTX_STAT", 2101 "type_ref": "CP_CNTX_STAT" 2102 }, 2103 { 2104 "chips": ["gfx6"], 2105 "map": {"at": 34532, "to": "mm"}, 2106 "name": "CP_ME_PREEMPTION", 2107 "type_ref": "CP_ME_PREEMPTION" 2108 }, 2109 { 2110 "chips": ["gfx6"], 2111 "map": {"at": 34552, "to": "mm"}, 2112 "name": "CP_RB2_RPTR", 2113 "type_ref": "CP_RB0_RPTR" 2114 }, 2115 { 2116 "chips": ["gfx6"], 2117 "map": {"at": 34556, "to": "mm"}, 2118 "name": "CP_RB1_RPTR", 2119 "type_ref": "CP_RB0_RPTR" 2120 }, 2121 { 2122 "chips": ["gfx6"], 2123 "map": {"at": 34560, "to": "mm"}, 2124 "name": "CP_RB0_RPTR", 2125 "type_ref": "CP_RB0_RPTR" 2126 }, 2127 { 2128 "chips": ["gfx6"], 2129 "map": {"at": 34564, "to": "mm"}, 2130 "name": "CP_RB_WPTR_DELAY", 2131 "type_ref": "CP_RB_WPTR_DELAY" 2132 }, 2133 { 2134 "chips": ["gfx6"], 2135 "map": {"at": 34568, "to": "mm"}, 2136 "name": "CP_RB_WPTR_POLL_CNTL", 2137 "type_ref": "CP_RB_WPTR_POLL_CNTL" 2138 }, 2139 { 2140 "chips": ["gfx6"], 2141 "map": {"at": 34572, "to": "mm"}, 2142 "name": "CP_CE_INIT_BASE_LO", 2143 "type_ref": "CP_CE_INIT_BASE_LO" 2144 }, 2145 { 2146 "chips": ["gfx6"], 2147 "map": {"at": 34576, "to": "mm"}, 2148 "name": "CP_CE_INIT_BASE_HI", 2149 "type_ref": "CP_CE_INIT_BASE_HI" 2150 }, 2151 { 2152 "chips": ["gfx6"], 2153 "map": {"at": 34580, "to": "mm"}, 2154 "name": "CP_CE_INIT_BUFSZ", 2155 "type_ref": "CP_CE_INIT_BUFSZ" 2156 }, 2157 { 2158 "chips": ["gfx6"], 2159 "map": {"at": 34584, "to": "mm"}, 2160 "name": "CP_CE_IB1_BASE_LO", 2161 "type_ref": "CP_CE_IB1_BASE_LO" 2162 }, 2163 { 2164 "chips": ["gfx6"], 2165 "map": {"at": 34588, "to": "mm"}, 2166 "name": "CP_CE_IB1_BASE_HI", 2167 "type_ref": "CP_CE_IB1_BASE_HI" 2168 }, 2169 { 2170 "chips": ["gfx6"], 2171 "map": {"at": 34592, "to": "mm"}, 2172 "name": "CP_CE_IB1_BUFSZ", 2173 "type_ref": "CP_CE_IB1_BUFSZ" 2174 }, 2175 { 2176 "chips": ["gfx6"], 2177 "map": {"at": 34596, "to": "mm"}, 2178 "name": "CP_CE_IB2_BASE_LO", 2179 "type_ref": "CP_CE_IB2_BASE_LO" 2180 }, 2181 { 2182 "chips": ["gfx6"], 2183 "map": {"at": 34600, "to": "mm"}, 2184 "name": "CP_CE_IB2_BASE_HI", 2185 "type_ref": "CP_CE_IB2_BASE_HI" 2186 }, 2187 { 2188 "chips": ["gfx6"], 2189 "map": {"at": 34604, "to": "mm"}, 2190 "name": "CP_CE_IB2_BUFSZ", 2191 "type_ref": "CP_CE_IB2_BUFSZ" 2192 }, 2193 { 2194 "chips": ["gfx6"], 2195 "map": {"at": 34608, "to": "mm"}, 2196 "name": "CP_IB1_BASE_LO", 2197 "type_ref": "CP_CE_IB1_BASE_LO" 2198 }, 2199 { 2200 "chips": ["gfx6"], 2201 "map": {"at": 34612, "to": "mm"}, 2202 "name": "CP_IB1_BASE_HI", 2203 "type_ref": "CP_CE_IB1_BASE_HI" 2204 }, 2205 { 2206 "chips": ["gfx6"], 2207 "map": {"at": 34616, "to": "mm"}, 2208 "name": "CP_IB1_BUFSZ", 2209 "type_ref": "CP_CE_IB1_BUFSZ" 2210 }, 2211 { 2212 "chips": ["gfx6"], 2213 "map": {"at": 34620, "to": "mm"}, 2214 "name": "CP_IB2_BASE_LO", 2215 "type_ref": "CP_CE_IB2_BASE_LO" 2216 }, 2217 { 2218 "chips": ["gfx6"], 2219 "map": {"at": 34624, "to": "mm"}, 2220 "name": "CP_IB2_BASE_HI", 2221 "type_ref": "CP_CE_IB2_BASE_HI" 2222 }, 2223 { 2224 "chips": ["gfx6"], 2225 "map": {"at": 34628, "to": "mm"}, 2226 "name": "CP_IB2_BUFSZ", 2227 "type_ref": "CP_CE_IB2_BUFSZ" 2228 }, 2229 { 2230 "chips": ["gfx6"], 2231 "map": {"at": 34632, "to": "mm"}, 2232 "name": "CP_ST_BASE_LO", 2233 "type_ref": "CP_ST_BASE_LO" 2234 }, 2235 { 2236 "chips": ["gfx6"], 2237 "map": {"at": 34636, "to": "mm"}, 2238 "name": "CP_ST_BASE_HI", 2239 "type_ref": "CP_ST_BASE_HI" 2240 }, 2241 { 2242 "chips": ["gfx6"], 2243 "map": {"at": 34640, "to": "mm"}, 2244 "name": "CP_ST_BUFSZ", 2245 "type_ref": "CP_ST_BUFSZ" 2246 }, 2247 { 2248 "chips": ["gfx6"], 2249 "map": {"at": 34644, "to": "mm"}, 2250 "name": "CP_ROQ1_THRESHOLDS", 2251 "type_ref": "CP_ROQ1_THRESHOLDS" 2252 }, 2253 { 2254 "chips": ["gfx6"], 2255 "map": {"at": 34648, "to": "mm"}, 2256 "name": "CP_ROQ2_THRESHOLDS", 2257 "type_ref": "CP_ROQ2_THRESHOLDS" 2258 }, 2259 { 2260 "chips": ["gfx6"], 2261 "map": {"at": 34652, "to": "mm"}, 2262 "name": "CP_STQ_THRESHOLDS", 2263 "type_ref": "CP_STQ_THRESHOLDS" 2264 }, 2265 { 2266 "chips": ["gfx6"], 2267 "map": {"at": 34656, "to": "mm"}, 2268 "name": "CP_QUEUE_THRESHOLDS", 2269 "type_ref": "CP_QUEUE_THRESHOLDS" 2270 }, 2271 { 2272 "chips": ["gfx6"], 2273 "map": {"at": 34660, "to": "mm"}, 2274 "name": "CP_MEQ_THRESHOLDS", 2275 "type_ref": "CP_MEQ_THRESHOLDS" 2276 }, 2277 { 2278 "chips": ["gfx6"], 2279 "map": {"at": 34664, "to": "mm"}, 2280 "name": "CP_ROQ_AVAIL", 2281 "type_ref": "CP_ROQ_AVAIL" 2282 }, 2283 { 2284 "chips": ["gfx6"], 2285 "map": {"at": 34668, "to": "mm"}, 2286 "name": "CP_STQ_AVAIL", 2287 "type_ref": "CP_STQ_AVAIL" 2288 }, 2289 { 2290 "chips": ["gfx6"], 2291 "map": {"at": 34672, "to": "mm"}, 2292 "name": "CP_ROQ2_AVAIL", 2293 "type_ref": "CP_ROQ2_AVAIL" 2294 }, 2295 { 2296 "chips": ["gfx6"], 2297 "map": {"at": 34676, "to": "mm"}, 2298 "name": "CP_MEQ_AVAIL", 2299 "type_ref": "CP_MEQ_AVAIL" 2300 }, 2301 { 2302 "chips": ["gfx6"], 2303 "map": {"at": 34680, "to": "mm"}, 2304 "name": "CP_CMD_INDEX", 2305 "type_ref": "CP_CMD_INDEX" 2306 }, 2307 { 2308 "chips": ["gfx6"], 2309 "map": {"at": 34684, "to": "mm"}, 2310 "name": "CP_CMD_DATA" 2311 }, 2312 { 2313 "chips": ["gfx6"], 2314 "map": {"at": 34688, "to": "mm"}, 2315 "name": "CP_ROQ_RB_STAT", 2316 "type_ref": "CP_ROQ_RB_STAT" 2317 }, 2318 { 2319 "chips": ["gfx6"], 2320 "map": {"at": 34692, "to": "mm"}, 2321 "name": "CP_ROQ_IB1_STAT", 2322 "type_ref": "CP_ROQ_IB1_STAT" 2323 }, 2324 { 2325 "chips": ["gfx6"], 2326 "map": {"at": 34696, "to": "mm"}, 2327 "name": "CP_ROQ_IB2_STAT", 2328 "type_ref": "CP_ROQ_IB2_STAT" 2329 }, 2330 { 2331 "chips": ["gfx6"], 2332 "map": {"at": 34700, "to": "mm"}, 2333 "name": "CP_STQ_STAT", 2334 "type_ref": "CP_STQ_STAT" 2335 }, 2336 { 2337 "chips": ["gfx6"], 2338 "map": {"at": 34708, "to": "mm"}, 2339 "name": "CP_MEQ_STAT", 2340 "type_ref": "CP_MEQ_STAT" 2341 }, 2342 { 2343 "chips": ["gfx6"], 2344 "map": {"at": 34712, "to": "mm"}, 2345 "name": "CP_CEQ1_AVAIL", 2346 "type_ref": "CP_CEQ1_AVAIL" 2347 }, 2348 { 2349 "chips": ["gfx6"], 2350 "map": {"at": 34716, "to": "mm"}, 2351 "name": "CP_CEQ2_AVAIL", 2352 "type_ref": "CP_CEQ2_AVAIL" 2353 }, 2354 { 2355 "chips": ["gfx6"], 2356 "map": {"at": 34720, "to": "mm"}, 2357 "name": "CP_CE_ROQ_RB_STAT", 2358 "type_ref": "CP_CE_ROQ_RB_STAT" 2359 }, 2360 { 2361 "chips": ["gfx6"], 2362 "map": {"at": 34724, "to": "mm"}, 2363 "name": "CP_CE_ROQ_IB1_STAT", 2364 "type_ref": "CP_CE_ROQ_IB1_STAT" 2365 }, 2366 { 2367 "chips": ["gfx6"], 2368 "map": {"at": 34728, "to": "mm"}, 2369 "name": "CP_CE_ROQ_IB2_STAT", 2370 "type_ref": "CP_CE_ROQ_IB2_STAT" 2371 }, 2372 { 2373 "chips": ["gfx6"], 2374 "map": {"at": 34780, "to": "mm"}, 2375 "name": "CP_INT_STAT_DEBUG", 2376 "type_ref": "CP_INT_STAT_DEBUG" 2377 }, 2378 { 2379 "chips": ["gfx6"], 2380 "map": {"at": 34812, "to": "mm"}, 2381 "name": "CP_PERFMON_CNTL", 2382 "type_ref": "CP_PERFMON_CNTL" 2383 }, 2384 { 2385 "chips": ["gfx6"], 2386 "map": {"at": 34944, "to": "mm"}, 2387 "name": "IA_PERFCOUNTER0_SELECT", 2388 "type_ref": "IA_PERFCOUNTER0_SELECT" 2389 }, 2390 { 2391 "chips": ["gfx6"], 2392 "map": {"at": 34948, "to": "mm"}, 2393 "name": "IA_PERFCOUNTER1_SELECT", 2394 "type_ref": "IA_PERFCOUNTER1_SELECT" 2395 }, 2396 { 2397 "chips": ["gfx6"], 2398 "map": {"at": 34952, "to": "mm"}, 2399 "name": "IA_PERFCOUNTER2_SELECT", 2400 "type_ref": "IA_PERFCOUNTER1_SELECT" 2401 }, 2402 { 2403 "chips": ["gfx6"], 2404 "map": {"at": 34956, "to": "mm"}, 2405 "name": "IA_PERFCOUNTER3_SELECT", 2406 "type_ref": "IA_PERFCOUNTER1_SELECT" 2407 }, 2408 { 2409 "chips": ["gfx6"], 2410 "map": {"at": 34960, "to": "mm"}, 2411 "name": "IA_PERFCOUNTER0_LO" 2412 }, 2413 { 2414 "chips": ["gfx6"], 2415 "map": {"at": 34964, "to": "mm"}, 2416 "name": "IA_PERFCOUNTER0_HI" 2417 }, 2418 { 2419 "chips": ["gfx6"], 2420 "map": {"at": 34968, "to": "mm"}, 2421 "name": "IA_PERFCOUNTER1_LO" 2422 }, 2423 { 2424 "chips": ["gfx6"], 2425 "map": {"at": 34972, "to": "mm"}, 2426 "name": "IA_PERFCOUNTER1_HI" 2427 }, 2428 { 2429 "chips": ["gfx6"], 2430 "map": {"at": 34976, "to": "mm"}, 2431 "name": "IA_PERFCOUNTER2_LO" 2432 }, 2433 { 2434 "chips": ["gfx6"], 2435 "map": {"at": 34980, "to": "mm"}, 2436 "name": "IA_PERFCOUNTER2_HI" 2437 }, 2438 { 2439 "chips": ["gfx6"], 2440 "map": {"at": 34984, "to": "mm"}, 2441 "name": "IA_PERFCOUNTER3_LO" 2442 }, 2443 { 2444 "chips": ["gfx6"], 2445 "map": {"at": 34988, "to": "mm"}, 2446 "name": "IA_PERFCOUNTER3_HI" 2447 }, 2448 { 2449 "chips": ["gfx6"], 2450 "map": {"at": 34992, "to": "mm"}, 2451 "name": "VGT_VTX_VECT_EJECT_REG", 2452 "type_ref": "VGT_VTX_VECT_EJECT_REG" 2453 }, 2454 { 2455 "chips": ["gfx6"], 2456 "map": {"at": 34996, "to": "mm"}, 2457 "name": "VGT_DMA_DATA_FIFO_DEPTH", 2458 "type_ref": "VGT_DMA_DATA_FIFO_DEPTH" 2459 }, 2460 { 2461 "chips": ["gfx6"], 2462 "map": {"at": 35000, "to": "mm"}, 2463 "name": "VGT_DMA_REQ_FIFO_DEPTH", 2464 "type_ref": "VGT_DMA_REQ_FIFO_DEPTH" 2465 }, 2466 { 2467 "chips": ["gfx6"], 2468 "map": {"at": 35004, "to": "mm"}, 2469 "name": "VGT_DRAW_INIT_FIFO_DEPTH", 2470 "type_ref": "VGT_DRAW_INIT_FIFO_DEPTH" 2471 }, 2472 { 2473 "chips": ["gfx6"], 2474 "map": {"at": 35008, "to": "mm"}, 2475 "name": "VGT_LAST_COPY_STATE", 2476 "type_ref": "VGT_LAST_COPY_STATE" 2477 }, 2478 { 2479 "chips": ["gfx6"], 2480 "map": {"at": 35012, "to": "mm"}, 2481 "name": "VGT_CACHE_INVALIDATION", 2482 "type_ref": "VGT_CACHE_INVALIDATION" 2483 }, 2484 { 2485 "chips": ["gfx6"], 2486 "map": {"at": 35016, "to": "mm"}, 2487 "name": "VGT_ESGS_RING_SIZE" 2488 }, 2489 { 2490 "chips": ["gfx6"], 2491 "map": {"at": 35020, "to": "mm"}, 2492 "name": "VGT_GSVS_RING_SIZE" 2493 }, 2494 { 2495 "chips": ["gfx6"], 2496 "map": {"at": 35024, "to": "mm"}, 2497 "name": "VGT_FIFO_DEPTHS", 2498 "type_ref": "VGT_FIFO_DEPTHS" 2499 }, 2500 { 2501 "chips": ["gfx6"], 2502 "map": {"at": 35028, "to": "mm"}, 2503 "name": "VGT_GS_VERTEX_REUSE", 2504 "type_ref": "VGT_GS_VERTEX_REUSE" 2505 }, 2506 { 2507 "chips": ["gfx6"], 2508 "map": {"at": 35032, "to": "mm"}, 2509 "name": "VGT_MC_LAT_CNTL", 2510 "type_ref": "VGT_MC_LAT_CNTL" 2511 }, 2512 { 2513 "chips": ["gfx6"], 2514 "map": {"at": 35036, "to": "mm"}, 2515 "name": "IA_CNTL_STATUS", 2516 "type_ref": "IA_CNTL_STATUS" 2517 }, 2518 { 2519 "chips": ["gfx6"], 2520 "map": {"at": 35040, "to": "mm"}, 2521 "name": "VGT_DEBUG_CNTL", 2522 "type_ref": "VGT_DEBUG_CNTL" 2523 }, 2524 { 2525 "chips": ["gfx6"], 2526 "map": {"at": 35044, "to": "mm"}, 2527 "name": "VGT_DEBUG_DATA" 2528 }, 2529 { 2530 "chips": ["gfx6"], 2531 "map": {"at": 35048, "to": "mm"}, 2532 "name": "IA_DEBUG_CNTL", 2533 "type_ref": "IA_DEBUG_CNTL" 2534 }, 2535 { 2536 "chips": ["gfx6"], 2537 "map": {"at": 35052, "to": "mm"}, 2538 "name": "IA_DEBUG_DATA" 2539 }, 2540 { 2541 "chips": ["gfx6"], 2542 "map": {"at": 35056, "to": "mm"}, 2543 "name": "VGT_CNTL_STATUS", 2544 "type_ref": "VGT_CNTL_STATUS" 2545 }, 2546 { 2547 "chips": ["gfx6"], 2548 "map": {"at": 35100, "to": "mm"}, 2549 "name": "VGT_PERFCOUNTER_SEID_MASK", 2550 "type_ref": "VGT_PERFCOUNTER_SEID_MASK" 2551 }, 2552 { 2553 "chips": ["gfx6"], 2554 "map": {"at": 35104, "to": "mm"}, 2555 "name": "VGT_PERFCOUNTER0_SELECT", 2556 "type_ref": "IA_PERFCOUNTER0_SELECT" 2557 }, 2558 { 2559 "chips": ["gfx6"], 2560 "map": {"at": 35108, "to": "mm"}, 2561 "name": "VGT_PERFCOUNTER1_SELECT", 2562 "type_ref": "IA_PERFCOUNTER0_SELECT" 2563 }, 2564 { 2565 "chips": ["gfx6"], 2566 "map": {"at": 35112, "to": "mm"}, 2567 "name": "VGT_PERFCOUNTER2_SELECT", 2568 "type_ref": "IA_PERFCOUNTER1_SELECT" 2569 }, 2570 { 2571 "chips": ["gfx6"], 2572 "map": {"at": 35116, "to": "mm"}, 2573 "name": "VGT_PERFCOUNTER3_SELECT", 2574 "type_ref": "IA_PERFCOUNTER1_SELECT" 2575 }, 2576 { 2577 "chips": ["gfx6"], 2578 "map": {"at": 35120, "to": "mm"}, 2579 "name": "VGT_PERFCOUNTER0_LO" 2580 }, 2581 { 2582 "chips": ["gfx6"], 2583 "map": {"at": 35124, "to": "mm"}, 2584 "name": "VGT_PERFCOUNTER0_HI" 2585 }, 2586 { 2587 "chips": ["gfx6"], 2588 "map": {"at": 35128, "to": "mm"}, 2589 "name": "VGT_PERFCOUNTER1_LO" 2590 }, 2591 { 2592 "chips": ["gfx6"], 2593 "map": {"at": 35132, "to": "mm"}, 2594 "name": "VGT_PERFCOUNTER1_HI" 2595 }, 2596 { 2597 "chips": ["gfx6"], 2598 "map": {"at": 35136, "to": "mm"}, 2599 "name": "VGT_PERFCOUNTER2_LO" 2600 }, 2601 { 2602 "chips": ["gfx6"], 2603 "map": {"at": 35140, "to": "mm"}, 2604 "name": "VGT_PERFCOUNTER2_HI" 2605 }, 2606 { 2607 "chips": ["gfx6"], 2608 "map": {"at": 35144, "to": "mm"}, 2609 "name": "VGT_PERFCOUNTER3_LO" 2610 }, 2611 { 2612 "chips": ["gfx6"], 2613 "map": {"at": 35148, "to": "mm"}, 2614 "name": "VGT_PERFCOUNTER3_HI" 2615 }, 2616 { 2617 "chips": ["gfx6"], 2618 "map": {"at": 35160, "to": "mm"}, 2619 "name": "VGT_PRIMITIVE_TYPE", 2620 "type_ref": "VGT_PRIMITIVE_TYPE" 2621 }, 2622 { 2623 "chips": ["gfx6"], 2624 "map": {"at": 35164, "to": "mm"}, 2625 "name": "VGT_INDEX_TYPE", 2626 "type_ref": "VGT_INDEX_TYPE" 2627 }, 2628 { 2629 "chips": ["gfx6"], 2630 "map": {"at": 35168, "to": "mm"}, 2631 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0" 2632 }, 2633 { 2634 "chips": ["gfx6"], 2635 "map": {"at": 35172, "to": "mm"}, 2636 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1" 2637 }, 2638 { 2639 "chips": ["gfx6"], 2640 "map": {"at": 35176, "to": "mm"}, 2641 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2" 2642 }, 2643 { 2644 "chips": ["gfx6"], 2645 "map": {"at": 35180, "to": "mm"}, 2646 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3" 2647 }, 2648 { 2649 "chips": ["gfx6"], 2650 "map": {"at": 35184, "to": "mm"}, 2651 "name": "VGT_NUM_INDICES" 2652 }, 2653 { 2654 "chips": ["gfx6"], 2655 "map": {"at": 35188, "to": "mm"}, 2656 "name": "VGT_NUM_INSTANCES" 2657 }, 2658 { 2659 "chips": ["gfx6"], 2660 "map": {"at": 35196, "to": "mm"}, 2661 "name": "CGTT_VGT_CLK_CTRL", 2662 "type_ref": "CGTT_VGT_CLK_CTRL" 2663 }, 2664 { 2665 "chips": ["gfx6"], 2666 "map": {"at": 35200, "to": "mm"}, 2667 "name": "IA_VMID_OVERRIDE", 2668 "type_ref": "IA_VMID_OVERRIDE" 2669 }, 2670 { 2671 "chips": ["gfx6"], 2672 "map": {"at": 35204, "to": "mm"}, 2673 "name": "CGTT_IA_CLK_CTRL", 2674 "type_ref": "CGTT_IA_CLK_CTRL" 2675 }, 2676 { 2677 "chips": ["gfx6"], 2678 "map": {"at": 35208, "to": "mm"}, 2679 "name": "VGT_TF_RING_SIZE", 2680 "type_ref": "VGT_TF_RING_SIZE" 2681 }, 2682 { 2683 "chips": ["gfx6"], 2684 "map": {"at": 35212, "to": "mm"}, 2685 "name": "VGT_SYS_CONFIG", 2686 "type_ref": "VGT_SYS_CONFIG" 2687 }, 2688 { 2689 "chips": ["gfx6"], 2690 "map": {"at": 35248, "to": "mm"}, 2691 "name": "VGT_HS_OFFCHIP_PARAM", 2692 "type_ref": "VGT_HS_OFFCHIP_PARAM" 2693 }, 2694 { 2695 "chips": ["gfx6"], 2696 "map": {"at": 35256, "to": "mm"}, 2697 "name": "VGT_TF_MEMORY_BASE" 2698 }, 2699 { 2700 "chips": ["gfx6"], 2701 "map": {"at": 35260, "to": "mm"}, 2702 "name": "CC_GC_SHADER_ARRAY_CONFIG", 2703 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG" 2704 }, 2705 { 2706 "chips": ["gfx6"], 2707 "map": {"at": 35264, "to": "mm"}, 2708 "name": "GC_USER_SHADER_ARRAY_CONFIG", 2709 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG" 2710 }, 2711 { 2712 "chips": ["gfx6"], 2713 "map": {"at": 35328, "to": "mm"}, 2714 "name": "PA_SU_DEBUG_CNTL", 2715 "type_ref": "PA_SU_DEBUG_CNTL" 2716 }, 2717 { 2718 "chips": ["gfx6"], 2719 "map": {"at": 35332, "to": "mm"}, 2720 "name": "PA_SU_DEBUG_DATA" 2721 }, 2722 { 2723 "chips": ["gfx6"], 2724 "map": {"at": 35344, "to": "mm"}, 2725 "name": "PA_CL_CNTL_STATUS", 2726 "type_ref": "PA_CL_CNTL_STATUS" 2727 }, 2728 { 2729 "chips": ["gfx6"], 2730 "map": {"at": 35348, "to": "mm"}, 2731 "name": "PA_CL_ENHANCE", 2732 "type_ref": "PA_CL_ENHANCE" 2733 }, 2734 { 2735 "chips": ["gfx6"], 2736 "map": {"at": 35352, "to": "mm"}, 2737 "name": "CGTT_PA_CLK_CTRL", 2738 "type_ref": "CGTT_PA_CLK_CTRL" 2739 }, 2740 { 2741 "chips": ["gfx6"], 2742 "map": {"at": 35360, "to": "mm"}, 2743 "name": "PA_SU_PERFCOUNTER0_SELECT", 2744 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 2745 }, 2746 { 2747 "chips": ["gfx6"], 2748 "map": {"at": 35364, "to": "mm"}, 2749 "name": "PA_SU_PERFCOUNTER1_SELECT", 2750 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 2751 }, 2752 { 2753 "chips": ["gfx6"], 2754 "map": {"at": 35368, "to": "mm"}, 2755 "name": "PA_SU_PERFCOUNTER2_SELECT", 2756 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 2757 }, 2758 { 2759 "chips": ["gfx6"], 2760 "map": {"at": 35372, "to": "mm"}, 2761 "name": "PA_SU_PERFCOUNTER3_SELECT", 2762 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 2763 }, 2764 { 2765 "chips": ["gfx6"], 2766 "map": {"at": 35376, "to": "mm"}, 2767 "name": "PA_SU_PERFCOUNTER0_LO" 2768 }, 2769 { 2770 "chips": ["gfx6"], 2771 "map": {"at": 35380, "to": "mm"}, 2772 "name": "PA_SU_PERFCOUNTER0_HI", 2773 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2774 }, 2775 { 2776 "chips": ["gfx6"], 2777 "map": {"at": 35384, "to": "mm"}, 2778 "name": "PA_SU_PERFCOUNTER1_LO" 2779 }, 2780 { 2781 "chips": ["gfx6"], 2782 "map": {"at": 35388, "to": "mm"}, 2783 "name": "PA_SU_PERFCOUNTER1_HI", 2784 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2785 }, 2786 { 2787 "chips": ["gfx6"], 2788 "map": {"at": 35392, "to": "mm"}, 2789 "name": "PA_SU_PERFCOUNTER2_LO" 2790 }, 2791 { 2792 "chips": ["gfx6"], 2793 "map": {"at": 35396, "to": "mm"}, 2794 "name": "PA_SU_PERFCOUNTER2_HI", 2795 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2796 }, 2797 { 2798 "chips": ["gfx6"], 2799 "map": {"at": 35400, "to": "mm"}, 2800 "name": "PA_SU_PERFCOUNTER3_LO" 2801 }, 2802 { 2803 "chips": ["gfx6"], 2804 "map": {"at": 35404, "to": "mm"}, 2805 "name": "PA_SU_PERFCOUNTER3_HI", 2806 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2807 }, 2808 { 2809 "chips": ["gfx6"], 2810 "map": {"at": 35408, "to": "mm"}, 2811 "name": "PA_SU_CNTL_STATUS", 2812 "type_ref": "PA_SU_CNTL_STATUS" 2813 }, 2814 { 2815 "chips": ["gfx6"], 2816 "map": {"at": 35412, "to": "mm"}, 2817 "name": "PA_SC_FIFO_DEPTH_CNTL", 2818 "type_ref": "PA_SC_FIFO_DEPTH_CNTL" 2819 }, 2820 { 2821 "chips": ["gfx6"], 2822 "map": {"at": 35424, "to": "mm"}, 2823 "name": "PA_SU_LINE_STIPPLE_VALUE", 2824 "type_ref": "PA_SU_LINE_STIPPLE_VALUE" 2825 }, 2826 { 2827 "chips": ["gfx6"], 2828 "map": {"at": 35456, "to": "mm"}, 2829 "name": "PA_SC_PERFCOUNTER0_SELECT", 2830 "type_ref": "PA_SC_PERFCOUNTER0_SELECT" 2831 }, 2832 { 2833 "chips": ["gfx6"], 2834 "map": {"at": 35460, "to": "mm"}, 2835 "name": "PA_SC_PERFCOUNTER1_SELECT", 2836 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2837 }, 2838 { 2839 "chips": ["gfx6"], 2840 "map": {"at": 35464, "to": "mm"}, 2841 "name": "PA_SC_PERFCOUNTER2_SELECT", 2842 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2843 }, 2844 { 2845 "chips": ["gfx6"], 2846 "map": {"at": 35468, "to": "mm"}, 2847 "name": "PA_SC_PERFCOUNTER3_SELECT", 2848 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2849 }, 2850 { 2851 "chips": ["gfx6"], 2852 "map": {"at": 35472, "to": "mm"}, 2853 "name": "PA_SC_PERFCOUNTER4_SELECT", 2854 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2855 }, 2856 { 2857 "chips": ["gfx6"], 2858 "map": {"at": 35476, "to": "mm"}, 2859 "name": "PA_SC_PERFCOUNTER5_SELECT", 2860 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2861 }, 2862 { 2863 "chips": ["gfx6"], 2864 "map": {"at": 35480, "to": "mm"}, 2865 "name": "PA_SC_PERFCOUNTER6_SELECT", 2866 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2867 }, 2868 { 2869 "chips": ["gfx6"], 2870 "map": {"at": 35484, "to": "mm"}, 2871 "name": "PA_SC_PERFCOUNTER7_SELECT", 2872 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2873 }, 2874 { 2875 "chips": ["gfx6"], 2876 "map": {"at": 35488, "to": "mm"}, 2877 "name": "PA_SC_PERFCOUNTER0_LO" 2878 }, 2879 { 2880 "chips": ["gfx6"], 2881 "map": {"at": 35492, "to": "mm"}, 2882 "name": "PA_SC_PERFCOUNTER0_HI" 2883 }, 2884 { 2885 "chips": ["gfx6"], 2886 "map": {"at": 35496, "to": "mm"}, 2887 "name": "PA_SC_PERFCOUNTER1_LO" 2888 }, 2889 { 2890 "chips": ["gfx6"], 2891 "map": {"at": 35500, "to": "mm"}, 2892 "name": "PA_SC_PERFCOUNTER1_HI" 2893 }, 2894 { 2895 "chips": ["gfx6"], 2896 "map": {"at": 35504, "to": "mm"}, 2897 "name": "PA_SC_PERFCOUNTER2_LO" 2898 }, 2899 { 2900 "chips": ["gfx6"], 2901 "map": {"at": 35508, "to": "mm"}, 2902 "name": "PA_SC_PERFCOUNTER2_HI" 2903 }, 2904 { 2905 "chips": ["gfx6"], 2906 "map": {"at": 35512, "to": "mm"}, 2907 "name": "PA_SC_PERFCOUNTER3_LO" 2908 }, 2909 { 2910 "chips": ["gfx6"], 2911 "map": {"at": 35516, "to": "mm"}, 2912 "name": "PA_SC_PERFCOUNTER3_HI" 2913 }, 2914 { 2915 "chips": ["gfx6"], 2916 "map": {"at": 35520, "to": "mm"}, 2917 "name": "PA_SC_PERFCOUNTER4_LO" 2918 }, 2919 { 2920 "chips": ["gfx6"], 2921 "map": {"at": 35524, "to": "mm"}, 2922 "name": "PA_SC_PERFCOUNTER4_HI" 2923 }, 2924 { 2925 "chips": ["gfx6"], 2926 "map": {"at": 35528, "to": "mm"}, 2927 "name": "PA_SC_PERFCOUNTER5_LO" 2928 }, 2929 { 2930 "chips": ["gfx6"], 2931 "map": {"at": 35532, "to": "mm"}, 2932 "name": "PA_SC_PERFCOUNTER5_HI" 2933 }, 2934 { 2935 "chips": ["gfx6"], 2936 "map": {"at": 35536, "to": "mm"}, 2937 "name": "PA_SC_PERFCOUNTER6_LO" 2938 }, 2939 { 2940 "chips": ["gfx6"], 2941 "map": {"at": 35540, "to": "mm"}, 2942 "name": "PA_SC_PERFCOUNTER6_HI" 2943 }, 2944 { 2945 "chips": ["gfx6"], 2946 "map": {"at": 35544, "to": "mm"}, 2947 "name": "PA_SC_PERFCOUNTER7_LO" 2948 }, 2949 { 2950 "chips": ["gfx6"], 2951 "map": {"at": 35548, "to": "mm"}, 2952 "name": "PA_SC_PERFCOUNTER7_HI" 2953 }, 2954 { 2955 "chips": ["gfx6"], 2956 "map": {"at": 35600, "to": "mm"}, 2957 "name": "PA_SC_LINE_STIPPLE_STATE", 2958 "type_ref": "PA_SC_LINE_STIPPLE_STATE" 2959 }, 2960 { 2961 "chips": ["gfx6"], 2962 "map": {"at": 35620, "to": "mm"}, 2963 "name": "PA_SC_FORCE_EOV_MAX_CNTS", 2964 "type_ref": "PA_SC_FORCE_EOV_MAX_CNTS" 2965 }, 2966 { 2967 "chips": ["gfx6"], 2968 "map": {"at": 35624, "to": "mm"}, 2969 "name": "CGTT_SC_CLK_CTRL", 2970 "type_ref": "CGTT_SC_CLK_CTRL" 2971 }, 2972 { 2973 "chips": ["gfx6"], 2974 "map": {"at": 35788, "to": "mm"}, 2975 "name": "PA_SC_FIFO_SIZE", 2976 "type_ref": "PA_SC_FIFO_SIZE" 2977 }, 2978 { 2979 "chips": ["gfx6"], 2980 "map": {"at": 35796, "to": "mm"}, 2981 "name": "PA_SC_IF_FIFO_SIZE", 2982 "type_ref": "PA_SC_IF_FIFO_SIZE" 2983 }, 2984 { 2985 "chips": ["gfx6"], 2986 "map": {"at": 35800, "to": "mm"}, 2987 "name": "PA_SC_DEBUG_CNTL", 2988 "type_ref": "PA_SC_DEBUG_CNTL" 2989 }, 2990 { 2991 "chips": ["gfx6"], 2992 "map": {"at": 35804, "to": "mm"}, 2993 "name": "PA_SC_DEBUG_DATA" 2994 }, 2995 { 2996 "chips": ["gfx6"], 2997 "map": {"at": 35824, "to": "mm"}, 2998 "name": "PA_SC_ENHANCE", 2999 "type_ref": "PA_SC_ENHANCE" 3000 }, 3001 { 3002 "chips": ["gfx6"], 3003 "map": {"at": 35840, "to": "mm"}, 3004 "name": "SQ_CONFIG", 3005 "type_ref": "SQ_CONFIG" 3006 }, 3007 { 3008 "chips": ["gfx6"], 3009 "map": {"at": 35844, "to": "mm"}, 3010 "name": "SQC_CONFIG", 3011 "type_ref": "SQC_CONFIG" 3012 }, 3013 { 3014 "chips": ["gfx6"], 3015 "map": {"at": 35848, "to": "mm"}, 3016 "name": "SQC_CACHES", 3017 "type_ref": "SQC_CACHES" 3018 }, 3019 { 3020 "chips": ["gfx6"], 3021 "map": {"at": 35852, "to": "mm"}, 3022 "name": "SQ_RANDOM_WAVE_PRI", 3023 "type_ref": "SQ_RANDOM_WAVE_PRI" 3024 }, 3025 { 3026 "chips": ["gfx6"], 3027 "map": {"at": 35856, "to": "mm"}, 3028 "name": "SQ_REG_CREDITS", 3029 "type_ref": "SQ_REG_CREDITS" 3030 }, 3031 { 3032 "chips": ["gfx6"], 3033 "map": {"at": 35860, "to": "mm"}, 3034 "name": "SQ_FIFO_SIZES", 3035 "type_ref": "SQ_FIFO_SIZES" 3036 }, 3037 { 3038 "chips": ["gfx6"], 3039 "map": {"at": 35864, "to": "mm"}, 3040 "name": "SQ_PERFCOUNTER_CTRL", 3041 "type_ref": "SQ_PERFCOUNTER_CTRL" 3042 }, 3043 { 3044 "chips": ["gfx6"], 3045 "map": {"at": 35868, "to": "mm"}, 3046 "name": "CC_SQC_BANK_DISABLE", 3047 "type_ref": "CC_SQC_BANK_DISABLE" 3048 }, 3049 { 3050 "chips": ["gfx6"], 3051 "map": {"at": 35872, "to": "mm"}, 3052 "name": "USER_SQC_BANK_DISABLE", 3053 "type_ref": "CC_SQC_BANK_DISABLE" 3054 }, 3055 { 3056 "chips": ["gfx6"], 3057 "map": {"at": 35876, "to": "mm"}, 3058 "name": "SQ_DEBUG_STS_GLOBAL", 3059 "type_ref": "SQ_DEBUG_STS_GLOBAL" 3060 }, 3061 { 3062 "chips": ["gfx6"], 3063 "map": {"at": 35968, "to": "mm"}, 3064 "name": "SQ_PERFCOUNTER0_LO" 3065 }, 3066 { 3067 "chips": ["gfx6"], 3068 "map": {"at": 35972, "to": "mm"}, 3069 "name": "SQ_PERFCOUNTER0_HI" 3070 }, 3071 { 3072 "chips": ["gfx6"], 3073 "map": {"at": 35976, "to": "mm"}, 3074 "name": "SQ_PERFCOUNTER1_LO" 3075 }, 3076 { 3077 "chips": ["gfx6"], 3078 "map": {"at": 35980, "to": "mm"}, 3079 "name": "SQ_PERFCOUNTER1_HI" 3080 }, 3081 { 3082 "chips": ["gfx6"], 3083 "map": {"at": 35984, "to": "mm"}, 3084 "name": "SQ_PERFCOUNTER2_LO" 3085 }, 3086 { 3087 "chips": ["gfx6"], 3088 "map": {"at": 35988, "to": "mm"}, 3089 "name": "SQ_PERFCOUNTER2_HI" 3090 }, 3091 { 3092 "chips": ["gfx6"], 3093 "map": {"at": 35992, "to": "mm"}, 3094 "name": "SQ_PERFCOUNTER3_LO" 3095 }, 3096 { 3097 "chips": ["gfx6"], 3098 "map": {"at": 35996, "to": "mm"}, 3099 "name": "SQ_PERFCOUNTER3_HI" 3100 }, 3101 { 3102 "chips": ["gfx6"], 3103 "map": {"at": 36000, "to": "mm"}, 3104 "name": "SQ_PERFCOUNTER4_LO" 3105 }, 3106 { 3107 "chips": ["gfx6"], 3108 "map": {"at": 36004, "to": "mm"}, 3109 "name": "SQ_PERFCOUNTER4_HI" 3110 }, 3111 { 3112 "chips": ["gfx6"], 3113 "map": {"at": 36008, "to": "mm"}, 3114 "name": "SQ_PERFCOUNTER5_LO" 3115 }, 3116 { 3117 "chips": ["gfx6"], 3118 "map": {"at": 36012, "to": "mm"}, 3119 "name": "SQ_PERFCOUNTER5_HI" 3120 }, 3121 { 3122 "chips": ["gfx6"], 3123 "map": {"at": 36016, "to": "mm"}, 3124 "name": "SQ_PERFCOUNTER6_LO" 3125 }, 3126 { 3127 "chips": ["gfx6"], 3128 "map": {"at": 36020, "to": "mm"}, 3129 "name": "SQ_PERFCOUNTER6_HI" 3130 }, 3131 { 3132 "chips": ["gfx6"], 3133 "map": {"at": 36024, "to": "mm"}, 3134 "name": "SQ_PERFCOUNTER7_LO" 3135 }, 3136 { 3137 "chips": ["gfx6"], 3138 "map": {"at": 36028, "to": "mm"}, 3139 "name": "SQ_PERFCOUNTER7_HI" 3140 }, 3141 { 3142 "chips": ["gfx6"], 3143 "map": {"at": 36032, "to": "mm"}, 3144 "name": "SQ_PERFCOUNTER8_LO" 3145 }, 3146 { 3147 "chips": ["gfx6"], 3148 "map": {"at": 36036, "to": "mm"}, 3149 "name": "SQ_PERFCOUNTER8_HI" 3150 }, 3151 { 3152 "chips": ["gfx6"], 3153 "map": {"at": 36040, "to": "mm"}, 3154 "name": "SQ_PERFCOUNTER9_LO" 3155 }, 3156 { 3157 "chips": ["gfx6"], 3158 "map": {"at": 36044, "to": "mm"}, 3159 "name": "SQ_PERFCOUNTER9_HI" 3160 }, 3161 { 3162 "chips": ["gfx6"], 3163 "map": {"at": 36048, "to": "mm"}, 3164 "name": "SQ_PERFCOUNTER10_LO" 3165 }, 3166 { 3167 "chips": ["gfx6"], 3168 "map": {"at": 36052, "to": "mm"}, 3169 "name": "SQ_PERFCOUNTER10_HI" 3170 }, 3171 { 3172 "chips": ["gfx6"], 3173 "map": {"at": 36056, "to": "mm"}, 3174 "name": "SQ_PERFCOUNTER11_LO" 3175 }, 3176 { 3177 "chips": ["gfx6"], 3178 "map": {"at": 36060, "to": "mm"}, 3179 "name": "SQ_PERFCOUNTER11_HI" 3180 }, 3181 { 3182 "chips": ["gfx6"], 3183 "map": {"at": 36064, "to": "mm"}, 3184 "name": "SQ_PERFCOUNTER12_LO" 3185 }, 3186 { 3187 "chips": ["gfx6"], 3188 "map": {"at": 36068, "to": "mm"}, 3189 "name": "SQ_PERFCOUNTER12_HI" 3190 }, 3191 { 3192 "chips": ["gfx6"], 3193 "map": {"at": 36072, "to": "mm"}, 3194 "name": "SQ_PERFCOUNTER13_LO" 3195 }, 3196 { 3197 "chips": ["gfx6"], 3198 "map": {"at": 36076, "to": "mm"}, 3199 "name": "SQ_PERFCOUNTER13_HI" 3200 }, 3201 { 3202 "chips": ["gfx6"], 3203 "map": {"at": 36080, "to": "mm"}, 3204 "name": "SQ_PERFCOUNTER14_LO" 3205 }, 3206 { 3207 "chips": ["gfx6"], 3208 "map": {"at": 36084, "to": "mm"}, 3209 "name": "SQ_PERFCOUNTER14_HI" 3210 }, 3211 { 3212 "chips": ["gfx6"], 3213 "map": {"at": 36088, "to": "mm"}, 3214 "name": "SQ_PERFCOUNTER15_LO" 3215 }, 3216 { 3217 "chips": ["gfx6"], 3218 "map": {"at": 36092, "to": "mm"}, 3219 "name": "SQ_PERFCOUNTER15_HI" 3220 }, 3221 { 3222 "chips": ["gfx6"], 3223 "map": {"at": 36096, "to": "mm"}, 3224 "name": "SQ_PERFCOUNTER0_SELECT", 3225 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3226 }, 3227 { 3228 "chips": ["gfx6"], 3229 "map": {"at": 36100, "to": "mm"}, 3230 "name": "SQ_PERFCOUNTER1_SELECT", 3231 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3232 }, 3233 { 3234 "chips": ["gfx6"], 3235 "map": {"at": 36104, "to": "mm"}, 3236 "name": "SQ_PERFCOUNTER2_SELECT", 3237 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3238 }, 3239 { 3240 "chips": ["gfx6"], 3241 "map": {"at": 36108, "to": "mm"}, 3242 "name": "SQ_PERFCOUNTER3_SELECT", 3243 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3244 }, 3245 { 3246 "chips": ["gfx6"], 3247 "map": {"at": 36112, "to": "mm"}, 3248 "name": "SQ_PERFCOUNTER4_SELECT", 3249 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3250 }, 3251 { 3252 "chips": ["gfx6"], 3253 "map": {"at": 36116, "to": "mm"}, 3254 "name": "SQ_PERFCOUNTER5_SELECT", 3255 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3256 }, 3257 { 3258 "chips": ["gfx6"], 3259 "map": {"at": 36120, "to": "mm"}, 3260 "name": "SQ_PERFCOUNTER6_SELECT", 3261 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3262 }, 3263 { 3264 "chips": ["gfx6"], 3265 "map": {"at": 36124, "to": "mm"}, 3266 "name": "SQ_PERFCOUNTER7_SELECT", 3267 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3268 }, 3269 { 3270 "chips": ["gfx6"], 3271 "map": {"at": 36128, "to": "mm"}, 3272 "name": "SQ_PERFCOUNTER8_SELECT", 3273 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3274 }, 3275 { 3276 "chips": ["gfx6"], 3277 "map": {"at": 36132, "to": "mm"}, 3278 "name": "SQ_PERFCOUNTER9_SELECT", 3279 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3280 }, 3281 { 3282 "chips": ["gfx6"], 3283 "map": {"at": 36136, "to": "mm"}, 3284 "name": "SQ_PERFCOUNTER10_SELECT", 3285 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3286 }, 3287 { 3288 "chips": ["gfx6"], 3289 "map": {"at": 36140, "to": "mm"}, 3290 "name": "SQ_PERFCOUNTER11_SELECT", 3291 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3292 }, 3293 { 3294 "chips": ["gfx6"], 3295 "map": {"at": 36144, "to": "mm"}, 3296 "name": "SQ_PERFCOUNTER12_SELECT", 3297 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3298 }, 3299 { 3300 "chips": ["gfx6"], 3301 "map": {"at": 36148, "to": "mm"}, 3302 "name": "SQ_PERFCOUNTER13_SELECT", 3303 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3304 }, 3305 { 3306 "chips": ["gfx6"], 3307 "map": {"at": 36152, "to": "mm"}, 3308 "name": "SQ_PERFCOUNTER14_SELECT", 3309 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3310 }, 3311 { 3312 "chips": ["gfx6"], 3313 "map": {"at": 36156, "to": "mm"}, 3314 "name": "SQ_PERFCOUNTER15_SELECT", 3315 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3316 }, 3317 { 3318 "chips": ["gfx6"], 3319 "map": {"at": 36224, "to": "mm"}, 3320 "name": "SQ_ALU_CLK_CTRL", 3321 "type_ref": "SQ_ALU_CLK_CTRL" 3322 }, 3323 { 3324 "chips": ["gfx6"], 3325 "map": {"at": 36228, "to": "mm"}, 3326 "name": "SQ_TEX_CLK_CTRL", 3327 "type_ref": "SQ_ALU_CLK_CTRL" 3328 }, 3329 { 3330 "chips": ["gfx6"], 3331 "map": {"at": 36232, "to": "mm"}, 3332 "name": "CGTT_SQ_CLK_CTRL", 3333 "type_ref": "CGTT_SQ_CLK_CTRL" 3334 }, 3335 { 3336 "chips": ["gfx6"], 3337 "map": {"at": 36236, "to": "mm"}, 3338 "name": "CGTT_SQG_CLK_CTRL", 3339 "type_ref": "CGTT_SQ_CLK_CTRL" 3340 }, 3341 { 3342 "chips": ["gfx6"], 3343 "map": {"at": 36320, "to": "mm"}, 3344 "name": "SQ_IND_INDEX", 3345 "type_ref": "SQ_IND_INDEX" 3346 }, 3347 { 3348 "chips": ["gfx6"], 3349 "map": {"at": 36324, "to": "mm"}, 3350 "name": "SQ_IND_DATA" 3351 }, 3352 { 3353 "chips": ["gfx6"], 3354 "map": {"at": 36336, "to": "mm"}, 3355 "name": "SQ_TIME_HI" 3356 }, 3357 { 3358 "chips": ["gfx6"], 3359 "map": {"at": 36340, "to": "mm"}, 3360 "name": "SQ_TIME_LO" 3361 }, 3362 { 3363 "chips": ["gfx6"], 3364 "map": {"at": 36352, "to": "mm"}, 3365 "name": "SQ_THREAD_TRACE_BASE" 3366 }, 3367 { 3368 "chips": ["gfx6"], 3369 "map": {"at": 36356, "to": "mm"}, 3370 "name": "SQ_THREAD_TRACE_SIZE", 3371 "type_ref": "SQ_THREAD_TRACE_SIZE" 3372 }, 3373 { 3374 "chips": ["gfx6"], 3375 "map": {"at": 36360, "to": "mm"}, 3376 "name": "SQ_THREAD_TRACE_MASK", 3377 "type_ref": "SQ_THREAD_TRACE_MASK" 3378 }, 3379 { 3380 "chips": ["gfx6"], 3381 "map": {"at": 36364, "to": "mm"}, 3382 "name": "SQ_THREAD_TRACE_TOKEN_MASK", 3383 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK" 3384 }, 3385 { 3386 "chips": ["gfx6"], 3387 "map": {"at": 36368, "to": "mm"}, 3388 "name": "SQ_THREAD_TRACE_PERF_MASK", 3389 "type_ref": "SQ_THREAD_TRACE_PERF_MASK" 3390 }, 3391 { 3392 "chips": ["gfx6"], 3393 "map": {"at": 36384, "to": "mm"}, 3394 "name": "SQ_THREAD_TRACE_USERDATA_0" 3395 }, 3396 { 3397 "chips": ["gfx6"], 3398 "map": {"at": 36388, "to": "mm"}, 3399 "name": "SQ_THREAD_TRACE_USERDATA_1" 3400 }, 3401 { 3402 "chips": ["gfx6"], 3403 "map": {"at": 36392, "to": "mm"}, 3404 "name": "SQ_THREAD_TRACE_USERDATA_2" 3405 }, 3406 { 3407 "chips": ["gfx6"], 3408 "map": {"at": 36396, "to": "mm"}, 3409 "name": "SQ_THREAD_TRACE_USERDATA_3" 3410 }, 3411 { 3412 "chips": ["gfx6"], 3413 "map": {"at": 36400, "to": "mm"}, 3414 "name": "SQ_THREAD_TRACE_WPTR", 3415 "type_ref": "SQ_THREAD_TRACE_WPTR" 3416 }, 3417 { 3418 "chips": ["gfx6"], 3419 "map": {"at": 36404, "to": "mm"}, 3420 "name": "SQ_THREAD_TRACE_STATUS", 3421 "type_ref": "SQ_THREAD_TRACE_STATUS" 3422 }, 3423 { 3424 "chips": ["gfx6"], 3425 "map": {"at": 36408, "to": "mm"}, 3426 "name": "SQ_THREAD_TRACE_MODE", 3427 "type_ref": "SQ_THREAD_TRACE_MODE" 3428 }, 3429 { 3430 "chips": ["gfx6"], 3431 "map": {"at": 36412, "to": "mm"}, 3432 "name": "SQ_THREAD_TRACE_CTRL", 3433 "type_ref": "SQ_THREAD_TRACE_CTRL" 3434 }, 3435 { 3436 "chips": ["gfx6"], 3437 "map": {"at": 36416, "to": "mm"}, 3438 "name": "SQ_THREAD_TRACE_CNTR" 3439 }, 3440 { 3441 "chips": ["gfx6"], 3442 "map": {"at": 36424, "to": "mm"}, 3443 "name": "SQ_THREAD_TRACE_HIWATER", 3444 "type_ref": "SQ_THREAD_TRACE_HIWATER" 3445 }, 3446 { 3447 "chips": ["gfx6"], 3448 "map": {"at": 36440, "to": "mm"}, 3449 "name": "SQ_POWER_THROTTLE", 3450 "type_ref": "SQ_POWER_THROTTLE" 3451 }, 3452 { 3453 "chips": ["gfx6"], 3454 "map": {"at": 36444, "to": "mm"}, 3455 "name": "SQ_POWER_THROTTLE2", 3456 "type_ref": "SQ_POWER_THROTTLE2" 3457 }, 3458 { 3459 "chips": ["gfx6"], 3460 "map": {"at": 36448, "to": "mm"}, 3461 "name": "SQ_LB_CTR_CTRL", 3462 "type_ref": "SQ_LB_CTR_CTRL" 3463 }, 3464 { 3465 "chips": ["gfx6"], 3466 "map": {"at": 36452, "to": "mm"}, 3467 "name": "SQ_LB_DATA_ALU_CYCLES" 3468 }, 3469 { 3470 "chips": ["gfx6"], 3471 "map": {"at": 36456, "to": "mm"}, 3472 "name": "SQ_LB_DATA_TEX_CYCLES" 3473 }, 3474 { 3475 "chips": ["gfx6"], 3476 "map": {"at": 36460, "to": "mm"}, 3477 "name": "SQ_LB_DATA_ALU_STALLS" 3478 }, 3479 { 3480 "chips": ["gfx6"], 3481 "map": {"at": 36464, "to": "mm"}, 3482 "name": "SQ_LB_DATA_TEX_STALLS" 3483 }, 3484 { 3485 "chips": ["gfx6"], 3486 "map": {"at": 36480, "to": "mm"}, 3487 "name": "SQC_SECDED_CNT", 3488 "type_ref": "SQC_SECDED_CNT" 3489 }, 3490 { 3491 "chips": ["gfx6"], 3492 "map": {"at": 36484, "to": "mm"}, 3493 "name": "SQ_SEC_CNT", 3494 "type_ref": "SQ_SEC_CNT" 3495 }, 3496 { 3497 "chips": ["gfx6"], 3498 "map": {"at": 36488, "to": "mm"}, 3499 "name": "SQ_DED_CNT", 3500 "type_ref": "SQ_DED_CNT" 3501 }, 3502 { 3503 "chips": ["gfx6"], 3504 "map": {"at": 36492, "to": "mm"}, 3505 "name": "SQ_DED_INFO", 3506 "type_ref": "SQ_DED_INFO" 3507 }, 3508 { 3509 "chips": ["gfx6"], 3510 "map": {"at": 36608, "to": "mm"}, 3511 "name": "SQ_BUF_RSRC_WORD0" 3512 }, 3513 { 3514 "chips": ["gfx6"], 3515 "map": {"at": 36612, "to": "mm"}, 3516 "name": "SQ_BUF_RSRC_WORD1", 3517 "type_ref": "SQ_BUF_RSRC_WORD1" 3518 }, 3519 { 3520 "chips": ["gfx6"], 3521 "map": {"at": 36616, "to": "mm"}, 3522 "name": "SQ_BUF_RSRC_WORD2" 3523 }, 3524 { 3525 "chips": ["gfx6"], 3526 "map": {"at": 36620, "to": "mm"}, 3527 "name": "SQ_BUF_RSRC_WORD3", 3528 "type_ref": "SQ_BUF_RSRC_WORD3" 3529 }, 3530 { 3531 "chips": ["gfx6"], 3532 "map": {"at": 36624, "to": "mm"}, 3533 "name": "SQ_IMG_RSRC_WORD0" 3534 }, 3535 { 3536 "chips": ["gfx6"], 3537 "map": {"at": 36628, "to": "mm"}, 3538 "name": "SQ_IMG_RSRC_WORD1", 3539 "type_ref": "SQ_IMG_RSRC_WORD1" 3540 }, 3541 { 3542 "chips": ["gfx6"], 3543 "map": {"at": 36632, "to": "mm"}, 3544 "name": "SQ_IMG_RSRC_WORD2", 3545 "type_ref": "SQ_IMG_RSRC_WORD2" 3546 }, 3547 { 3548 "chips": ["gfx6"], 3549 "map": {"at": 36636, "to": "mm"}, 3550 "name": "SQ_IMG_RSRC_WORD3", 3551 "type_ref": "SQ_IMG_RSRC_WORD3" 3552 }, 3553 { 3554 "chips": ["gfx6"], 3555 "map": {"at": 36640, "to": "mm"}, 3556 "name": "SQ_IMG_RSRC_WORD4", 3557 "type_ref": "SQ_IMG_RSRC_WORD4" 3558 }, 3559 { 3560 "chips": ["gfx6"], 3561 "map": {"at": 36644, "to": "mm"}, 3562 "name": "SQ_IMG_RSRC_WORD5", 3563 "type_ref": "SQ_IMG_RSRC_WORD5" 3564 }, 3565 { 3566 "chips": ["gfx6"], 3567 "map": {"at": 36648, "to": "mm"}, 3568 "name": "SQ_IMG_RSRC_WORD6", 3569 "type_ref": "SQ_IMG_RSRC_WORD6" 3570 }, 3571 { 3572 "chips": ["gfx6"], 3573 "map": {"at": 36652, "to": "mm"}, 3574 "name": "SQ_IMG_RSRC_WORD7" 3575 }, 3576 { 3577 "chips": ["gfx6"], 3578 "map": {"at": 36656, "to": "mm"}, 3579 "name": "SQ_IMG_SAMP_WORD0", 3580 "type_ref": "SQ_IMG_SAMP_WORD0" 3581 }, 3582 { 3583 "chips": ["gfx6"], 3584 "map": {"at": 36660, "to": "mm"}, 3585 "name": "SQ_IMG_SAMP_WORD1", 3586 "type_ref": "SQ_IMG_SAMP_WORD1" 3587 }, 3588 { 3589 "chips": ["gfx6"], 3590 "map": {"at": 36664, "to": "mm"}, 3591 "name": "SQ_IMG_SAMP_WORD2", 3592 "type_ref": "SQ_IMG_SAMP_WORD2" 3593 }, 3594 { 3595 "chips": ["gfx6"], 3596 "map": {"at": 36668, "to": "mm"}, 3597 "name": "SQ_IMG_SAMP_WORD3", 3598 "type_ref": "SQ_IMG_SAMP_WORD3" 3599 }, 3600 { 3601 "chips": ["gfx6"], 3602 "map": {"at": 37120, "to": "mm"}, 3603 "name": "SPI_CONFIG_CNTL", 3604 "type_ref": "SPI_CONFIG_CNTL" 3605 }, 3606 { 3607 "chips": ["gfx6"], 3608 "map": {"at": 38156, "to": "mm"}, 3609 "name": "TA_CS_BC_BASE_ADDR" 3610 }, 3611 { 3612 "chips": ["gfx6"], 3613 "map": {"at": 39160, "to": "mm"}, 3614 "name": "GB_ADDR_CONFIG", 3615 "type_ref": "GB_ADDR_CONFIG" 3616 }, 3617 { 3618 "chips": ["gfx6"], 3619 "map": {"at": 39184, "to": "mm"}, 3620 "name": "GB_TILE_MODE0", 3621 "type_ref": "GB_TILE_MODE0" 3622 }, 3623 { 3624 "chips": ["gfx6"], 3625 "map": {"at": 39188, "to": "mm"}, 3626 "name": "GB_TILE_MODE1", 3627 "type_ref": "GB_TILE_MODE10" 3628 }, 3629 { 3630 "chips": ["gfx6"], 3631 "map": {"at": 39192, "to": "mm"}, 3632 "name": "GB_TILE_MODE2", 3633 "type_ref": "GB_TILE_MODE10" 3634 }, 3635 { 3636 "chips": ["gfx6"], 3637 "map": {"at": 39196, "to": "mm"}, 3638 "name": "GB_TILE_MODE3", 3639 "type_ref": "GB_TILE_MODE10" 3640 }, 3641 { 3642 "chips": ["gfx6"], 3643 "map": {"at": 39200, "to": "mm"}, 3644 "name": "GB_TILE_MODE4", 3645 "type_ref": "GB_TILE_MODE10" 3646 }, 3647 { 3648 "chips": ["gfx6"], 3649 "map": {"at": 39204, "to": "mm"}, 3650 "name": "GB_TILE_MODE5", 3651 "type_ref": "GB_TILE_MODE10" 3652 }, 3653 { 3654 "chips": ["gfx6"], 3655 "map": {"at": 39208, "to": "mm"}, 3656 "name": "GB_TILE_MODE6", 3657 "type_ref": "GB_TILE_MODE10" 3658 }, 3659 { 3660 "chips": ["gfx6"], 3661 "map": {"at": 39212, "to": "mm"}, 3662 "name": "GB_TILE_MODE7", 3663 "type_ref": "GB_TILE_MODE10" 3664 }, 3665 { 3666 "chips": ["gfx6"], 3667 "map": {"at": 39216, "to": "mm"}, 3668 "name": "GB_TILE_MODE8", 3669 "type_ref": "GB_TILE_MODE10" 3670 }, 3671 { 3672 "chips": ["gfx6"], 3673 "map": {"at": 39220, "to": "mm"}, 3674 "name": "GB_TILE_MODE9", 3675 "type_ref": "GB_TILE_MODE10" 3676 }, 3677 { 3678 "chips": ["gfx6"], 3679 "map": {"at": 39224, "to": "mm"}, 3680 "name": "GB_TILE_MODE10", 3681 "type_ref": "GB_TILE_MODE10" 3682 }, 3683 { 3684 "chips": ["gfx6"], 3685 "map": {"at": 39228, "to": "mm"}, 3686 "name": "GB_TILE_MODE11", 3687 "type_ref": "GB_TILE_MODE10" 3688 }, 3689 { 3690 "chips": ["gfx6"], 3691 "map": {"at": 39232, "to": "mm"}, 3692 "name": "GB_TILE_MODE12", 3693 "type_ref": "GB_TILE_MODE10" 3694 }, 3695 { 3696 "chips": ["gfx6"], 3697 "map": {"at": 39236, "to": "mm"}, 3698 "name": "GB_TILE_MODE13", 3699 "type_ref": "GB_TILE_MODE10" 3700 }, 3701 { 3702 "chips": ["gfx6"], 3703 "map": {"at": 39240, "to": "mm"}, 3704 "name": "GB_TILE_MODE14", 3705 "type_ref": "GB_TILE_MODE10" 3706 }, 3707 { 3708 "chips": ["gfx6"], 3709 "map": {"at": 39244, "to": "mm"}, 3710 "name": "GB_TILE_MODE15", 3711 "type_ref": "GB_TILE_MODE10" 3712 }, 3713 { 3714 "chips": ["gfx6"], 3715 "map": {"at": 39248, "to": "mm"}, 3716 "name": "GB_TILE_MODE16", 3717 "type_ref": "GB_TILE_MODE10" 3718 }, 3719 { 3720 "chips": ["gfx6"], 3721 "map": {"at": 39252, "to": "mm"}, 3722 "name": "GB_TILE_MODE17", 3723 "type_ref": "GB_TILE_MODE10" 3724 }, 3725 { 3726 "chips": ["gfx6"], 3727 "map": {"at": 39256, "to": "mm"}, 3728 "name": "GB_TILE_MODE18", 3729 "type_ref": "GB_TILE_MODE10" 3730 }, 3731 { 3732 "chips": ["gfx6"], 3733 "map": {"at": 39260, "to": "mm"}, 3734 "name": "GB_TILE_MODE19", 3735 "type_ref": "GB_TILE_MODE10" 3736 }, 3737 { 3738 "chips": ["gfx6"], 3739 "map": {"at": 39264, "to": "mm"}, 3740 "name": "GB_TILE_MODE20", 3741 "type_ref": "GB_TILE_MODE10" 3742 }, 3743 { 3744 "chips": ["gfx6"], 3745 "map": {"at": 39268, "to": "mm"}, 3746 "name": "GB_TILE_MODE21", 3747 "type_ref": "GB_TILE_MODE10" 3748 }, 3749 { 3750 "chips": ["gfx6"], 3751 "map": {"at": 39272, "to": "mm"}, 3752 "name": "GB_TILE_MODE22", 3753 "type_ref": "GB_TILE_MODE10" 3754 }, 3755 { 3756 "chips": ["gfx6"], 3757 "map": {"at": 39276, "to": "mm"}, 3758 "name": "GB_TILE_MODE23", 3759 "type_ref": "GB_TILE_MODE10" 3760 }, 3761 { 3762 "chips": ["gfx6"], 3763 "map": {"at": 39280, "to": "mm"}, 3764 "name": "GB_TILE_MODE24", 3765 "type_ref": "GB_TILE_MODE10" 3766 }, 3767 { 3768 "chips": ["gfx6"], 3769 "map": {"at": 39284, "to": "mm"}, 3770 "name": "GB_TILE_MODE25", 3771 "type_ref": "GB_TILE_MODE10" 3772 }, 3773 { 3774 "chips": ["gfx6"], 3775 "map": {"at": 39288, "to": "mm"}, 3776 "name": "GB_TILE_MODE26", 3777 "type_ref": "GB_TILE_MODE10" 3778 }, 3779 { 3780 "chips": ["gfx6"], 3781 "map": {"at": 39292, "to": "mm"}, 3782 "name": "GB_TILE_MODE27", 3783 "type_ref": "GB_TILE_MODE10" 3784 }, 3785 { 3786 "chips": ["gfx6"], 3787 "map": {"at": 39296, "to": "mm"}, 3788 "name": "GB_TILE_MODE28", 3789 "type_ref": "GB_TILE_MODE10" 3790 }, 3791 { 3792 "chips": ["gfx6"], 3793 "map": {"at": 39300, "to": "mm"}, 3794 "name": "GB_TILE_MODE29", 3795 "type_ref": "GB_TILE_MODE10" 3796 }, 3797 { 3798 "chips": ["gfx6"], 3799 "map": {"at": 39304, "to": "mm"}, 3800 "name": "GB_TILE_MODE30", 3801 "type_ref": "GB_TILE_MODE10" 3802 }, 3803 { 3804 "chips": ["gfx6"], 3805 "map": {"at": 39308, "to": "mm"}, 3806 "name": "GB_TILE_MODE31", 3807 "type_ref": "GB_TILE_MODE10" 3808 }, 3809 { 3810 "chips": ["gfx6"], 3811 "map": {"at": 45056, "to": "mm"}, 3812 "name": "SPI_SHADER_TBA_LO_PS" 3813 }, 3814 { 3815 "chips": ["gfx6"], 3816 "map": {"at": 45060, "to": "mm"}, 3817 "name": "SPI_SHADER_TBA_HI_PS", 3818 "type_ref": "SPI_SHADER_PGM_HI_ES" 3819 }, 3820 { 3821 "chips": ["gfx6"], 3822 "map": {"at": 45064, "to": "mm"}, 3823 "name": "SPI_SHADER_TMA_LO_PS" 3824 }, 3825 { 3826 "chips": ["gfx6"], 3827 "map": {"at": 45068, "to": "mm"}, 3828 "name": "SPI_SHADER_TMA_HI_PS", 3829 "type_ref": "SPI_SHADER_PGM_HI_ES" 3830 }, 3831 { 3832 "chips": ["gfx6"], 3833 "map": {"at": 45088, "to": "mm"}, 3834 "name": "SPI_SHADER_PGM_LO_PS" 3835 }, 3836 { 3837 "chips": ["gfx6"], 3838 "map": {"at": 45092, "to": "mm"}, 3839 "name": "SPI_SHADER_PGM_HI_PS", 3840 "type_ref": "SPI_SHADER_PGM_HI_ES" 3841 }, 3842 { 3843 "chips": ["gfx6"], 3844 "map": {"at": 45096, "to": "mm"}, 3845 "name": "SPI_SHADER_PGM_RSRC1_PS", 3846 "type_ref": "SPI_SHADER_PGM_RSRC1_PS" 3847 }, 3848 { 3849 "chips": ["gfx6"], 3850 "map": {"at": 45100, "to": "mm"}, 3851 "name": "SPI_SHADER_PGM_RSRC2_PS", 3852 "type_ref": "SPI_SHADER_PGM_RSRC2_PS" 3853 }, 3854 { 3855 "chips": ["gfx6"], 3856 "map": {"at": 45104, "to": "mm"}, 3857 "name": "SPI_SHADER_USER_DATA_PS_0" 3858 }, 3859 { 3860 "chips": ["gfx6"], 3861 "map": {"at": 45108, "to": "mm"}, 3862 "name": "SPI_SHADER_USER_DATA_PS_1" 3863 }, 3864 { 3865 "chips": ["gfx6"], 3866 "map": {"at": 45112, "to": "mm"}, 3867 "name": "SPI_SHADER_USER_DATA_PS_2" 3868 }, 3869 { 3870 "chips": ["gfx6"], 3871 "map": {"at": 45116, "to": "mm"}, 3872 "name": "SPI_SHADER_USER_DATA_PS_3" 3873 }, 3874 { 3875 "chips": ["gfx6"], 3876 "map": {"at": 45120, "to": "mm"}, 3877 "name": "SPI_SHADER_USER_DATA_PS_4" 3878 }, 3879 { 3880 "chips": ["gfx6"], 3881 "map": {"at": 45124, "to": "mm"}, 3882 "name": "SPI_SHADER_USER_DATA_PS_5" 3883 }, 3884 { 3885 "chips": ["gfx6"], 3886 "map": {"at": 45128, "to": "mm"}, 3887 "name": "SPI_SHADER_USER_DATA_PS_6" 3888 }, 3889 { 3890 "chips": ["gfx6"], 3891 "map": {"at": 45132, "to": "mm"}, 3892 "name": "SPI_SHADER_USER_DATA_PS_7" 3893 }, 3894 { 3895 "chips": ["gfx6"], 3896 "map": {"at": 45136, "to": "mm"}, 3897 "name": "SPI_SHADER_USER_DATA_PS_8" 3898 }, 3899 { 3900 "chips": ["gfx6"], 3901 "map": {"at": 45140, "to": "mm"}, 3902 "name": "SPI_SHADER_USER_DATA_PS_9" 3903 }, 3904 { 3905 "chips": ["gfx6"], 3906 "map": {"at": 45144, "to": "mm"}, 3907 "name": "SPI_SHADER_USER_DATA_PS_10" 3908 }, 3909 { 3910 "chips": ["gfx6"], 3911 "map": {"at": 45148, "to": "mm"}, 3912 "name": "SPI_SHADER_USER_DATA_PS_11" 3913 }, 3914 { 3915 "chips": ["gfx6"], 3916 "map": {"at": 45152, "to": "mm"}, 3917 "name": "SPI_SHADER_USER_DATA_PS_12" 3918 }, 3919 { 3920 "chips": ["gfx6"], 3921 "map": {"at": 45156, "to": "mm"}, 3922 "name": "SPI_SHADER_USER_DATA_PS_13" 3923 }, 3924 { 3925 "chips": ["gfx6"], 3926 "map": {"at": 45160, "to": "mm"}, 3927 "name": "SPI_SHADER_USER_DATA_PS_14" 3928 }, 3929 { 3930 "chips": ["gfx6"], 3931 "map": {"at": 45164, "to": "mm"}, 3932 "name": "SPI_SHADER_USER_DATA_PS_15" 3933 }, 3934 { 3935 "chips": ["gfx6"], 3936 "map": {"at": 45312, "to": "mm"}, 3937 "name": "SPI_SHADER_TBA_LO_VS" 3938 }, 3939 { 3940 "chips": ["gfx6"], 3941 "map": {"at": 45316, "to": "mm"}, 3942 "name": "SPI_SHADER_TBA_HI_VS", 3943 "type_ref": "SPI_SHADER_PGM_HI_ES" 3944 }, 3945 { 3946 "chips": ["gfx6"], 3947 "map": {"at": 45320, "to": "mm"}, 3948 "name": "SPI_SHADER_TMA_LO_VS" 3949 }, 3950 { 3951 "chips": ["gfx6"], 3952 "map": {"at": 45324, "to": "mm"}, 3953 "name": "SPI_SHADER_TMA_HI_VS", 3954 "type_ref": "SPI_SHADER_PGM_HI_ES" 3955 }, 3956 { 3957 "chips": ["gfx6"], 3958 "map": {"at": 45344, "to": "mm"}, 3959 "name": "SPI_SHADER_PGM_LO_VS" 3960 }, 3961 { 3962 "chips": ["gfx6"], 3963 "map": {"at": 45348, "to": "mm"}, 3964 "name": "SPI_SHADER_PGM_HI_VS", 3965 "type_ref": "SPI_SHADER_PGM_HI_ES" 3966 }, 3967 { 3968 "chips": ["gfx6"], 3969 "map": {"at": 45352, "to": "mm"}, 3970 "name": "SPI_SHADER_PGM_RSRC1_VS", 3971 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 3972 }, 3973 { 3974 "chips": ["gfx6"], 3975 "map": {"at": 45356, "to": "mm"}, 3976 "name": "SPI_SHADER_PGM_RSRC2_VS", 3977 "type_ref": "SPI_SHADER_PGM_RSRC2_VS" 3978 }, 3979 { 3980 "chips": ["gfx6"], 3981 "map": {"at": 45360, "to": "mm"}, 3982 "name": "SPI_SHADER_USER_DATA_VS_0" 3983 }, 3984 { 3985 "chips": ["gfx6"], 3986 "map": {"at": 45364, "to": "mm"}, 3987 "name": "SPI_SHADER_USER_DATA_VS_1" 3988 }, 3989 { 3990 "chips": ["gfx6"], 3991 "map": {"at": 45368, "to": "mm"}, 3992 "name": "SPI_SHADER_USER_DATA_VS_2" 3993 }, 3994 { 3995 "chips": ["gfx6"], 3996 "map": {"at": 45372, "to": "mm"}, 3997 "name": "SPI_SHADER_USER_DATA_VS_3" 3998 }, 3999 { 4000 "chips": ["gfx6"], 4001 "map": {"at": 45376, "to": "mm"}, 4002 "name": "SPI_SHADER_USER_DATA_VS_4" 4003 }, 4004 { 4005 "chips": ["gfx6"], 4006 "map": {"at": 45380, "to": "mm"}, 4007 "name": "SPI_SHADER_USER_DATA_VS_5" 4008 }, 4009 { 4010 "chips": ["gfx6"], 4011 "map": {"at": 45384, "to": "mm"}, 4012 "name": "SPI_SHADER_USER_DATA_VS_6" 4013 }, 4014 { 4015 "chips": ["gfx6"], 4016 "map": {"at": 45388, "to": "mm"}, 4017 "name": "SPI_SHADER_USER_DATA_VS_7" 4018 }, 4019 { 4020 "chips": ["gfx6"], 4021 "map": {"at": 45392, "to": "mm"}, 4022 "name": "SPI_SHADER_USER_DATA_VS_8" 4023 }, 4024 { 4025 "chips": ["gfx6"], 4026 "map": {"at": 45396, "to": "mm"}, 4027 "name": "SPI_SHADER_USER_DATA_VS_9" 4028 }, 4029 { 4030 "chips": ["gfx6"], 4031 "map": {"at": 45400, "to": "mm"}, 4032 "name": "SPI_SHADER_USER_DATA_VS_10" 4033 }, 4034 { 4035 "chips": ["gfx6"], 4036 "map": {"at": 45404, "to": "mm"}, 4037 "name": "SPI_SHADER_USER_DATA_VS_11" 4038 }, 4039 { 4040 "chips": ["gfx6"], 4041 "map": {"at": 45408, "to": "mm"}, 4042 "name": "SPI_SHADER_USER_DATA_VS_12" 4043 }, 4044 { 4045 "chips": ["gfx6"], 4046 "map": {"at": 45412, "to": "mm"}, 4047 "name": "SPI_SHADER_USER_DATA_VS_13" 4048 }, 4049 { 4050 "chips": ["gfx6"], 4051 "map": {"at": 45416, "to": "mm"}, 4052 "name": "SPI_SHADER_USER_DATA_VS_14" 4053 }, 4054 { 4055 "chips": ["gfx6"], 4056 "map": {"at": 45420, "to": "mm"}, 4057 "name": "SPI_SHADER_USER_DATA_VS_15" 4058 }, 4059 { 4060 "chips": ["gfx6"], 4061 "map": {"at": 45568, "to": "mm"}, 4062 "name": "SPI_SHADER_TBA_LO_GS" 4063 }, 4064 { 4065 "chips": ["gfx6"], 4066 "map": {"at": 45572, "to": "mm"}, 4067 "name": "SPI_SHADER_TBA_HI_GS", 4068 "type_ref": "SPI_SHADER_PGM_HI_ES" 4069 }, 4070 { 4071 "chips": ["gfx6"], 4072 "map": {"at": 45576, "to": "mm"}, 4073 "name": "SPI_SHADER_TMA_LO_GS" 4074 }, 4075 { 4076 "chips": ["gfx6"], 4077 "map": {"at": 45580, "to": "mm"}, 4078 "name": "SPI_SHADER_TMA_HI_GS", 4079 "type_ref": "SPI_SHADER_PGM_HI_ES" 4080 }, 4081 { 4082 "chips": ["gfx6"], 4083 "map": {"at": 45600, "to": "mm"}, 4084 "name": "SPI_SHADER_PGM_LO_GS" 4085 }, 4086 { 4087 "chips": ["gfx6"], 4088 "map": {"at": 45604, "to": "mm"}, 4089 "name": "SPI_SHADER_PGM_HI_GS", 4090 "type_ref": "SPI_SHADER_PGM_HI_ES" 4091 }, 4092 { 4093 "chips": ["gfx6"], 4094 "map": {"at": 45608, "to": "mm"}, 4095 "name": "SPI_SHADER_PGM_RSRC1_GS", 4096 "type_ref": "SPI_SHADER_PGM_RSRC1_GS" 4097 }, 4098 { 4099 "chips": ["gfx6"], 4100 "map": {"at": 45612, "to": "mm"}, 4101 "name": "SPI_SHADER_PGM_RSRC2_GS", 4102 "type_ref": "SPI_SHADER_PGM_RSRC2_GS" 4103 }, 4104 { 4105 "chips": ["gfx6"], 4106 "map": {"at": 45616, "to": "mm"}, 4107 "name": "SPI_SHADER_USER_DATA_GS_0" 4108 }, 4109 { 4110 "chips": ["gfx6"], 4111 "map": {"at": 45620, "to": "mm"}, 4112 "name": "SPI_SHADER_USER_DATA_GS_1" 4113 }, 4114 { 4115 "chips": ["gfx6"], 4116 "map": {"at": 45624, "to": "mm"}, 4117 "name": "SPI_SHADER_USER_DATA_GS_2" 4118 }, 4119 { 4120 "chips": ["gfx6"], 4121 "map": {"at": 45628, "to": "mm"}, 4122 "name": "SPI_SHADER_USER_DATA_GS_3" 4123 }, 4124 { 4125 "chips": ["gfx6"], 4126 "map": {"at": 45632, "to": "mm"}, 4127 "name": "SPI_SHADER_USER_DATA_GS_4" 4128 }, 4129 { 4130 "chips": ["gfx6"], 4131 "map": {"at": 45636, "to": "mm"}, 4132 "name": "SPI_SHADER_USER_DATA_GS_5" 4133 }, 4134 { 4135 "chips": ["gfx6"], 4136 "map": {"at": 45640, "to": "mm"}, 4137 "name": "SPI_SHADER_USER_DATA_GS_6" 4138 }, 4139 { 4140 "chips": ["gfx6"], 4141 "map": {"at": 45644, "to": "mm"}, 4142 "name": "SPI_SHADER_USER_DATA_GS_7" 4143 }, 4144 { 4145 "chips": ["gfx6"], 4146 "map": {"at": 45648, "to": "mm"}, 4147 "name": "SPI_SHADER_USER_DATA_GS_8" 4148 }, 4149 { 4150 "chips": ["gfx6"], 4151 "map": {"at": 45652, "to": "mm"}, 4152 "name": "SPI_SHADER_USER_DATA_GS_9" 4153 }, 4154 { 4155 "chips": ["gfx6"], 4156 "map": {"at": 45656, "to": "mm"}, 4157 "name": "SPI_SHADER_USER_DATA_GS_10" 4158 }, 4159 { 4160 "chips": ["gfx6"], 4161 "map": {"at": 45660, "to": "mm"}, 4162 "name": "SPI_SHADER_USER_DATA_GS_11" 4163 }, 4164 { 4165 "chips": ["gfx6"], 4166 "map": {"at": 45664, "to": "mm"}, 4167 "name": "SPI_SHADER_USER_DATA_GS_12" 4168 }, 4169 { 4170 "chips": ["gfx6"], 4171 "map": {"at": 45668, "to": "mm"}, 4172 "name": "SPI_SHADER_USER_DATA_GS_13" 4173 }, 4174 { 4175 "chips": ["gfx6"], 4176 "map": {"at": 45672, "to": "mm"}, 4177 "name": "SPI_SHADER_USER_DATA_GS_14" 4178 }, 4179 { 4180 "chips": ["gfx6"], 4181 "map": {"at": 45676, "to": "mm"}, 4182 "name": "SPI_SHADER_USER_DATA_GS_15" 4183 }, 4184 { 4185 "chips": ["gfx6"], 4186 "map": {"at": 45824, "to": "mm"}, 4187 "name": "SPI_SHADER_TBA_LO_ES" 4188 }, 4189 { 4190 "chips": ["gfx6"], 4191 "map": {"at": 45828, "to": "mm"}, 4192 "name": "SPI_SHADER_TBA_HI_ES", 4193 "type_ref": "SPI_SHADER_PGM_HI_ES" 4194 }, 4195 { 4196 "chips": ["gfx6"], 4197 "map": {"at": 45832, "to": "mm"}, 4198 "name": "SPI_SHADER_TMA_LO_ES" 4199 }, 4200 { 4201 "chips": ["gfx6"], 4202 "map": {"at": 45836, "to": "mm"}, 4203 "name": "SPI_SHADER_TMA_HI_ES", 4204 "type_ref": "SPI_SHADER_PGM_HI_ES" 4205 }, 4206 { 4207 "chips": ["gfx6"], 4208 "map": {"at": 45856, "to": "mm"}, 4209 "name": "SPI_SHADER_PGM_LO_ES" 4210 }, 4211 { 4212 "chips": ["gfx6"], 4213 "map": {"at": 45860, "to": "mm"}, 4214 "name": "SPI_SHADER_PGM_HI_ES", 4215 "type_ref": "SPI_SHADER_PGM_HI_ES" 4216 }, 4217 { 4218 "chips": ["gfx6"], 4219 "map": {"at": 45864, "to": "mm"}, 4220 "name": "SPI_SHADER_PGM_RSRC1_ES", 4221 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 4222 }, 4223 { 4224 "chips": ["gfx6"], 4225 "map": {"at": 45868, "to": "mm"}, 4226 "name": "SPI_SHADER_PGM_RSRC2_ES", 4227 "type_ref": "SPI_SHADER_PGM_RSRC2_ES" 4228 }, 4229 { 4230 "chips": ["gfx6"], 4231 "map": {"at": 45872, "to": "mm"}, 4232 "name": "SPI_SHADER_USER_DATA_ES_0" 4233 }, 4234 { 4235 "chips": ["gfx6"], 4236 "map": {"at": 45876, "to": "mm"}, 4237 "name": "SPI_SHADER_USER_DATA_ES_1" 4238 }, 4239 { 4240 "chips": ["gfx6"], 4241 "map": {"at": 45880, "to": "mm"}, 4242 "name": "SPI_SHADER_USER_DATA_ES_2" 4243 }, 4244 { 4245 "chips": ["gfx6"], 4246 "map": {"at": 45884, "to": "mm"}, 4247 "name": "SPI_SHADER_USER_DATA_ES_3" 4248 }, 4249 { 4250 "chips": ["gfx6"], 4251 "map": {"at": 45888, "to": "mm"}, 4252 "name": "SPI_SHADER_USER_DATA_ES_4" 4253 }, 4254 { 4255 "chips": ["gfx6"], 4256 "map": {"at": 45892, "to": "mm"}, 4257 "name": "SPI_SHADER_USER_DATA_ES_5" 4258 }, 4259 { 4260 "chips": ["gfx6"], 4261 "map": {"at": 45896, "to": "mm"}, 4262 "name": "SPI_SHADER_USER_DATA_ES_6" 4263 }, 4264 { 4265 "chips": ["gfx6"], 4266 "map": {"at": 45900, "to": "mm"}, 4267 "name": "SPI_SHADER_USER_DATA_ES_7" 4268 }, 4269 { 4270 "chips": ["gfx6"], 4271 "map": {"at": 45904, "to": "mm"}, 4272 "name": "SPI_SHADER_USER_DATA_ES_8" 4273 }, 4274 { 4275 "chips": ["gfx6"], 4276 "map": {"at": 45908, "to": "mm"}, 4277 "name": "SPI_SHADER_USER_DATA_ES_9" 4278 }, 4279 { 4280 "chips": ["gfx6"], 4281 "map": {"at": 45912, "to": "mm"}, 4282 "name": "SPI_SHADER_USER_DATA_ES_10" 4283 }, 4284 { 4285 "chips": ["gfx6"], 4286 "map": {"at": 45916, "to": "mm"}, 4287 "name": "SPI_SHADER_USER_DATA_ES_11" 4288 }, 4289 { 4290 "chips": ["gfx6"], 4291 "map": {"at": 45920, "to": "mm"}, 4292 "name": "SPI_SHADER_USER_DATA_ES_12" 4293 }, 4294 { 4295 "chips": ["gfx6"], 4296 "map": {"at": 45924, "to": "mm"}, 4297 "name": "SPI_SHADER_USER_DATA_ES_13" 4298 }, 4299 { 4300 "chips": ["gfx6"], 4301 "map": {"at": 45928, "to": "mm"}, 4302 "name": "SPI_SHADER_USER_DATA_ES_14" 4303 }, 4304 { 4305 "chips": ["gfx6"], 4306 "map": {"at": 45932, "to": "mm"}, 4307 "name": "SPI_SHADER_USER_DATA_ES_15" 4308 }, 4309 { 4310 "chips": ["gfx6"], 4311 "map": {"at": 46080, "to": "mm"}, 4312 "name": "SPI_SHADER_TBA_LO_HS" 4313 }, 4314 { 4315 "chips": ["gfx6"], 4316 "map": {"at": 46084, "to": "mm"}, 4317 "name": "SPI_SHADER_TBA_HI_HS", 4318 "type_ref": "SPI_SHADER_PGM_HI_ES" 4319 }, 4320 { 4321 "chips": ["gfx6"], 4322 "map": {"at": 46088, "to": "mm"}, 4323 "name": "SPI_SHADER_TMA_LO_HS" 4324 }, 4325 { 4326 "chips": ["gfx6"], 4327 "map": {"at": 46092, "to": "mm"}, 4328 "name": "SPI_SHADER_TMA_HI_HS", 4329 "type_ref": "SPI_SHADER_PGM_HI_ES" 4330 }, 4331 { 4332 "chips": ["gfx6"], 4333 "map": {"at": 46112, "to": "mm"}, 4334 "name": "SPI_SHADER_PGM_LO_HS" 4335 }, 4336 { 4337 "chips": ["gfx6"], 4338 "map": {"at": 46116, "to": "mm"}, 4339 "name": "SPI_SHADER_PGM_HI_HS", 4340 "type_ref": "SPI_SHADER_PGM_HI_ES" 4341 }, 4342 { 4343 "chips": ["gfx6"], 4344 "map": {"at": 46120, "to": "mm"}, 4345 "name": "SPI_SHADER_PGM_RSRC1_HS", 4346 "type_ref": "SPI_SHADER_PGM_RSRC1_HS" 4347 }, 4348 { 4349 "chips": ["gfx6"], 4350 "map": {"at": 46124, "to": "mm"}, 4351 "name": "SPI_SHADER_PGM_RSRC2_HS", 4352 "type_ref": "SPI_SHADER_PGM_RSRC2_HS" 4353 }, 4354 { 4355 "chips": ["gfx6"], 4356 "map": {"at": 46128, "to": "mm"}, 4357 "name": "SPI_SHADER_USER_DATA_HS_0" 4358 }, 4359 { 4360 "chips": ["gfx6"], 4361 "map": {"at": 46132, "to": "mm"}, 4362 "name": "SPI_SHADER_USER_DATA_HS_1" 4363 }, 4364 { 4365 "chips": ["gfx6"], 4366 "map": {"at": 46136, "to": "mm"}, 4367 "name": "SPI_SHADER_USER_DATA_HS_2" 4368 }, 4369 { 4370 "chips": ["gfx6"], 4371 "map": {"at": 46140, "to": "mm"}, 4372 "name": "SPI_SHADER_USER_DATA_HS_3" 4373 }, 4374 { 4375 "chips": ["gfx6"], 4376 "map": {"at": 46144, "to": "mm"}, 4377 "name": "SPI_SHADER_USER_DATA_HS_4" 4378 }, 4379 { 4380 "chips": ["gfx6"], 4381 "map": {"at": 46148, "to": "mm"}, 4382 "name": "SPI_SHADER_USER_DATA_HS_5" 4383 }, 4384 { 4385 "chips": ["gfx6"], 4386 "map": {"at": 46152, "to": "mm"}, 4387 "name": "SPI_SHADER_USER_DATA_HS_6" 4388 }, 4389 { 4390 "chips": ["gfx6"], 4391 "map": {"at": 46156, "to": "mm"}, 4392 "name": "SPI_SHADER_USER_DATA_HS_7" 4393 }, 4394 { 4395 "chips": ["gfx6"], 4396 "map": {"at": 46160, "to": "mm"}, 4397 "name": "SPI_SHADER_USER_DATA_HS_8" 4398 }, 4399 { 4400 "chips": ["gfx6"], 4401 "map": {"at": 46164, "to": "mm"}, 4402 "name": "SPI_SHADER_USER_DATA_HS_9" 4403 }, 4404 { 4405 "chips": ["gfx6"], 4406 "map": {"at": 46168, "to": "mm"}, 4407 "name": "SPI_SHADER_USER_DATA_HS_10" 4408 }, 4409 { 4410 "chips": ["gfx6"], 4411 "map": {"at": 46172, "to": "mm"}, 4412 "name": "SPI_SHADER_USER_DATA_HS_11" 4413 }, 4414 { 4415 "chips": ["gfx6"], 4416 "map": {"at": 46176, "to": "mm"}, 4417 "name": "SPI_SHADER_USER_DATA_HS_12" 4418 }, 4419 { 4420 "chips": ["gfx6"], 4421 "map": {"at": 46180, "to": "mm"}, 4422 "name": "SPI_SHADER_USER_DATA_HS_13" 4423 }, 4424 { 4425 "chips": ["gfx6"], 4426 "map": {"at": 46184, "to": "mm"}, 4427 "name": "SPI_SHADER_USER_DATA_HS_14" 4428 }, 4429 { 4430 "chips": ["gfx6"], 4431 "map": {"at": 46188, "to": "mm"}, 4432 "name": "SPI_SHADER_USER_DATA_HS_15" 4433 }, 4434 { 4435 "chips": ["gfx6"], 4436 "map": {"at": 46336, "to": "mm"}, 4437 "name": "SPI_SHADER_TBA_LO_LS" 4438 }, 4439 { 4440 "chips": ["gfx6"], 4441 "map": {"at": 46340, "to": "mm"}, 4442 "name": "SPI_SHADER_TBA_HI_LS", 4443 "type_ref": "SPI_SHADER_PGM_HI_ES" 4444 }, 4445 { 4446 "chips": ["gfx6"], 4447 "map": {"at": 46344, "to": "mm"}, 4448 "name": "SPI_SHADER_TMA_LO_LS" 4449 }, 4450 { 4451 "chips": ["gfx6"], 4452 "map": {"at": 46348, "to": "mm"}, 4453 "name": "SPI_SHADER_TMA_HI_LS", 4454 "type_ref": "SPI_SHADER_PGM_HI_ES" 4455 }, 4456 { 4457 "chips": ["gfx6"], 4458 "map": {"at": 46368, "to": "mm"}, 4459 "name": "SPI_SHADER_PGM_LO_LS" 4460 }, 4461 { 4462 "chips": ["gfx6"], 4463 "map": {"at": 46372, "to": "mm"}, 4464 "name": "SPI_SHADER_PGM_HI_LS", 4465 "type_ref": "SPI_SHADER_PGM_HI_ES" 4466 }, 4467 { 4468 "chips": ["gfx6"], 4469 "map": {"at": 46376, "to": "mm"}, 4470 "name": "SPI_SHADER_PGM_RSRC1_LS", 4471 "type_ref": "SPI_SHADER_PGM_RSRC1_LS" 4472 }, 4473 { 4474 "chips": ["gfx6"], 4475 "map": {"at": 46380, "to": "mm"}, 4476 "name": "SPI_SHADER_PGM_RSRC2_LS", 4477 "type_ref": "SPI_SHADER_PGM_RSRC2_LS" 4478 }, 4479 { 4480 "chips": ["gfx6"], 4481 "map": {"at": 46384, "to": "mm"}, 4482 "name": "SPI_SHADER_USER_DATA_LS_0" 4483 }, 4484 { 4485 "chips": ["gfx6"], 4486 "map": {"at": 46388, "to": "mm"}, 4487 "name": "SPI_SHADER_USER_DATA_LS_1" 4488 }, 4489 { 4490 "chips": ["gfx6"], 4491 "map": {"at": 46392, "to": "mm"}, 4492 "name": "SPI_SHADER_USER_DATA_LS_2" 4493 }, 4494 { 4495 "chips": ["gfx6"], 4496 "map": {"at": 46396, "to": "mm"}, 4497 "name": "SPI_SHADER_USER_DATA_LS_3" 4498 }, 4499 { 4500 "chips": ["gfx6"], 4501 "map": {"at": 46400, "to": "mm"}, 4502 "name": "SPI_SHADER_USER_DATA_LS_4" 4503 }, 4504 { 4505 "chips": ["gfx6"], 4506 "map": {"at": 46404, "to": "mm"}, 4507 "name": "SPI_SHADER_USER_DATA_LS_5" 4508 }, 4509 { 4510 "chips": ["gfx6"], 4511 "map": {"at": 46408, "to": "mm"}, 4512 "name": "SPI_SHADER_USER_DATA_LS_6" 4513 }, 4514 { 4515 "chips": ["gfx6"], 4516 "map": {"at": 46412, "to": "mm"}, 4517 "name": "SPI_SHADER_USER_DATA_LS_7" 4518 }, 4519 { 4520 "chips": ["gfx6"], 4521 "map": {"at": 46416, "to": "mm"}, 4522 "name": "SPI_SHADER_USER_DATA_LS_8" 4523 }, 4524 { 4525 "chips": ["gfx6"], 4526 "map": {"at": 46420, "to": "mm"}, 4527 "name": "SPI_SHADER_USER_DATA_LS_9" 4528 }, 4529 { 4530 "chips": ["gfx6"], 4531 "map": {"at": 46424, "to": "mm"}, 4532 "name": "SPI_SHADER_USER_DATA_LS_10" 4533 }, 4534 { 4535 "chips": ["gfx6"], 4536 "map": {"at": 46428, "to": "mm"}, 4537 "name": "SPI_SHADER_USER_DATA_LS_11" 4538 }, 4539 { 4540 "chips": ["gfx6"], 4541 "map": {"at": 46432, "to": "mm"}, 4542 "name": "SPI_SHADER_USER_DATA_LS_12" 4543 }, 4544 { 4545 "chips": ["gfx6"], 4546 "map": {"at": 46436, "to": "mm"}, 4547 "name": "SPI_SHADER_USER_DATA_LS_13" 4548 }, 4549 { 4550 "chips": ["gfx6"], 4551 "map": {"at": 46440, "to": "mm"}, 4552 "name": "SPI_SHADER_USER_DATA_LS_14" 4553 }, 4554 { 4555 "chips": ["gfx6"], 4556 "map": {"at": 46444, "to": "mm"}, 4557 "name": "SPI_SHADER_USER_DATA_LS_15" 4558 }, 4559 { 4560 "chips": ["gfx6"], 4561 "map": {"at": 47104, "to": "mm"}, 4562 "name": "COMPUTE_DISPATCH_INITIATOR", 4563 "type_ref": "COMPUTE_DISPATCH_INITIATOR" 4564 }, 4565 { 4566 "chips": ["gfx6"], 4567 "map": {"at": 47108, "to": "mm"}, 4568 "name": "COMPUTE_DIM_X" 4569 }, 4570 { 4571 "chips": ["gfx6"], 4572 "map": {"at": 47112, "to": "mm"}, 4573 "name": "COMPUTE_DIM_Y" 4574 }, 4575 { 4576 "chips": ["gfx6"], 4577 "map": {"at": 47116, "to": "mm"}, 4578 "name": "COMPUTE_DIM_Z" 4579 }, 4580 { 4581 "chips": ["gfx6"], 4582 "map": {"at": 47120, "to": "mm"}, 4583 "name": "COMPUTE_START_X" 4584 }, 4585 { 4586 "chips": ["gfx6"], 4587 "map": {"at": 47124, "to": "mm"}, 4588 "name": "COMPUTE_START_Y" 4589 }, 4590 { 4591 "chips": ["gfx6"], 4592 "map": {"at": 47128, "to": "mm"}, 4593 "name": "COMPUTE_START_Z" 4594 }, 4595 { 4596 "chips": ["gfx6"], 4597 "map": {"at": 47132, "to": "mm"}, 4598 "name": "COMPUTE_NUM_THREAD_X", 4599 "type_ref": "COMPUTE_NUM_THREAD_X" 4600 }, 4601 { 4602 "chips": ["gfx6"], 4603 "map": {"at": 47136, "to": "mm"}, 4604 "name": "COMPUTE_NUM_THREAD_Y", 4605 "type_ref": "COMPUTE_NUM_THREAD_X" 4606 }, 4607 { 4608 "chips": ["gfx6"], 4609 "map": {"at": 47140, "to": "mm"}, 4610 "name": "COMPUTE_NUM_THREAD_Z", 4611 "type_ref": "COMPUTE_NUM_THREAD_X" 4612 }, 4613 { 4614 "chips": ["gfx6"], 4615 "map": {"at": 47152, "to": "mm"}, 4616 "name": "COMPUTE_PGM_LO" 4617 }, 4618 { 4619 "chips": ["gfx6"], 4620 "map": {"at": 47156, "to": "mm"}, 4621 "name": "COMPUTE_PGM_HI", 4622 "type_ref": "COMPUTE_PGM_HI" 4623 }, 4624 { 4625 "chips": ["gfx6"], 4626 "map": {"at": 47160, "to": "mm"}, 4627 "name": "COMPUTE_TBA_LO" 4628 }, 4629 { 4630 "chips": ["gfx6"], 4631 "map": {"at": 47164, "to": "mm"}, 4632 "name": "COMPUTE_TBA_HI", 4633 "type_ref": "COMPUTE_TBA_HI" 4634 }, 4635 { 4636 "chips": ["gfx6"], 4637 "map": {"at": 47168, "to": "mm"}, 4638 "name": "COMPUTE_TMA_LO" 4639 }, 4640 { 4641 "chips": ["gfx6"], 4642 "map": {"at": 47172, "to": "mm"}, 4643 "name": "COMPUTE_TMA_HI", 4644 "type_ref": "COMPUTE_TBA_HI" 4645 }, 4646 { 4647 "chips": ["gfx6"], 4648 "map": {"at": 47176, "to": "mm"}, 4649 "name": "COMPUTE_PGM_RSRC1", 4650 "type_ref": "COMPUTE_PGM_RSRC1" 4651 }, 4652 { 4653 "chips": ["gfx6"], 4654 "map": {"at": 47180, "to": "mm"}, 4655 "name": "COMPUTE_PGM_RSRC2", 4656 "type_ref": "COMPUTE_PGM_RSRC2" 4657 }, 4658 { 4659 "chips": ["gfx6"], 4660 "map": {"at": 47184, "to": "mm"}, 4661 "name": "COMPUTE_VMID", 4662 "type_ref": "COMPUTE_VMID" 4663 }, 4664 { 4665 "chips": ["gfx6"], 4666 "map": {"at": 47188, "to": "mm"}, 4667 "name": "COMPUTE_RESOURCE_LIMITS", 4668 "type_ref": "COMPUTE_RESOURCE_LIMITS" 4669 }, 4670 { 4671 "chips": ["gfx6"], 4672 "map": {"at": 47192, "to": "mm"}, 4673 "name": "COMPUTE_STATIC_THREAD_MGMT_SE0", 4674 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 4675 }, 4676 { 4677 "chips": ["gfx6"], 4678 "map": {"at": 47196, "to": "mm"}, 4679 "name": "COMPUTE_STATIC_THREAD_MGMT_SE1", 4680 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 4681 }, 4682 { 4683 "chips": ["gfx6"], 4684 "map": {"at": 47200, "to": "mm"}, 4685 "name": "COMPUTE_TMPRING_SIZE", 4686 "type_ref": "COMPUTE_TMPRING_SIZE" 4687 }, 4688 { 4689 "chips": ["gfx6"], 4690 "map": {"at": 47360, "to": "mm"}, 4691 "name": "COMPUTE_USER_DATA_0" 4692 }, 4693 { 4694 "chips": ["gfx6"], 4695 "map": {"at": 47364, "to": "mm"}, 4696 "name": "COMPUTE_USER_DATA_1" 4697 }, 4698 { 4699 "chips": ["gfx6"], 4700 "map": {"at": 47368, "to": "mm"}, 4701 "name": "COMPUTE_USER_DATA_2" 4702 }, 4703 { 4704 "chips": ["gfx6"], 4705 "map": {"at": 47372, "to": "mm"}, 4706 "name": "COMPUTE_USER_DATA_3" 4707 }, 4708 { 4709 "chips": ["gfx6"], 4710 "map": {"at": 47376, "to": "mm"}, 4711 "name": "COMPUTE_USER_DATA_4" 4712 }, 4713 { 4714 "chips": ["gfx6"], 4715 "map": {"at": 47380, "to": "mm"}, 4716 "name": "COMPUTE_USER_DATA_5" 4717 }, 4718 { 4719 "chips": ["gfx6"], 4720 "map": {"at": 47384, "to": "mm"}, 4721 "name": "COMPUTE_USER_DATA_6" 4722 }, 4723 { 4724 "chips": ["gfx6"], 4725 "map": {"at": 47388, "to": "mm"}, 4726 "name": "COMPUTE_USER_DATA_7" 4727 }, 4728 { 4729 "chips": ["gfx6"], 4730 "map": {"at": 47392, "to": "mm"}, 4731 "name": "COMPUTE_USER_DATA_8" 4732 }, 4733 { 4734 "chips": ["gfx6"], 4735 "map": {"at": 47396, "to": "mm"}, 4736 "name": "COMPUTE_USER_DATA_9" 4737 }, 4738 { 4739 "chips": ["gfx6"], 4740 "map": {"at": 47400, "to": "mm"}, 4741 "name": "COMPUTE_USER_DATA_10" 4742 }, 4743 { 4744 "chips": ["gfx6"], 4745 "map": {"at": 47404, "to": "mm"}, 4746 "name": "COMPUTE_USER_DATA_11" 4747 }, 4748 { 4749 "chips": ["gfx6"], 4750 "map": {"at": 47408, "to": "mm"}, 4751 "name": "COMPUTE_USER_DATA_12" 4752 }, 4753 { 4754 "chips": ["gfx6"], 4755 "map": {"at": 47412, "to": "mm"}, 4756 "name": "COMPUTE_USER_DATA_13" 4757 }, 4758 { 4759 "chips": ["gfx6"], 4760 "map": {"at": 47416, "to": "mm"}, 4761 "name": "COMPUTE_USER_DATA_14" 4762 }, 4763 { 4764 "chips": ["gfx6"], 4765 "map": {"at": 47420, "to": "mm"}, 4766 "name": "COMPUTE_USER_DATA_15" 4767 }, 4768 { 4769 "chips": ["gfx6"], 4770 "map": {"at": 163840, "to": "mm"}, 4771 "name": "DB_RENDER_CONTROL", 4772 "type_ref": "DB_RENDER_CONTROL" 4773 }, 4774 { 4775 "chips": ["gfx6"], 4776 "map": {"at": 163844, "to": "mm"}, 4777 "name": "DB_COUNT_CONTROL", 4778 "type_ref": "DB_COUNT_CONTROL" 4779 }, 4780 { 4781 "chips": ["gfx6"], 4782 "map": {"at": 163848, "to": "mm"}, 4783 "name": "DB_DEPTH_VIEW", 4784 "type_ref": "DB_DEPTH_VIEW" 4785 }, 4786 { 4787 "chips": ["gfx6"], 4788 "map": {"at": 163852, "to": "mm"}, 4789 "name": "DB_RENDER_OVERRIDE", 4790 "type_ref": "DB_RENDER_OVERRIDE" 4791 }, 4792 { 4793 "chips": ["gfx6"], 4794 "map": {"at": 163856, "to": "mm"}, 4795 "name": "DB_RENDER_OVERRIDE2", 4796 "type_ref": "DB_RENDER_OVERRIDE2" 4797 }, 4798 { 4799 "chips": ["gfx6"], 4800 "map": {"at": 163860, "to": "mm"}, 4801 "name": "DB_HTILE_DATA_BASE" 4802 }, 4803 { 4804 "chips": ["gfx6"], 4805 "map": {"at": 163872, "to": "mm"}, 4806 "name": "DB_DEPTH_BOUNDS_MIN" 4807 }, 4808 { 4809 "chips": ["gfx6"], 4810 "map": {"at": 163876, "to": "mm"}, 4811 "name": "DB_DEPTH_BOUNDS_MAX" 4812 }, 4813 { 4814 "chips": ["gfx6"], 4815 "map": {"at": 163880, "to": "mm"}, 4816 "name": "DB_STENCIL_CLEAR", 4817 "type_ref": "DB_STENCIL_CLEAR" 4818 }, 4819 { 4820 "chips": ["gfx6"], 4821 "map": {"at": 163884, "to": "mm"}, 4822 "name": "DB_DEPTH_CLEAR" 4823 }, 4824 { 4825 "chips": ["gfx6"], 4826 "map": {"at": 163888, "to": "mm"}, 4827 "name": "PA_SC_SCREEN_SCISSOR_TL", 4828 "type_ref": "PA_SC_SCREEN_SCISSOR_TL" 4829 }, 4830 { 4831 "chips": ["gfx6"], 4832 "map": {"at": 163892, "to": "mm"}, 4833 "name": "PA_SC_SCREEN_SCISSOR_BR", 4834 "type_ref": "PA_SC_SCREEN_SCISSOR_BR" 4835 }, 4836 { 4837 "chips": ["gfx6"], 4838 "map": {"at": 163900, "to": "mm"}, 4839 "name": "DB_DEPTH_INFO", 4840 "type_ref": "DB_DEPTH_INFO" 4841 }, 4842 { 4843 "chips": ["gfx6"], 4844 "map": {"at": 163904, "to": "mm"}, 4845 "name": "DB_Z_INFO", 4846 "type_ref": "DB_Z_INFO" 4847 }, 4848 { 4849 "chips": ["gfx6"], 4850 "map": {"at": 163908, "to": "mm"}, 4851 "name": "DB_STENCIL_INFO", 4852 "type_ref": "DB_STENCIL_INFO" 4853 }, 4854 { 4855 "chips": ["gfx6"], 4856 "map": {"at": 163912, "to": "mm"}, 4857 "name": "DB_Z_READ_BASE" 4858 }, 4859 { 4860 "chips": ["gfx6"], 4861 "map": {"at": 163916, "to": "mm"}, 4862 "name": "DB_STENCIL_READ_BASE" 4863 }, 4864 { 4865 "chips": ["gfx6"], 4866 "map": {"at": 163920, "to": "mm"}, 4867 "name": "DB_Z_WRITE_BASE" 4868 }, 4869 { 4870 "chips": ["gfx6"], 4871 "map": {"at": 163924, "to": "mm"}, 4872 "name": "DB_STENCIL_WRITE_BASE" 4873 }, 4874 { 4875 "chips": ["gfx6"], 4876 "map": {"at": 163928, "to": "mm"}, 4877 "name": "DB_DEPTH_SIZE", 4878 "type_ref": "DB_DEPTH_SIZE" 4879 }, 4880 { 4881 "chips": ["gfx6"], 4882 "map": {"at": 163932, "to": "mm"}, 4883 "name": "DB_DEPTH_SLICE", 4884 "type_ref": "DB_DEPTH_SLICE" 4885 }, 4886 { 4887 "chips": ["gfx6"], 4888 "map": {"at": 163968, "to": "mm"}, 4889 "name": "TA_BC_BASE_ADDR" 4890 }, 4891 { 4892 "chips": ["gfx6"], 4893 "map": {"at": 164344, "to": "mm"}, 4894 "name": "COHER_DEST_BASE_2" 4895 }, 4896 { 4897 "chips": ["gfx6"], 4898 "map": {"at": 164348, "to": "mm"}, 4899 "name": "COHER_DEST_BASE_3" 4900 }, 4901 { 4902 "chips": ["gfx6"], 4903 "map": {"at": 164352, "to": "mm"}, 4904 "name": "PA_SC_WINDOW_OFFSET", 4905 "type_ref": "PA_SC_WINDOW_OFFSET" 4906 }, 4907 { 4908 "chips": ["gfx6"], 4909 "map": {"at": 164356, "to": "mm"}, 4910 "name": "PA_SC_WINDOW_SCISSOR_TL", 4911 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 4912 }, 4913 { 4914 "chips": ["gfx6"], 4915 "map": {"at": 164360, "to": "mm"}, 4916 "name": "PA_SC_WINDOW_SCISSOR_BR", 4917 "type_ref": "PA_SC_CLIPRECT_0_BR" 4918 }, 4919 { 4920 "chips": ["gfx6"], 4921 "map": {"at": 164364, "to": "mm"}, 4922 "name": "PA_SC_CLIPRECT_RULE", 4923 "type_ref": "PA_SC_CLIPRECT_RULE" 4924 }, 4925 { 4926 "chips": ["gfx6"], 4927 "map": {"at": 164368, "to": "mm"}, 4928 "name": "PA_SC_CLIPRECT_0_TL", 4929 "type_ref": "PA_SC_CLIPRECT_0_TL" 4930 }, 4931 { 4932 "chips": ["gfx6"], 4933 "map": {"at": 164372, "to": "mm"}, 4934 "name": "PA_SC_CLIPRECT_0_BR", 4935 "type_ref": "PA_SC_CLIPRECT_0_BR" 4936 }, 4937 { 4938 "chips": ["gfx6"], 4939 "map": {"at": 164376, "to": "mm"}, 4940 "name": "PA_SC_CLIPRECT_1_TL", 4941 "type_ref": "PA_SC_CLIPRECT_0_TL" 4942 }, 4943 { 4944 "chips": ["gfx6"], 4945 "map": {"at": 164380, "to": "mm"}, 4946 "name": "PA_SC_CLIPRECT_1_BR", 4947 "type_ref": "PA_SC_CLIPRECT_0_BR" 4948 }, 4949 { 4950 "chips": ["gfx6"], 4951 "map": {"at": 164384, "to": "mm"}, 4952 "name": "PA_SC_CLIPRECT_2_TL", 4953 "type_ref": "PA_SC_CLIPRECT_0_TL" 4954 }, 4955 { 4956 "chips": ["gfx6"], 4957 "map": {"at": 164388, "to": "mm"}, 4958 "name": "PA_SC_CLIPRECT_2_BR", 4959 "type_ref": "PA_SC_CLIPRECT_0_BR" 4960 }, 4961 { 4962 "chips": ["gfx6"], 4963 "map": {"at": 164392, "to": "mm"}, 4964 "name": "PA_SC_CLIPRECT_3_TL", 4965 "type_ref": "PA_SC_CLIPRECT_0_TL" 4966 }, 4967 { 4968 "chips": ["gfx6"], 4969 "map": {"at": 164396, "to": "mm"}, 4970 "name": "PA_SC_CLIPRECT_3_BR", 4971 "type_ref": "PA_SC_CLIPRECT_0_BR" 4972 }, 4973 { 4974 "chips": ["gfx6"], 4975 "map": {"at": 164400, "to": "mm"}, 4976 "name": "PA_SC_EDGERULE", 4977 "type_ref": "PA_SC_EDGERULE" 4978 }, 4979 { 4980 "chips": ["gfx6"], 4981 "map": {"at": 164404, "to": "mm"}, 4982 "name": "PA_SU_HARDWARE_SCREEN_OFFSET", 4983 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET" 4984 }, 4985 { 4986 "chips": ["gfx6"], 4987 "map": {"at": 164408, "to": "mm"}, 4988 "name": "CB_TARGET_MASK", 4989 "type_ref": "CB_TARGET_MASK" 4990 }, 4991 { 4992 "chips": ["gfx6"], 4993 "map": {"at": 164412, "to": "mm"}, 4994 "name": "CB_SHADER_MASK", 4995 "type_ref": "CB_SHADER_MASK" 4996 }, 4997 { 4998 "chips": ["gfx6"], 4999 "map": {"at": 164416, "to": "mm"}, 5000 "name": "PA_SC_GENERIC_SCISSOR_TL", 5001 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5002 }, 5003 { 5004 "chips": ["gfx6"], 5005 "map": {"at": 164420, "to": "mm"}, 5006 "name": "PA_SC_GENERIC_SCISSOR_BR", 5007 "type_ref": "PA_SC_CLIPRECT_0_BR" 5008 }, 5009 { 5010 "chips": ["gfx6"], 5011 "map": {"at": 164424, "to": "mm"}, 5012 "name": "COHER_DEST_BASE_0" 5013 }, 5014 { 5015 "chips": ["gfx6"], 5016 "map": {"at": 164428, "to": "mm"}, 5017 "name": "COHER_DEST_BASE_1" 5018 }, 5019 { 5020 "chips": ["gfx6"], 5021 "map": {"at": 164432, "to": "mm"}, 5022 "name": "PA_SC_VPORT_SCISSOR_0_TL", 5023 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5024 }, 5025 { 5026 "chips": ["gfx6"], 5027 "map": {"at": 164436, "to": "mm"}, 5028 "name": "PA_SC_VPORT_SCISSOR_0_BR", 5029 "type_ref": "PA_SC_CLIPRECT_0_BR" 5030 }, 5031 { 5032 "chips": ["gfx6"], 5033 "map": {"at": 164440, "to": "mm"}, 5034 "name": "PA_SC_VPORT_SCISSOR_1_TL", 5035 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5036 }, 5037 { 5038 "chips": ["gfx6"], 5039 "map": {"at": 164444, "to": "mm"}, 5040 "name": "PA_SC_VPORT_SCISSOR_1_BR", 5041 "type_ref": "PA_SC_CLIPRECT_0_BR" 5042 }, 5043 { 5044 "chips": ["gfx6"], 5045 "map": {"at": 164448, "to": "mm"}, 5046 "name": "PA_SC_VPORT_SCISSOR_2_TL", 5047 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5048 }, 5049 { 5050 "chips": ["gfx6"], 5051 "map": {"at": 164452, "to": "mm"}, 5052 "name": "PA_SC_VPORT_SCISSOR_2_BR", 5053 "type_ref": "PA_SC_CLIPRECT_0_BR" 5054 }, 5055 { 5056 "chips": ["gfx6"], 5057 "map": {"at": 164456, "to": "mm"}, 5058 "name": "PA_SC_VPORT_SCISSOR_3_TL", 5059 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5060 }, 5061 { 5062 "chips": ["gfx6"], 5063 "map": {"at": 164460, "to": "mm"}, 5064 "name": "PA_SC_VPORT_SCISSOR_3_BR", 5065 "type_ref": "PA_SC_CLIPRECT_0_BR" 5066 }, 5067 { 5068 "chips": ["gfx6"], 5069 "map": {"at": 164464, "to": "mm"}, 5070 "name": "PA_SC_VPORT_SCISSOR_4_TL", 5071 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5072 }, 5073 { 5074 "chips": ["gfx6"], 5075 "map": {"at": 164468, "to": "mm"}, 5076 "name": "PA_SC_VPORT_SCISSOR_4_BR", 5077 "type_ref": "PA_SC_CLIPRECT_0_BR" 5078 }, 5079 { 5080 "chips": ["gfx6"], 5081 "map": {"at": 164472, "to": "mm"}, 5082 "name": "PA_SC_VPORT_SCISSOR_5_TL", 5083 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5084 }, 5085 { 5086 "chips": ["gfx6"], 5087 "map": {"at": 164476, "to": "mm"}, 5088 "name": "PA_SC_VPORT_SCISSOR_5_BR", 5089 "type_ref": "PA_SC_CLIPRECT_0_BR" 5090 }, 5091 { 5092 "chips": ["gfx6"], 5093 "map": {"at": 164480, "to": "mm"}, 5094 "name": "PA_SC_VPORT_SCISSOR_6_TL", 5095 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5096 }, 5097 { 5098 "chips": ["gfx6"], 5099 "map": {"at": 164484, "to": "mm"}, 5100 "name": "PA_SC_VPORT_SCISSOR_6_BR", 5101 "type_ref": "PA_SC_CLIPRECT_0_BR" 5102 }, 5103 { 5104 "chips": ["gfx6"], 5105 "map": {"at": 164488, "to": "mm"}, 5106 "name": "PA_SC_VPORT_SCISSOR_7_TL", 5107 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5108 }, 5109 { 5110 "chips": ["gfx6"], 5111 "map": {"at": 164492, "to": "mm"}, 5112 "name": "PA_SC_VPORT_SCISSOR_7_BR", 5113 "type_ref": "PA_SC_CLIPRECT_0_BR" 5114 }, 5115 { 5116 "chips": ["gfx6"], 5117 "map": {"at": 164496, "to": "mm"}, 5118 "name": "PA_SC_VPORT_SCISSOR_8_TL", 5119 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5120 }, 5121 { 5122 "chips": ["gfx6"], 5123 "map": {"at": 164500, "to": "mm"}, 5124 "name": "PA_SC_VPORT_SCISSOR_8_BR", 5125 "type_ref": "PA_SC_CLIPRECT_0_BR" 5126 }, 5127 { 5128 "chips": ["gfx6"], 5129 "map": {"at": 164504, "to": "mm"}, 5130 "name": "PA_SC_VPORT_SCISSOR_9_TL", 5131 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5132 }, 5133 { 5134 "chips": ["gfx6"], 5135 "map": {"at": 164508, "to": "mm"}, 5136 "name": "PA_SC_VPORT_SCISSOR_9_BR", 5137 "type_ref": "PA_SC_CLIPRECT_0_BR" 5138 }, 5139 { 5140 "chips": ["gfx6"], 5141 "map": {"at": 164512, "to": "mm"}, 5142 "name": "PA_SC_VPORT_SCISSOR_10_TL", 5143 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5144 }, 5145 { 5146 "chips": ["gfx6"], 5147 "map": {"at": 164516, "to": "mm"}, 5148 "name": "PA_SC_VPORT_SCISSOR_10_BR", 5149 "type_ref": "PA_SC_CLIPRECT_0_BR" 5150 }, 5151 { 5152 "chips": ["gfx6"], 5153 "map": {"at": 164520, "to": "mm"}, 5154 "name": "PA_SC_VPORT_SCISSOR_11_TL", 5155 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5156 }, 5157 { 5158 "chips": ["gfx6"], 5159 "map": {"at": 164524, "to": "mm"}, 5160 "name": "PA_SC_VPORT_SCISSOR_11_BR", 5161 "type_ref": "PA_SC_CLIPRECT_0_BR" 5162 }, 5163 { 5164 "chips": ["gfx6"], 5165 "map": {"at": 164528, "to": "mm"}, 5166 "name": "PA_SC_VPORT_SCISSOR_12_TL", 5167 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5168 }, 5169 { 5170 "chips": ["gfx6"], 5171 "map": {"at": 164532, "to": "mm"}, 5172 "name": "PA_SC_VPORT_SCISSOR_12_BR", 5173 "type_ref": "PA_SC_CLIPRECT_0_BR" 5174 }, 5175 { 5176 "chips": ["gfx6"], 5177 "map": {"at": 164536, "to": "mm"}, 5178 "name": "PA_SC_VPORT_SCISSOR_13_TL", 5179 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5180 }, 5181 { 5182 "chips": ["gfx6"], 5183 "map": {"at": 164540, "to": "mm"}, 5184 "name": "PA_SC_VPORT_SCISSOR_13_BR", 5185 "type_ref": "PA_SC_CLIPRECT_0_BR" 5186 }, 5187 { 5188 "chips": ["gfx6"], 5189 "map": {"at": 164544, "to": "mm"}, 5190 "name": "PA_SC_VPORT_SCISSOR_14_TL", 5191 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5192 }, 5193 { 5194 "chips": ["gfx6"], 5195 "map": {"at": 164548, "to": "mm"}, 5196 "name": "PA_SC_VPORT_SCISSOR_14_BR", 5197 "type_ref": "PA_SC_CLIPRECT_0_BR" 5198 }, 5199 { 5200 "chips": ["gfx6"], 5201 "map": {"at": 164552, "to": "mm"}, 5202 "name": "PA_SC_VPORT_SCISSOR_15_TL", 5203 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5204 }, 5205 { 5206 "chips": ["gfx6"], 5207 "map": {"at": 164556, "to": "mm"}, 5208 "name": "PA_SC_VPORT_SCISSOR_15_BR", 5209 "type_ref": "PA_SC_CLIPRECT_0_BR" 5210 }, 5211 { 5212 "chips": ["gfx6"], 5213 "map": {"at": 164560, "to": "mm"}, 5214 "name": "PA_SC_VPORT_ZMIN_0" 5215 }, 5216 { 5217 "chips": ["gfx6"], 5218 "map": {"at": 164564, "to": "mm"}, 5219 "name": "PA_SC_VPORT_ZMAX_0" 5220 }, 5221 { 5222 "chips": ["gfx6"], 5223 "map": {"at": 164568, "to": "mm"}, 5224 "name": "PA_SC_VPORT_ZMIN_1" 5225 }, 5226 { 5227 "chips": ["gfx6"], 5228 "map": {"at": 164572, "to": "mm"}, 5229 "name": "PA_SC_VPORT_ZMAX_1" 5230 }, 5231 { 5232 "chips": ["gfx6"], 5233 "map": {"at": 164576, "to": "mm"}, 5234 "name": "PA_SC_VPORT_ZMIN_2" 5235 }, 5236 { 5237 "chips": ["gfx6"], 5238 "map": {"at": 164580, "to": "mm"}, 5239 "name": "PA_SC_VPORT_ZMAX_2" 5240 }, 5241 { 5242 "chips": ["gfx6"], 5243 "map": {"at": 164584, "to": "mm"}, 5244 "name": "PA_SC_VPORT_ZMIN_3" 5245 }, 5246 { 5247 "chips": ["gfx6"], 5248 "map": {"at": 164588, "to": "mm"}, 5249 "name": "PA_SC_VPORT_ZMAX_3" 5250 }, 5251 { 5252 "chips": ["gfx6"], 5253 "map": {"at": 164592, "to": "mm"}, 5254 "name": "PA_SC_VPORT_ZMIN_4" 5255 }, 5256 { 5257 "chips": ["gfx6"], 5258 "map": {"at": 164596, "to": "mm"}, 5259 "name": "PA_SC_VPORT_ZMAX_4" 5260 }, 5261 { 5262 "chips": ["gfx6"], 5263 "map": {"at": 164600, "to": "mm"}, 5264 "name": "PA_SC_VPORT_ZMIN_5" 5265 }, 5266 { 5267 "chips": ["gfx6"], 5268 "map": {"at": 164604, "to": "mm"}, 5269 "name": "PA_SC_VPORT_ZMAX_5" 5270 }, 5271 { 5272 "chips": ["gfx6"], 5273 "map": {"at": 164608, "to": "mm"}, 5274 "name": "PA_SC_VPORT_ZMIN_6" 5275 }, 5276 { 5277 "chips": ["gfx6"], 5278 "map": {"at": 164612, "to": "mm"}, 5279 "name": "PA_SC_VPORT_ZMAX_6" 5280 }, 5281 { 5282 "chips": ["gfx6"], 5283 "map": {"at": 164616, "to": "mm"}, 5284 "name": "PA_SC_VPORT_ZMIN_7" 5285 }, 5286 { 5287 "chips": ["gfx6"], 5288 "map": {"at": 164620, "to": "mm"}, 5289 "name": "PA_SC_VPORT_ZMAX_7" 5290 }, 5291 { 5292 "chips": ["gfx6"], 5293 "map": {"at": 164624, "to": "mm"}, 5294 "name": "PA_SC_VPORT_ZMIN_8" 5295 }, 5296 { 5297 "chips": ["gfx6"], 5298 "map": {"at": 164628, "to": "mm"}, 5299 "name": "PA_SC_VPORT_ZMAX_8" 5300 }, 5301 { 5302 "chips": ["gfx6"], 5303 "map": {"at": 164632, "to": "mm"}, 5304 "name": "PA_SC_VPORT_ZMIN_9" 5305 }, 5306 { 5307 "chips": ["gfx6"], 5308 "map": {"at": 164636, "to": "mm"}, 5309 "name": "PA_SC_VPORT_ZMAX_9" 5310 }, 5311 { 5312 "chips": ["gfx6"], 5313 "map": {"at": 164640, "to": "mm"}, 5314 "name": "PA_SC_VPORT_ZMIN_10" 5315 }, 5316 { 5317 "chips": ["gfx6"], 5318 "map": {"at": 164644, "to": "mm"}, 5319 "name": "PA_SC_VPORT_ZMAX_10" 5320 }, 5321 { 5322 "chips": ["gfx6"], 5323 "map": {"at": 164648, "to": "mm"}, 5324 "name": "PA_SC_VPORT_ZMIN_11" 5325 }, 5326 { 5327 "chips": ["gfx6"], 5328 "map": {"at": 164652, "to": "mm"}, 5329 "name": "PA_SC_VPORT_ZMAX_11" 5330 }, 5331 { 5332 "chips": ["gfx6"], 5333 "map": {"at": 164656, "to": "mm"}, 5334 "name": "PA_SC_VPORT_ZMIN_12" 5335 }, 5336 { 5337 "chips": ["gfx6"], 5338 "map": {"at": 164660, "to": "mm"}, 5339 "name": "PA_SC_VPORT_ZMAX_12" 5340 }, 5341 { 5342 "chips": ["gfx6"], 5343 "map": {"at": 164664, "to": "mm"}, 5344 "name": "PA_SC_VPORT_ZMIN_13" 5345 }, 5346 { 5347 "chips": ["gfx6"], 5348 "map": {"at": 164668, "to": "mm"}, 5349 "name": "PA_SC_VPORT_ZMAX_13" 5350 }, 5351 { 5352 "chips": ["gfx6"], 5353 "map": {"at": 164672, "to": "mm"}, 5354 "name": "PA_SC_VPORT_ZMIN_14" 5355 }, 5356 { 5357 "chips": ["gfx6"], 5358 "map": {"at": 164676, "to": "mm"}, 5359 "name": "PA_SC_VPORT_ZMAX_14" 5360 }, 5361 { 5362 "chips": ["gfx6"], 5363 "map": {"at": 164680, "to": "mm"}, 5364 "name": "PA_SC_VPORT_ZMIN_15" 5365 }, 5366 { 5367 "chips": ["gfx6"], 5368 "map": {"at": 164684, "to": "mm"}, 5369 "name": "PA_SC_VPORT_ZMAX_15" 5370 }, 5371 { 5372 "chips": ["gfx6"], 5373 "map": {"at": 164688, "to": "mm"}, 5374 "name": "PA_SC_RASTER_CONFIG", 5375 "type_ref": "PA_SC_RASTER_CONFIG" 5376 }, 5377 { 5378 "chips": ["gfx6"], 5379 "map": {"at": 164704, "to": "mm"}, 5380 "name": "CP_PERFMON_CNTX_CNTL", 5381 "type_ref": "CP_PERFMON_CNTX_CNTL" 5382 }, 5383 { 5384 "chips": ["gfx6"], 5385 "map": {"at": 164708, "to": "mm"}, 5386 "name": "CP_RINGID", 5387 "type_ref": "CP_RINGID" 5388 }, 5389 { 5390 "chips": ["gfx6"], 5391 "map": {"at": 164712, "to": "mm"}, 5392 "name": "CP_VMID", 5393 "type_ref": "CP_VMID" 5394 }, 5395 { 5396 "chips": ["gfx6"], 5397 "map": {"at": 164864, "to": "mm"}, 5398 "name": "VGT_MAX_VTX_INDX" 5399 }, 5400 { 5401 "chips": ["gfx6"], 5402 "map": {"at": 164868, "to": "mm"}, 5403 "name": "VGT_MIN_VTX_INDX" 5404 }, 5405 { 5406 "chips": ["gfx6"], 5407 "map": {"at": 164872, "to": "mm"}, 5408 "name": "VGT_INDX_OFFSET" 5409 }, 5410 { 5411 "chips": ["gfx6"], 5412 "map": {"at": 164876, "to": "mm"}, 5413 "name": "VGT_MULTI_PRIM_IB_RESET_INDX" 5414 }, 5415 { 5416 "chips": ["gfx6"], 5417 "map": {"at": 164884, "to": "mm"}, 5418 "name": "CB_BLEND_RED" 5419 }, 5420 { 5421 "chips": ["gfx6"], 5422 "map": {"at": 164888, "to": "mm"}, 5423 "name": "CB_BLEND_GREEN" 5424 }, 5425 { 5426 "chips": ["gfx6"], 5427 "map": {"at": 164892, "to": "mm"}, 5428 "name": "CB_BLEND_BLUE" 5429 }, 5430 { 5431 "chips": ["gfx6"], 5432 "map": {"at": 164896, "to": "mm"}, 5433 "name": "CB_BLEND_ALPHA" 5434 }, 5435 { 5436 "chips": ["gfx6"], 5437 "map": {"at": 164908, "to": "mm"}, 5438 "name": "DB_STENCIL_CONTROL", 5439 "type_ref": "DB_STENCIL_CONTROL" 5440 }, 5441 { 5442 "chips": ["gfx6"], 5443 "map": {"at": 164912, "to": "mm"}, 5444 "name": "DB_STENCILREFMASK", 5445 "type_ref": "DB_STENCILREFMASK" 5446 }, 5447 { 5448 "chips": ["gfx6"], 5449 "map": {"at": 164916, "to": "mm"}, 5450 "name": "DB_STENCILREFMASK_BF", 5451 "type_ref": "DB_STENCILREFMASK_BF" 5452 }, 5453 { 5454 "chips": ["gfx6"], 5455 "map": {"at": 164924, "to": "mm"}, 5456 "name": "PA_CL_VPORT_XSCALE" 5457 }, 5458 { 5459 "chips": ["gfx6"], 5460 "map": {"at": 164928, "to": "mm"}, 5461 "name": "PA_CL_VPORT_XOFFSET" 5462 }, 5463 { 5464 "chips": ["gfx6"], 5465 "map": {"at": 164932, "to": "mm"}, 5466 "name": "PA_CL_VPORT_YSCALE" 5467 }, 5468 { 5469 "chips": ["gfx6"], 5470 "map": {"at": 164936, "to": "mm"}, 5471 "name": "PA_CL_VPORT_YOFFSET" 5472 }, 5473 { 5474 "chips": ["gfx6"], 5475 "map": {"at": 164940, "to": "mm"}, 5476 "name": "PA_CL_VPORT_ZSCALE" 5477 }, 5478 { 5479 "chips": ["gfx6"], 5480 "map": {"at": 164944, "to": "mm"}, 5481 "name": "PA_CL_VPORT_ZOFFSET" 5482 }, 5483 { 5484 "chips": ["gfx6"], 5485 "map": {"at": 164948, "to": "mm"}, 5486 "name": "PA_CL_VPORT_XSCALE_1" 5487 }, 5488 { 5489 "chips": ["gfx6"], 5490 "map": {"at": 164952, "to": "mm"}, 5491 "name": "PA_CL_VPORT_XOFFSET_1" 5492 }, 5493 { 5494 "chips": ["gfx6"], 5495 "map": {"at": 164956, "to": "mm"}, 5496 "name": "PA_CL_VPORT_YSCALE_1" 5497 }, 5498 { 5499 "chips": ["gfx6"], 5500 "map": {"at": 164960, "to": "mm"}, 5501 "name": "PA_CL_VPORT_YOFFSET_1" 5502 }, 5503 { 5504 "chips": ["gfx6"], 5505 "map": {"at": 164964, "to": "mm"}, 5506 "name": "PA_CL_VPORT_ZSCALE_1" 5507 }, 5508 { 5509 "chips": ["gfx6"], 5510 "map": {"at": 164968, "to": "mm"}, 5511 "name": "PA_CL_VPORT_ZOFFSET_1" 5512 }, 5513 { 5514 "chips": ["gfx6"], 5515 "map": {"at": 164972, "to": "mm"}, 5516 "name": "PA_CL_VPORT_XSCALE_2" 5517 }, 5518 { 5519 "chips": ["gfx6"], 5520 "map": {"at": 164976, "to": "mm"}, 5521 "name": "PA_CL_VPORT_XOFFSET_2" 5522 }, 5523 { 5524 "chips": ["gfx6"], 5525 "map": {"at": 164980, "to": "mm"}, 5526 "name": "PA_CL_VPORT_YSCALE_2" 5527 }, 5528 { 5529 "chips": ["gfx6"], 5530 "map": {"at": 164984, "to": "mm"}, 5531 "name": "PA_CL_VPORT_YOFFSET_2" 5532 }, 5533 { 5534 "chips": ["gfx6"], 5535 "map": {"at": 164988, "to": "mm"}, 5536 "name": "PA_CL_VPORT_ZSCALE_2" 5537 }, 5538 { 5539 "chips": ["gfx6"], 5540 "map": {"at": 164992, "to": "mm"}, 5541 "name": "PA_CL_VPORT_ZOFFSET_2" 5542 }, 5543 { 5544 "chips": ["gfx6"], 5545 "map": {"at": 164996, "to": "mm"}, 5546 "name": "PA_CL_VPORT_XSCALE_3" 5547 }, 5548 { 5549 "chips": ["gfx6"], 5550 "map": {"at": 165000, "to": "mm"}, 5551 "name": "PA_CL_VPORT_XOFFSET_3" 5552 }, 5553 { 5554 "chips": ["gfx6"], 5555 "map": {"at": 165004, "to": "mm"}, 5556 "name": "PA_CL_VPORT_YSCALE_3" 5557 }, 5558 { 5559 "chips": ["gfx6"], 5560 "map": {"at": 165008, "to": "mm"}, 5561 "name": "PA_CL_VPORT_YOFFSET_3" 5562 }, 5563 { 5564 "chips": ["gfx6"], 5565 "map": {"at": 165012, "to": "mm"}, 5566 "name": "PA_CL_VPORT_ZSCALE_3" 5567 }, 5568 { 5569 "chips": ["gfx6"], 5570 "map": {"at": 165016, "to": "mm"}, 5571 "name": "PA_CL_VPORT_ZOFFSET_3" 5572 }, 5573 { 5574 "chips": ["gfx6"], 5575 "map": {"at": 165020, "to": "mm"}, 5576 "name": "PA_CL_VPORT_XSCALE_4" 5577 }, 5578 { 5579 "chips": ["gfx6"], 5580 "map": {"at": 165024, "to": "mm"}, 5581 "name": "PA_CL_VPORT_XOFFSET_4" 5582 }, 5583 { 5584 "chips": ["gfx6"], 5585 "map": {"at": 165028, "to": "mm"}, 5586 "name": "PA_CL_VPORT_YSCALE_4" 5587 }, 5588 { 5589 "chips": ["gfx6"], 5590 "map": {"at": 165032, "to": "mm"}, 5591 "name": "PA_CL_VPORT_YOFFSET_4" 5592 }, 5593 { 5594 "chips": ["gfx6"], 5595 "map": {"at": 165036, "to": "mm"}, 5596 "name": "PA_CL_VPORT_ZSCALE_4" 5597 }, 5598 { 5599 "chips": ["gfx6"], 5600 "map": {"at": 165040, "to": "mm"}, 5601 "name": "PA_CL_VPORT_ZOFFSET_4" 5602 }, 5603 { 5604 "chips": ["gfx6"], 5605 "map": {"at": 165044, "to": "mm"}, 5606 "name": "PA_CL_VPORT_XSCALE_5" 5607 }, 5608 { 5609 "chips": ["gfx6"], 5610 "map": {"at": 165048, "to": "mm"}, 5611 "name": "PA_CL_VPORT_XOFFSET_5" 5612 }, 5613 { 5614 "chips": ["gfx6"], 5615 "map": {"at": 165052, "to": "mm"}, 5616 "name": "PA_CL_VPORT_YSCALE_5" 5617 }, 5618 { 5619 "chips": ["gfx6"], 5620 "map": {"at": 165056, "to": "mm"}, 5621 "name": "PA_CL_VPORT_YOFFSET_5" 5622 }, 5623 { 5624 "chips": ["gfx6"], 5625 "map": {"at": 165060, "to": "mm"}, 5626 "name": "PA_CL_VPORT_ZSCALE_5" 5627 }, 5628 { 5629 "chips": ["gfx6"], 5630 "map": {"at": 165064, "to": "mm"}, 5631 "name": "PA_CL_VPORT_ZOFFSET_5" 5632 }, 5633 { 5634 "chips": ["gfx6"], 5635 "map": {"at": 165068, "to": "mm"}, 5636 "name": "PA_CL_VPORT_XSCALE_6" 5637 }, 5638 { 5639 "chips": ["gfx6"], 5640 "map": {"at": 165072, "to": "mm"}, 5641 "name": "PA_CL_VPORT_XOFFSET_6" 5642 }, 5643 { 5644 "chips": ["gfx6"], 5645 "map": {"at": 165076, "to": "mm"}, 5646 "name": "PA_CL_VPORT_YSCALE_6" 5647 }, 5648 { 5649 "chips": ["gfx6"], 5650 "map": {"at": 165080, "to": "mm"}, 5651 "name": "PA_CL_VPORT_YOFFSET_6" 5652 }, 5653 { 5654 "chips": ["gfx6"], 5655 "map": {"at": 165084, "to": "mm"}, 5656 "name": "PA_CL_VPORT_ZSCALE_6" 5657 }, 5658 { 5659 "chips": ["gfx6"], 5660 "map": {"at": 165088, "to": "mm"}, 5661 "name": "PA_CL_VPORT_ZOFFSET_6" 5662 }, 5663 { 5664 "chips": ["gfx6"], 5665 "map": {"at": 165092, "to": "mm"}, 5666 "name": "PA_CL_VPORT_XSCALE_7" 5667 }, 5668 { 5669 "chips": ["gfx6"], 5670 "map": {"at": 165096, "to": "mm"}, 5671 "name": "PA_CL_VPORT_XOFFSET_7" 5672 }, 5673 { 5674 "chips": ["gfx6"], 5675 "map": {"at": 165100, "to": "mm"}, 5676 "name": "PA_CL_VPORT_YSCALE_7" 5677 }, 5678 { 5679 "chips": ["gfx6"], 5680 "map": {"at": 165104, "to": "mm"}, 5681 "name": "PA_CL_VPORT_YOFFSET_7" 5682 }, 5683 { 5684 "chips": ["gfx6"], 5685 "map": {"at": 165108, "to": "mm"}, 5686 "name": "PA_CL_VPORT_ZSCALE_7" 5687 }, 5688 { 5689 "chips": ["gfx6"], 5690 "map": {"at": 165112, "to": "mm"}, 5691 "name": "PA_CL_VPORT_ZOFFSET_7" 5692 }, 5693 { 5694 "chips": ["gfx6"], 5695 "map": {"at": 165116, "to": "mm"}, 5696 "name": "PA_CL_VPORT_XSCALE_8" 5697 }, 5698 { 5699 "chips": ["gfx6"], 5700 "map": {"at": 165120, "to": "mm"}, 5701 "name": "PA_CL_VPORT_XOFFSET_8" 5702 }, 5703 { 5704 "chips": ["gfx6"], 5705 "map": {"at": 165124, "to": "mm"}, 5706 "name": "PA_CL_VPORT_YSCALE_8" 5707 }, 5708 { 5709 "chips": ["gfx6"], 5710 "map": {"at": 165128, "to": "mm"}, 5711 "name": "PA_CL_VPORT_YOFFSET_8" 5712 }, 5713 { 5714 "chips": ["gfx6"], 5715 "map": {"at": 165132, "to": "mm"}, 5716 "name": "PA_CL_VPORT_ZSCALE_8" 5717 }, 5718 { 5719 "chips": ["gfx6"], 5720 "map": {"at": 165136, "to": "mm"}, 5721 "name": "PA_CL_VPORT_ZOFFSET_8" 5722 }, 5723 { 5724 "chips": ["gfx6"], 5725 "map": {"at": 165140, "to": "mm"}, 5726 "name": "PA_CL_VPORT_XSCALE_9" 5727 }, 5728 { 5729 "chips": ["gfx6"], 5730 "map": {"at": 165144, "to": "mm"}, 5731 "name": "PA_CL_VPORT_XOFFSET_9" 5732 }, 5733 { 5734 "chips": ["gfx6"], 5735 "map": {"at": 165148, "to": "mm"}, 5736 "name": "PA_CL_VPORT_YSCALE_9" 5737 }, 5738 { 5739 "chips": ["gfx6"], 5740 "map": {"at": 165152, "to": "mm"}, 5741 "name": "PA_CL_VPORT_YOFFSET_9" 5742 }, 5743 { 5744 "chips": ["gfx6"], 5745 "map": {"at": 165156, "to": "mm"}, 5746 "name": "PA_CL_VPORT_ZSCALE_9" 5747 }, 5748 { 5749 "chips": ["gfx6"], 5750 "map": {"at": 165160, "to": "mm"}, 5751 "name": "PA_CL_VPORT_ZOFFSET_9" 5752 }, 5753 { 5754 "chips": ["gfx6"], 5755 "map": {"at": 165164, "to": "mm"}, 5756 "name": "PA_CL_VPORT_XSCALE_10" 5757 }, 5758 { 5759 "chips": ["gfx6"], 5760 "map": {"at": 165168, "to": "mm"}, 5761 "name": "PA_CL_VPORT_XOFFSET_10" 5762 }, 5763 { 5764 "chips": ["gfx6"], 5765 "map": {"at": 165172, "to": "mm"}, 5766 "name": "PA_CL_VPORT_YSCALE_10" 5767 }, 5768 { 5769 "chips": ["gfx6"], 5770 "map": {"at": 165176, "to": "mm"}, 5771 "name": "PA_CL_VPORT_YOFFSET_10" 5772 }, 5773 { 5774 "chips": ["gfx6"], 5775 "map": {"at": 165180, "to": "mm"}, 5776 "name": "PA_CL_VPORT_ZSCALE_10" 5777 }, 5778 { 5779 "chips": ["gfx6"], 5780 "map": {"at": 165184, "to": "mm"}, 5781 "name": "PA_CL_VPORT_ZOFFSET_10" 5782 }, 5783 { 5784 "chips": ["gfx6"], 5785 "map": {"at": 165188, "to": "mm"}, 5786 "name": "PA_CL_VPORT_XSCALE_11" 5787 }, 5788 { 5789 "chips": ["gfx6"], 5790 "map": {"at": 165192, "to": "mm"}, 5791 "name": "PA_CL_VPORT_XOFFSET_11" 5792 }, 5793 { 5794 "chips": ["gfx6"], 5795 "map": {"at": 165196, "to": "mm"}, 5796 "name": "PA_CL_VPORT_YSCALE_11" 5797 }, 5798 { 5799 "chips": ["gfx6"], 5800 "map": {"at": 165200, "to": "mm"}, 5801 "name": "PA_CL_VPORT_YOFFSET_11" 5802 }, 5803 { 5804 "chips": ["gfx6"], 5805 "map": {"at": 165204, "to": "mm"}, 5806 "name": "PA_CL_VPORT_ZSCALE_11" 5807 }, 5808 { 5809 "chips": ["gfx6"], 5810 "map": {"at": 165208, "to": "mm"}, 5811 "name": "PA_CL_VPORT_ZOFFSET_11" 5812 }, 5813 { 5814 "chips": ["gfx6"], 5815 "map": {"at": 165212, "to": "mm"}, 5816 "name": "PA_CL_VPORT_XSCALE_12" 5817 }, 5818 { 5819 "chips": ["gfx6"], 5820 "map": {"at": 165216, "to": "mm"}, 5821 "name": "PA_CL_VPORT_XOFFSET_12" 5822 }, 5823 { 5824 "chips": ["gfx6"], 5825 "map": {"at": 165220, "to": "mm"}, 5826 "name": "PA_CL_VPORT_YSCALE_12" 5827 }, 5828 { 5829 "chips": ["gfx6"], 5830 "map": {"at": 165224, "to": "mm"}, 5831 "name": "PA_CL_VPORT_YOFFSET_12" 5832 }, 5833 { 5834 "chips": ["gfx6"], 5835 "map": {"at": 165228, "to": "mm"}, 5836 "name": "PA_CL_VPORT_ZSCALE_12" 5837 }, 5838 { 5839 "chips": ["gfx6"], 5840 "map": {"at": 165232, "to": "mm"}, 5841 "name": "PA_CL_VPORT_ZOFFSET_12" 5842 }, 5843 { 5844 "chips": ["gfx6"], 5845 "map": {"at": 165236, "to": "mm"}, 5846 "name": "PA_CL_VPORT_XSCALE_13" 5847 }, 5848 { 5849 "chips": ["gfx6"], 5850 "map": {"at": 165240, "to": "mm"}, 5851 "name": "PA_CL_VPORT_XOFFSET_13" 5852 }, 5853 { 5854 "chips": ["gfx6"], 5855 "map": {"at": 165244, "to": "mm"}, 5856 "name": "PA_CL_VPORT_YSCALE_13" 5857 }, 5858 { 5859 "chips": ["gfx6"], 5860 "map": {"at": 165248, "to": "mm"}, 5861 "name": "PA_CL_VPORT_YOFFSET_13" 5862 }, 5863 { 5864 "chips": ["gfx6"], 5865 "map": {"at": 165252, "to": "mm"}, 5866 "name": "PA_CL_VPORT_ZSCALE_13" 5867 }, 5868 { 5869 "chips": ["gfx6"], 5870 "map": {"at": 165256, "to": "mm"}, 5871 "name": "PA_CL_VPORT_ZOFFSET_13" 5872 }, 5873 { 5874 "chips": ["gfx6"], 5875 "map": {"at": 165260, "to": "mm"}, 5876 "name": "PA_CL_VPORT_XSCALE_14" 5877 }, 5878 { 5879 "chips": ["gfx6"], 5880 "map": {"at": 165264, "to": "mm"}, 5881 "name": "PA_CL_VPORT_XOFFSET_14" 5882 }, 5883 { 5884 "chips": ["gfx6"], 5885 "map": {"at": 165268, "to": "mm"}, 5886 "name": "PA_CL_VPORT_YSCALE_14" 5887 }, 5888 { 5889 "chips": ["gfx6"], 5890 "map": {"at": 165272, "to": "mm"}, 5891 "name": "PA_CL_VPORT_YOFFSET_14" 5892 }, 5893 { 5894 "chips": ["gfx6"], 5895 "map": {"at": 165276, "to": "mm"}, 5896 "name": "PA_CL_VPORT_ZSCALE_14" 5897 }, 5898 { 5899 "chips": ["gfx6"], 5900 "map": {"at": 165280, "to": "mm"}, 5901 "name": "PA_CL_VPORT_ZOFFSET_14" 5902 }, 5903 { 5904 "chips": ["gfx6"], 5905 "map": {"at": 165284, "to": "mm"}, 5906 "name": "PA_CL_VPORT_XSCALE_15" 5907 }, 5908 { 5909 "chips": ["gfx6"], 5910 "map": {"at": 165288, "to": "mm"}, 5911 "name": "PA_CL_VPORT_XOFFSET_15" 5912 }, 5913 { 5914 "chips": ["gfx6"], 5915 "map": {"at": 165292, "to": "mm"}, 5916 "name": "PA_CL_VPORT_YSCALE_15" 5917 }, 5918 { 5919 "chips": ["gfx6"], 5920 "map": {"at": 165296, "to": "mm"}, 5921 "name": "PA_CL_VPORT_YOFFSET_15" 5922 }, 5923 { 5924 "chips": ["gfx6"], 5925 "map": {"at": 165300, "to": "mm"}, 5926 "name": "PA_CL_VPORT_ZSCALE_15" 5927 }, 5928 { 5929 "chips": ["gfx6"], 5930 "map": {"at": 165304, "to": "mm"}, 5931 "name": "PA_CL_VPORT_ZOFFSET_15" 5932 }, 5933 { 5934 "chips": ["gfx6"], 5935 "map": {"at": 165308, "to": "mm"}, 5936 "name": "PA_CL_UCP_0_X" 5937 }, 5938 { 5939 "chips": ["gfx6"], 5940 "map": {"at": 165312, "to": "mm"}, 5941 "name": "PA_CL_UCP_0_Y" 5942 }, 5943 { 5944 "chips": ["gfx6"], 5945 "map": {"at": 165316, "to": "mm"}, 5946 "name": "PA_CL_UCP_0_Z" 5947 }, 5948 { 5949 "chips": ["gfx6"], 5950 "map": {"at": 165320, "to": "mm"}, 5951 "name": "PA_CL_UCP_0_W" 5952 }, 5953 { 5954 "chips": ["gfx6"], 5955 "map": {"at": 165324, "to": "mm"}, 5956 "name": "PA_CL_UCP_1_X" 5957 }, 5958 { 5959 "chips": ["gfx6"], 5960 "map": {"at": 165328, "to": "mm"}, 5961 "name": "PA_CL_UCP_1_Y" 5962 }, 5963 { 5964 "chips": ["gfx6"], 5965 "map": {"at": 165332, "to": "mm"}, 5966 "name": "PA_CL_UCP_1_Z" 5967 }, 5968 { 5969 "chips": ["gfx6"], 5970 "map": {"at": 165336, "to": "mm"}, 5971 "name": "PA_CL_UCP_1_W" 5972 }, 5973 { 5974 "chips": ["gfx6"], 5975 "map": {"at": 165340, "to": "mm"}, 5976 "name": "PA_CL_UCP_2_X" 5977 }, 5978 { 5979 "chips": ["gfx6"], 5980 "map": {"at": 165344, "to": "mm"}, 5981 "name": "PA_CL_UCP_2_Y" 5982 }, 5983 { 5984 "chips": ["gfx6"], 5985 "map": {"at": 165348, "to": "mm"}, 5986 "name": "PA_CL_UCP_2_Z" 5987 }, 5988 { 5989 "chips": ["gfx6"], 5990 "map": {"at": 165352, "to": "mm"}, 5991 "name": "PA_CL_UCP_2_W" 5992 }, 5993 { 5994 "chips": ["gfx6"], 5995 "map": {"at": 165356, "to": "mm"}, 5996 "name": "PA_CL_UCP_3_X" 5997 }, 5998 { 5999 "chips": ["gfx6"], 6000 "map": {"at": 165360, "to": "mm"}, 6001 "name": "PA_CL_UCP_3_Y" 6002 }, 6003 { 6004 "chips": ["gfx6"], 6005 "map": {"at": 165364, "to": "mm"}, 6006 "name": "PA_CL_UCP_3_Z" 6007 }, 6008 { 6009 "chips": ["gfx6"], 6010 "map": {"at": 165368, "to": "mm"}, 6011 "name": "PA_CL_UCP_3_W" 6012 }, 6013 { 6014 "chips": ["gfx6"], 6015 "map": {"at": 165372, "to": "mm"}, 6016 "name": "PA_CL_UCP_4_X" 6017 }, 6018 { 6019 "chips": ["gfx6"], 6020 "map": {"at": 165376, "to": "mm"}, 6021 "name": "PA_CL_UCP_4_Y" 6022 }, 6023 { 6024 "chips": ["gfx6"], 6025 "map": {"at": 165380, "to": "mm"}, 6026 "name": "PA_CL_UCP_4_Z" 6027 }, 6028 { 6029 "chips": ["gfx6"], 6030 "map": {"at": 165384, "to": "mm"}, 6031 "name": "PA_CL_UCP_4_W" 6032 }, 6033 { 6034 "chips": ["gfx6"], 6035 "map": {"at": 165388, "to": "mm"}, 6036 "name": "PA_CL_UCP_5_X" 6037 }, 6038 { 6039 "chips": ["gfx6"], 6040 "map": {"at": 165392, "to": "mm"}, 6041 "name": "PA_CL_UCP_5_Y" 6042 }, 6043 { 6044 "chips": ["gfx6"], 6045 "map": {"at": 165396, "to": "mm"}, 6046 "name": "PA_CL_UCP_5_Z" 6047 }, 6048 { 6049 "chips": ["gfx6"], 6050 "map": {"at": 165400, "to": "mm"}, 6051 "name": "PA_CL_UCP_5_W" 6052 }, 6053 { 6054 "chips": ["gfx6"], 6055 "map": {"at": 165444, "to": "mm"}, 6056 "name": "SPI_PS_INPUT_CNTL_0", 6057 "type_ref": "SPI_PS_INPUT_CNTL_0" 6058 }, 6059 { 6060 "chips": ["gfx6"], 6061 "map": {"at": 165448, "to": "mm"}, 6062 "name": "SPI_PS_INPUT_CNTL_1", 6063 "type_ref": "SPI_PS_INPUT_CNTL_0" 6064 }, 6065 { 6066 "chips": ["gfx6"], 6067 "map": {"at": 165452, "to": "mm"}, 6068 "name": "SPI_PS_INPUT_CNTL_2", 6069 "type_ref": "SPI_PS_INPUT_CNTL_0" 6070 }, 6071 { 6072 "chips": ["gfx6"], 6073 "map": {"at": 165456, "to": "mm"}, 6074 "name": "SPI_PS_INPUT_CNTL_3", 6075 "type_ref": "SPI_PS_INPUT_CNTL_0" 6076 }, 6077 { 6078 "chips": ["gfx6"], 6079 "map": {"at": 165460, "to": "mm"}, 6080 "name": "SPI_PS_INPUT_CNTL_4", 6081 "type_ref": "SPI_PS_INPUT_CNTL_0" 6082 }, 6083 { 6084 "chips": ["gfx6"], 6085 "map": {"at": 165464, "to": "mm"}, 6086 "name": "SPI_PS_INPUT_CNTL_5", 6087 "type_ref": "SPI_PS_INPUT_CNTL_0" 6088 }, 6089 { 6090 "chips": ["gfx6"], 6091 "map": {"at": 165468, "to": "mm"}, 6092 "name": "SPI_PS_INPUT_CNTL_6", 6093 "type_ref": "SPI_PS_INPUT_CNTL_0" 6094 }, 6095 { 6096 "chips": ["gfx6"], 6097 "map": {"at": 165472, "to": "mm"}, 6098 "name": "SPI_PS_INPUT_CNTL_7", 6099 "type_ref": "SPI_PS_INPUT_CNTL_0" 6100 }, 6101 { 6102 "chips": ["gfx6"], 6103 "map": {"at": 165476, "to": "mm"}, 6104 "name": "SPI_PS_INPUT_CNTL_8", 6105 "type_ref": "SPI_PS_INPUT_CNTL_0" 6106 }, 6107 { 6108 "chips": ["gfx6"], 6109 "map": {"at": 165480, "to": "mm"}, 6110 "name": "SPI_PS_INPUT_CNTL_9", 6111 "type_ref": "SPI_PS_INPUT_CNTL_0" 6112 }, 6113 { 6114 "chips": ["gfx6"], 6115 "map": {"at": 165484, "to": "mm"}, 6116 "name": "SPI_PS_INPUT_CNTL_10", 6117 "type_ref": "SPI_PS_INPUT_CNTL_0" 6118 }, 6119 { 6120 "chips": ["gfx6"], 6121 "map": {"at": 165488, "to": "mm"}, 6122 "name": "SPI_PS_INPUT_CNTL_11", 6123 "type_ref": "SPI_PS_INPUT_CNTL_0" 6124 }, 6125 { 6126 "chips": ["gfx6"], 6127 "map": {"at": 165492, "to": "mm"}, 6128 "name": "SPI_PS_INPUT_CNTL_12", 6129 "type_ref": "SPI_PS_INPUT_CNTL_0" 6130 }, 6131 { 6132 "chips": ["gfx6"], 6133 "map": {"at": 165496, "to": "mm"}, 6134 "name": "SPI_PS_INPUT_CNTL_13", 6135 "type_ref": "SPI_PS_INPUT_CNTL_0" 6136 }, 6137 { 6138 "chips": ["gfx6"], 6139 "map": {"at": 165500, "to": "mm"}, 6140 "name": "SPI_PS_INPUT_CNTL_14", 6141 "type_ref": "SPI_PS_INPUT_CNTL_0" 6142 }, 6143 { 6144 "chips": ["gfx6"], 6145 "map": {"at": 165504, "to": "mm"}, 6146 "name": "SPI_PS_INPUT_CNTL_15", 6147 "type_ref": "SPI_PS_INPUT_CNTL_0" 6148 }, 6149 { 6150 "chips": ["gfx6"], 6151 "map": {"at": 165508, "to": "mm"}, 6152 "name": "SPI_PS_INPUT_CNTL_16", 6153 "type_ref": "SPI_PS_INPUT_CNTL_0" 6154 }, 6155 { 6156 "chips": ["gfx6"], 6157 "map": {"at": 165512, "to": "mm"}, 6158 "name": "SPI_PS_INPUT_CNTL_17", 6159 "type_ref": "SPI_PS_INPUT_CNTL_0" 6160 }, 6161 { 6162 "chips": ["gfx6"], 6163 "map": {"at": 165516, "to": "mm"}, 6164 "name": "SPI_PS_INPUT_CNTL_18", 6165 "type_ref": "SPI_PS_INPUT_CNTL_0" 6166 }, 6167 { 6168 "chips": ["gfx6"], 6169 "map": {"at": 165520, "to": "mm"}, 6170 "name": "SPI_PS_INPUT_CNTL_19", 6171 "type_ref": "SPI_PS_INPUT_CNTL_0" 6172 }, 6173 { 6174 "chips": ["gfx6"], 6175 "map": {"at": 165524, "to": "mm"}, 6176 "name": "SPI_PS_INPUT_CNTL_20", 6177 "type_ref": "SPI_PS_INPUT_CNTL_20" 6178 }, 6179 { 6180 "chips": ["gfx6"], 6181 "map": {"at": 165528, "to": "mm"}, 6182 "name": "SPI_PS_INPUT_CNTL_21", 6183 "type_ref": "SPI_PS_INPUT_CNTL_20" 6184 }, 6185 { 6186 "chips": ["gfx6"], 6187 "map": {"at": 165532, "to": "mm"}, 6188 "name": "SPI_PS_INPUT_CNTL_22", 6189 "type_ref": "SPI_PS_INPUT_CNTL_20" 6190 }, 6191 { 6192 "chips": ["gfx6"], 6193 "map": {"at": 165536, "to": "mm"}, 6194 "name": "SPI_PS_INPUT_CNTL_23", 6195 "type_ref": "SPI_PS_INPUT_CNTL_20" 6196 }, 6197 { 6198 "chips": ["gfx6"], 6199 "map": {"at": 165540, "to": "mm"}, 6200 "name": "SPI_PS_INPUT_CNTL_24", 6201 "type_ref": "SPI_PS_INPUT_CNTL_20" 6202 }, 6203 { 6204 "chips": ["gfx6"], 6205 "map": {"at": 165544, "to": "mm"}, 6206 "name": "SPI_PS_INPUT_CNTL_25", 6207 "type_ref": "SPI_PS_INPUT_CNTL_20" 6208 }, 6209 { 6210 "chips": ["gfx6"], 6211 "map": {"at": 165548, "to": "mm"}, 6212 "name": "SPI_PS_INPUT_CNTL_26", 6213 "type_ref": "SPI_PS_INPUT_CNTL_20" 6214 }, 6215 { 6216 "chips": ["gfx6"], 6217 "map": {"at": 165552, "to": "mm"}, 6218 "name": "SPI_PS_INPUT_CNTL_27", 6219 "type_ref": "SPI_PS_INPUT_CNTL_20" 6220 }, 6221 { 6222 "chips": ["gfx6"], 6223 "map": {"at": 165556, "to": "mm"}, 6224 "name": "SPI_PS_INPUT_CNTL_28", 6225 "type_ref": "SPI_PS_INPUT_CNTL_20" 6226 }, 6227 { 6228 "chips": ["gfx6"], 6229 "map": {"at": 165560, "to": "mm"}, 6230 "name": "SPI_PS_INPUT_CNTL_29", 6231 "type_ref": "SPI_PS_INPUT_CNTL_20" 6232 }, 6233 { 6234 "chips": ["gfx6"], 6235 "map": {"at": 165564, "to": "mm"}, 6236 "name": "SPI_PS_INPUT_CNTL_30", 6237 "type_ref": "SPI_PS_INPUT_CNTL_20" 6238 }, 6239 { 6240 "chips": ["gfx6"], 6241 "map": {"at": 165568, "to": "mm"}, 6242 "name": "SPI_PS_INPUT_CNTL_31", 6243 "type_ref": "SPI_PS_INPUT_CNTL_20" 6244 }, 6245 { 6246 "chips": ["gfx6"], 6247 "map": {"at": 165572, "to": "mm"}, 6248 "name": "SPI_VS_OUT_CONFIG", 6249 "type_ref": "SPI_VS_OUT_CONFIG" 6250 }, 6251 { 6252 "chips": ["gfx6"], 6253 "map": {"at": 165580, "to": "mm"}, 6254 "name": "SPI_PS_INPUT_ENA", 6255 "type_ref": "SPI_PS_INPUT_ADDR" 6256 }, 6257 { 6258 "chips": ["gfx6"], 6259 "map": {"at": 165584, "to": "mm"}, 6260 "name": "SPI_PS_INPUT_ADDR", 6261 "type_ref": "SPI_PS_INPUT_ADDR" 6262 }, 6263 { 6264 "chips": ["gfx6"], 6265 "map": {"at": 165588, "to": "mm"}, 6266 "name": "SPI_INTERP_CONTROL_0", 6267 "type_ref": "SPI_INTERP_CONTROL_0" 6268 }, 6269 { 6270 "chips": ["gfx6"], 6271 "map": {"at": 165592, "to": "mm"}, 6272 "name": "SPI_PS_IN_CONTROL", 6273 "type_ref": "SPI_PS_IN_CONTROL" 6274 }, 6275 { 6276 "chips": ["gfx6"], 6277 "map": {"at": 165600, "to": "mm"}, 6278 "name": "SPI_BARYC_CNTL", 6279 "type_ref": "SPI_BARYC_CNTL" 6280 }, 6281 { 6282 "chips": ["gfx6"], 6283 "map": {"at": 165608, "to": "mm"}, 6284 "name": "SPI_TMPRING_SIZE", 6285 "type_ref": "COMPUTE_TMPRING_SIZE" 6286 }, 6287 { 6288 "chips": ["gfx6"], 6289 "map": {"at": 165644, "to": "mm"}, 6290 "name": "SPI_SHADER_POS_FORMAT", 6291 "type_ref": "SPI_SHADER_POS_FORMAT" 6292 }, 6293 { 6294 "chips": ["gfx6"], 6295 "map": {"at": 165648, "to": "mm"}, 6296 "name": "SPI_SHADER_Z_FORMAT", 6297 "type_ref": "SPI_SHADER_Z_FORMAT" 6298 }, 6299 { 6300 "chips": ["gfx6"], 6301 "map": {"at": 165652, "to": "mm"}, 6302 "name": "SPI_SHADER_COL_FORMAT", 6303 "type_ref": "SPI_SHADER_COL_FORMAT" 6304 }, 6305 { 6306 "chips": ["gfx6"], 6307 "map": {"at": 165760, "to": "mm"}, 6308 "name": "CB_BLEND0_CONTROL", 6309 "type_ref": "CB_BLEND0_CONTROL" 6310 }, 6311 { 6312 "chips": ["gfx6"], 6313 "map": {"at": 165764, "to": "mm"}, 6314 "name": "CB_BLEND1_CONTROL", 6315 "type_ref": "CB_BLEND0_CONTROL" 6316 }, 6317 { 6318 "chips": ["gfx6"], 6319 "map": {"at": 165768, "to": "mm"}, 6320 "name": "CB_BLEND2_CONTROL", 6321 "type_ref": "CB_BLEND0_CONTROL" 6322 }, 6323 { 6324 "chips": ["gfx6"], 6325 "map": {"at": 165772, "to": "mm"}, 6326 "name": "CB_BLEND3_CONTROL", 6327 "type_ref": "CB_BLEND0_CONTROL" 6328 }, 6329 { 6330 "chips": ["gfx6"], 6331 "map": {"at": 165776, "to": "mm"}, 6332 "name": "CB_BLEND4_CONTROL", 6333 "type_ref": "CB_BLEND0_CONTROL" 6334 }, 6335 { 6336 "chips": ["gfx6"], 6337 "map": {"at": 165780, "to": "mm"}, 6338 "name": "CB_BLEND5_CONTROL", 6339 "type_ref": "CB_BLEND0_CONTROL" 6340 }, 6341 { 6342 "chips": ["gfx6"], 6343 "map": {"at": 165784, "to": "mm"}, 6344 "name": "CB_BLEND6_CONTROL", 6345 "type_ref": "CB_BLEND0_CONTROL" 6346 }, 6347 { 6348 "chips": ["gfx6"], 6349 "map": {"at": 165788, "to": "mm"}, 6350 "name": "CB_BLEND7_CONTROL", 6351 "type_ref": "CB_BLEND0_CONTROL" 6352 }, 6353 { 6354 "chips": ["gfx6"], 6355 "map": {"at": 165836, "to": "mm"}, 6356 "name": "CS_COPY_STATE", 6357 "type_ref": "CS_COPY_STATE" 6358 }, 6359 { 6360 "chips": ["gfx6"], 6361 "map": {"at": 165840, "to": "mm"}, 6362 "name": "GFX_COPY_STATE", 6363 "type_ref": "CS_COPY_STATE" 6364 }, 6365 { 6366 "chips": ["gfx6"], 6367 "map": {"at": 165844, "to": "mm"}, 6368 "name": "PA_CL_POINT_X_RAD" 6369 }, 6370 { 6371 "chips": ["gfx6"], 6372 "map": {"at": 165848, "to": "mm"}, 6373 "name": "PA_CL_POINT_Y_RAD" 6374 }, 6375 { 6376 "chips": ["gfx6"], 6377 "map": {"at": 165852, "to": "mm"}, 6378 "name": "PA_CL_POINT_SIZE" 6379 }, 6380 { 6381 "chips": ["gfx6"], 6382 "map": {"at": 165856, "to": "mm"}, 6383 "name": "PA_CL_POINT_CULL_RAD" 6384 }, 6385 { 6386 "chips": ["gfx6"], 6387 "map": {"at": 165860, "to": "mm"}, 6388 "name": "VGT_DMA_BASE_HI", 6389 "type_ref": "VGT_DMA_BASE_HI" 6390 }, 6391 { 6392 "chips": ["gfx6"], 6393 "map": {"at": 165864, "to": "mm"}, 6394 "name": "VGT_DMA_BASE" 6395 }, 6396 { 6397 "chips": ["gfx6"], 6398 "map": {"at": 165872, "to": "mm"}, 6399 "name": "VGT_DRAW_INITIATOR", 6400 "type_ref": "VGT_DRAW_INITIATOR" 6401 }, 6402 { 6403 "chips": ["gfx6"], 6404 "map": {"at": 165876, "to": "mm"}, 6405 "name": "VGT_IMMED_DATA" 6406 }, 6407 { 6408 "chips": ["gfx6"], 6409 "map": {"at": 165880, "to": "mm"}, 6410 "name": "VGT_EVENT_ADDRESS_REG", 6411 "type_ref": "VGT_EVENT_ADDRESS_REG" 6412 }, 6413 { 6414 "chips": ["gfx6"], 6415 "map": {"at": 165888, "to": "mm"}, 6416 "name": "DB_DEPTH_CONTROL", 6417 "type_ref": "DB_DEPTH_CONTROL" 6418 }, 6419 { 6420 "chips": ["gfx6"], 6421 "map": {"at": 165892, "to": "mm"}, 6422 "name": "DB_EQAA", 6423 "type_ref": "DB_EQAA" 6424 }, 6425 { 6426 "chips": ["gfx6"], 6427 "map": {"at": 165896, "to": "mm"}, 6428 "name": "CB_COLOR_CONTROL", 6429 "type_ref": "CB_COLOR_CONTROL" 6430 }, 6431 { 6432 "chips": ["gfx6"], 6433 "map": {"at": 165900, "to": "mm"}, 6434 "name": "DB_SHADER_CONTROL", 6435 "type_ref": "DB_SHADER_CONTROL" 6436 }, 6437 { 6438 "chips": ["gfx6"], 6439 "map": {"at": 165904, "to": "mm"}, 6440 "name": "PA_CL_CLIP_CNTL", 6441 "type_ref": "PA_CL_CLIP_CNTL" 6442 }, 6443 { 6444 "chips": ["gfx6"], 6445 "map": {"at": 165908, "to": "mm"}, 6446 "name": "PA_SU_SC_MODE_CNTL", 6447 "type_ref": "PA_SU_SC_MODE_CNTL" 6448 }, 6449 { 6450 "chips": ["gfx6"], 6451 "map": {"at": 165912, "to": "mm"}, 6452 "name": "PA_CL_VTE_CNTL", 6453 "type_ref": "PA_CL_VTE_CNTL" 6454 }, 6455 { 6456 "chips": ["gfx6"], 6457 "map": {"at": 165916, "to": "mm"}, 6458 "name": "PA_CL_VS_OUT_CNTL", 6459 "type_ref": "PA_CL_VS_OUT_CNTL" 6460 }, 6461 { 6462 "chips": ["gfx6"], 6463 "map": {"at": 165920, "to": "mm"}, 6464 "name": "PA_CL_NANINF_CNTL", 6465 "type_ref": "PA_CL_NANINF_CNTL" 6466 }, 6467 { 6468 "chips": ["gfx6"], 6469 "map": {"at": 165924, "to": "mm"}, 6470 "name": "PA_SU_LINE_STIPPLE_CNTL", 6471 "type_ref": "PA_SU_LINE_STIPPLE_CNTL" 6472 }, 6473 { 6474 "chips": ["gfx6"], 6475 "map": {"at": 165928, "to": "mm"}, 6476 "name": "PA_SU_LINE_STIPPLE_SCALE" 6477 }, 6478 { 6479 "chips": ["gfx6"], 6480 "map": {"at": 165932, "to": "mm"}, 6481 "name": "PA_SU_PRIM_FILTER_CNTL", 6482 "type_ref": "PA_SU_PRIM_FILTER_CNTL" 6483 }, 6484 { 6485 "chips": ["gfx6"], 6486 "map": {"at": 166400, "to": "mm"}, 6487 "name": "PA_SU_POINT_SIZE", 6488 "type_ref": "PA_SU_POINT_SIZE" 6489 }, 6490 { 6491 "chips": ["gfx6"], 6492 "map": {"at": 166404, "to": "mm"}, 6493 "name": "PA_SU_POINT_MINMAX", 6494 "type_ref": "PA_SU_POINT_MINMAX" 6495 }, 6496 { 6497 "chips": ["gfx6"], 6498 "map": {"at": 166408, "to": "mm"}, 6499 "name": "PA_SU_LINE_CNTL", 6500 "type_ref": "PA_SU_LINE_CNTL" 6501 }, 6502 { 6503 "chips": ["gfx6"], 6504 "map": {"at": 166412, "to": "mm"}, 6505 "name": "PA_SC_LINE_STIPPLE", 6506 "type_ref": "PA_SC_LINE_STIPPLE" 6507 }, 6508 { 6509 "chips": ["gfx6"], 6510 "map": {"at": 166416, "to": "mm"}, 6511 "name": "VGT_OUTPUT_PATH_CNTL", 6512 "type_ref": "VGT_OUTPUT_PATH_CNTL" 6513 }, 6514 { 6515 "chips": ["gfx6"], 6516 "map": {"at": 166420, "to": "mm"}, 6517 "name": "VGT_HOS_CNTL", 6518 "type_ref": "VGT_HOS_CNTL" 6519 }, 6520 { 6521 "chips": ["gfx6"], 6522 "map": {"at": 166424, "to": "mm"}, 6523 "name": "VGT_HOS_MAX_TESS_LEVEL" 6524 }, 6525 { 6526 "chips": ["gfx6"], 6527 "map": {"at": 166428, "to": "mm"}, 6528 "name": "VGT_HOS_MIN_TESS_LEVEL" 6529 }, 6530 { 6531 "chips": ["gfx6"], 6532 "map": {"at": 166432, "to": "mm"}, 6533 "name": "VGT_HOS_REUSE_DEPTH", 6534 "type_ref": "VGT_HOS_REUSE_DEPTH" 6535 }, 6536 { 6537 "chips": ["gfx6"], 6538 "map": {"at": 166436, "to": "mm"}, 6539 "name": "VGT_GROUP_PRIM_TYPE", 6540 "type_ref": "VGT_GROUP_PRIM_TYPE" 6541 }, 6542 { 6543 "chips": ["gfx6"], 6544 "map": {"at": 166440, "to": "mm"}, 6545 "name": "VGT_GROUP_FIRST_DECR", 6546 "type_ref": "VGT_GROUP_FIRST_DECR" 6547 }, 6548 { 6549 "chips": ["gfx6"], 6550 "map": {"at": 166444, "to": "mm"}, 6551 "name": "VGT_GROUP_DECR", 6552 "type_ref": "VGT_GROUP_DECR" 6553 }, 6554 { 6555 "chips": ["gfx6"], 6556 "map": {"at": 166448, "to": "mm"}, 6557 "name": "VGT_GROUP_VECT_0_CNTL", 6558 "type_ref": "VGT_GROUP_VECT_0_CNTL" 6559 }, 6560 { 6561 "chips": ["gfx6"], 6562 "map": {"at": 166452, "to": "mm"}, 6563 "name": "VGT_GROUP_VECT_1_CNTL", 6564 "type_ref": "VGT_GROUP_VECT_0_CNTL" 6565 }, 6566 { 6567 "chips": ["gfx6"], 6568 "map": {"at": 166456, "to": "mm"}, 6569 "name": "VGT_GROUP_VECT_0_FMT_CNTL", 6570 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 6571 }, 6572 { 6573 "chips": ["gfx6"], 6574 "map": {"at": 166460, "to": "mm"}, 6575 "name": "VGT_GROUP_VECT_1_FMT_CNTL", 6576 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 6577 }, 6578 { 6579 "chips": ["gfx6"], 6580 "map": {"at": 166464, "to": "mm"}, 6581 "name": "VGT_GS_MODE", 6582 "type_ref": "VGT_GS_MODE" 6583 }, 6584 { 6585 "chips": ["gfx6"], 6586 "map": {"at": 166472, "to": "mm"}, 6587 "name": "PA_SC_MODE_CNTL_0", 6588 "type_ref": "PA_SC_MODE_CNTL_0" 6589 }, 6590 { 6591 "chips": ["gfx6"], 6592 "map": {"at": 166476, "to": "mm"}, 6593 "name": "PA_SC_MODE_CNTL_1", 6594 "type_ref": "PA_SC_MODE_CNTL_1" 6595 }, 6596 { 6597 "chips": ["gfx6"], 6598 "map": {"at": 166480, "to": "mm"}, 6599 "name": "VGT_ENHANCE" 6600 }, 6601 { 6602 "chips": ["gfx6"], 6603 "map": {"at": 166484, "to": "mm"}, 6604 "name": "VGT_GS_PER_ES", 6605 "type_ref": "VGT_GS_PER_ES" 6606 }, 6607 { 6608 "chips": ["gfx6"], 6609 "map": {"at": 166488, "to": "mm"}, 6610 "name": "VGT_ES_PER_GS", 6611 "type_ref": "VGT_ES_PER_GS" 6612 }, 6613 { 6614 "chips": ["gfx6"], 6615 "map": {"at": 166492, "to": "mm"}, 6616 "name": "VGT_GS_PER_VS", 6617 "type_ref": "VGT_GS_PER_VS" 6618 }, 6619 { 6620 "chips": ["gfx6"], 6621 "map": {"at": 166496, "to": "mm"}, 6622 "name": "VGT_GSVS_RING_OFFSET_1", 6623 "type_ref": "VGT_GSVS_RING_OFFSET_1" 6624 }, 6625 { 6626 "chips": ["gfx6"], 6627 "map": {"at": 166500, "to": "mm"}, 6628 "name": "VGT_GSVS_RING_OFFSET_2", 6629 "type_ref": "VGT_GSVS_RING_OFFSET_1" 6630 }, 6631 { 6632 "chips": ["gfx6"], 6633 "map": {"at": 166504, "to": "mm"}, 6634 "name": "VGT_GSVS_RING_OFFSET_3", 6635 "type_ref": "VGT_GSVS_RING_OFFSET_1" 6636 }, 6637 { 6638 "chips": ["gfx6"], 6639 "map": {"at": 166508, "to": "mm"}, 6640 "name": "VGT_GS_OUT_PRIM_TYPE", 6641 "type_ref": "VGT_GS_OUT_PRIM_TYPE" 6642 }, 6643 { 6644 "chips": ["gfx6"], 6645 "map": {"at": 166512, "to": "mm"}, 6646 "name": "IA_ENHANCE" 6647 }, 6648 { 6649 "chips": ["gfx6"], 6650 "map": {"at": 166516, "to": "mm"}, 6651 "name": "VGT_DMA_SIZE" 6652 }, 6653 { 6654 "chips": ["gfx6"], 6655 "map": {"at": 166520, "to": "mm"}, 6656 "name": "VGT_DMA_MAX_SIZE" 6657 }, 6658 { 6659 "chips": ["gfx6"], 6660 "map": {"at": 166524, "to": "mm"}, 6661 "name": "VGT_DMA_INDEX_TYPE", 6662 "type_ref": "VGT_DMA_INDEX_TYPE" 6663 }, 6664 { 6665 "chips": ["gfx6"], 6666 "map": {"at": 166532, "to": "mm"}, 6667 "name": "VGT_PRIMITIVEID_EN", 6668 "type_ref": "VGT_PRIMITIVEID_EN" 6669 }, 6670 { 6671 "chips": ["gfx6"], 6672 "map": {"at": 166536, "to": "mm"}, 6673 "name": "VGT_DMA_NUM_INSTANCES" 6674 }, 6675 { 6676 "chips": ["gfx6"], 6677 "map": {"at": 166540, "to": "mm"}, 6678 "name": "VGT_PRIMITIVEID_RESET" 6679 }, 6680 { 6681 "chips": ["gfx6"], 6682 "map": {"at": 166544, "to": "mm"}, 6683 "name": "VGT_EVENT_INITIATOR", 6684 "type_ref": "VGT_EVENT_INITIATOR" 6685 }, 6686 { 6687 "chips": ["gfx6"], 6688 "map": {"at": 166548, "to": "mm"}, 6689 "name": "VGT_MULTI_PRIM_IB_RESET_EN", 6690 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN" 6691 }, 6692 { 6693 "chips": ["gfx6"], 6694 "map": {"at": 166560, "to": "mm"}, 6695 "name": "VGT_INSTANCE_STEP_RATE_0" 6696 }, 6697 { 6698 "chips": ["gfx6"], 6699 "map": {"at": 166564, "to": "mm"}, 6700 "name": "VGT_INSTANCE_STEP_RATE_1" 6701 }, 6702 { 6703 "chips": ["gfx6"], 6704 "map": {"at": 166568, "to": "mm"}, 6705 "name": "IA_MULTI_VGT_PARAM", 6706 "type_ref": "IA_MULTI_VGT_PARAM" 6707 }, 6708 { 6709 "chips": ["gfx6"], 6710 "map": {"at": 166572, "to": "mm"}, 6711 "name": "VGT_ESGS_RING_ITEMSIZE", 6712 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6713 }, 6714 { 6715 "chips": ["gfx6"], 6716 "map": {"at": 166576, "to": "mm"}, 6717 "name": "VGT_GSVS_RING_ITEMSIZE", 6718 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6719 }, 6720 { 6721 "chips": ["gfx6"], 6722 "map": {"at": 166580, "to": "mm"}, 6723 "name": "VGT_REUSE_OFF", 6724 "type_ref": "VGT_REUSE_OFF" 6725 }, 6726 { 6727 "chips": ["gfx6"], 6728 "map": {"at": 166584, "to": "mm"}, 6729 "name": "VGT_VTX_CNT_EN", 6730 "type_ref": "VGT_VTX_CNT_EN" 6731 }, 6732 { 6733 "chips": ["gfx6"], 6734 "map": {"at": 166588, "to": "mm"}, 6735 "name": "DB_HTILE_SURFACE", 6736 "type_ref": "DB_HTILE_SURFACE" 6737 }, 6738 { 6739 "chips": ["gfx6"], 6740 "map": {"at": 166592, "to": "mm"}, 6741 "name": "DB_SRESULTS_COMPARE_STATE0", 6742 "type_ref": "DB_SRESULTS_COMPARE_STATE0" 6743 }, 6744 { 6745 "chips": ["gfx6"], 6746 "map": {"at": 166596, "to": "mm"}, 6747 "name": "DB_SRESULTS_COMPARE_STATE1", 6748 "type_ref": "DB_SRESULTS_COMPARE_STATE1" 6749 }, 6750 { 6751 "chips": ["gfx6"], 6752 "map": {"at": 166600, "to": "mm"}, 6753 "name": "DB_PRELOAD_CONTROL", 6754 "type_ref": "DB_PRELOAD_CONTROL" 6755 }, 6756 { 6757 "chips": ["gfx6"], 6758 "map": {"at": 166608, "to": "mm"}, 6759 "name": "VGT_STRMOUT_BUFFER_SIZE_0" 6760 }, 6761 { 6762 "chips": ["gfx6"], 6763 "map": {"at": 166612, "to": "mm"}, 6764 "name": "VGT_STRMOUT_VTX_STRIDE_0", 6765 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6766 }, 6767 { 6768 "chips": ["gfx6"], 6769 "map": {"at": 166620, "to": "mm"}, 6770 "name": "VGT_STRMOUT_BUFFER_OFFSET_0" 6771 }, 6772 { 6773 "chips": ["gfx6"], 6774 "map": {"at": 166624, "to": "mm"}, 6775 "name": "VGT_STRMOUT_BUFFER_SIZE_1" 6776 }, 6777 { 6778 "chips": ["gfx6"], 6779 "map": {"at": 166628, "to": "mm"}, 6780 "name": "VGT_STRMOUT_VTX_STRIDE_1", 6781 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6782 }, 6783 { 6784 "chips": ["gfx6"], 6785 "map": {"at": 166636, "to": "mm"}, 6786 "name": "VGT_STRMOUT_BUFFER_OFFSET_1" 6787 }, 6788 { 6789 "chips": ["gfx6"], 6790 "map": {"at": 166640, "to": "mm"}, 6791 "name": "VGT_STRMOUT_BUFFER_SIZE_2" 6792 }, 6793 { 6794 "chips": ["gfx6"], 6795 "map": {"at": 166644, "to": "mm"}, 6796 "name": "VGT_STRMOUT_VTX_STRIDE_2", 6797 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6798 }, 6799 { 6800 "chips": ["gfx6"], 6801 "map": {"at": 166652, "to": "mm"}, 6802 "name": "VGT_STRMOUT_BUFFER_OFFSET_2" 6803 }, 6804 { 6805 "chips": ["gfx6"], 6806 "map": {"at": 166656, "to": "mm"}, 6807 "name": "VGT_STRMOUT_BUFFER_SIZE_3" 6808 }, 6809 { 6810 "chips": ["gfx6"], 6811 "map": {"at": 166660, "to": "mm"}, 6812 "name": "VGT_STRMOUT_VTX_STRIDE_3", 6813 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6814 }, 6815 { 6816 "chips": ["gfx6"], 6817 "map": {"at": 166668, "to": "mm"}, 6818 "name": "VGT_STRMOUT_BUFFER_OFFSET_3" 6819 }, 6820 { 6821 "chips": ["gfx6"], 6822 "map": {"at": 166696, "to": "mm"}, 6823 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET" 6824 }, 6825 { 6826 "chips": ["gfx6"], 6827 "map": {"at": 166700, "to": "mm"}, 6828 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE" 6829 }, 6830 { 6831 "chips": ["gfx6"], 6832 "map": {"at": 166704, "to": "mm"}, 6833 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", 6834 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE" 6835 }, 6836 { 6837 "chips": ["gfx6"], 6838 "map": {"at": 166712, "to": "mm"}, 6839 "name": "VGT_GS_MAX_VERT_OUT", 6840 "type_ref": "VGT_GS_MAX_VERT_OUT" 6841 }, 6842 { 6843 "chips": ["gfx6"], 6844 "map": {"at": 166740, "to": "mm"}, 6845 "name": "VGT_SHADER_STAGES_EN", 6846 "type_ref": "VGT_SHADER_STAGES_EN" 6847 }, 6848 { 6849 "chips": ["gfx6"], 6850 "map": {"at": 166744, "to": "mm"}, 6851 "name": "VGT_LS_HS_CONFIG", 6852 "type_ref": "VGT_LS_HS_CONFIG" 6853 }, 6854 { 6855 "chips": ["gfx6"], 6856 "map": {"at": 166748, "to": "mm"}, 6857 "name": "VGT_GS_VERT_ITEMSIZE", 6858 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6859 }, 6860 { 6861 "chips": ["gfx6"], 6862 "map": {"at": 166752, "to": "mm"}, 6863 "name": "VGT_GS_VERT_ITEMSIZE_1", 6864 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6865 }, 6866 { 6867 "chips": ["gfx6"], 6868 "map": {"at": 166756, "to": "mm"}, 6869 "name": "VGT_GS_VERT_ITEMSIZE_2", 6870 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6871 }, 6872 { 6873 "chips": ["gfx6"], 6874 "map": {"at": 166760, "to": "mm"}, 6875 "name": "VGT_GS_VERT_ITEMSIZE_3", 6876 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6877 }, 6878 { 6879 "chips": ["gfx6"], 6880 "map": {"at": 166764, "to": "mm"}, 6881 "name": "VGT_TF_PARAM", 6882 "type_ref": "VGT_TF_PARAM" 6883 }, 6884 { 6885 "chips": ["gfx6"], 6886 "map": {"at": 166768, "to": "mm"}, 6887 "name": "DB_ALPHA_TO_MASK", 6888 "type_ref": "DB_ALPHA_TO_MASK" 6889 }, 6890 { 6891 "chips": ["gfx6"], 6892 "map": {"at": 166776, "to": "mm"}, 6893 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL", 6894 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL" 6895 }, 6896 { 6897 "chips": ["gfx6"], 6898 "map": {"at": 166780, "to": "mm"}, 6899 "name": "PA_SU_POLY_OFFSET_CLAMP" 6900 }, 6901 { 6902 "chips": ["gfx6"], 6903 "map": {"at": 166784, "to": "mm"}, 6904 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE" 6905 }, 6906 { 6907 "chips": ["gfx6"], 6908 "map": {"at": 166788, "to": "mm"}, 6909 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET" 6910 }, 6911 { 6912 "chips": ["gfx6"], 6913 "map": {"at": 166792, "to": "mm"}, 6914 "name": "PA_SU_POLY_OFFSET_BACK_SCALE" 6915 }, 6916 { 6917 "chips": ["gfx6"], 6918 "map": {"at": 166796, "to": "mm"}, 6919 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET" 6920 }, 6921 { 6922 "chips": ["gfx6"], 6923 "map": {"at": 166800, "to": "mm"}, 6924 "name": "VGT_GS_INSTANCE_CNT", 6925 "type_ref": "VGT_GS_INSTANCE_CNT" 6926 }, 6927 { 6928 "chips": ["gfx6"], 6929 "map": {"at": 166804, "to": "mm"}, 6930 "name": "VGT_STRMOUT_CONFIG", 6931 "type_ref": "VGT_STRMOUT_CONFIG" 6932 }, 6933 { 6934 "chips": ["gfx6"], 6935 "map": {"at": 166808, "to": "mm"}, 6936 "name": "VGT_STRMOUT_BUFFER_CONFIG", 6937 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG" 6938 }, 6939 { 6940 "chips": ["gfx6"], 6941 "map": {"at": 166868, "to": "mm"}, 6942 "name": "PA_SC_CENTROID_PRIORITY_0", 6943 "type_ref": "PA_SC_CENTROID_PRIORITY_0" 6944 }, 6945 { 6946 "chips": ["gfx6"], 6947 "map": {"at": 166872, "to": "mm"}, 6948 "name": "PA_SC_CENTROID_PRIORITY_1", 6949 "type_ref": "PA_SC_CENTROID_PRIORITY_1" 6950 }, 6951 { 6952 "chips": ["gfx6"], 6953 "map": {"at": 166876, "to": "mm"}, 6954 "name": "PA_SC_LINE_CNTL", 6955 "type_ref": "PA_SC_LINE_CNTL" 6956 }, 6957 { 6958 "chips": ["gfx6"], 6959 "map": {"at": 166880, "to": "mm"}, 6960 "name": "PA_SC_AA_CONFIG", 6961 "type_ref": "PA_SC_AA_CONFIG" 6962 }, 6963 { 6964 "chips": ["gfx6"], 6965 "map": {"at": 166884, "to": "mm"}, 6966 "name": "PA_SU_VTX_CNTL", 6967 "type_ref": "PA_SU_VTX_CNTL" 6968 }, 6969 { 6970 "chips": ["gfx6"], 6971 "map": {"at": 166888, "to": "mm"}, 6972 "name": "PA_CL_GB_VERT_CLIP_ADJ" 6973 }, 6974 { 6975 "chips": ["gfx6"], 6976 "map": {"at": 166892, "to": "mm"}, 6977 "name": "PA_CL_GB_VERT_DISC_ADJ" 6978 }, 6979 { 6980 "chips": ["gfx6"], 6981 "map": {"at": 166896, "to": "mm"}, 6982 "name": "PA_CL_GB_HORZ_CLIP_ADJ" 6983 }, 6984 { 6985 "chips": ["gfx6"], 6986 "map": {"at": 166900, "to": "mm"}, 6987 "name": "PA_CL_GB_HORZ_DISC_ADJ" 6988 }, 6989 { 6990 "chips": ["gfx6"], 6991 "map": {"at": 166904, "to": "mm"}, 6992 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", 6993 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 6994 }, 6995 { 6996 "chips": ["gfx6"], 6997 "map": {"at": 166908, "to": "mm"}, 6998 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", 6999 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7000 }, 7001 { 7002 "chips": ["gfx6"], 7003 "map": {"at": 166912, "to": "mm"}, 7004 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", 7005 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7006 }, 7007 { 7008 "chips": ["gfx6"], 7009 "map": {"at": 166916, "to": "mm"}, 7010 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", 7011 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7012 }, 7013 { 7014 "chips": ["gfx6"], 7015 "map": {"at": 166920, "to": "mm"}, 7016 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", 7017 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7018 }, 7019 { 7020 "chips": ["gfx6"], 7021 "map": {"at": 166924, "to": "mm"}, 7022 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", 7023 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7024 }, 7025 { 7026 "chips": ["gfx6"], 7027 "map": {"at": 166928, "to": "mm"}, 7028 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", 7029 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7030 }, 7031 { 7032 "chips": ["gfx6"], 7033 "map": {"at": 166932, "to": "mm"}, 7034 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", 7035 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7036 }, 7037 { 7038 "chips": ["gfx6"], 7039 "map": {"at": 166936, "to": "mm"}, 7040 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", 7041 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7042 }, 7043 { 7044 "chips": ["gfx6"], 7045 "map": {"at": 166940, "to": "mm"}, 7046 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", 7047 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7048 }, 7049 { 7050 "chips": ["gfx6"], 7051 "map": {"at": 166944, "to": "mm"}, 7052 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", 7053 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7054 }, 7055 { 7056 "chips": ["gfx6"], 7057 "map": {"at": 166948, "to": "mm"}, 7058 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", 7059 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7060 }, 7061 { 7062 "chips": ["gfx6"], 7063 "map": {"at": 166952, "to": "mm"}, 7064 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", 7065 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7066 }, 7067 { 7068 "chips": ["gfx6"], 7069 "map": {"at": 166956, "to": "mm"}, 7070 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", 7071 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7072 }, 7073 { 7074 "chips": ["gfx6"], 7075 "map": {"at": 166960, "to": "mm"}, 7076 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", 7077 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7078 }, 7079 { 7080 "chips": ["gfx6"], 7081 "map": {"at": 166964, "to": "mm"}, 7082 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", 7083 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7084 }, 7085 { 7086 "chips": ["gfx6"], 7087 "map": {"at": 166968, "to": "mm"}, 7088 "name": "PA_SC_AA_MASK_X0Y0_X1Y0", 7089 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0" 7090 }, 7091 { 7092 "chips": ["gfx6"], 7093 "map": {"at": 166972, "to": "mm"}, 7094 "name": "PA_SC_AA_MASK_X0Y1_X1Y1", 7095 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1" 7096 }, 7097 { 7098 "chips": ["gfx6"], 7099 "map": {"at": 167000, "to": "mm"}, 7100 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL", 7101 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL" 7102 }, 7103 { 7104 "chips": ["gfx6"], 7105 "map": {"at": 167004, "to": "mm"}, 7106 "name": "VGT_OUT_DEALLOC_CNTL", 7107 "type_ref": "VGT_OUT_DEALLOC_CNTL" 7108 }, 7109 { 7110 "chips": ["gfx6"], 7111 "map": {"at": 167008, "to": "mm"}, 7112 "name": "CB_COLOR0_BASE" 7113 }, 7114 { 7115 "chips": ["gfx6"], 7116 "map": {"at": 167012, "to": "mm"}, 7117 "name": "CB_COLOR0_PITCH", 7118 "type_ref": "CB_COLOR0_PITCH" 7119 }, 7120 { 7121 "chips": ["gfx6"], 7122 "map": {"at": 167016, "to": "mm"}, 7123 "name": "CB_COLOR0_SLICE", 7124 "type_ref": "CB_COLOR0_FMASK_SLICE" 7125 }, 7126 { 7127 "chips": ["gfx6"], 7128 "map": {"at": 167020, "to": "mm"}, 7129 "name": "CB_COLOR0_VIEW", 7130 "type_ref": "CB_COLOR0_VIEW" 7131 }, 7132 { 7133 "chips": ["gfx6"], 7134 "map": {"at": 167024, "to": "mm"}, 7135 "name": "CB_COLOR0_INFO", 7136 "type_ref": "CB_COLOR0_INFO" 7137 }, 7138 { 7139 "chips": ["gfx6"], 7140 "map": {"at": 167028, "to": "mm"}, 7141 "name": "CB_COLOR0_ATTRIB", 7142 "type_ref": "CB_COLOR0_ATTRIB" 7143 }, 7144 { 7145 "chips": ["gfx6"], 7146 "map": {"at": 167036, "to": "mm"}, 7147 "name": "CB_COLOR0_CMASK" 7148 }, 7149 { 7150 "chips": ["gfx6"], 7151 "map": {"at": 167040, "to": "mm"}, 7152 "name": "CB_COLOR0_CMASK_SLICE", 7153 "type_ref": "CB_COLOR0_CMASK_SLICE" 7154 }, 7155 { 7156 "chips": ["gfx6"], 7157 "map": {"at": 167044, "to": "mm"}, 7158 "name": "CB_COLOR0_FMASK" 7159 }, 7160 { 7161 "chips": ["gfx6"], 7162 "map": {"at": 167048, "to": "mm"}, 7163 "name": "CB_COLOR0_FMASK_SLICE", 7164 "type_ref": "CB_COLOR0_FMASK_SLICE" 7165 }, 7166 { 7167 "chips": ["gfx6"], 7168 "map": {"at": 167052, "to": "mm"}, 7169 "name": "CB_COLOR0_CLEAR_WORD0" 7170 }, 7171 { 7172 "chips": ["gfx6"], 7173 "map": {"at": 167056, "to": "mm"}, 7174 "name": "CB_COLOR0_CLEAR_WORD1" 7175 }, 7176 { 7177 "chips": ["gfx6"], 7178 "map": {"at": 167068, "to": "mm"}, 7179 "name": "CB_COLOR1_BASE" 7180 }, 7181 { 7182 "chips": ["gfx6"], 7183 "map": {"at": 167072, "to": "mm"}, 7184 "name": "CB_COLOR1_PITCH", 7185 "type_ref": "CB_COLOR0_PITCH" 7186 }, 7187 { 7188 "chips": ["gfx6"], 7189 "map": {"at": 167076, "to": "mm"}, 7190 "name": "CB_COLOR1_SLICE", 7191 "type_ref": "CB_COLOR0_FMASK_SLICE" 7192 }, 7193 { 7194 "chips": ["gfx6"], 7195 "map": {"at": 167080, "to": "mm"}, 7196 "name": "CB_COLOR1_VIEW", 7197 "type_ref": "CB_COLOR0_VIEW" 7198 }, 7199 { 7200 "chips": ["gfx6"], 7201 "map": {"at": 167084, "to": "mm"}, 7202 "name": "CB_COLOR1_INFO", 7203 "type_ref": "CB_COLOR0_INFO" 7204 }, 7205 { 7206 "chips": ["gfx6"], 7207 "map": {"at": 167088, "to": "mm"}, 7208 "name": "CB_COLOR1_ATTRIB", 7209 "type_ref": "CB_COLOR0_ATTRIB" 7210 }, 7211 { 7212 "chips": ["gfx6"], 7213 "map": {"at": 167096, "to": "mm"}, 7214 "name": "CB_COLOR1_CMASK" 7215 }, 7216 { 7217 "chips": ["gfx6"], 7218 "map": {"at": 167100, "to": "mm"}, 7219 "name": "CB_COLOR1_CMASK_SLICE", 7220 "type_ref": "CB_COLOR0_CMASK_SLICE" 7221 }, 7222 { 7223 "chips": ["gfx6"], 7224 "map": {"at": 167104, "to": "mm"}, 7225 "name": "CB_COLOR1_FMASK" 7226 }, 7227 { 7228 "chips": ["gfx6"], 7229 "map": {"at": 167108, "to": "mm"}, 7230 "name": "CB_COLOR1_FMASK_SLICE", 7231 "type_ref": "CB_COLOR0_FMASK_SLICE" 7232 }, 7233 { 7234 "chips": ["gfx6"], 7235 "map": {"at": 167112, "to": "mm"}, 7236 "name": "CB_COLOR1_CLEAR_WORD0" 7237 }, 7238 { 7239 "chips": ["gfx6"], 7240 "map": {"at": 167116, "to": "mm"}, 7241 "name": "CB_COLOR1_CLEAR_WORD1" 7242 }, 7243 { 7244 "chips": ["gfx6"], 7245 "map": {"at": 167128, "to": "mm"}, 7246 "name": "CB_COLOR2_BASE" 7247 }, 7248 { 7249 "chips": ["gfx6"], 7250 "map": {"at": 167132, "to": "mm"}, 7251 "name": "CB_COLOR2_PITCH", 7252 "type_ref": "CB_COLOR0_PITCH" 7253 }, 7254 { 7255 "chips": ["gfx6"], 7256 "map": {"at": 167136, "to": "mm"}, 7257 "name": "CB_COLOR2_SLICE", 7258 "type_ref": "CB_COLOR0_FMASK_SLICE" 7259 }, 7260 { 7261 "chips": ["gfx6"], 7262 "map": {"at": 167140, "to": "mm"}, 7263 "name": "CB_COLOR2_VIEW", 7264 "type_ref": "CB_COLOR0_VIEW" 7265 }, 7266 { 7267 "chips": ["gfx6"], 7268 "map": {"at": 167144, "to": "mm"}, 7269 "name": "CB_COLOR2_INFO", 7270 "type_ref": "CB_COLOR0_INFO" 7271 }, 7272 { 7273 "chips": ["gfx6"], 7274 "map": {"at": 167148, "to": "mm"}, 7275 "name": "CB_COLOR2_ATTRIB", 7276 "type_ref": "CB_COLOR0_ATTRIB" 7277 }, 7278 { 7279 "chips": ["gfx6"], 7280 "map": {"at": 167156, "to": "mm"}, 7281 "name": "CB_COLOR2_CMASK" 7282 }, 7283 { 7284 "chips": ["gfx6"], 7285 "map": {"at": 167160, "to": "mm"}, 7286 "name": "CB_COLOR2_CMASK_SLICE", 7287 "type_ref": "CB_COLOR0_CMASK_SLICE" 7288 }, 7289 { 7290 "chips": ["gfx6"], 7291 "map": {"at": 167164, "to": "mm"}, 7292 "name": "CB_COLOR2_FMASK" 7293 }, 7294 { 7295 "chips": ["gfx6"], 7296 "map": {"at": 167168, "to": "mm"}, 7297 "name": "CB_COLOR2_FMASK_SLICE", 7298 "type_ref": "CB_COLOR0_FMASK_SLICE" 7299 }, 7300 { 7301 "chips": ["gfx6"], 7302 "map": {"at": 167172, "to": "mm"}, 7303 "name": "CB_COLOR2_CLEAR_WORD0" 7304 }, 7305 { 7306 "chips": ["gfx6"], 7307 "map": {"at": 167176, "to": "mm"}, 7308 "name": "CB_COLOR2_CLEAR_WORD1" 7309 }, 7310 { 7311 "chips": ["gfx6"], 7312 "map": {"at": 167188, "to": "mm"}, 7313 "name": "CB_COLOR3_BASE" 7314 }, 7315 { 7316 "chips": ["gfx6"], 7317 "map": {"at": 167192, "to": "mm"}, 7318 "name": "CB_COLOR3_PITCH", 7319 "type_ref": "CB_COLOR0_PITCH" 7320 }, 7321 { 7322 "chips": ["gfx6"], 7323 "map": {"at": 167196, "to": "mm"}, 7324 "name": "CB_COLOR3_SLICE", 7325 "type_ref": "CB_COLOR0_FMASK_SLICE" 7326 }, 7327 { 7328 "chips": ["gfx6"], 7329 "map": {"at": 167200, "to": "mm"}, 7330 "name": "CB_COLOR3_VIEW", 7331 "type_ref": "CB_COLOR0_VIEW" 7332 }, 7333 { 7334 "chips": ["gfx6"], 7335 "map": {"at": 167204, "to": "mm"}, 7336 "name": "CB_COLOR3_INFO", 7337 "type_ref": "CB_COLOR0_INFO" 7338 }, 7339 { 7340 "chips": ["gfx6"], 7341 "map": {"at": 167208, "to": "mm"}, 7342 "name": "CB_COLOR3_ATTRIB", 7343 "type_ref": "CB_COLOR0_ATTRIB" 7344 }, 7345 { 7346 "chips": ["gfx6"], 7347 "map": {"at": 167216, "to": "mm"}, 7348 "name": "CB_COLOR3_CMASK" 7349 }, 7350 { 7351 "chips": ["gfx6"], 7352 "map": {"at": 167220, "to": "mm"}, 7353 "name": "CB_COLOR3_CMASK_SLICE", 7354 "type_ref": "CB_COLOR0_CMASK_SLICE" 7355 }, 7356 { 7357 "chips": ["gfx6"], 7358 "map": {"at": 167224, "to": "mm"}, 7359 "name": "CB_COLOR3_FMASK" 7360 }, 7361 { 7362 "chips": ["gfx6"], 7363 "map": {"at": 167228, "to": "mm"}, 7364 "name": "CB_COLOR3_FMASK_SLICE", 7365 "type_ref": "CB_COLOR0_FMASK_SLICE" 7366 }, 7367 { 7368 "chips": ["gfx6"], 7369 "map": {"at": 167232, "to": "mm"}, 7370 "name": "CB_COLOR3_CLEAR_WORD0" 7371 }, 7372 { 7373 "chips": ["gfx6"], 7374 "map": {"at": 167236, "to": "mm"}, 7375 "name": "CB_COLOR3_CLEAR_WORD1" 7376 }, 7377 { 7378 "chips": ["gfx6"], 7379 "map": {"at": 167248, "to": "mm"}, 7380 "name": "CB_COLOR4_BASE" 7381 }, 7382 { 7383 "chips": ["gfx6"], 7384 "map": {"at": 167252, "to": "mm"}, 7385 "name": "CB_COLOR4_PITCH", 7386 "type_ref": "CB_COLOR0_PITCH" 7387 }, 7388 { 7389 "chips": ["gfx6"], 7390 "map": {"at": 167256, "to": "mm"}, 7391 "name": "CB_COLOR4_SLICE", 7392 "type_ref": "CB_COLOR0_FMASK_SLICE" 7393 }, 7394 { 7395 "chips": ["gfx6"], 7396 "map": {"at": 167260, "to": "mm"}, 7397 "name": "CB_COLOR4_VIEW", 7398 "type_ref": "CB_COLOR0_VIEW" 7399 }, 7400 { 7401 "chips": ["gfx6"], 7402 "map": {"at": 167264, "to": "mm"}, 7403 "name": "CB_COLOR4_INFO", 7404 "type_ref": "CB_COLOR0_INFO" 7405 }, 7406 { 7407 "chips": ["gfx6"], 7408 "map": {"at": 167268, "to": "mm"}, 7409 "name": "CB_COLOR4_ATTRIB", 7410 "type_ref": "CB_COLOR0_ATTRIB" 7411 }, 7412 { 7413 "chips": ["gfx6"], 7414 "map": {"at": 167276, "to": "mm"}, 7415 "name": "CB_COLOR4_CMASK" 7416 }, 7417 { 7418 "chips": ["gfx6"], 7419 "map": {"at": 167280, "to": "mm"}, 7420 "name": "CB_COLOR4_CMASK_SLICE", 7421 "type_ref": "CB_COLOR0_CMASK_SLICE" 7422 }, 7423 { 7424 "chips": ["gfx6"], 7425 "map": {"at": 167284, "to": "mm"}, 7426 "name": "CB_COLOR4_FMASK" 7427 }, 7428 { 7429 "chips": ["gfx6"], 7430 "map": {"at": 167288, "to": "mm"}, 7431 "name": "CB_COLOR4_FMASK_SLICE", 7432 "type_ref": "CB_COLOR0_FMASK_SLICE" 7433 }, 7434 { 7435 "chips": ["gfx6"], 7436 "map": {"at": 167292, "to": "mm"}, 7437 "name": "CB_COLOR4_CLEAR_WORD0" 7438 }, 7439 { 7440 "chips": ["gfx6"], 7441 "map": {"at": 167296, "to": "mm"}, 7442 "name": "CB_COLOR4_CLEAR_WORD1" 7443 }, 7444 { 7445 "chips": ["gfx6"], 7446 "map": {"at": 167308, "to": "mm"}, 7447 "name": "CB_COLOR5_BASE" 7448 }, 7449 { 7450 "chips": ["gfx6"], 7451 "map": {"at": 167312, "to": "mm"}, 7452 "name": "CB_COLOR5_PITCH", 7453 "type_ref": "CB_COLOR0_PITCH" 7454 }, 7455 { 7456 "chips": ["gfx6"], 7457 "map": {"at": 167316, "to": "mm"}, 7458 "name": "CB_COLOR5_SLICE", 7459 "type_ref": "CB_COLOR0_FMASK_SLICE" 7460 }, 7461 { 7462 "chips": ["gfx6"], 7463 "map": {"at": 167320, "to": "mm"}, 7464 "name": "CB_COLOR5_VIEW", 7465 "type_ref": "CB_COLOR0_VIEW" 7466 }, 7467 { 7468 "chips": ["gfx6"], 7469 "map": {"at": 167324, "to": "mm"}, 7470 "name": "CB_COLOR5_INFO", 7471 "type_ref": "CB_COLOR0_INFO" 7472 }, 7473 { 7474 "chips": ["gfx6"], 7475 "map": {"at": 167328, "to": "mm"}, 7476 "name": "CB_COLOR5_ATTRIB", 7477 "type_ref": "CB_COLOR0_ATTRIB" 7478 }, 7479 { 7480 "chips": ["gfx6"], 7481 "map": {"at": 167336, "to": "mm"}, 7482 "name": "CB_COLOR5_CMASK" 7483 }, 7484 { 7485 "chips": ["gfx6"], 7486 "map": {"at": 167340, "to": "mm"}, 7487 "name": "CB_COLOR5_CMASK_SLICE", 7488 "type_ref": "CB_COLOR0_CMASK_SLICE" 7489 }, 7490 { 7491 "chips": ["gfx6"], 7492 "map": {"at": 167344, "to": "mm"}, 7493 "name": "CB_COLOR5_FMASK" 7494 }, 7495 { 7496 "chips": ["gfx6"], 7497 "map": {"at": 167348, "to": "mm"}, 7498 "name": "CB_COLOR5_FMASK_SLICE", 7499 "type_ref": "CB_COLOR0_FMASK_SLICE" 7500 }, 7501 { 7502 "chips": ["gfx6"], 7503 "map": {"at": 167352, "to": "mm"}, 7504 "name": "CB_COLOR5_CLEAR_WORD0" 7505 }, 7506 { 7507 "chips": ["gfx6"], 7508 "map": {"at": 167356, "to": "mm"}, 7509 "name": "CB_COLOR5_CLEAR_WORD1" 7510 }, 7511 { 7512 "chips": ["gfx6"], 7513 "map": {"at": 167368, "to": "mm"}, 7514 "name": "CB_COLOR6_BASE" 7515 }, 7516 { 7517 "chips": ["gfx6"], 7518 "map": {"at": 167372, "to": "mm"}, 7519 "name": "CB_COLOR6_PITCH", 7520 "type_ref": "CB_COLOR0_PITCH" 7521 }, 7522 { 7523 "chips": ["gfx6"], 7524 "map": {"at": 167376, "to": "mm"}, 7525 "name": "CB_COLOR6_SLICE", 7526 "type_ref": "CB_COLOR0_FMASK_SLICE" 7527 }, 7528 { 7529 "chips": ["gfx6"], 7530 "map": {"at": 167380, "to": "mm"}, 7531 "name": "CB_COLOR6_VIEW", 7532 "type_ref": "CB_COLOR0_VIEW" 7533 }, 7534 { 7535 "chips": ["gfx6"], 7536 "map": {"at": 167384, "to": "mm"}, 7537 "name": "CB_COLOR6_INFO", 7538 "type_ref": "CB_COLOR0_INFO" 7539 }, 7540 { 7541 "chips": ["gfx6"], 7542 "map": {"at": 167388, "to": "mm"}, 7543 "name": "CB_COLOR6_ATTRIB", 7544 "type_ref": "CB_COLOR0_ATTRIB" 7545 }, 7546 { 7547 "chips": ["gfx6"], 7548 "map": {"at": 167396, "to": "mm"}, 7549 "name": "CB_COLOR6_CMASK" 7550 }, 7551 { 7552 "chips": ["gfx6"], 7553 "map": {"at": 167400, "to": "mm"}, 7554 "name": "CB_COLOR6_CMASK_SLICE", 7555 "type_ref": "CB_COLOR0_CMASK_SLICE" 7556 }, 7557 { 7558 "chips": ["gfx6"], 7559 "map": {"at": 167404, "to": "mm"}, 7560 "name": "CB_COLOR6_FMASK" 7561 }, 7562 { 7563 "chips": ["gfx6"], 7564 "map": {"at": 167408, "to": "mm"}, 7565 "name": "CB_COLOR6_FMASK_SLICE", 7566 "type_ref": "CB_COLOR0_FMASK_SLICE" 7567 }, 7568 { 7569 "chips": ["gfx6"], 7570 "map": {"at": 167412, "to": "mm"}, 7571 "name": "CB_COLOR6_CLEAR_WORD0" 7572 }, 7573 { 7574 "chips": ["gfx6"], 7575 "map": {"at": 167416, "to": "mm"}, 7576 "name": "CB_COLOR6_CLEAR_WORD1" 7577 }, 7578 { 7579 "chips": ["gfx6"], 7580 "map": {"at": 167428, "to": "mm"}, 7581 "name": "CB_COLOR7_BASE" 7582 }, 7583 { 7584 "chips": ["gfx6"], 7585 "map": {"at": 167432, "to": "mm"}, 7586 "name": "CB_COLOR7_PITCH", 7587 "type_ref": "CB_COLOR0_PITCH" 7588 }, 7589 { 7590 "chips": ["gfx6"], 7591 "map": {"at": 167436, "to": "mm"}, 7592 "name": "CB_COLOR7_SLICE", 7593 "type_ref": "CB_COLOR0_FMASK_SLICE" 7594 }, 7595 { 7596 "chips": ["gfx6"], 7597 "map": {"at": 167440, "to": "mm"}, 7598 "name": "CB_COLOR7_VIEW", 7599 "type_ref": "CB_COLOR0_VIEW" 7600 }, 7601 { 7602 "chips": ["gfx6"], 7603 "map": {"at": 167444, "to": "mm"}, 7604 "name": "CB_COLOR7_INFO", 7605 "type_ref": "CB_COLOR0_INFO" 7606 }, 7607 { 7608 "chips": ["gfx6"], 7609 "map": {"at": 167448, "to": "mm"}, 7610 "name": "CB_COLOR7_ATTRIB", 7611 "type_ref": "CB_COLOR0_ATTRIB" 7612 }, 7613 { 7614 "chips": ["gfx6"], 7615 "map": {"at": 167456, "to": "mm"}, 7616 "name": "CB_COLOR7_CMASK" 7617 }, 7618 { 7619 "chips": ["gfx6"], 7620 "map": {"at": 167460, "to": "mm"}, 7621 "name": "CB_COLOR7_CMASK_SLICE", 7622 "type_ref": "CB_COLOR0_CMASK_SLICE" 7623 }, 7624 { 7625 "chips": ["gfx6"], 7626 "map": {"at": 167464, "to": "mm"}, 7627 "name": "CB_COLOR7_FMASK" 7628 }, 7629 { 7630 "chips": ["gfx6"], 7631 "map": {"at": 167468, "to": "mm"}, 7632 "name": "CB_COLOR7_FMASK_SLICE", 7633 "type_ref": "CB_COLOR0_FMASK_SLICE" 7634 }, 7635 { 7636 "chips": ["gfx6"], 7637 "map": {"at": 167472, "to": "mm"}, 7638 "name": "CB_COLOR7_CLEAR_WORD0" 7639 }, 7640 { 7641 "chips": ["gfx6"], 7642 "map": {"at": 167476, "to": "mm"}, 7643 "name": "CB_COLOR7_CLEAR_WORD1" 7644 } 7645 ], 7646 "register_types": { 7647 "CB_BLEND0_CONTROL": { 7648 "fields": [ 7649 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, 7650 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, 7651 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, 7652 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, 7653 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, 7654 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, 7655 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, 7656 {"bits": [30, 30], "name": "ENABLE"}, 7657 {"bits": [31, 31], "name": "DISABLE_ROP3"} 7658 ] 7659 }, 7660 "CB_COLOR0_ATTRIB": { 7661 "fields": [ 7662 {"bits": [0, 4], "name": "TILE_MODE_INDEX"}, 7663 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, 7664 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, 7665 {"bits": [12, 14], "name": "NUM_SAMPLES"}, 7666 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, 7667 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"} 7668 ] 7669 }, 7670 "CB_COLOR0_CMASK_SLICE": { 7671 "fields": [ 7672 {"bits": [0, 13], "name": "TILE_MAX"} 7673 ] 7674 }, 7675 "CB_COLOR0_FMASK_SLICE": { 7676 "fields": [ 7677 {"bits": [0, 21], "name": "TILE_MAX"} 7678 ] 7679 }, 7680 "CB_COLOR0_INFO": { 7681 "fields": [ 7682 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, 7683 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, 7684 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, 7685 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, 7686 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, 7687 {"bits": [13, 13], "name": "FAST_CLEAR"}, 7688 {"bits": [14, 14], "name": "COMPRESSION"}, 7689 {"bits": [15, 15], "name": "BLEND_CLAMP"}, 7690 {"bits": [16, 16], "name": "BLEND_BYPASS"}, 7691 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, 7692 {"bits": [18, 18], "name": "ROUND_MODE"}, 7693 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, 7694 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, 7695 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, 7696 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"} 7697 ] 7698 }, 7699 "CB_COLOR0_PITCH": { 7700 "fields": [ 7701 {"bits": [0, 10], "name": "TILE_MAX"}, 7702 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} 7703 ] 7704 }, 7705 "CB_COLOR0_VIEW": { 7706 "fields": [ 7707 {"bits": [0, 10], "name": "SLICE_START"}, 7708 {"bits": [13, 23], "name": "SLICE_MAX"} 7709 ] 7710 }, 7711 "CB_COLOR_CONTROL": { 7712 "fields": [ 7713 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, 7714 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, 7715 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} 7716 ] 7717 }, 7718 "CB_SHADER_MASK": { 7719 "fields": [ 7720 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, 7721 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, 7722 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, 7723 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, 7724 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, 7725 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, 7726 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, 7727 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} 7728 ] 7729 }, 7730 "CB_TARGET_MASK": { 7731 "fields": [ 7732 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, 7733 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, 7734 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, 7735 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, 7736 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, 7737 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, 7738 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, 7739 {"bits": [28, 31], "name": "TARGET7_ENABLE"} 7740 ] 7741 }, 7742 "CC_GC_SHADER_ARRAY_CONFIG": { 7743 "fields": [ 7744 {"bits": [1, 2], "name": "DPFP_RATE"}, 7745 {"bits": [3, 3], "name": "SQC_BALANCE_DISABLE"}, 7746 {"bits": [4, 4], "name": "HALF_LDS"}, 7747 {"bits": [16, 31], "name": "INACTIVE_CUS"} 7748 ] 7749 }, 7750 "CC_SQC_BANK_DISABLE": { 7751 "fields": [ 7752 {"bits": [16, 19], "name": "SQC0_BANK_DISABLE"}, 7753 {"bits": [20, 23], "name": "SQC1_BANK_DISABLE"}, 7754 {"bits": [24, 27], "name": "SQC2_BANK_DISABLE"}, 7755 {"bits": [28, 31], "name": "SQC3_BANK_DISABLE"} 7756 ] 7757 }, 7758 "CGTT_IA_CLK_CTRL": { 7759 "fields": [ 7760 {"bits": [0, 3], "name": "ON_DELAY"}, 7761 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7762 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7763 {"bits": [25, 25], "name": "PERF_ENABLE"}, 7764 {"bits": [26, 26], "name": "DBG_ENABLE"}, 7765 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7766 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7767 {"bits": [29, 29], "name": "CORE_OVERRIDE"}, 7768 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, 7769 {"bits": [31, 31], "name": "REG_OVERRIDE"} 7770 ] 7771 }, 7772 "CGTT_PA_CLK_CTRL": { 7773 "fields": [ 7774 {"bits": [0, 3], "name": "ON_DELAY"}, 7775 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7776 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7777 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, 7778 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, 7779 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7780 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7781 {"bits": [29, 29], "name": "SU_CLK_OVERRIDE"}, 7782 {"bits": [30, 30], "name": "CL_CLK_OVERRIDE"}, 7783 {"bits": [31, 31], "name": "REG_CLK_OVERRIDE"} 7784 ] 7785 }, 7786 "CGTT_SC_CLK_CTRL": { 7787 "fields": [ 7788 {"bits": [0, 3], "name": "ON_DELAY"}, 7789 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7790 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7791 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, 7792 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, 7793 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7794 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7795 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, 7796 {"bits": [30, 30], "name": "SOFT_OVERRIDE1"}, 7797 {"bits": [31, 31], "name": "SOFT_OVERRIDE0"} 7798 ] 7799 }, 7800 "CGTT_SQ_CLK_CTRL": { 7801 "fields": [ 7802 {"bits": [0, 3], "name": "ON_DELAY"}, 7803 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7804 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, 7805 {"bits": [31, 31], "name": "REG_OVERRIDE"} 7806 ] 7807 }, 7808 "CGTT_VGT_CLK_CTRL": { 7809 "fields": [ 7810 {"bits": [0, 3], "name": "ON_DELAY"}, 7811 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7812 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7813 {"bits": [25, 25], "name": "PERF_ENABLE"}, 7814 {"bits": [26, 26], "name": "DBG_ENABLE"}, 7815 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7816 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7817 {"bits": [29, 29], "name": "GS_OVERRIDE"}, 7818 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, 7819 {"bits": [31, 31], "name": "REG_OVERRIDE"} 7820 ] 7821 }, 7822 "COMPUTE_DISPATCH_INITIATOR": { 7823 "fields": [ 7824 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, 7825 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, 7826 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, 7827 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, 7828 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, 7829 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, 7830 {"bits": [6, 6], "name": "ORDER_MODE"}, 7831 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"}, 7832 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, 7833 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, 7834 {"bits": [12, 12], "name": "DATA_ATC"}, 7835 {"bits": [14, 14], "name": "RESTORE"} 7836 ] 7837 }, 7838 "COMPUTE_NUM_THREAD_X": { 7839 "fields": [ 7840 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, 7841 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} 7842 ] 7843 }, 7844 "COMPUTE_PGM_HI": { 7845 "fields": [ 7846 {"bits": [0, 7], "name": "DATA"}, 7847 {"bits": [8, 8], "name": "INST_ATC"} 7848 ] 7849 }, 7850 "COMPUTE_PGM_RSRC1": { 7851 "fields": [ 7852 {"bits": [0, 5], "name": "VGPRS"}, 7853 {"bits": [6, 9], "name": "SGPRS"}, 7854 {"bits": [10, 11], "name": "PRIORITY"}, 7855 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 7856 {"bits": [20, 20], "name": "PRIV"}, 7857 {"bits": [21, 21], "name": "DX10_CLAMP"}, 7858 {"bits": [22, 22], "name": "DEBUG_MODE"}, 7859 {"bits": [23, 23], "name": "IEEE_MODE"}, 7860 {"bits": [24, 24], "name": "BULKY"}, 7861 {"bits": [25, 25], "name": "CDBG_USER"} 7862 ] 7863 }, 7864 "COMPUTE_PGM_RSRC2": { 7865 "fields": [ 7866 {"bits": [0, 0], "name": "SCRATCH_EN"}, 7867 {"bits": [1, 5], "name": "USER_SGPR"}, 7868 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 7869 {"bits": [7, 7], "name": "TGID_X_EN"}, 7870 {"bits": [8, 8], "name": "TGID_Y_EN"}, 7871 {"bits": [9, 9], "name": "TGID_Z_EN"}, 7872 {"bits": [10, 10], "name": "TG_SIZE_EN"}, 7873 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, 7874 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, 7875 {"bits": [15, 23], "name": "LDS_SIZE"}, 7876 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 7877 ] 7878 }, 7879 "COMPUTE_RESOURCE_LIMITS": { 7880 "fields": [ 7881 {"bits": [0, 5], "name": "WAVES_PER_SH"}, 7882 {"bits": [0, 5], "name": "WAVES_PER_SH_GFX6"}, 7883 {"bits": [12, 15], "name": "TG_PER_CU"}, 7884 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, 7885 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, 7886 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, 7887 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} 7888 ] 7889 }, 7890 "COMPUTE_STATIC_THREAD_MGMT_SE0": { 7891 "fields": [ 7892 {"bits": [0, 15], "name": "SH0_CU_EN"}, 7893 {"bits": [16, 31], "name": "SH1_CU_EN"} 7894 ] 7895 }, 7896 "COMPUTE_TBA_HI": { 7897 "fields": [ 7898 {"bits": [0, 7], "name": "DATA"} 7899 ] 7900 }, 7901 "COMPUTE_TMPRING_SIZE": { 7902 "fields": [ 7903 {"bits": [0, 11], "name": "WAVES"}, 7904 {"bits": [12, 24], "name": "WAVESIZE"} 7905 ] 7906 }, 7907 "COMPUTE_VMID": { 7908 "fields": [ 7909 {"bits": [0, 3], "name": "DATA"} 7910 ] 7911 }, 7912 "CP_APPEND_ADDR_HI": { 7913 "fields": [ 7914 {"bits": [0, 7], "name": "MEM_ADDR_HI"}, 7915 {"bits": [16, 17], "name": "CS_PS_SEL"}, 7916 {"bits": [29, 31], "name": "COMMAND"} 7917 ] 7918 }, 7919 "CP_APPEND_ADDR_LO": { 7920 "fields": [ 7921 {"bits": [2, 31], "name": "MEM_ADDR_LO"} 7922 ] 7923 }, 7924 "CP_BUSY_STAT": { 7925 "fields": [ 7926 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, 7927 {"bits": [6, 6], "name": "COHER_CNT_NEQ_ZERO"}, 7928 {"bits": [7, 7], "name": "PFP_PARSING_PACKETS"}, 7929 {"bits": [8, 8], "name": "ME_PARSING_PACKETS"}, 7930 {"bits": [9, 9], "name": "RCIU_PFP_BUSY"}, 7931 {"bits": [10, 10], "name": "RCIU_ME_BUSY"}, 7932 {"bits": [12, 12], "name": "SEM_CMDFIFO_NOT_EMPTY"}, 7933 {"bits": [13, 13], "name": "SEM_FAILED_AND_HOLDING"}, 7934 {"bits": [14, 14], "name": "SEM_POLLING_FOR_PASS"}, 7935 {"bits": [15, 15], "name": "GFX_CONTEXT_BUSY"}, 7936 {"bits": [17, 17], "name": "ME_PARSER_BUSY"}, 7937 {"bits": [18, 18], "name": "EOP_DONE_BUSY"}, 7938 {"bits": [19, 19], "name": "STRM_OUT_BUSY"}, 7939 {"bits": [20, 20], "name": "PIPE_STATS_BUSY"}, 7940 {"bits": [21, 21], "name": "RCIU_CE_BUSY"}, 7941 {"bits": [22, 22], "name": "CE_PARSING_PACKETS"} 7942 ] 7943 }, 7944 "CP_CEQ1_AVAIL": { 7945 "fields": [ 7946 {"bits": [0, 10], "name": "CEQ_CNT_RING"}, 7947 {"bits": [16, 26], "name": "CEQ_CNT_IB1"} 7948 ] 7949 }, 7950 "CP_CEQ2_AVAIL": { 7951 "fields": [ 7952 {"bits": [0, 10], "name": "CEQ_CNT_IB2"} 7953 ] 7954 }, 7955 "CP_CE_IB1_BASE_HI": { 7956 "fields": [ 7957 {"bits": [0, 7], "name": "IB1_BASE_HI"} 7958 ] 7959 }, 7960 "CP_CE_IB1_BASE_LO": { 7961 "fields": [ 7962 {"bits": [2, 31], "name": "IB1_BASE_LO"} 7963 ] 7964 }, 7965 "CP_CE_IB1_BUFSZ": { 7966 "fields": [ 7967 {"bits": [0, 19], "name": "IB1_BUFSZ"} 7968 ] 7969 }, 7970 "CP_CE_IB2_BASE_HI": { 7971 "fields": [ 7972 {"bits": [0, 7], "name": "IB2_BASE_HI"} 7973 ] 7974 }, 7975 "CP_CE_IB2_BASE_LO": { 7976 "fields": [ 7977 {"bits": [2, 31], "name": "IB2_BASE_LO"} 7978 ] 7979 }, 7980 "CP_CE_IB2_BUFSZ": { 7981 "fields": [ 7982 {"bits": [0, 19], "name": "IB2_BUFSZ"} 7983 ] 7984 }, 7985 "CP_CE_INIT_BASE_HI": { 7986 "fields": [ 7987 {"bits": [0, 7], "name": "INIT_BASE_HI"} 7988 ] 7989 }, 7990 "CP_CE_INIT_BASE_LO": { 7991 "fields": [ 7992 {"bits": [5, 31], "name": "INIT_BASE_LO"} 7993 ] 7994 }, 7995 "CP_CE_INIT_BUFSZ": { 7996 "fields": [ 7997 {"bits": [0, 11], "name": "INIT_BUFSZ"} 7998 ] 7999 }, 8000 "CP_CE_ROQ_IB1_STAT": { 8001 "fields": [ 8002 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT1"}, 8003 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT1"} 8004 ] 8005 }, 8006 "CP_CE_ROQ_IB2_STAT": { 8007 "fields": [ 8008 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT2"}, 8009 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT2"} 8010 ] 8011 }, 8012 "CP_CE_ROQ_RB_STAT": { 8013 "fields": [ 8014 {"bits": [0, 9], "name": "CEQ_RPTR_PRIMARY"}, 8015 {"bits": [16, 25], "name": "CEQ_WPTR_PRIMARY"} 8016 ] 8017 }, 8018 "CP_CMD_INDEX": { 8019 "fields": [ 8020 {"bits": [0, 10], "name": "CMD_INDEX"}, 8021 {"bits": [12, 13], "name": "CMD_ME_SEL"}, 8022 {"bits": [16, 17], "name": "CMD_QUEUE_SEL"} 8023 ] 8024 }, 8025 "CP_CNTX_STAT": { 8026 "fields": [ 8027 {"bits": [0, 7], "name": "ACTIVE_HP3D_CONTEXTS"}, 8028 {"bits": [8, 10], "name": "CURRENT_HP3D_CONTEXT"}, 8029 {"bits": [20, 27], "name": "ACTIVE_GFX_CONTEXTS"}, 8030 {"bits": [28, 30], "name": "CURRENT_GFX_CONTEXT"} 8031 ] 8032 }, 8033 "CP_COHER_CNTL": { 8034 "fields": [ 8035 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, 8036 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, 8037 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, 8038 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, 8039 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, 8040 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, 8041 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, 8042 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, 8043 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, 8044 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, 8045 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, 8046 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, 8047 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"}, 8048 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, 8049 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, 8050 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}, 8051 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, 8052 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, 8053 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, 8054 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, 8055 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, 8056 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, 8057 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"} 8058 ] 8059 }, 8060 "CP_COHER_START_DELAY": { 8061 "fields": [ 8062 {"bits": [0, 5], "name": "START_DELAY_COUNT"} 8063 ] 8064 }, 8065 "CP_COHER_STATUS": { 8066 "fields": [ 8067 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, 8068 {"bits": [24, 25], "name": "MEID"}, 8069 {"bits": [30, 30], "name": "PHASE1_STATUS"}, 8070 {"bits": [31, 31], "name": "STATUS"} 8071 ] 8072 }, 8073 "CP_CSF_CNTL": { 8074 "fields": [ 8075 {"bits": [0, 3], "name": "FETCH_BUFFER_DEPTH"} 8076 ] 8077 }, 8078 "CP_CSF_STAT": { 8079 "fields": [ 8080 {"bits": [0, 3], "name": "BUFFER_SLOTS_ALLOCATED"}, 8081 {"bits": [8, 13], "name": "BUFFER_REQUEST_COUNT"} 8082 ] 8083 }, 8084 "CP_DMA_CNTL": { 8085 "fields": [ 8086 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, 8087 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, 8088 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, 8089 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, 8090 {"bits": [30, 31], "name": "PIO_COUNT"} 8091 ] 8092 }, 8093 "CP_DMA_ME_COMMAND": { 8094 "fields": [ 8095 {"bits": [0, 20], "name": "BYTE_COUNT"}, 8096 {"bits": [21, 21], "name": "DIS_WC"}, 8097 {"bits": [22, 23], "name": "SRC_SWAP"}, 8098 {"bits": [24, 25], "name": "DST_SWAP"}, 8099 {"bits": [26, 26], "name": "SAS"}, 8100 {"bits": [27, 27], "name": "DAS"}, 8101 {"bits": [28, 28], "name": "SAIC"}, 8102 {"bits": [29, 29], "name": "DAIC"}, 8103 {"bits": [30, 30], "name": "RAW_WAIT"} 8104 ] 8105 }, 8106 "CP_DMA_ME_DST_ADDR_HI": { 8107 "fields": [ 8108 {"bits": [0, 7], "name": "DST_ADDR_HI"} 8109 ] 8110 }, 8111 "CP_DMA_ME_SRC_ADDR_HI": { 8112 "fields": [ 8113 {"bits": [0, 7], "name": "SRC_ADDR_HI"} 8114 ] 8115 }, 8116 "CP_DMA_READ_TAGS": { 8117 "fields": [ 8118 {"bits": [0, 25], "name": "DMA_READ_TAG"}, 8119 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} 8120 ] 8121 }, 8122 "CP_EOP_DONE_ADDR_HI": { 8123 "fields": [ 8124 {"bits": [0, 15], "name": "ADDR_HI"} 8125 ] 8126 }, 8127 "CP_EOP_DONE_ADDR_LO": { 8128 "fields": [ 8129 {"bits": [0, 1], "name": "ADDR_SWAP"}, 8130 {"bits": [2, 31], "name": "ADDR_LO"} 8131 ] 8132 }, 8133 "CP_GRBM_FREE_COUNT": { 8134 "fields": [ 8135 {"bits": [0, 5], "name": "FREE_COUNT"}, 8136 {"bits": [8, 13], "name": "FREE_COUNT_GDS"}, 8137 {"bits": [16, 21], "name": "FREE_COUNT_PFP"} 8138 ] 8139 }, 8140 "CP_IB1_OFFSET": { 8141 "fields": [ 8142 {"bits": [0, 19], "name": "IB1_OFFSET"} 8143 ] 8144 }, 8145 "CP_IB1_PREAMBLE_BEGIN": { 8146 "fields": [ 8147 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} 8148 ] 8149 }, 8150 "CP_IB1_PREAMBLE_END": { 8151 "fields": [ 8152 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} 8153 ] 8154 }, 8155 "CP_IB2_OFFSET": { 8156 "fields": [ 8157 {"bits": [0, 19], "name": "IB2_OFFSET"} 8158 ] 8159 }, 8160 "CP_IB2_PREAMBLE_BEGIN": { 8161 "fields": [ 8162 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} 8163 ] 8164 }, 8165 "CP_IB2_PREAMBLE_END": { 8166 "fields": [ 8167 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} 8168 ] 8169 }, 8170 "CP_INT_STAT_DEBUG": { 8171 "fields": [ 8172 {"bits": [14, 14], "name": "CP_ECC_ERROR_INT_ASSERTED"}, 8173 {"bits": [17, 17], "name": "WRM_POLL_TIMEOUT_INT_ASSERTED"}, 8174 {"bits": [19, 19], "name": "CNTX_BUSY_INT_ASSERTED"}, 8175 {"bits": [20, 20], "name": "CNTX_EMPTY_INT_ASSERTED"}, 8176 {"bits": [22, 22], "name": "PRIV_INSTR_INT_ASSERTED"}, 8177 {"bits": [23, 23], "name": "PRIV_REG_INT_ASSERTED"}, 8178 {"bits": [24, 24], "name": "OPCODE_ERROR_INT_ASSERTED"}, 8179 {"bits": [26, 26], "name": "TIME_STAMP_INT_ASSERTED"}, 8180 {"bits": [27, 27], "name": "RESERVED_BIT_ERROR_INT_ASSERTED"}, 8181 {"bits": [29, 29], "name": "GENERIC2_INT_ASSERTED"}, 8182 {"bits": [30, 30], "name": "GENERIC1_INT_ASSERTED"}, 8183 {"bits": [31, 31], "name": "GENERIC0_INT_ASSERTED"} 8184 ] 8185 }, 8186 "CP_MC_PACK_DELAY_CNT": { 8187 "fields": [ 8188 {"bits": [0, 4], "name": "PACK_DELAY_CNT"} 8189 ] 8190 }, 8191 "CP_MEQ_AVAIL": { 8192 "fields": [ 8193 {"bits": [0, 9], "name": "MEQ_CNT"} 8194 ] 8195 }, 8196 "CP_MEQ_STAT": { 8197 "fields": [ 8198 {"bits": [0, 9], "name": "MEQ_RPTR"}, 8199 {"bits": [16, 25], "name": "MEQ_WPTR"} 8200 ] 8201 }, 8202 "CP_MEQ_THRESHOLDS": { 8203 "fields": [ 8204 {"bits": [0, 7], "name": "MEQ1_START"}, 8205 {"bits": [8, 15], "name": "MEQ2_START"} 8206 ] 8207 }, 8208 "CP_ME_CNTL": { 8209 "fields": [ 8210 {"bits": [4, 4], "name": "CE_INVALIDATE_ICACHE"}, 8211 {"bits": [6, 6], "name": "PFP_INVALIDATE_ICACHE"}, 8212 {"bits": [8, 8], "name": "ME_INVALIDATE_ICACHE"}, 8213 {"bits": [24, 24], "name": "CE_HALT"}, 8214 {"bits": [25, 25], "name": "CE_STEP"}, 8215 {"bits": [26, 26], "name": "PFP_HALT"}, 8216 {"bits": [27, 27], "name": "PFP_STEP"}, 8217 {"bits": [28, 28], "name": "ME_HALT"}, 8218 {"bits": [29, 29], "name": "ME_STEP"} 8219 ] 8220 }, 8221 "CP_ME_MC_RADDR_HI": { 8222 "fields": [ 8223 {"bits": [0, 7], "name": "ME_MC_RADDR_HI"} 8224 ] 8225 }, 8226 "CP_ME_MC_RADDR_LO": { 8227 "fields": [ 8228 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"}, 8229 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} 8230 ] 8231 }, 8232 "CP_ME_MC_WADDR_HI": { 8233 "fields": [ 8234 {"bits": [0, 7], "name": "ME_MC_WADDR_HI"} 8235 ] 8236 }, 8237 "CP_ME_MC_WADDR_LO": { 8238 "fields": [ 8239 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"}, 8240 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} 8241 ] 8242 }, 8243 "CP_ME_PREEMPTION": { 8244 "fields": [ 8245 {"bits": [0, 0], "name": "ME_CNTXSW_PREEMPTION"} 8246 ] 8247 }, 8248 "CP_PERFMON_CNTL": { 8249 "fields": [ 8250 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 8251 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, 8252 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, 8253 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 8254 ] 8255 }, 8256 "CP_PERFMON_CNTX_CNTL": { 8257 "fields": [ 8258 {"bits": [31, 31], "name": "PERFMON_ENABLE"} 8259 ] 8260 }, 8261 "CP_PFP_IB_CONTROL": { 8262 "fields": [ 8263 {"bits": [0, 0], "name": "IB_EN"} 8264 ] 8265 }, 8266 "CP_PFP_LOAD_CONTROL": { 8267 "fields": [ 8268 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, 8269 {"bits": [1, 1], "name": "CNTX_REG_EN"}, 8270 {"bits": [15, 15], "name": "UCONFIG_REG_EN"}, 8271 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, 8272 {"bits": [24, 24], "name": "SH_CS_REG_EN"} 8273 ] 8274 }, 8275 "CP_PIPE_STATS_ADDR_LO": { 8276 "fields": [ 8277 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"}, 8278 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} 8279 ] 8280 }, 8281 "CP_QUEUE_THRESHOLDS": { 8282 "fields": [ 8283 {"bits": [0, 5], "name": "ROQ_IB1_START"}, 8284 {"bits": [8, 13], "name": "ROQ_IB2_START"} 8285 ] 8286 }, 8287 "CP_RB0_RPTR": { 8288 "fields": [ 8289 {"bits": [0, 19], "name": "RB_RPTR"} 8290 ] 8291 }, 8292 "CP_RB_OFFSET": { 8293 "fields": [ 8294 {"bits": [0, 19], "name": "RB_OFFSET"} 8295 ] 8296 }, 8297 "CP_RB_WPTR_DELAY": { 8298 "fields": [ 8299 {"bits": [0, 27], "name": "PRE_WRITE_TIMER"}, 8300 {"bits": [28, 31], "name": "PRE_WRITE_LIMIT"} 8301 ] 8302 }, 8303 "CP_RB_WPTR_POLL_CNTL": { 8304 "fields": [ 8305 {"bits": [0, 15], "name": "POLL_FREQUENCY"}, 8306 {"bits": [16, 31], "name": "IDLE_POLL_COUNT"} 8307 ] 8308 }, 8309 "CP_RINGID": { 8310 "fields": [ 8311 {"bits": [0, 1], "name": "RINGID"} 8312 ] 8313 }, 8314 "CP_ROQ1_THRESHOLDS": { 8315 "fields": [ 8316 {"bits": [0, 7], "name": "RB1_START"}, 8317 {"bits": [8, 15], "name": "RB2_START"}, 8318 {"bits": [16, 23], "name": "R0_IB1_START"}, 8319 {"bits": [24, 31], "name": "R1_IB1_START"} 8320 ] 8321 }, 8322 "CP_ROQ2_AVAIL": { 8323 "fields": [ 8324 {"bits": [0, 10], "name": "ROQ_CNT_IB2"} 8325 ] 8326 }, 8327 "CP_ROQ2_THRESHOLDS": { 8328 "fields": [ 8329 {"bits": [0, 7], "name": "R2_IB1_START"}, 8330 {"bits": [8, 15], "name": "R0_IB2_START"}, 8331 {"bits": [16, 23], "name": "R1_IB2_START"}, 8332 {"bits": [24, 31], "name": "R2_IB2_START"} 8333 ] 8334 }, 8335 "CP_ROQ_AVAIL": { 8336 "fields": [ 8337 {"bits": [0, 10], "name": "ROQ_CNT_RING"}, 8338 {"bits": [16, 26], "name": "ROQ_CNT_IB1"} 8339 ] 8340 }, 8341 "CP_ROQ_IB1_STAT": { 8342 "fields": [ 8343 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT1"}, 8344 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT1"} 8345 ] 8346 }, 8347 "CP_ROQ_IB2_STAT": { 8348 "fields": [ 8349 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT2"}, 8350 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT2"} 8351 ] 8352 }, 8353 "CP_ROQ_RB_STAT": { 8354 "fields": [ 8355 {"bits": [0, 9], "name": "ROQ_RPTR_PRIMARY"}, 8356 {"bits": [16, 25], "name": "ROQ_WPTR_PRIMARY"} 8357 ] 8358 }, 8359 "CP_SCRATCH_INDEX": { 8360 "fields": [ 8361 {"bits": [0, 7], "name": "SCRATCH_INDEX"} 8362 ] 8363 }, 8364 "CP_SIG_SEM_ADDR_HI": { 8365 "fields": [ 8366 {"bits": [0, 7], "name": "SEM_ADDR_HI"}, 8367 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, 8368 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, 8369 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, 8370 {"bits": [29, 31], "name": "SEM_SELECT"} 8371 ] 8372 }, 8373 "CP_SIG_SEM_ADDR_LO": { 8374 "fields": [ 8375 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, 8376 {"bits": [3, 31], "name": "SEM_ADDR_LO"} 8377 ] 8378 }, 8379 "CP_STALLED_STAT1": { 8380 "fields": [ 8381 {"bits": [0, 0], "name": "RBIU_TO_DMA_NOT_RDY_TO_RCV"}, 8382 {"bits": [2, 2], "name": "RBIU_TO_SEM_NOT_RDY_TO_RCV"}, 8383 {"bits": [4, 4], "name": "RBIU_TO_MEMWR_NOT_RDY_TO_RCV"}, 8384 {"bits": [10, 10], "name": "ME_HAS_ACTIVE_CE_BUFFER_FLAG"}, 8385 {"bits": [11, 11], "name": "ME_HAS_ACTIVE_DE_BUFFER_FLAG"}, 8386 {"bits": [12, 12], "name": "ME_STALLED_ON_TC_WR_CONFIRM"}, 8387 {"bits": [13, 13], "name": "ME_STALLED_ON_ATOMIC_RTN_DATA"}, 8388 {"bits": [14, 14], "name": "ME_WAITING_ON_MC_READ_DATA"}, 8389 {"bits": [15, 15], "name": "ME_WAITING_ON_REG_READ_DATA"}, 8390 {"bits": [16, 16], "name": "MIU_WAITING_ON_RDREQ_FREE"}, 8391 {"bits": [17, 17], "name": "MIU_WAITING_ON_WRREQ_FREE"}, 8392 {"bits": [23, 23], "name": "RCIU_WAITING_ON_GDS_FREE"}, 8393 {"bits": [24, 24], "name": "RCIU_WAITING_ON_GRBM_FREE"}, 8394 {"bits": [25, 25], "name": "RCIU_WAITING_ON_VGT_FREE"}, 8395 {"bits": [26, 26], "name": "RCIU_STALLED_ON_ME_READ"}, 8396 {"bits": [27, 27], "name": "RCIU_STALLED_ON_DMA_READ"}, 8397 {"bits": [28, 28], "name": "RCIU_HALTED_BY_REG_VIOLATION"}, 8398 {"bits": [28, 28], "name": "RCIU_STALLED_ON_APPEND_READ"} 8399 ] 8400 }, 8401 "CP_STALLED_STAT2": { 8402 "fields": [ 8403 {"bits": [0, 0], "name": "PFP_TO_CSF_NOT_RDY_TO_RCV"}, 8404 {"bits": [1, 1], "name": "PFP_TO_MEQ_NOT_RDY_TO_RCV"}, 8405 {"bits": [2, 2], "name": "PFP_TO_RCIU_NOT_RDY_TO_RCV"}, 8406 {"bits": [4, 4], "name": "PFP_TO_VGT_WRITES_PENDING"}, 8407 {"bits": [5, 5], "name": "PFP_RCIU_READ_PENDING"}, 8408 {"bits": [6, 6], "name": "PFP_MIU_READ_PENDING"}, 8409 {"bits": [7, 7], "name": "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, 8410 {"bits": [8, 8], "name": "PFP_WAITING_ON_BUFFER_DATA"}, 8411 {"bits": [9, 9], "name": "ME_WAIT_ON_CE_COUNTER"}, 8412 {"bits": [10, 10], "name": "ME_WAIT_ON_AVAIL_BUFFER"}, 8413 {"bits": [11, 11], "name": "GFX_CNTX_NOT_AVAIL_TO_ME"}, 8414 {"bits": [12, 12], "name": "ME_RCIU_NOT_RDY_TO_RCV"}, 8415 {"bits": [13, 13], "name": "ME_TO_CONST_NOT_RDY_TO_RCV"}, 8416 {"bits": [14, 14], "name": "ME_WAITING_DATA_FROM_PFP"}, 8417 {"bits": [15, 15], "name": "ME_WAITING_ON_PARTIAL_FLUSH"}, 8418 {"bits": [16, 16], "name": "MEQ_TO_ME_NOT_RDY_TO_RCV"}, 8419 {"bits": [17, 17], "name": "STQ_TO_ME_NOT_RDY_TO_RCV"}, 8420 {"bits": [18, 18], "name": "ME_WAITING_DATA_FROM_STQ"}, 8421 {"bits": [19, 19], "name": "PFP_STALLED_ON_TC_WR_CONFIRM"}, 8422 {"bits": [20, 20], "name": "PFP_STALLED_ON_ATOMIC_RTN_DATA"}, 8423 {"bits": [21, 21], "name": "EOPD_FIFO_NEEDS_SC_EOP_DONE"}, 8424 {"bits": [22, 22], "name": "EOPD_FIFO_NEEDS_WR_CONFIRM"}, 8425 {"bits": [23, 23], "name": "STRMO_WR_OF_PRIM_DATA_PENDING"}, 8426 {"bits": [24, 24], "name": "PIPE_STATS_WR_DATA_PENDING"}, 8427 {"bits": [25, 25], "name": "APPEND_RDY_WAIT_ON_CS_DONE"}, 8428 {"bits": [26, 26], "name": "APPEND_RDY_WAIT_ON_PS_DONE"}, 8429 {"bits": [27, 27], "name": "APPEND_WAIT_ON_WR_CONFIRM"}, 8430 {"bits": [28, 28], "name": "APPEND_ACTIVE_PARTITION"}, 8431 {"bits": [29, 29], "name": "APPEND_WAITING_TO_SEND_MEMWRITE"}, 8432 {"bits": [30, 30], "name": "SURF_SYNC_NEEDS_IDLE_CNTXS"}, 8433 {"bits": [31, 31], "name": "SURF_SYNC_NEEDS_ALL_CLEAN"} 8434 ] 8435 }, 8436 "CP_STALLED_STAT3": { 8437 "fields": [ 8438 {"bits": [0, 0], "name": "CE_TO_CSF_NOT_RDY_TO_RCV"}, 8439 {"bits": [1, 1], "name": "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV"}, 8440 {"bits": [2, 2], "name": "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER"}, 8441 {"bits": [3, 3], "name": "CE_TO_RAM_INIT_NOT_RDY"}, 8442 {"bits": [4, 4], "name": "CE_TO_RAM_DUMP_NOT_RDY"}, 8443 {"bits": [5, 5], "name": "CE_TO_RAM_WRITE_NOT_RDY"}, 8444 {"bits": [6, 6], "name": "CE_TO_INC_FIFO_NOT_RDY_TO_RCV"}, 8445 {"bits": [7, 7], "name": "CE_TO_WR_FIFO_NOT_RDY_TO_RCV"}, 8446 {"bits": [8, 8], "name": "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, 8447 {"bits": [10, 10], "name": "CE_WAITING_ON_BUFFER_DATA"}, 8448 {"bits": [11, 11], "name": "CE_WAITING_ON_CE_BUFFER_FLAG"}, 8449 {"bits": [12, 12], "name": "CE_WAITING_ON_DE_COUNTER"}, 8450 {"bits": [13, 13], "name": "CE_WAITING_ON_DE_COUNTER_UNDERFLOW"}, 8451 {"bits": [14, 14], "name": "TCIU_WAITING_ON_FREE"}, 8452 {"bits": [15, 15], "name": "TCIU_WAITING_ON_TAGS"} 8453 ] 8454 }, 8455 "CP_STAT": { 8456 "fields": [ 8457 {"bits": [7, 7], "name": "MIU_RDREQ_BUSY"}, 8458 {"bits": [8, 8], "name": "MIU_WRREQ_BUSY"}, 8459 {"bits": [9, 9], "name": "ROQ_RING_BUSY"}, 8460 {"bits": [10, 10], "name": "ROQ_INDIRECT1_BUSY"}, 8461 {"bits": [11, 11], "name": "ROQ_INDIRECT2_BUSY"}, 8462 {"bits": [12, 12], "name": "ROQ_STATE_BUSY"}, 8463 {"bits": [13, 13], "name": "DC_BUSY"}, 8464 {"bits": [15, 15], "name": "PFP_BUSY"}, 8465 {"bits": [16, 16], "name": "MEQ_BUSY"}, 8466 {"bits": [17, 17], "name": "ME_BUSY"}, 8467 {"bits": [18, 18], "name": "QUERY_BUSY"}, 8468 {"bits": [19, 19], "name": "SEMAPHORE_BUSY"}, 8469 {"bits": [20, 20], "name": "INTERRUPT_BUSY"}, 8470 {"bits": [21, 21], "name": "SURFACE_SYNC_BUSY"}, 8471 {"bits": [22, 22], "name": "DMA_BUSY"}, 8472 {"bits": [23, 23], "name": "RCIU_BUSY"}, 8473 {"bits": [24, 24], "name": "SCRATCH_RAM_BUSY"}, 8474 {"bits": [25, 25], "name": "CPC_CPG_BUSY"}, 8475 {"bits": [26, 26], "name": "CE_BUSY"}, 8476 {"bits": [27, 27], "name": "TCIU_BUSY"}, 8477 {"bits": [28, 28], "name": "ROQ_CE_RING_BUSY"}, 8478 {"bits": [29, 29], "name": "ROQ_CE_INDIRECT1_BUSY"}, 8479 {"bits": [30, 30], "name": "ROQ_CE_INDIRECT2_BUSY"}, 8480 {"bits": [31, 31], "name": "CP_BUSY"} 8481 ] 8482 }, 8483 "CP_STQ_AVAIL": { 8484 "fields": [ 8485 {"bits": [0, 8], "name": "STQ_CNT"} 8486 ] 8487 }, 8488 "CP_STQ_STAT": { 8489 "fields": [ 8490 {"bits": [0, 9], "name": "STQ_RPTR"} 8491 ] 8492 }, 8493 "CP_STQ_THRESHOLDS": { 8494 "fields": [ 8495 {"bits": [0, 7], "name": "STQ0_START"}, 8496 {"bits": [8, 15], "name": "STQ1_START"}, 8497 {"bits": [16, 23], "name": "STQ2_START"} 8498 ] 8499 }, 8500 "CP_STREAM_OUT_ADDR_LO": { 8501 "fields": [ 8502 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"}, 8503 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} 8504 ] 8505 }, 8506 "CP_STRMOUT_CNTL": { 8507 "fields": [ 8508 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} 8509 ] 8510 }, 8511 "CP_ST_BASE_HI": { 8512 "fields": [ 8513 {"bits": [0, 7], "name": "ST_BASE_HI"} 8514 ] 8515 }, 8516 "CP_ST_BASE_LO": { 8517 "fields": [ 8518 {"bits": [2, 31], "name": "ST_BASE_LO"} 8519 ] 8520 }, 8521 "CP_ST_BUFSZ": { 8522 "fields": [ 8523 {"bits": [0, 19], "name": "ST_BUFSZ"} 8524 ] 8525 }, 8526 "CP_VMID": { 8527 "fields": [ 8528 {"bits": [0, 3], "name": "VMID"} 8529 ] 8530 }, 8531 "CS_COPY_STATE": { 8532 "fields": [ 8533 {"bits": [0, 2], "name": "SRC_STATE_ID"} 8534 ] 8535 }, 8536 "DB_ALPHA_TO_MASK": { 8537 "fields": [ 8538 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, 8539 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, 8540 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, 8541 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, 8542 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, 8543 {"bits": [16, 16], "name": "OFFSET_ROUND"} 8544 ] 8545 }, 8546 "DB_COUNT_CONTROL": { 8547 "fields": [ 8548 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, 8549 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, 8550 {"bits": [4, 6], "name": "SAMPLE_RATE"}, 8551 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, 8552 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, 8553 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, 8554 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, 8555 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, 8556 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} 8557 ] 8558 }, 8559 "DB_DEPTH_CONTROL": { 8560 "fields": [ 8561 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, 8562 {"bits": [1, 1], "name": "Z_ENABLE"}, 8563 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, 8564 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, 8565 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, 8566 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, 8567 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, 8568 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, 8569 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, 8570 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} 8571 ] 8572 }, 8573 "DB_DEPTH_INFO": { 8574 "fields": [ 8575 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"}, 8576 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 8577 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 8578 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, 8579 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, 8580 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, 8581 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} 8582 ] 8583 }, 8584 "DB_DEPTH_SIZE": { 8585 "fields": [ 8586 {"bits": [0, 10], "name": "PITCH_TILE_MAX"}, 8587 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"} 8588 ] 8589 }, 8590 "DB_DEPTH_SLICE": { 8591 "fields": [ 8592 {"bits": [0, 21], "name": "SLICE_TILE_MAX"} 8593 ] 8594 }, 8595 "DB_DEPTH_VIEW": { 8596 "fields": [ 8597 {"bits": [0, 10], "name": "SLICE_START"}, 8598 {"bits": [13, 23], "name": "SLICE_MAX"}, 8599 {"bits": [24, 24], "name": "Z_READ_ONLY"}, 8600 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"} 8601 ] 8602 }, 8603 "DB_EQAA": { 8604 "fields": [ 8605 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, 8606 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, 8607 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, 8608 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, 8609 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, 8610 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, 8611 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, 8612 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, 8613 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, 8614 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, 8615 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, 8616 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} 8617 ] 8618 }, 8619 "DB_HTILE_SURFACE": { 8620 "fields": [ 8621 {"bits": [0, 0], "name": "LINEAR"}, 8622 {"bits": [1, 1], "name": "FULL_CACHE"}, 8623 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, 8624 {"bits": [3, 3], "name": "PRELOAD"}, 8625 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, 8626 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, 8627 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"} 8628 ] 8629 }, 8630 "DB_PRELOAD_CONTROL": { 8631 "fields": [ 8632 {"bits": [0, 7], "name": "START_X"}, 8633 {"bits": [8, 15], "name": "START_Y"}, 8634 {"bits": [16, 23], "name": "MAX_X"}, 8635 {"bits": [24, 31], "name": "MAX_Y"} 8636 ] 8637 }, 8638 "DB_RENDER_CONTROL": { 8639 "fields": [ 8640 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, 8641 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, 8642 {"bits": [2, 2], "name": "DEPTH_COPY"}, 8643 {"bits": [3, 3], "name": "STENCIL_COPY"}, 8644 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, 8645 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, 8646 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, 8647 {"bits": [7, 7], "name": "COPY_CENTROID"}, 8648 {"bits": [8, 11], "name": "COPY_SAMPLE"} 8649 ] 8650 }, 8651 "DB_RENDER_OVERRIDE": { 8652 "fields": [ 8653 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, 8654 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, 8655 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, 8656 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, 8657 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, 8658 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, 8659 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, 8660 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, 8661 {"bits": [11, 11], "name": "FORCE_Z_READ"}, 8662 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, 8663 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, 8664 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, 8665 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, 8666 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, 8667 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, 8668 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, 8669 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, 8670 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, 8671 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, 8672 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, 8673 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, 8674 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, 8675 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} 8676 ] 8677 }, 8678 "DB_RENDER_OVERRIDE2": { 8679 "fields": [ 8680 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, 8681 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, 8682 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, 8683 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, 8684 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, 8685 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, 8686 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, 8687 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, 8688 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, 8689 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, 8690 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, 8691 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, 8692 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, 8693 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, 8694 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"} 8695 ] 8696 }, 8697 "DB_SHADER_CONTROL": { 8698 "fields": [ 8699 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, 8700 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, 8701 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, 8702 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, 8703 {"bits": [6, 6], "name": "KILL_ENABLE"}, 8704 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, 8705 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, 8706 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, 8707 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, 8708 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, 8709 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, 8710 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} 8711 ] 8712 }, 8713 "DB_SRESULTS_COMPARE_STATE0": { 8714 "fields": [ 8715 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, 8716 {"bits": [4, 11], "name": "COMPAREVALUE0"}, 8717 {"bits": [12, 19], "name": "COMPAREMASK0"}, 8718 {"bits": [24, 24], "name": "ENABLE0"} 8719 ] 8720 }, 8721 "DB_SRESULTS_COMPARE_STATE1": { 8722 "fields": [ 8723 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, 8724 {"bits": [4, 11], "name": "COMPAREVALUE1"}, 8725 {"bits": [12, 19], "name": "COMPAREMASK1"}, 8726 {"bits": [24, 24], "name": "ENABLE1"} 8727 ] 8728 }, 8729 "DB_STENCILREFMASK": { 8730 "fields": [ 8731 {"bits": [0, 7], "name": "STENCILTESTVAL"}, 8732 {"bits": [8, 15], "name": "STENCILMASK"}, 8733 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, 8734 {"bits": [24, 31], "name": "STENCILOPVAL"} 8735 ] 8736 }, 8737 "DB_STENCILREFMASK_BF": { 8738 "fields": [ 8739 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, 8740 {"bits": [8, 15], "name": "STENCILMASK_BF"}, 8741 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, 8742 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} 8743 ] 8744 }, 8745 "DB_STENCIL_CLEAR": { 8746 "fields": [ 8747 {"bits": [0, 7], "name": "CLEAR"} 8748 ] 8749 }, 8750 "DB_STENCIL_CONTROL": { 8751 "fields": [ 8752 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, 8753 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, 8754 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, 8755 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, 8756 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, 8757 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} 8758 ] 8759 }, 8760 "DB_STENCIL_INFO": { 8761 "fields": [ 8762 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, 8763 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8764 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, 8765 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 8766 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} 8767 ] 8768 }, 8769 "DB_Z_INFO": { 8770 "fields": [ 8771 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, 8772 {"bits": [2, 3], "name": "NUM_SAMPLES"}, 8773 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8774 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, 8775 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 8776 {"bits": [28, 28], "name": "READ_SIZE"}, 8777 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, 8778 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} 8779 ] 8780 }, 8781 "DEBUG_INDEX": { 8782 "fields": [ 8783 {"bits": [0, 17], "name": "DEBUG_INDEX"} 8784 ] 8785 }, 8786 "GB_ADDR_CONFIG": { 8787 "fields": [ 8788 {"bits": [0, 2], "name": "NUM_PIPES"}, 8789 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"}, 8790 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, 8791 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"}, 8792 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, 8793 {"bits": [20, 22], "name": "NUM_GPUS"}, 8794 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, 8795 {"bits": [28, 29], "name": "ROW_SIZE"}, 8796 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"} 8797 ] 8798 }, 8799 "GB_TILE_MODE0": { 8800 "fields": [ 8801 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"}, 8802 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 8803 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 8804 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8805 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 8806 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 8807 ] 8808 }, 8809 "GB_TILE_MODE10": { 8810 "fields": [ 8811 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 8812 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 8813 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8814 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 8815 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 8816 ] 8817 }, 8818 "GRBM_CNTL": { 8819 "fields": [ 8820 {"bits": [0, 7], "name": "READ_TIMEOUT"} 8821 ] 8822 }, 8823 "GRBM_DEBUG": { 8824 "fields": [ 8825 {"bits": [1, 1], "name": "IGNORE_RDY"}, 8826 {"bits": [5, 5], "name": "IGNORE_FAO"}, 8827 {"bits": [6, 6], "name": "DISABLE_READ_TIMEOUT"}, 8828 {"bits": [7, 7], "name": "SNAPSHOT_FREE_CNTRS"}, 8829 {"bits": [8, 11], "name": "HYSTERESIS_GUI_ACTIVE"}, 8830 {"bits": [12, 12], "name": "GFX_CLOCK_DOMAIN_OVERRIDE"} 8831 ] 8832 }, 8833 "GRBM_DEBUG_CNTL": { 8834 "fields": [ 8835 {"bits": [0, 5], "name": "GRBM_DEBUG_INDEX"} 8836 ] 8837 }, 8838 "GRBM_DEBUG_SNAPSHOT": { 8839 "fields": [ 8840 {"bits": [0, 0], "name": "CPF_RDY"}, 8841 {"bits": [1, 1], "name": "CPG_RDY"}, 8842 {"bits": [1, 1], "name": "SRBM_RDY"}, 8843 {"bits": [3, 3], "name": "WD_ME0PIPE0_RDY"}, 8844 {"bits": [4, 4], "name": "WD_ME0PIPE1_RDY"}, 8845 {"bits": [6, 6], "name": "SE0SPI_ME0PIPE0_RDY0"}, 8846 {"bits": [7, 7], "name": "SE0SPI_ME0PIPE1_RDY0"}, 8847 {"bits": [8, 8], "name": "SE1SPI_ME0PIPE0_RDY0"}, 8848 {"bits": [9, 9], "name": "GDS_RDY"}, 8849 {"bits": [9, 9], "name": "SE1SPI_ME0PIPE1_RDY0"}, 8850 {"bits": [10, 10], "name": "SE2SPI_ME0PIPE0_RDY0"}, 8851 {"bits": [11, 11], "name": "SE2SPI_ME0PIPE1_RDY0"}, 8852 {"bits": [12, 12], "name": "SE3SPI_ME0PIPE0_RDY0"}, 8853 {"bits": [13, 13], "name": "SE3SPI_ME0PIPE1_RDY0"}, 8854 {"bits": [14, 14], "name": "SE0SPI_ME0PIPE0_RDY1"}, 8855 {"bits": [15, 15], "name": "SE0SPI_ME0PIPE1_RDY1"}, 8856 {"bits": [16, 16], "name": "SE1SPI_ME0PIPE0_RDY1"}, 8857 {"bits": [17, 17], "name": "SE1SPI_ME0PIPE1_RDY1"}, 8858 {"bits": [18, 18], "name": "SE2SPI_ME0PIPE0_RDY1"}, 8859 {"bits": [19, 19], "name": "SE2SPI_ME0PIPE1_RDY1"}, 8860 {"bits": [20, 20], "name": "SE3SPI_ME0PIPE0_RDY1"}, 8861 {"bits": [21, 21], "name": "SE3SPI_ME0PIPE1_RDY1"} 8862 ] 8863 }, 8864 "GRBM_GFX_CLKEN_CNTL": { 8865 "fields": [ 8866 {"bits": [0, 3], "name": "PREFIX_DELAY_CNT"}, 8867 {"bits": [8, 12], "name": "POST_DELAY_CNT"} 8868 ] 8869 }, 8870 "GRBM_GFX_INDEX": { 8871 "fields": [ 8872 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, 8873 {"bits": [8, 15], "name": "SH_INDEX"}, 8874 {"bits": [16, 23], "name": "SE_INDEX"}, 8875 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, 8876 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, 8877 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} 8878 ] 8879 }, 8880 "GRBM_INT_CNTL": { 8881 "fields": [ 8882 {"bits": [0, 0], "name": "RDERR_INT_ENABLE"}, 8883 {"bits": [19, 19], "name": "GUI_IDLE_INT_ENABLE"} 8884 ] 8885 }, 8886 "GRBM_PERFCOUNTER0_SELECT": { 8887 "fields": [ 8888 {"bits": [0, 5], "name": "PERF_SEL"}, 8889 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 8890 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 8891 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 8892 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, 8893 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, 8894 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 8895 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, 8896 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, 8897 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, 8898 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, 8899 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, 8900 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, 8901 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, 8902 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, 8903 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 8904 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, 8905 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, 8906 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"} 8907 ] 8908 }, 8909 "GRBM_PWR_CNTL": { 8910 "fields": [ 8911 {"bits": [0, 3], "name": "REQ_TYPE"}, 8912 {"bits": [4, 7], "name": "RSP_TYPE"} 8913 ] 8914 }, 8915 "GRBM_READ_ERROR": { 8916 "fields": [ 8917 {"bits": [2, 17], "name": "READ_ADDRESS"}, 8918 {"bits": [20, 21], "name": "READ_PIPEID"}, 8919 {"bits": [22, 23], "name": "READ_MEID"}, 8920 {"bits": [31, 31], "name": "READ_ERROR"} 8921 ] 8922 }, 8923 "GRBM_SE0_PERFCOUNTER_SELECT": { 8924 "fields": [ 8925 {"bits": [0, 5], "name": "PERF_SEL"}, 8926 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 8927 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 8928 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, 8929 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, 8930 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 8931 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, 8932 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, 8933 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, 8934 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 8935 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, 8936 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"} 8937 ] 8938 }, 8939 "GRBM_SKEW_CNTL": { 8940 "fields": [ 8941 {"bits": [0, 5], "name": "SKEW_TOP_THRESHOLD"}, 8942 {"bits": [6, 11], "name": "SKEW_COUNT"} 8943 ] 8944 }, 8945 "GRBM_SOFT_RESET": { 8946 "fields": [ 8947 {"bits": [0, 0], "name": "SOFT_RESET_CP"}, 8948 {"bits": [2, 2], "name": "SOFT_RESET_RLC"}, 8949 {"bits": [16, 16], "name": "SOFT_RESET_GFX"}, 8950 {"bits": [17, 17], "name": "SOFT_RESET_CPF"}, 8951 {"bits": [18, 18], "name": "SOFT_RESET_CPC"}, 8952 {"bits": [19, 19], "name": "SOFT_RESET_CPG"} 8953 ] 8954 }, 8955 "GRBM_STATUS": { 8956 "fields": [ 8957 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, 8958 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"}, 8959 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, 8960 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, 8961 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, 8962 {"bits": [12, 12], "name": "DB_CLEAN"}, 8963 {"bits": [13, 13], "name": "CB_CLEAN"}, 8964 {"bits": [14, 14], "name": "TA_BUSY"}, 8965 {"bits": [15, 15], "name": "GDS_BUSY"}, 8966 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, 8967 {"bits": [17, 17], "name": "VGT_BUSY"}, 8968 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, 8969 {"bits": [19, 19], "name": "IA_BUSY"}, 8970 {"bits": [20, 20], "name": "SX_BUSY"}, 8971 {"bits": [21, 21], "name": "WD_BUSY"}, 8972 {"bits": [22, 22], "name": "SPI_BUSY"}, 8973 {"bits": [23, 23], "name": "BCI_BUSY"}, 8974 {"bits": [24, 24], "name": "SC_BUSY"}, 8975 {"bits": [25, 25], "name": "PA_BUSY"}, 8976 {"bits": [26, 26], "name": "DB_BUSY"}, 8977 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, 8978 {"bits": [29, 29], "name": "CP_BUSY"}, 8979 {"bits": [30, 30], "name": "CB_BUSY"}, 8980 {"bits": [31, 31], "name": "GUI_ACTIVE"} 8981 ] 8982 }, 8983 "GRBM_STATUS2": { 8984 "fields": [ 8985 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, 8986 {"bits": [0, 0], "name": "RLC_RQ_PENDING"}, 8987 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, 8988 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, 8989 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, 8990 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, 8991 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, 8992 {"bits": [8, 8], "name": "RLC_BUSY"}, 8993 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, 8994 {"bits": [9, 9], "name": "TC_BUSY"}, 8995 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, 8996 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, 8997 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, 8998 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, 8999 {"bits": [28, 28], "name": "CPF_BUSY"}, 9000 {"bits": [29, 29], "name": "CPC_BUSY"}, 9001 {"bits": [30, 30], "name": "CPG_BUSY"} 9002 ] 9003 }, 9004 "GRBM_STATUS_SE0": { 9005 "fields": [ 9006 {"bits": [1, 1], "name": "DB_CLEAN"}, 9007 {"bits": [2, 2], "name": "CB_CLEAN"}, 9008 {"bits": [22, 22], "name": "BCI_BUSY"}, 9009 {"bits": [23, 23], "name": "VGT_BUSY"}, 9010 {"bits": [24, 24], "name": "PA_BUSY"}, 9011 {"bits": [25, 25], "name": "TA_BUSY"}, 9012 {"bits": [26, 26], "name": "SX_BUSY"}, 9013 {"bits": [27, 27], "name": "SPI_BUSY"}, 9014 {"bits": [29, 29], "name": "SC_BUSY"}, 9015 {"bits": [30, 30], "name": "DB_BUSY"}, 9016 {"bits": [31, 31], "name": "CB_BUSY"} 9017 ] 9018 }, 9019 "GRBM_WAIT_IDLE_CLOCKS": { 9020 "fields": [ 9021 {"bits": [0, 7], "name": "WAIT_IDLE_CLOCKS"} 9022 ] 9023 }, 9024 "IA_CNTL_STATUS": { 9025 "fields": [ 9026 {"bits": [0, 0], "name": "IA_BUSY"}, 9027 {"bits": [1, 1], "name": "IA_DMA_BUSY"}, 9028 {"bits": [2, 2], "name": "IA_DMA_REQ_BUSY"}, 9029 {"bits": [3, 3], "name": "IA_GRP_BUSY"}, 9030 {"bits": [4, 4], "name": "IA_ADC_BUSY"} 9031 ] 9032 }, 9033 "IA_DEBUG_CNTL": { 9034 "fields": [ 9035 {"bits": [0, 5], "name": "IA_DEBUG_INDX"}, 9036 {"bits": [6, 6], "name": "IA_DEBUG_SEL_BUS_B"} 9037 ] 9038 }, 9039 "IA_MULTI_VGT_PARAM": { 9040 "fields": [ 9041 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, 9042 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, 9043 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, 9044 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, 9045 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, 9046 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} 9047 ] 9048 }, 9049 "IA_PERFCOUNTER0_SELECT": { 9050 "fields": [ 9051 {"bits": [0, 7], "name": "PERF_SEL"}, 9052 {"bits": [10, 19], "name": "PERF_SEL1"}, 9053 {"bits": [20, 23], "name": "CNTR_MODE"}, 9054 {"bits": [24, 27], "name": "PERF_MODE1"}, 9055 {"bits": [28, 31], "name": "PERF_MODE"} 9056 ] 9057 }, 9058 "IA_PERFCOUNTER1_SELECT": { 9059 "fields": [ 9060 {"bits": [0, 7], "name": "PERF_SEL"}, 9061 {"bits": [28, 31], "name": "PERF_MODE"} 9062 ] 9063 }, 9064 "IA_VMID_OVERRIDE": { 9065 "fields": [ 9066 {"bits": [0, 0], "name": "ENABLE"}, 9067 {"bits": [1, 4], "name": "VMID"} 9068 ] 9069 }, 9070 "PA_CL_CLIP_CNTL": { 9071 "fields": [ 9072 {"bits": [0, 0], "name": "UCP_ENA_0"}, 9073 {"bits": [1, 1], "name": "UCP_ENA_1"}, 9074 {"bits": [2, 2], "name": "UCP_ENA_2"}, 9075 {"bits": [3, 3], "name": "UCP_ENA_3"}, 9076 {"bits": [4, 4], "name": "UCP_ENA_4"}, 9077 {"bits": [5, 5], "name": "UCP_ENA_5"}, 9078 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, 9079 {"bits": [14, 15], "name": "PS_UCP_MODE"}, 9080 {"bits": [16, 16], "name": "CLIP_DISABLE"}, 9081 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, 9082 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, 9083 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, 9084 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, 9085 {"bits": [21, 21], "name": "VTX_KILL_OR"}, 9086 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, 9087 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, 9088 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, 9089 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, 9090 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"} 9091 ] 9092 }, 9093 "PA_CL_CNTL_STATUS": { 9094 "fields": [ 9095 {"bits": [31, 31], "name": "CL_BUSY"} 9096 ] 9097 }, 9098 "PA_CL_ENHANCE": { 9099 "fields": [ 9100 {"bits": [0, 0], "name": "CLIP_VTX_REORDER_ENA"}, 9101 {"bits": [1, 2], "name": "NUM_CLIP_SEQ"}, 9102 {"bits": [3, 3], "name": "CLIPPED_PRIM_SEQ_STALL"}, 9103 {"bits": [4, 4], "name": "VE_NAN_PROC_DISABLE"}, 9104 {"bits": [5, 5], "name": "XTRA_DEBUG_REG_SEL"}, 9105 {"bits": [28, 28], "name": "ECO_SPARE3"}, 9106 {"bits": [29, 29], "name": "ECO_SPARE2"}, 9107 {"bits": [30, 30], "name": "ECO_SPARE1"}, 9108 {"bits": [31, 31], "name": "ECO_SPARE0"} 9109 ] 9110 }, 9111 "PA_CL_NANINF_CNTL": { 9112 "fields": [ 9113 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, 9114 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, 9115 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, 9116 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, 9117 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, 9118 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, 9119 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, 9120 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, 9121 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, 9122 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, 9123 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, 9124 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, 9125 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, 9126 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, 9127 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, 9128 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} 9129 ] 9130 }, 9131 "PA_CL_VS_OUT_CNTL": { 9132 "fields": [ 9133 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, 9134 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, 9135 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, 9136 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, 9137 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, 9138 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, 9139 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, 9140 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, 9141 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, 9142 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, 9143 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, 9144 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, 9145 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, 9146 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, 9147 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, 9148 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, 9149 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, 9150 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, 9151 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, 9152 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, 9153 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, 9154 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, 9155 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, 9156 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, 9157 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, 9158 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"} 9159 ] 9160 }, 9161 "PA_CL_VTE_CNTL": { 9162 "fields": [ 9163 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, 9164 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, 9165 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, 9166 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, 9167 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, 9168 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, 9169 {"bits": [8, 8], "name": "VTX_XY_FMT"}, 9170 {"bits": [9, 9], "name": "VTX_Z_FMT"}, 9171 {"bits": [10, 10], "name": "VTX_W0_FMT"}, 9172 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} 9173 ] 9174 }, 9175 "PA_SC_AA_CONFIG": { 9176 "fields": [ 9177 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, 9178 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, 9179 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, 9180 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, 9181 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"} 9182 ] 9183 }, 9184 "PA_SC_AA_MASK_X0Y0_X1Y0": { 9185 "fields": [ 9186 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, 9187 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} 9188 ] 9189 }, 9190 "PA_SC_AA_MASK_X0Y1_X1Y1": { 9191 "fields": [ 9192 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, 9193 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} 9194 ] 9195 }, 9196 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": { 9197 "fields": [ 9198 {"bits": [0, 3], "name": "S0_X"}, 9199 {"bits": [4, 7], "name": "S0_Y"}, 9200 {"bits": [8, 11], "name": "S1_X"}, 9201 {"bits": [12, 15], "name": "S1_Y"}, 9202 {"bits": [16, 19], "name": "S2_X"}, 9203 {"bits": [20, 23], "name": "S2_Y"}, 9204 {"bits": [24, 27], "name": "S3_X"}, 9205 {"bits": [28, 31], "name": "S3_Y"} 9206 ] 9207 }, 9208 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": { 9209 "fields": [ 9210 {"bits": [0, 3], "name": "S4_X"}, 9211 {"bits": [4, 7], "name": "S4_Y"}, 9212 {"bits": [8, 11], "name": "S5_X"}, 9213 {"bits": [12, 15], "name": "S5_Y"}, 9214 {"bits": [16, 19], "name": "S6_X"}, 9215 {"bits": [20, 23], "name": "S6_Y"}, 9216 {"bits": [24, 27], "name": "S7_X"}, 9217 {"bits": [28, 31], "name": "S7_Y"} 9218 ] 9219 }, 9220 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": { 9221 "fields": [ 9222 {"bits": [0, 3], "name": "S8_X"}, 9223 {"bits": [4, 7], "name": "S8_Y"}, 9224 {"bits": [8, 11], "name": "S9_X"}, 9225 {"bits": [12, 15], "name": "S9_Y"}, 9226 {"bits": [16, 19], "name": "S10_X"}, 9227 {"bits": [20, 23], "name": "S10_Y"}, 9228 {"bits": [24, 27], "name": "S11_X"}, 9229 {"bits": [28, 31], "name": "S11_Y"} 9230 ] 9231 }, 9232 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": { 9233 "fields": [ 9234 {"bits": [0, 3], "name": "S12_X"}, 9235 {"bits": [4, 7], "name": "S12_Y"}, 9236 {"bits": [8, 11], "name": "S13_X"}, 9237 {"bits": [12, 15], "name": "S13_Y"}, 9238 {"bits": [16, 19], "name": "S14_X"}, 9239 {"bits": [20, 23], "name": "S14_Y"}, 9240 {"bits": [24, 27], "name": "S15_X"}, 9241 {"bits": [28, 31], "name": "S15_Y"} 9242 ] 9243 }, 9244 "PA_SC_CENTROID_PRIORITY_0": { 9245 "fields": [ 9246 {"bits": [0, 3], "name": "DISTANCE_0"}, 9247 {"bits": [4, 7], "name": "DISTANCE_1"}, 9248 {"bits": [8, 11], "name": "DISTANCE_2"}, 9249 {"bits": [12, 15], "name": "DISTANCE_3"}, 9250 {"bits": [16, 19], "name": "DISTANCE_4"}, 9251 {"bits": [20, 23], "name": "DISTANCE_5"}, 9252 {"bits": [24, 27], "name": "DISTANCE_6"}, 9253 {"bits": [28, 31], "name": "DISTANCE_7"} 9254 ] 9255 }, 9256 "PA_SC_CENTROID_PRIORITY_1": { 9257 "fields": [ 9258 {"bits": [0, 3], "name": "DISTANCE_8"}, 9259 {"bits": [4, 7], "name": "DISTANCE_9"}, 9260 {"bits": [8, 11], "name": "DISTANCE_10"}, 9261 {"bits": [12, 15], "name": "DISTANCE_11"}, 9262 {"bits": [16, 19], "name": "DISTANCE_12"}, 9263 {"bits": [20, 23], "name": "DISTANCE_13"}, 9264 {"bits": [24, 27], "name": "DISTANCE_14"}, 9265 {"bits": [28, 31], "name": "DISTANCE_15"} 9266 ] 9267 }, 9268 "PA_SC_CLIPRECT_0_BR": { 9269 "fields": [ 9270 {"bits": [0, 14], "name": "BR_X"}, 9271 {"bits": [16, 30], "name": "BR_Y"} 9272 ] 9273 }, 9274 "PA_SC_CLIPRECT_0_TL": { 9275 "fields": [ 9276 {"bits": [0, 14], "name": "TL_X"}, 9277 {"bits": [16, 30], "name": "TL_Y"} 9278 ] 9279 }, 9280 "PA_SC_CLIPRECT_RULE": { 9281 "fields": [ 9282 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} 9283 ] 9284 }, 9285 "PA_SC_DEBUG_CNTL": { 9286 "fields": [ 9287 {"bits": [0, 5], "name": "SC_DEBUG_INDX"} 9288 ] 9289 }, 9290 "PA_SC_EDGERULE": { 9291 "fields": [ 9292 {"bits": [0, 3], "name": "ER_TRI"}, 9293 {"bits": [4, 7], "name": "ER_POINT"}, 9294 {"bits": [8, 11], "name": "ER_RECT"}, 9295 {"bits": [12, 17], "name": "ER_LINE_LR"}, 9296 {"bits": [18, 23], "name": "ER_LINE_RL"}, 9297 {"bits": [24, 27], "name": "ER_LINE_TB"}, 9298 {"bits": [28, 31], "name": "ER_LINE_BT"} 9299 ] 9300 }, 9301 "PA_SC_ENHANCE": { 9302 "fields": [ 9303 {"bits": [0, 0], "name": "ENABLE_PA_SC_OUT_OF_ORDER"}, 9304 {"bits": [1, 1], "name": "DISABLE_SC_DB_TILE_FIX"}, 9305 {"bits": [2, 2], "name": "DISABLE_AA_MASK_FULL_FIX"}, 9306 {"bits": [3, 3], "name": "ENABLE_1XMSAA_SAMPLE_LOCATIONS"}, 9307 {"bits": [4, 4], "name": "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID"}, 9308 {"bits": [5, 5], "name": "DISABLE_SCISSOR_FIX"}, 9309 {"bits": [6, 7], "name": "DISABLE_PW_BUBBLE_COLLAPSE"}, 9310 {"bits": [8, 8], "name": "SEND_UNLIT_STILES_TO_PACKER"}, 9311 {"bits": [9, 9], "name": "DISABLE_DUALGRAD_PERF_OPTIMIZATION"}, 9312 {"bits": [10, 10], "name": "DISABLE_SC_PROCESS_RESET_PRIM"}, 9313 {"bits": [11, 11], "name": "DISABLE_SC_PROCESS_RESET_SUPERTILE"}, 9314 {"bits": [12, 12], "name": "DISABLE_SC_PROCESS_RESET_TILE"}, 9315 {"bits": [13, 13], "name": "DISABLE_PA_SC_GUIDANCE"}, 9316 {"bits": [14, 14], "name": "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS"}, 9317 {"bits": [15, 15], "name": "ENABLE_MULTICYCLE_BUBBLE_FREEZE"}, 9318 {"bits": [16, 16], "name": "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE"}, 9319 {"bits": [17, 17], "name": "ENABLE_OUT_OF_ORDER_POLY_MODE"}, 9320 {"bits": [18, 18], "name": "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST"}, 9321 {"bits": [19, 19], "name": "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING"}, 9322 {"bits": [20, 20], "name": "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY"}, 9323 {"bits": [21, 21], "name": "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING"}, 9324 {"bits": [22, 22], "name": "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING"}, 9325 {"bits": [23, 23], "name": "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS"}, 9326 {"bits": [24, 24], "name": "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID"}, 9327 {"bits": [30, 30], "name": "ECO_SPARE1"}, 9328 {"bits": [31, 31], "name": "ECO_SPARE0"} 9329 ] 9330 }, 9331 "PA_SC_FIFO_DEPTH_CNTL": { 9332 "fields": [ 9333 {"bits": [0, 7], "name": "DEPTH"} 9334 ] 9335 }, 9336 "PA_SC_FIFO_SIZE": { 9337 "fields": [ 9338 {"bits": [0, 5], "name": "SC_FRONTEND_PRIM_FIFO_SIZE"}, 9339 {"bits": [6, 14], "name": "SC_BACKEND_PRIM_FIFO_SIZE"}, 9340 {"bits": [15, 20], "name": "SC_HIZ_TILE_FIFO_SIZE"}, 9341 {"bits": [23, 31], "name": "SC_EARLYZ_TILE_FIFO_SIZE"} 9342 ] 9343 }, 9344 "PA_SC_FORCE_EOV_MAX_CNTS": { 9345 "fields": [ 9346 {"bits": [0, 15], "name": "FORCE_EOV_MAX_CLK_CNT"}, 9347 {"bits": [16, 31], "name": "FORCE_EOV_MAX_REZ_CNT"} 9348 ] 9349 }, 9350 "PA_SC_GENERIC_SCISSOR_TL": { 9351 "fields": [ 9352 {"bits": [0, 14], "name": "TL_X"}, 9353 {"bits": [16, 30], "name": "TL_Y"}, 9354 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} 9355 ] 9356 }, 9357 "PA_SC_IF_FIFO_SIZE": { 9358 "fields": [ 9359 {"bits": [0, 5], "name": "SC_DB_TILE_IF_FIFO_SIZE"}, 9360 {"bits": [6, 11], "name": "SC_DB_QUAD_IF_FIFO_SIZE"}, 9361 {"bits": [12, 17], "name": "SC_SPI_IF_FIFO_SIZE"}, 9362 {"bits": [18, 23], "name": "SC_BCI_IF_FIFO_SIZE"} 9363 ] 9364 }, 9365 "PA_SC_LINE_CNTL": { 9366 "fields": [ 9367 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, 9368 {"bits": [10, 10], "name": "LAST_PIXEL"}, 9369 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, 9370 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"} 9371 ] 9372 }, 9373 "PA_SC_LINE_STIPPLE": { 9374 "fields": [ 9375 {"bits": [0, 15], "name": "LINE_PATTERN"}, 9376 {"bits": [16, 23], "name": "REPEAT_COUNT"}, 9377 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, 9378 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} 9379 ] 9380 }, 9381 "PA_SC_LINE_STIPPLE_STATE": { 9382 "fields": [ 9383 {"bits": [0, 3], "name": "CURRENT_PTR"}, 9384 {"bits": [8, 15], "name": "CURRENT_COUNT"} 9385 ] 9386 }, 9387 "PA_SC_MODE_CNTL_0": { 9388 "fields": [ 9389 {"bits": [0, 0], "name": "MSAA_ENABLE"}, 9390 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, 9391 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, 9392 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"} 9393 ] 9394 }, 9395 "PA_SC_MODE_CNTL_1": { 9396 "fields": [ 9397 {"bits": [0, 0], "name": "WALK_SIZE"}, 9398 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, 9399 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, 9400 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, 9401 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, 9402 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, 9403 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, 9404 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, 9405 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, 9406 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, 9407 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, 9408 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, 9409 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, 9410 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, 9411 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, 9412 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, 9413 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, 9414 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, 9415 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, 9416 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, 9417 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, 9418 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, 9419 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, 9420 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} 9421 ] 9422 }, 9423 "PA_SC_PERFCOUNTER0_SELECT": { 9424 "fields": [ 9425 {"bits": [0, 8], "name": "PERF_SEL"}, 9426 {"bits": [10, 19], "name": "PERF_SEL1"}, 9427 {"bits": [20, 23], "name": "CNTR_MODE"} 9428 ] 9429 }, 9430 "PA_SC_PERFCOUNTER1_SELECT": { 9431 "fields": [ 9432 {"bits": [0, 8], "name": "PERF_SEL"} 9433 ] 9434 }, 9435 "PA_SC_RASTER_CONFIG": { 9436 "fields": [ 9437 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, 9438 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, 9439 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, 9440 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, 9441 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, 9442 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, 9443 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, 9444 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, 9445 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, 9446 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, 9447 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, 9448 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, 9449 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, 9450 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, 9451 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} 9452 ] 9453 }, 9454 "PA_SC_SCREEN_SCISSOR_BR": { 9455 "fields": [ 9456 {"bits": [0, 15], "name": "BR_X"}, 9457 {"bits": [16, 31], "name": "BR_Y"} 9458 ] 9459 }, 9460 "PA_SC_SCREEN_SCISSOR_TL": { 9461 "fields": [ 9462 {"bits": [0, 15], "name": "TL_X"}, 9463 {"bits": [16, 31], "name": "TL_Y"} 9464 ] 9465 }, 9466 "PA_SC_WINDOW_OFFSET": { 9467 "fields": [ 9468 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, 9469 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} 9470 ] 9471 }, 9472 "PA_SU_CNTL_STATUS": { 9473 "fields": [ 9474 {"bits": [31, 31], "name": "SU_BUSY"} 9475 ] 9476 }, 9477 "PA_SU_DEBUG_CNTL": { 9478 "fields": [ 9479 {"bits": [0, 4], "name": "SU_DEBUG_INDX"} 9480 ] 9481 }, 9482 "PA_SU_HARDWARE_SCREEN_OFFSET": { 9483 "fields": [ 9484 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, 9485 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} 9486 ] 9487 }, 9488 "PA_SU_LINE_CNTL": { 9489 "fields": [ 9490 {"bits": [0, 15], "name": "WIDTH"} 9491 ] 9492 }, 9493 "PA_SU_LINE_STIPPLE_CNTL": { 9494 "fields": [ 9495 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, 9496 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, 9497 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, 9498 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} 9499 ] 9500 }, 9501 "PA_SU_LINE_STIPPLE_VALUE": { 9502 "fields": [ 9503 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} 9504 ] 9505 }, 9506 "PA_SU_PERFCOUNTER0_HI": { 9507 "fields": [ 9508 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} 9509 ] 9510 }, 9511 "PA_SU_PERFCOUNTER0_SELECT": { 9512 "fields": [ 9513 {"bits": [0, 7], "name": "PERF_SEL"}, 9514 {"bits": [10, 19], "name": "PERF_SEL1"}, 9515 {"bits": [20, 23], "name": "CNTR_MODE"} 9516 ] 9517 }, 9518 "PA_SU_PERFCOUNTER2_SELECT": { 9519 "fields": [ 9520 {"bits": [0, 7], "name": "PERF_SEL"}, 9521 {"bits": [20, 23], "name": "CNTR_MODE"} 9522 ] 9523 }, 9524 "PA_SU_POINT_MINMAX": { 9525 "fields": [ 9526 {"bits": [0, 15], "name": "MIN_SIZE"}, 9527 {"bits": [16, 31], "name": "MAX_SIZE"} 9528 ] 9529 }, 9530 "PA_SU_POINT_SIZE": { 9531 "fields": [ 9532 {"bits": [0, 15], "name": "HEIGHT"}, 9533 {"bits": [16, 31], "name": "WIDTH"} 9534 ] 9535 }, 9536 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": { 9537 "fields": [ 9538 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, 9539 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} 9540 ] 9541 }, 9542 "PA_SU_PRIM_FILTER_CNTL": { 9543 "fields": [ 9544 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, 9545 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, 9546 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, 9547 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, 9548 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, 9549 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, 9550 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, 9551 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, 9552 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, 9553 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, 9554 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} 9555 ] 9556 }, 9557 "PA_SU_SC_MODE_CNTL": { 9558 "fields": [ 9559 {"bits": [0, 0], "name": "CULL_FRONT"}, 9560 {"bits": [1, 1], "name": "CULL_BACK"}, 9561 {"bits": [2, 2], "name": "FACE"}, 9562 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, 9563 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"}, 9564 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"}, 9565 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, 9566 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, 9567 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, 9568 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, 9569 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, 9570 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, 9571 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"} 9572 ] 9573 }, 9574 "PA_SU_VTX_CNTL": { 9575 "fields": [ 9576 {"bits": [0, 0], "name": "PIX_CENTER"}, 9577 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, 9578 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} 9579 ] 9580 }, 9581 "SCRATCH_UMSK": { 9582 "fields": [ 9583 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, 9584 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} 9585 ] 9586 }, 9587 "SPI_BARYC_CNTL": { 9588 "fields": [ 9589 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, 9590 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, 9591 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, 9592 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, 9593 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, 9594 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, 9595 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} 9596 ] 9597 }, 9598 "SPI_CONFIG_CNTL": { 9599 "fields": [ 9600 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, 9601 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, 9602 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, 9603 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, 9604 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, 9605 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"} 9606 ] 9607 }, 9608 "SPI_INTERP_CONTROL_0": { 9609 "fields": [ 9610 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, 9611 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, 9612 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, 9613 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, 9614 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, 9615 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, 9616 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} 9617 ] 9618 }, 9619 "SPI_PS_INPUT_ADDR": { 9620 "fields": [ 9621 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, 9622 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, 9623 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, 9624 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, 9625 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, 9626 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, 9627 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, 9628 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, 9629 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, 9630 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, 9631 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, 9632 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, 9633 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, 9634 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, 9635 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, 9636 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} 9637 ] 9638 }, 9639 "SPI_PS_INPUT_CNTL_0": { 9640 "fields": [ 9641 {"bits": [0, 5], "name": "OFFSET"}, 9642 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 9643 {"bits": [10, 10], "name": "FLAT_SHADE"}, 9644 {"bits": [13, 16], "name": "CYL_WRAP"}, 9645 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, 9646 {"bits": [18, 18], "name": "DUP"} 9647 ] 9648 }, 9649 "SPI_PS_INPUT_CNTL_20": { 9650 "fields": [ 9651 {"bits": [0, 5], "name": "OFFSET"}, 9652 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 9653 {"bits": [10, 10], "name": "FLAT_SHADE"}, 9654 {"bits": [18, 18], "name": "DUP"} 9655 ] 9656 }, 9657 "SPI_PS_IN_CONTROL": { 9658 "fields": [ 9659 {"bits": [0, 5], "name": "NUM_INTERP"}, 9660 {"bits": [6, 6], "name": "PARAM_GEN"}, 9661 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} 9662 ] 9663 }, 9664 "SPI_SHADER_COL_FORMAT": { 9665 "fields": [ 9666 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, 9667 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, 9668 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, 9669 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, 9670 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, 9671 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, 9672 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, 9673 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} 9674 ] 9675 }, 9676 "SPI_SHADER_PGM_HI_ES": { 9677 "fields": [ 9678 {"bits": [0, 7], "name": "MEM_BASE"} 9679 ] 9680 }, 9681 "SPI_SHADER_PGM_RSRC1_ES": { 9682 "fields": [ 9683 {"bits": [0, 5], "name": "VGPRS"}, 9684 {"bits": [6, 9], "name": "SGPRS"}, 9685 {"bits": [10, 11], "name": "PRIORITY"}, 9686 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9687 {"bits": [20, 20], "name": "PRIV"}, 9688 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9689 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9690 {"bits": [23, 23], "name": "IEEE_MODE"}, 9691 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 9692 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, 9693 {"bits": [27, 29], "name": "CACHE_CTL"}, 9694 {"bits": [30, 30], "name": "CDBG_USER"} 9695 ] 9696 }, 9697 "SPI_SHADER_PGM_RSRC1_GS": { 9698 "fields": [ 9699 {"bits": [0, 5], "name": "VGPRS"}, 9700 {"bits": [6, 9], "name": "SGPRS"}, 9701 {"bits": [10, 11], "name": "PRIORITY"}, 9702 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9703 {"bits": [20, 20], "name": "PRIV"}, 9704 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9705 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9706 {"bits": [23, 23], "name": "IEEE_MODE"}, 9707 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, 9708 {"bits": [25, 27], "name": "CACHE_CTL"}, 9709 {"bits": [28, 28], "name": "CDBG_USER"} 9710 ] 9711 }, 9712 "SPI_SHADER_PGM_RSRC1_HS": { 9713 "fields": [ 9714 {"bits": [0, 5], "name": "VGPRS"}, 9715 {"bits": [6, 9], "name": "SGPRS"}, 9716 {"bits": [10, 11], "name": "PRIORITY"}, 9717 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9718 {"bits": [20, 20], "name": "PRIV"}, 9719 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9720 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9721 {"bits": [23, 23], "name": "IEEE_MODE"}, 9722 {"bits": [24, 26], "name": "CACHE_CTL"}, 9723 {"bits": [27, 27], "name": "CDBG_USER"} 9724 ] 9725 }, 9726 "SPI_SHADER_PGM_RSRC1_LS": { 9727 "fields": [ 9728 {"bits": [0, 5], "name": "VGPRS"}, 9729 {"bits": [6, 9], "name": "SGPRS"}, 9730 {"bits": [10, 11], "name": "PRIORITY"}, 9731 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9732 {"bits": [20, 20], "name": "PRIV"}, 9733 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9734 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9735 {"bits": [23, 23], "name": "IEEE_MODE"}, 9736 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 9737 {"bits": [26, 28], "name": "CACHE_CTL"}, 9738 {"bits": [29, 29], "name": "CDBG_USER"} 9739 ] 9740 }, 9741 "SPI_SHADER_PGM_RSRC1_PS": { 9742 "fields": [ 9743 {"bits": [0, 5], "name": "VGPRS"}, 9744 {"bits": [6, 9], "name": "SGPRS"}, 9745 {"bits": [10, 11], "name": "PRIORITY"}, 9746 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9747 {"bits": [20, 20], "name": "PRIV"}, 9748 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9749 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9750 {"bits": [23, 23], "name": "IEEE_MODE"}, 9751 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, 9752 {"bits": [25, 27], "name": "CACHE_CTL"}, 9753 {"bits": [28, 28], "name": "CDBG_USER"} 9754 ] 9755 }, 9756 "SPI_SHADER_PGM_RSRC2_ES": { 9757 "fields": [ 9758 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9759 {"bits": [1, 5], "name": "USER_SGPR"}, 9760 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9761 {"bits": [7, 7], "name": "OC_LDS_EN"}, 9762 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 9763 {"bits": [20, 28], "name": "LDS_SIZE"} 9764 ] 9765 }, 9766 "SPI_SHADER_PGM_RSRC2_GS": { 9767 "fields": [ 9768 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9769 {"bits": [1, 5], "name": "USER_SGPR"}, 9770 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9771 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9772 ] 9773 }, 9774 "SPI_SHADER_PGM_RSRC2_HS": { 9775 "fields": [ 9776 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9777 {"bits": [1, 5], "name": "USER_SGPR"}, 9778 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9779 {"bits": [7, 7], "name": "OC_LDS_EN"}, 9780 {"bits": [8, 8], "name": "TG_SIZE_EN"}, 9781 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9782 ] 9783 }, 9784 "SPI_SHADER_PGM_RSRC2_LS": { 9785 "fields": [ 9786 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9787 {"bits": [1, 5], "name": "USER_SGPR"}, 9788 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9789 {"bits": [7, 15], "name": "LDS_SIZE"}, 9790 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9791 ] 9792 }, 9793 "SPI_SHADER_PGM_RSRC2_PS": { 9794 "fields": [ 9795 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9796 {"bits": [1, 5], "name": "USER_SGPR"}, 9797 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9798 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, 9799 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, 9800 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9801 ] 9802 }, 9803 "SPI_SHADER_PGM_RSRC2_VS": { 9804 "fields": [ 9805 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9806 {"bits": [1, 5], "name": "USER_SGPR"}, 9807 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9808 {"bits": [7, 7], "name": "OC_LDS_EN"}, 9809 {"bits": [8, 8], "name": "SO_BASE0_EN"}, 9810 {"bits": [9, 9], "name": "SO_BASE1_EN"}, 9811 {"bits": [10, 10], "name": "SO_BASE2_EN"}, 9812 {"bits": [11, 11], "name": "SO_BASE3_EN"}, 9813 {"bits": [12, 12], "name": "SO_EN"}, 9814 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9815 ] 9816 }, 9817 "SPI_SHADER_POS_FORMAT": { 9818 "fields": [ 9819 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, 9820 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, 9821 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, 9822 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} 9823 ] 9824 }, 9825 "SPI_SHADER_Z_FORMAT": { 9826 "fields": [ 9827 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} 9828 ] 9829 }, 9830 "SPI_VS_OUT_CONFIG": { 9831 "fields": [ 9832 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, 9833 {"bits": [6, 6], "name": "VS_HALF_PACK"} 9834 ] 9835 }, 9836 "SQC_CACHES": { 9837 "fields": [ 9838 {"bits": [0, 0], "name": "INST_INVALIDATE"}, 9839 {"bits": [1, 1], "name": "DATA_INVALIDATE"}, 9840 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"} 9841 ] 9842 }, 9843 "SQC_CONFIG": { 9844 "fields": [ 9845 {"bits": [0, 1], "name": "INST_CACHE_SIZE"}, 9846 {"bits": [2, 3], "name": "DATA_CACHE_SIZE"}, 9847 {"bits": [4, 5], "name": "MISS_FIFO_DEPTH"}, 9848 {"bits": [6, 6], "name": "HIT_FIFO_DEPTH"}, 9849 {"bits": [7, 7], "name": "FORCE_ALWAYS_MISS"}, 9850 {"bits": [8, 8], "name": "FORCE_IN_ORDER"}, 9851 {"bits": [9, 9], "name": "IDENTITY_HASH_BANK"}, 9852 {"bits": [10, 10], "name": "IDENTITY_HASH_SET"}, 9853 {"bits": [11, 11], "name": "PER_VMID_INV_DISABLE"} 9854 ] 9855 }, 9856 "SQC_SECDED_CNT": { 9857 "fields": [ 9858 {"bits": [0, 7], "name": "INST_SEC"}, 9859 {"bits": [8, 15], "name": "INST_DED"}, 9860 {"bits": [16, 23], "name": "DATA_SEC"}, 9861 {"bits": [24, 31], "name": "DATA_DED"} 9862 ] 9863 }, 9864 "SQ_ALU_CLK_CTRL": { 9865 "fields": [ 9866 {"bits": [0, 15], "name": "FORCE_CU_ON_SH0"}, 9867 {"bits": [16, 31], "name": "FORCE_CU_ON_SH1"} 9868 ] 9869 }, 9870 "SQ_BUF_RSRC_WORD1": { 9871 "fields": [ 9872 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, 9873 {"bits": [16, 29], "name": "STRIDE"}, 9874 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, 9875 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} 9876 ] 9877 }, 9878 "SQ_BUF_RSRC_WORD3": { 9879 "fields": [ 9880 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 9881 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 9882 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 9883 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 9884 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, 9885 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, 9886 {"bits": [19, 20], "name": "ELEMENT_SIZE"}, 9887 {"bits": [21, 22], "name": "INDEX_STRIDE"}, 9888 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, 9889 {"bits": [24, 24], "name": "ATC"}, 9890 {"bits": [25, 25], "name": "HASH_ENABLE"}, 9891 {"bits": [26, 26], "name": "HEAP"}, 9892 {"bits": [27, 29], "name": "MTYPE"}, 9893 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} 9894 ] 9895 }, 9896 "SQ_CONFIG": { 9897 "fields": [ 9898 {"bits": [0, 7], "name": "UNUSED"}, 9899 {"bits": [8, 8], "name": "DEBUG_EN"}, 9900 {"bits": [9, 9], "name": "DISABLE_SCA_BYPASS"}, 9901 {"bits": [10, 10], "name": "DISABLE_IB_DEP_CHECK"}, 9902 {"bits": [11, 11], "name": "ENABLE_SOFT_CLAUSE"}, 9903 {"bits": [12, 12], "name": "EARLY_TA_DONE_DISABLE"}, 9904 {"bits": [13, 13], "name": "DUA_FLAT_LOCK_ENABLE"}, 9905 {"bits": [14, 14], "name": "DUA_LDS_BYPASS_DISABLE"}, 9906 {"bits": [15, 15], "name": "DUA_FLAT_LDS_PINGPONG_DISABLE"} 9907 ] 9908 }, 9909 "SQ_DEBUG_STS_GLOBAL": { 9910 "fields": [ 9911 {"bits": [0, 0], "name": "BUSY"}, 9912 {"bits": [1, 1], "name": "INTERRUPT_MSG_BUSY"}, 9913 {"bits": [4, 15], "name": "WAVE_LEVEL_SH0"}, 9914 {"bits": [16, 27], "name": "WAVE_LEVEL_SH1"} 9915 ] 9916 }, 9917 "SQ_DED_CNT": { 9918 "fields": [ 9919 {"bits": [0, 5], "name": "LDS_DED"}, 9920 {"bits": [8, 12], "name": "SGPR_DED"}, 9921 {"bits": [16, 24], "name": "VGPR_DED"} 9922 ] 9923 }, 9924 "SQ_DED_INFO": { 9925 "fields": [ 9926 {"bits": [0, 3], "name": "WAVE_ID"}, 9927 {"bits": [4, 5], "name": "SIMD_ID"}, 9928 {"bits": [6, 8], "name": "SOURCE"}, 9929 {"bits": [9, 12], "name": "VM_ID"} 9930 ] 9931 }, 9932 "SQ_FIFO_SIZES": { 9933 "fields": [ 9934 {"bits": [0, 3], "name": "INTERRUPT_FIFO_SIZE"}, 9935 {"bits": [8, 11], "name": "TTRACE_FIFO_SIZE"}, 9936 {"bits": [16, 17], "name": "EXPORT_BUF_SIZE"}, 9937 {"bits": [18, 19], "name": "VMEM_DATA_FIFO_SIZE"} 9938 ] 9939 }, 9940 "SQ_IMG_RSRC_WORD1": { 9941 "fields": [ 9942 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, 9943 {"bits": [8, 19], "name": "MIN_LOD"}, 9944 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, 9945 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, 9946 {"bits": [30, 31], "name": "MTYPE"} 9947 ] 9948 }, 9949 "SQ_IMG_RSRC_WORD2": { 9950 "fields": [ 9951 {"bits": [0, 13], "name": "WIDTH"}, 9952 {"bits": [14, 27], "name": "HEIGHT"}, 9953 {"bits": [28, 30], "name": "PERF_MOD"}, 9954 {"bits": [31, 31], "name": "INTERLACED"} 9955 ] 9956 }, 9957 "SQ_IMG_RSRC_WORD3": { 9958 "fields": [ 9959 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 9960 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 9961 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 9962 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 9963 {"bits": [12, 15], "name": "BASE_LEVEL"}, 9964 {"bits": [16, 19], "name": "LAST_LEVEL"}, 9965 {"bits": [20, 24], "name": "TILING_INDEX"}, 9966 {"bits": [25, 25], "name": "POW2_PAD"}, 9967 {"bits": [26, 26], "name": "MTYPE"}, 9968 {"bits": [27, 27], "name": "ATC"}, 9969 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} 9970 ] 9971 }, 9972 "SQ_IMG_RSRC_WORD4": { 9973 "fields": [ 9974 {"bits": [0, 12], "name": "DEPTH"}, 9975 {"bits": [13, 26], "name": "PITCH"} 9976 ] 9977 }, 9978 "SQ_IMG_RSRC_WORD5": { 9979 "fields": [ 9980 {"bits": [0, 12], "name": "BASE_ARRAY"}, 9981 {"bits": [13, 25], "name": "LAST_ARRAY"} 9982 ] 9983 }, 9984 "SQ_IMG_RSRC_WORD6": { 9985 "fields": [ 9986 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, 9987 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, 9988 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, 9989 {"bits": [21, 31], "name": "UNUNSED"} 9990 ] 9991 }, 9992 "SQ_IMG_SAMP_WORD0": { 9993 "fields": [ 9994 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, 9995 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, 9996 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, 9997 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, 9998 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, 9999 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, 10000 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, 10001 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, 10002 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, 10003 {"bits": [21, 26], "name": "ANISO_BIAS"}, 10004 {"bits": [27, 27], "name": "TRUNC_COORD"}, 10005 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, 10006 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} 10007 ] 10008 }, 10009 "SQ_IMG_SAMP_WORD1": { 10010 "fields": [ 10011 {"bits": [0, 11], "name": "MIN_LOD"}, 10012 {"bits": [12, 23], "name": "MAX_LOD"}, 10013 {"bits": [24, 27], "name": "PERF_MIP"}, 10014 {"bits": [28, 31], "name": "PERF_Z"} 10015 ] 10016 }, 10017 "SQ_IMG_SAMP_WORD2": { 10018 "fields": [ 10019 {"bits": [0, 13], "name": "LOD_BIAS"}, 10020 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, 10021 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, 10022 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, 10023 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, 10024 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, 10025 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, 10026 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"}, 10027 {"bits": [30, 30], "name": "FILTER_PREC_FIX"} 10028 ] 10029 }, 10030 "SQ_IMG_SAMP_WORD3": { 10031 "fields": [ 10032 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, 10033 {"bits": [29, 29], "name": "UPGRADED_DEPTH"}, 10034 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} 10035 ] 10036 }, 10037 "SQ_IND_INDEX": { 10038 "fields": [ 10039 {"bits": [0, 3], "name": "WAVE_ID"}, 10040 {"bits": [4, 5], "name": "SIMD_ID"}, 10041 {"bits": [6, 11], "name": "THREAD_ID"}, 10042 {"bits": [12, 12], "name": "AUTO_INCR"}, 10043 {"bits": [13, 13], "name": "FORCE_READ"}, 10044 {"bits": [14, 14], "name": "READ_TIMEOUT"}, 10045 {"bits": [15, 15], "name": "UNINDEXED"}, 10046 {"bits": [16, 31], "name": "INDEX"} 10047 ] 10048 }, 10049 "SQ_INTERRUPT_WORD_AUTO": { 10050 "fields": [ 10051 {"bits": [0, 0], "name": "THREAD_TRACE"}, 10052 {"bits": [1, 1], "name": "WLT"}, 10053 {"bits": [2, 2], "name": "THREAD_TRACE_BUF_FULL"}, 10054 {"bits": [3, 3], "name": "REG_TIMESTAMP"}, 10055 {"bits": [4, 4], "name": "CMD_TIMESTAMP"}, 10056 {"bits": [5, 5], "name": "HOST_CMD_OVERFLOW"}, 10057 {"bits": [6, 6], "name": "HOST_REG_OVERFLOW"}, 10058 {"bits": [7, 7], "name": "IMMED_OVERFLOW"}, 10059 {"bits": [25, 25], "name": "SE_ID"}, 10060 {"bits": [26, 27], "name": "ENCODING"} 10061 ] 10062 }, 10063 "SQ_LB_CTR_CTRL": { 10064 "fields": [ 10065 {"bits": [0, 0], "name": "START"}, 10066 {"bits": [1, 1], "name": "LOAD"}, 10067 {"bits": [2, 2], "name": "CLEAR"} 10068 ] 10069 }, 10070 "SQ_PERFCOUNTER0_SELECT": { 10071 "fields": [ 10072 {"bits": [0, 8], "name": "PERF_SEL"}, 10073 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, 10074 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, 10075 {"bits": [20, 23], "name": "SPM_MODE"}, 10076 {"bits": [24, 27], "name": "SIMD_MASK"}, 10077 {"bits": [28, 31], "name": "PERF_MODE"} 10078 ] 10079 }, 10080 "SQ_PERFCOUNTER_CTRL": { 10081 "fields": [ 10082 {"bits": [0, 0], "name": "PS_EN"}, 10083 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 10084 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 10085 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 10086 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 10087 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 10088 {"bits": [6, 6], "name": "CS_EN"}, 10089 {"bits": [8, 12], "name": "CNTR_RATE"}, 10090 {"bits": [13, 13], "name": "DISABLE_FLUSH"} 10091 ] 10092 }, 10093 "SQ_POWER_THROTTLE": { 10094 "fields": [ 10095 {"bits": [0, 13], "name": "MIN_POWER"}, 10096 {"bits": [16, 29], "name": "MAX_POWER"}, 10097 {"bits": [30, 31], "name": "PHASE_OFFSET"} 10098 ] 10099 }, 10100 "SQ_POWER_THROTTLE2": { 10101 "fields": [ 10102 {"bits": [0, 13], "name": "MAX_POWER_DELTA"}, 10103 {"bits": [16, 25], "name": "SHORT_TERM_INTERVAL_SIZE"}, 10104 {"bits": [27, 30], "name": "LONG_TERM_INTERVAL_RATIO"}, 10105 {"bits": [31, 31], "name": "USE_REF_CLOCK"} 10106 ] 10107 }, 10108 "SQ_RANDOM_WAVE_PRI": { 10109 "fields": [ 10110 {"bits": [0, 6], "name": "RET"}, 10111 {"bits": [7, 9], "name": "RUI"}, 10112 {"bits": [10, 20], "name": "RNG"} 10113 ] 10114 }, 10115 "SQ_REG_CREDITS": { 10116 "fields": [ 10117 {"bits": [0, 5], "name": "SRBM_CREDITS"}, 10118 {"bits": [8, 11], "name": "CMD_CREDITS"}, 10119 {"bits": [28, 28], "name": "REG_BUSY"}, 10120 {"bits": [29, 29], "name": "SRBM_OVERFLOW"}, 10121 {"bits": [30, 30], "name": "IMMED_OVERFLOW"}, 10122 {"bits": [31, 31], "name": "CMD_OVERFLOW"} 10123 ] 10124 }, 10125 "SQ_SEC_CNT": { 10126 "fields": [ 10127 {"bits": [0, 5], "name": "LDS_SEC"}, 10128 {"bits": [8, 12], "name": "SGPR_SEC"}, 10129 {"bits": [16, 24], "name": "VGPR_SEC"} 10130 ] 10131 }, 10132 "SQ_THREAD_TRACE_CTRL": { 10133 "fields": [ 10134 {"bits": [31, 31], "name": "RESET_BUFFER"} 10135 ] 10136 }, 10137 "SQ_THREAD_TRACE_HIWATER": { 10138 "fields": [ 10139 {"bits": [0, 2], "name": "HIWATER"} 10140 ] 10141 }, 10142 "SQ_THREAD_TRACE_MASK": { 10143 "fields": [ 10144 {"bits": [0, 4], "name": "CU_SEL"}, 10145 {"bits": [5, 5], "name": "SH_SEL"}, 10146 {"bits": [7, 7], "name": "REG_STALL_EN"}, 10147 {"bits": [12, 13], "name": "VM_ID_MASK"}, 10148 {"bits": [14, 14], "name": "SPI_STALL_EN"}, 10149 {"bits": [15, 15], "name": "SQ_STALL_EN"}, 10150 {"bits": [16, 31], "name": "RANDOM_SEED"}, 10151 {"bits": [16, 31], "name": "RANDOM_SEED"} 10152 ] 10153 }, 10154 "SQ_THREAD_TRACE_MODE": { 10155 "fields": [ 10156 {"bits": [0, 2], "name": "MASK_PS"}, 10157 {"bits": [3, 5], "name": "MASK_VS"}, 10158 {"bits": [6, 8], "name": "MASK_GS"}, 10159 {"bits": [9, 11], "name": "MASK_ES"}, 10160 {"bits": [12, 14], "name": "MASK_HS"}, 10161 {"bits": [15, 17], "name": "MASK_LS"}, 10162 {"bits": [18, 20], "name": "MASK_CS"}, 10163 {"bits": [21, 22], "name": "MODE"}, 10164 {"bits": [23, 24], "name": "CAPTURE_MODE"}, 10165 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, 10166 {"bits": [26, 26], "name": "PRIV"}, 10167 {"bits": [27, 28], "name": "ISSUE_MASK"}, 10168 {"bits": [29, 29], "name": "TEST_MODE"}, 10169 {"bits": [30, 30], "name": "INTERRUPT_EN"}, 10170 {"bits": [31, 31], "name": "WRAP"} 10171 ] 10172 }, 10173 "SQ_THREAD_TRACE_PERF_MASK": { 10174 "fields": [ 10175 {"bits": [0, 15], "name": "SH0_MASK"}, 10176 {"bits": [16, 31], "name": "SH1_MASK"} 10177 ] 10178 }, 10179 "SQ_THREAD_TRACE_SIZE": { 10180 "fields": [ 10181 {"bits": [0, 21], "name": "SIZE"} 10182 ] 10183 }, 10184 "SQ_THREAD_TRACE_STATUS": { 10185 "fields": [ 10186 {"bits": [0, 2], "name": "FINISH_PENDING"}, 10187 {"bits": [16, 18], "name": "FINISH_DONE"}, 10188 {"bits": [29, 29], "name": "NEW_BUF"}, 10189 {"bits": [30, 30], "name": "BUSY"}, 10190 {"bits": [31, 31], "name": "FULL"} 10191 ] 10192 }, 10193 "SQ_THREAD_TRACE_TOKEN_MASK": { 10194 "fields": [ 10195 {"bits": [0, 15], "name": "TOKEN_MASK"}, 10196 {"bits": [16, 23], "name": "REG_MASK"}, 10197 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} 10198 ] 10199 }, 10200 "SQ_THREAD_TRACE_WPTR": { 10201 "fields": [ 10202 {"bits": [0, 29], "name": "WPTR"}, 10203 {"bits": [30, 31], "name": "READ_OFFSET"} 10204 ] 10205 }, 10206 "SQ_WAVE_GPR_ALLOC": { 10207 "fields": [ 10208 {"bits": [0, 5], "name": "VGPR_BASE"}, 10209 {"bits": [8, 13], "name": "VGPR_SIZE"}, 10210 {"bits": [16, 21], "name": "SGPR_BASE"}, 10211 {"bits": [24, 27], "name": "SGPR_SIZE"} 10212 ] 10213 }, 10214 "SQ_WAVE_HW_ID": { 10215 "fields": [ 10216 {"bits": [0, 3], "name": "WAVE_ID"}, 10217 {"bits": [4, 5], "name": "SIMD_ID"}, 10218 {"bits": [6, 7], "name": "PIPE_ID"}, 10219 {"bits": [8, 11], "name": "CU_ID"}, 10220 {"bits": [12, 12], "name": "SH_ID"}, 10221 {"bits": [13, 13], "name": "SE_ID"}, 10222 {"bits": [16, 19], "name": "TG_ID"}, 10223 {"bits": [20, 23], "name": "VM_ID"}, 10224 {"bits": [24, 26], "name": "QUEUE_ID"}, 10225 {"bits": [27, 29], "name": "STATE_ID"}, 10226 {"bits": [30, 31], "name": "ME_ID"} 10227 ] 10228 }, 10229 "SQ_WAVE_IB_DBG0": { 10230 "fields": [ 10231 {"bits": [0, 2], "name": "IBUF_ST"}, 10232 {"bits": [3, 3], "name": "PC_INVALID"}, 10233 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, 10234 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, 10235 {"bits": [8, 9], "name": "IBUF_RPTR"}, 10236 {"bits": [10, 11], "name": "IBUF_WPTR"}, 10237 {"bits": [16, 18], "name": "INST_STR_ST"}, 10238 {"bits": [19, 21], "name": "MISC_CNT"}, 10239 {"bits": [22, 23], "name": "ECC_ST"}, 10240 {"bits": [24, 24], "name": "IS_HYB"}, 10241 {"bits": [25, 26], "name": "HYB_CNT"}, 10242 {"bits": [27, 27], "name": "KILL"}, 10243 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"} 10244 ] 10245 }, 10246 "SQ_WAVE_IB_STS": { 10247 "fields": [ 10248 {"bits": [0, 3], "name": "VM_CNT"}, 10249 {"bits": [4, 6], "name": "EXP_CNT"}, 10250 {"bits": [8, 12], "name": "LGKM_CNT"}, 10251 {"bits": [13, 15], "name": "VALU_CNT"} 10252 ] 10253 }, 10254 "SQ_WAVE_LDS_ALLOC": { 10255 "fields": [ 10256 {"bits": [0, 7], "name": "LDS_BASE"}, 10257 {"bits": [12, 20], "name": "LDS_SIZE"} 10258 ] 10259 }, 10260 "SQ_WAVE_MODE": { 10261 "fields": [ 10262 {"bits": [0, 3], "name": "FP_ROUND"}, 10263 {"bits": [4, 7], "name": "FP_DENORM"}, 10264 {"bits": [8, 8], "name": "DX10_CLAMP"}, 10265 {"bits": [9, 9], "name": "IEEE"}, 10266 {"bits": [10, 10], "name": "LOD_CLAMPED"}, 10267 {"bits": [11, 11], "name": "DEBUG_EN"}, 10268 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 10269 {"bits": [28, 28], "name": "VSKIP"}, 10270 {"bits": [29, 31], "name": "CSP"} 10271 ] 10272 }, 10273 "SQ_WAVE_PC_HI": { 10274 "fields": [ 10275 {"bits": [0, 7], "name": "PC_HI"} 10276 ] 10277 }, 10278 "SQ_WAVE_STATUS": { 10279 "fields": [ 10280 {"bits": [0, 0], "name": "SCC"}, 10281 {"bits": [1, 2], "name": "SPI_PRIO"}, 10282 {"bits": [3, 4], "name": "WAVE_PRIO"}, 10283 {"bits": [5, 5], "name": "PRIV"}, 10284 {"bits": [6, 6], "name": "TRAP_EN"}, 10285 {"bits": [7, 7], "name": "TTRACE_EN"}, 10286 {"bits": [8, 8], "name": "EXPORT_RDY"}, 10287 {"bits": [9, 9], "name": "EXECZ"}, 10288 {"bits": [10, 10], "name": "VCCZ"}, 10289 {"bits": [11, 11], "name": "IN_TG"}, 10290 {"bits": [12, 12], "name": "IN_BARRIER"}, 10291 {"bits": [13, 13], "name": "HALT"}, 10292 {"bits": [14, 14], "name": "TRAP"}, 10293 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, 10294 {"bits": [16, 16], "name": "VALID"}, 10295 {"bits": [17, 17], "name": "ECC_ERR"}, 10296 {"bits": [18, 18], "name": "SKIP_EXPORT"}, 10297 {"bits": [19, 19], "name": "PERF_EN"}, 10298 {"bits": [20, 20], "name": "COND_DBG_USER"}, 10299 {"bits": [21, 21], "name": "COND_DBG_SYS"}, 10300 {"bits": [22, 22], "name": "DATA_ATC"}, 10301 {"bits": [23, 23], "name": "INST_ATC"}, 10302 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"}, 10303 {"bits": [27, 27], "name": "MUST_EXPORT"} 10304 ] 10305 }, 10306 "SQ_WAVE_TBA_HI": { 10307 "fields": [ 10308 {"bits": [0, 7], "name": "ADDR_HI"} 10309 ] 10310 }, 10311 "SQ_WAVE_TRAPSTS": { 10312 "fields": [ 10313 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"}, 10314 {"bits": [16, 21], "name": "EXCP_CYCLE"}, 10315 {"bits": [29, 31], "name": "DP_RATE"} 10316 ] 10317 }, 10318 "VGT_CACHE_INVALIDATION": { 10319 "fields": [ 10320 {"bits": [0, 1], "name": "CACHE_INVALIDATION"}, 10321 {"bits": [5, 5], "name": "VS_NO_EXTRA_BUFFER"}, 10322 {"bits": [6, 7], "name": "AUTO_INVLD_EN"}, 10323 {"bits": [9, 9], "name": "USE_GS_DONE"}, 10324 {"bits": [11, 11], "name": "DIS_RANGE_FULL_INVLD"}, 10325 {"bits": [12, 12], "name": "GS_LATE_ALLOC_EN"}, 10326 {"bits": [13, 13], "name": "STREAMOUT_FULL_FLUSH"}, 10327 {"bits": [16, 20], "name": "ES_LIMIT"} 10328 ] 10329 }, 10330 "VGT_CNTL_STATUS": { 10331 "fields": [ 10332 {"bits": [0, 0], "name": "VGT_BUSY"}, 10333 {"bits": [1, 1], "name": "VGT_OUT_INDX_BUSY"}, 10334 {"bits": [2, 2], "name": "VGT_OUT_BUSY"}, 10335 {"bits": [3, 3], "name": "VGT_PT_BUSY"}, 10336 {"bits": [4, 4], "name": "VGT_TE_BUSY"}, 10337 {"bits": [5, 5], "name": "VGT_VR_BUSY"}, 10338 {"bits": [6, 6], "name": "VGT_PI_BUSY"}, 10339 {"bits": [7, 7], "name": "VGT_GS_BUSY"}, 10340 {"bits": [8, 8], "name": "VGT_HS_BUSY"}, 10341 {"bits": [9, 9], "name": "VGT_TE11_BUSY"} 10342 ] 10343 }, 10344 "VGT_DEBUG_CNTL": { 10345 "fields": [ 10346 {"bits": [0, 5], "name": "VGT_DEBUG_INDX"}, 10347 {"bits": [6, 6], "name": "VGT_DEBUG_SEL_BUS_B"} 10348 ] 10349 }, 10350 "VGT_DMA_BASE_HI": { 10351 "fields": [ 10352 {"bits": [0, 7], "name": "BASE_ADDR"} 10353 ] 10354 }, 10355 "VGT_DMA_DATA_FIFO_DEPTH": { 10356 "fields": [ 10357 {"bits": [0, 8], "name": "DMA_DATA_FIFO_DEPTH"} 10358 ] 10359 }, 10360 "VGT_DMA_INDEX_TYPE": { 10361 "fields": [ 10362 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, 10363 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, 10364 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, 10365 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 10366 {"bits": [8, 8], "name": "ATC"}, 10367 {"bits": [9, 9], "name": "NOT_EOP"}, 10368 {"bits": [10, 10], "name": "REQ_PATH"} 10369 ] 10370 }, 10371 "VGT_DMA_REQ_FIFO_DEPTH": { 10372 "fields": [ 10373 {"bits": [0, 5], "name": "DMA_REQ_FIFO_DEPTH"} 10374 ] 10375 }, 10376 "VGT_DRAW_INITIATOR": { 10377 "fields": [ 10378 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, 10379 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, 10380 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, 10381 {"bits": [5, 5], "name": "NOT_EOP"}, 10382 {"bits": [6, 6], "name": "USE_OPAQUE"} 10383 ] 10384 }, 10385 "VGT_DRAW_INIT_FIFO_DEPTH": { 10386 "fields": [ 10387 {"bits": [0, 5], "name": "DRAW_INIT_FIFO_DEPTH"} 10388 ] 10389 }, 10390 "VGT_ESGS_RING_ITEMSIZE": { 10391 "fields": [ 10392 {"bits": [0, 14], "name": "ITEMSIZE"} 10393 ] 10394 }, 10395 "VGT_ES_PER_GS": { 10396 "fields": [ 10397 {"bits": [0, 10], "name": "ES_PER_GS"} 10398 ] 10399 }, 10400 "VGT_EVENT_ADDRESS_REG": { 10401 "fields": [ 10402 {"bits": [0, 27], "name": "ADDRESS_LOW"} 10403 ] 10404 }, 10405 "VGT_EVENT_INITIATOR": { 10406 "fields": [ 10407 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, 10408 {"bits": [18, 26], "name": "ADDRESS_HI"}, 10409 {"bits": [27, 27], "name": "EXTENDED_EVENT"} 10410 ] 10411 }, 10412 "VGT_FIFO_DEPTHS": { 10413 "fields": [ 10414 {"bits": [0, 6], "name": "VS_DEALLOC_TBL_DEPTH"}, 10415 {"bits": [7, 7], "name": "RESERVED_0"}, 10416 {"bits": [8, 21], "name": "CLIPP_FIFO_DEPTH"}, 10417 {"bits": [22, 31], "name": "RESERVED_1"} 10418 ] 10419 }, 10420 "VGT_GROUP_DECR": { 10421 "fields": [ 10422 {"bits": [0, 3], "name": "DECR"} 10423 ] 10424 }, 10425 "VGT_GROUP_FIRST_DECR": { 10426 "fields": [ 10427 {"bits": [0, 3], "name": "FIRST_DECR"} 10428 ] 10429 }, 10430 "VGT_GROUP_PRIM_TYPE": { 10431 "fields": [ 10432 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, 10433 {"bits": [14, 14], "name": "RETAIN_ORDER"}, 10434 {"bits": [15, 15], "name": "RETAIN_QUADS"}, 10435 {"bits": [16, 18], "name": "PRIM_ORDER"} 10436 ] 10437 }, 10438 "VGT_GROUP_VECT_0_CNTL": { 10439 "fields": [ 10440 {"bits": [0, 0], "name": "COMP_X_EN"}, 10441 {"bits": [1, 1], "name": "COMP_Y_EN"}, 10442 {"bits": [2, 2], "name": "COMP_Z_EN"}, 10443 {"bits": [3, 3], "name": "COMP_W_EN"}, 10444 {"bits": [8, 15], "name": "STRIDE"}, 10445 {"bits": [16, 23], "name": "SHIFT"} 10446 ] 10447 }, 10448 "VGT_GROUP_VECT_0_FMT_CNTL": { 10449 "fields": [ 10450 {"bits": [0, 3], "name": "X_CONV"}, 10451 {"bits": [4, 7], "name": "X_OFFSET"}, 10452 {"bits": [8, 11], "name": "Y_CONV"}, 10453 {"bits": [12, 15], "name": "Y_OFFSET"}, 10454 {"bits": [16, 19], "name": "Z_CONV"}, 10455 {"bits": [20, 23], "name": "Z_OFFSET"}, 10456 {"bits": [24, 27], "name": "W_CONV"}, 10457 {"bits": [28, 31], "name": "W_OFFSET"} 10458 ] 10459 }, 10460 "VGT_GSVS_RING_OFFSET_1": { 10461 "fields": [ 10462 {"bits": [0, 14], "name": "OFFSET"} 10463 ] 10464 }, 10465 "VGT_GS_INSTANCE_CNT": { 10466 "fields": [ 10467 {"bits": [0, 0], "name": "ENABLE"}, 10468 {"bits": [2, 8], "name": "CNT"} 10469 ] 10470 }, 10471 "VGT_GS_MAX_VERT_OUT": { 10472 "fields": [ 10473 {"bits": [0, 10], "name": "MAX_VERT_OUT"} 10474 ] 10475 }, 10476 "VGT_GS_MODE": { 10477 "fields": [ 10478 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, 10479 {"bits": [3, 3], "name": "RESERVED_0"}, 10480 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, 10481 {"bits": [6, 10], "name": "RESERVED_1"}, 10482 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, 10483 {"bits": [12, 12], "name": "RESERVED_2"}, 10484 {"bits": [13, 13], "name": "ES_PASSTHRU"}, 10485 {"bits": [14, 14], "name": "COMPUTE_MODE"}, 10486 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, 10487 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, 10488 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, 10489 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, 10490 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, 10491 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, 10492 {"bits": [21, 22], "name": "ONCHIP"} 10493 ] 10494 }, 10495 "VGT_GS_OUT_PRIM_TYPE": { 10496 "fields": [ 10497 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, 10498 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, 10499 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, 10500 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, 10501 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} 10502 ] 10503 }, 10504 "VGT_GS_PER_ES": { 10505 "fields": [ 10506 {"bits": [0, 10], "name": "GS_PER_ES"} 10507 ] 10508 }, 10509 "VGT_GS_PER_VS": { 10510 "fields": [ 10511 {"bits": [0, 3], "name": "GS_PER_VS"} 10512 ] 10513 }, 10514 "VGT_GS_VERTEX_REUSE": { 10515 "fields": [ 10516 {"bits": [0, 4], "name": "VERT_REUSE"} 10517 ] 10518 }, 10519 "VGT_HOS_CNTL": { 10520 "fields": [ 10521 {"bits": [0, 1], "name": "TESS_MODE"} 10522 ] 10523 }, 10524 "VGT_HOS_REUSE_DEPTH": { 10525 "fields": [ 10526 {"bits": [0, 7], "name": "REUSE_DEPTH"} 10527 ] 10528 }, 10529 "VGT_HS_OFFCHIP_PARAM": { 10530 "fields": [ 10531 {"bits": [0, 6], "name": "OFFCHIP_BUFFERING"}, 10532 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"} 10533 ] 10534 }, 10535 "VGT_INDEX_TYPE": { 10536 "fields": [ 10537 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} 10538 ] 10539 }, 10540 "VGT_LAST_COPY_STATE": { 10541 "fields": [ 10542 {"bits": [0, 2], "name": "SRC_STATE_ID"}, 10543 {"bits": [16, 18], "name": "DST_STATE_ID"} 10544 ] 10545 }, 10546 "VGT_LS_HS_CONFIG": { 10547 "fields": [ 10548 {"bits": [0, 7], "name": "NUM_PATCHES"}, 10549 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, 10550 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} 10551 ] 10552 }, 10553 "VGT_MC_LAT_CNTL": { 10554 "fields": [ 10555 {"bits": [0, 1], "name": "MC_TIME_STAMP_RES"} 10556 ] 10557 }, 10558 "VGT_MULTI_PRIM_IB_RESET_EN": { 10559 "fields": [ 10560 {"bits": [0, 0], "name": "RESET_EN"} 10561 ] 10562 }, 10563 "VGT_OUTPUT_PATH_CNTL": { 10564 "fields": [ 10565 {"bits": [0, 2], "name": "PATH_SELECT"} 10566 ] 10567 }, 10568 "VGT_OUT_DEALLOC_CNTL": { 10569 "fields": [ 10570 {"bits": [0, 6], "name": "DEALLOC_DIST"} 10571 ] 10572 }, 10573 "VGT_PERFCOUNTER_SEID_MASK": { 10574 "fields": [ 10575 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} 10576 ] 10577 }, 10578 "VGT_PRIMITIVEID_EN": { 10579 "fields": [ 10580 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, 10581 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"} 10582 ] 10583 }, 10584 "VGT_PRIMITIVE_TYPE": { 10585 "fields": [ 10586 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} 10587 ] 10588 }, 10589 "VGT_REUSE_OFF": { 10590 "fields": [ 10591 {"bits": [0, 0], "name": "REUSE_OFF"} 10592 ] 10593 }, 10594 "VGT_SHADER_STAGES_EN": { 10595 "fields": [ 10596 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 10597 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 10598 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 10599 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 10600 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 10601 {"bits": [8, 8], "name": "DYNAMIC_HS"} 10602 ] 10603 }, 10604 "VGT_STRMOUT_BUFFER_CONFIG": { 10605 "fields": [ 10606 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, 10607 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, 10608 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, 10609 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} 10610 ] 10611 }, 10612 "VGT_STRMOUT_CONFIG": { 10613 "fields": [ 10614 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, 10615 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, 10616 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, 10617 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, 10618 {"bits": [4, 6], "name": "RAST_STREAM"}, 10619 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, 10620 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} 10621 ] 10622 }, 10623 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": { 10624 "fields": [ 10625 {"bits": [0, 8], "name": "VERTEX_STRIDE"} 10626 ] 10627 }, 10628 "VGT_STRMOUT_VTX_STRIDE_0": { 10629 "fields": [ 10630 {"bits": [0, 9], "name": "STRIDE"} 10631 ] 10632 }, 10633 "VGT_SYS_CONFIG": { 10634 "fields": [ 10635 {"bits": [0, 0], "name": "DUAL_CORE_EN"}, 10636 {"bits": [1, 6], "name": "MAX_LS_HS_THDGRP"}, 10637 {"bits": [7, 7], "name": "ADC_EVENT_FILTER_DISABLE"} 10638 ] 10639 }, 10640 "VGT_TF_PARAM": { 10641 "fields": [ 10642 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, 10643 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, 10644 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, 10645 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, 10646 {"bits": [9, 9], "name": "DEPRECATED"}, 10647 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, 10648 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, 10649 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} 10650 ] 10651 }, 10652 "VGT_TF_RING_SIZE": { 10653 "fields": [ 10654 {"bits": [0, 15], "name": "SIZE"} 10655 ] 10656 }, 10657 "VGT_VERTEX_REUSE_BLOCK_CNTL": { 10658 "fields": [ 10659 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} 10660 ] 10661 }, 10662 "VGT_VTX_CNT_EN": { 10663 "fields": [ 10664 {"bits": [0, 0], "name": "VTX_CNT_EN"} 10665 ] 10666 }, 10667 "VGT_VTX_VECT_EJECT_REG": { 10668 "fields": [ 10669 {"bits": [0, 9], "name": "PRIM_COUNT"} 10670 ] 10671 } 10672 } 10673} 10674