1{
2 "enums": {
3  "BinMapMode": {
4   "entries": [
5    {"name": "BIN_MAP_MODE_NONE", "value": 0},
6    {"name": "BIN_MAP_MODE_RTA_INDEX", "value": 1},
7    {"name": "BIN_MAP_MODE_POPS", "value": 2}
8   ]
9  },
10  "BinSizeExtend": {
11   "entries": [
12    {"name": "BIN_SIZE_32_PIXELS", "value": 0},
13    {"name": "BIN_SIZE_64_PIXELS", "value": 1},
14    {"name": "BIN_SIZE_128_PIXELS", "value": 2},
15    {"name": "BIN_SIZE_256_PIXELS", "value": 3},
16    {"name": "BIN_SIZE_512_PIXELS", "value": 4}
17   ]
18  },
19  "BinningMode": {
20   "entries": [
21    {"name": "BINNING_ALLOWED", "value": 0},
22    {"name": "FORCE_BINNING_ON", "value": 1},
23    {"name": "DISABLE_BINNING_USE_NEW_SC", "value": 2},
24    {"name": "DISABLE_BINNING_USE_LEGACY_SC", "value": 3}
25   ]
26  },
27  "BlendOp": {
28   "entries": [
29    {"name": "BLEND_ZERO", "value": 0},
30    {"name": "BLEND_ONE", "value": 1},
31    {"name": "BLEND_SRC_COLOR", "value": 2},
32    {"name": "BLEND_ONE_MINUS_SRC_COLOR", "value": 3},
33    {"name": "BLEND_SRC_ALPHA", "value": 4},
34    {"name": "BLEND_ONE_MINUS_SRC_ALPHA", "value": 5},
35    {"name": "BLEND_DST_ALPHA", "value": 6},
36    {"name": "BLEND_ONE_MINUS_DST_ALPHA", "value": 7},
37    {"name": "BLEND_DST_COLOR", "value": 8},
38    {"name": "BLEND_ONE_MINUS_DST_COLOR", "value": 9},
39    {"name": "BLEND_SRC_ALPHA_SATURATE", "value": 10},
40    {"name": "BLEND_CONSTANT_COLOR", "value": 11},
41    {"name": "BLEND_ONE_MINUS_CONSTANT_COLOR", "value": 12},
42    {"name": "BLEND_SRC1_COLOR", "value": 13},
43    {"name": "BLEND_INV_SRC1_COLOR", "value": 14},
44    {"name": "BLEND_SRC1_ALPHA", "value": 15},
45    {"name": "BLEND_INV_SRC1_ALPHA", "value": 16},
46    {"name": "BLEND_CONSTANT_ALPHA", "value": 17},
47    {"name": "BLEND_ONE_MINUS_CONSTANT_ALPHA", "value": 18}
48   ]
49  },
50  "BlendOpt": {
51   "entries": [
52    {"name": "FORCE_OPT_AUTO", "value": 0},
53    {"name": "FORCE_OPT_DISABLE", "value": 1},
54    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_0", "value": 2},
55    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_0", "value": 3},
56    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_0", "value": 4},
57    {"name": "FORCE_OPT_ENABLE_IF_SRC_A_1", "value": 5},
58    {"name": "FORCE_OPT_ENABLE_IF_SRC_RGB_1", "value": 6},
59    {"name": "FORCE_OPT_ENABLE_IF_SRC_ARGB_1", "value": 7}
60   ]
61  },
62  "CBMode": {
63   "entries": [
64    {"name": "CB_DISABLE", "value": 0},
65    {"name": "CB_NORMAL", "value": 1},
66    {"name": "CB_ELIMINATE_FAST_CLEAR", "value": 2},
67    {"name": "CB_DCC_DECOMPRESS", "value": 3},
68    {"name": "CB_RESERVED", "value": 4}
69   ]
70  },
71  "CBPerfClearFilterSel": {
72   "entries": [
73    {"name": "CB_PERF_CLEAR_FILTER_SEL_NONCLEAR", "value": 0},
74    {"name": "CB_PERF_CLEAR_FILTER_SEL_CLEAR", "value": 1}
75   ]
76  },
77  "CBPerfOpFilterSel": {
78   "entries": [
79    {"name": "CB_PERF_OP_FILTER_SEL_WRITE_ONLY", "value": 0},
80    {"name": "CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION", "value": 1},
81    {"name": "CB_PERF_OP_FILTER_SEL_RESOLVE", "value": 2},
82    {"name": "CB_PERF_OP_FILTER_SEL_DECOMPRESS", "value": 3},
83    {"name": "CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS", "value": 4},
84    {"name": "CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR", "value": 5}
85   ]
86  },
87  "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE": {
88   "entries": [
89    {"name": "MAX_BLOCK_SIZE_64B", "value": 0},
90    {"name": "MAX_BLOCK_SIZE_128B", "value": 1},
91    {"name": "MAX_BLOCK_SIZE_256B", "value": 2}
92   ]
93  },
94  "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE": {
95   "entries": [
96    {"name": "MIN_BLOCK_SIZE_32B", "value": 0},
97    {"name": "MIN_BLOCK_SIZE_64B", "value": 1}
98   ]
99  },
100  "CLIP_RULE": {
101   "entries": [
102    {"name": "OUT", "value": 1},
103    {"name": "IN_0", "value": 2},
104    {"name": "IN_1", "value": 4},
105    {"name": "IN_10", "value": 8},
106    {"name": "IN_2", "value": 16},
107    {"name": "IN_20", "value": 32},
108    {"name": "IN_21", "value": 64},
109    {"name": "IN_210", "value": 128},
110    {"name": "IN_3", "value": 256},
111    {"name": "IN_30", "value": 512},
112    {"name": "IN_31", "value": 1024},
113    {"name": "IN_310", "value": 2048},
114    {"name": "IN_32", "value": 4096},
115    {"name": "IN_320", "value": 8192},
116    {"name": "IN_321", "value": 16384},
117    {"name": "IN_3210", "value": 32768}
118   ]
119  },
120  "CP_PERFMON_ENABLE_MODE": {
121   "entries": [
122    {"name": "CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT", "value": 0},
123    {"name": "CP_PERFMON_ENABLE_MODE_RESERVED_1", "value": 1},
124    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE", "value": 2},
125    {"name": "CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE", "value": 3}
126   ]
127  },
128  "CP_PERFMON_STATE": {
129   "entries": [
130    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
131    {"name": "CP_PERFMON_STATE_START_COUNTING", "value": 1},
132    {"name": "CP_PERFMON_STATE_STOP_COUNTING", "value": 2},
133    {"name": "CP_PERFMON_STATE_RESERVED_3", "value": 3},
134    {"name": "CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
135    {"name": "CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
136   ]
137  },
138  "ColorFormat": {
139   "entries": [
140    {"name": "COLOR_INVALID", "value": 0},
141    {"name": "COLOR_8", "value": 1},
142    {"name": "COLOR_16", "value": 2},
143    {"name": "COLOR_8_8", "value": 3},
144    {"name": "COLOR_32", "value": 4},
145    {"name": "COLOR_16_16", "value": 5},
146    {"name": "COLOR_10_11_11", "value": 6},
147    {"name": "COLOR_11_11_10", "value": 7},
148    {"name": "COLOR_10_10_10_2", "value": 8},
149    {"name": "COLOR_2_10_10_10", "value": 9},
150    {"name": "COLOR_8_8_8_8", "value": 10},
151    {"name": "COLOR_32_32", "value": 11},
152    {"name": "COLOR_16_16_16_16", "value": 12},
153    {"name": "COLOR_32_32_32_32", "value": 14},
154    {"name": "COLOR_5_6_5", "value": 16},
155    {"name": "COLOR_1_5_5_5", "value": 17},
156    {"name": "COLOR_5_5_5_1", "value": 18},
157    {"name": "COLOR_4_4_4_4", "value": 19},
158    {"name": "COLOR_8_24", "value": 20},
159    {"name": "COLOR_24_8", "value": 21},
160    {"name": "COLOR_X24_8_32_FLOAT", "value": 22},
161    {"name": "COLOR_5_9_9_9", "value": 24}
162   ]
163  },
164  "CombFunc": {
165   "entries": [
166    {"name": "COMB_DST_PLUS_SRC", "value": 0},
167    {"name": "COMB_SRC_MINUS_DST", "value": 1},
168    {"name": "COMB_MIN_DST_SRC", "value": 2},
169    {"name": "COMB_MAX_DST_SRC", "value": 3},
170    {"name": "COMB_DST_MINUS_SRC", "value": 4}
171   ]
172  },
173  "CompareFrag": {
174   "entries": [
175    {"name": "FRAG_NEVER", "value": 0},
176    {"name": "FRAG_LESS", "value": 1},
177    {"name": "FRAG_EQUAL", "value": 2},
178    {"name": "FRAG_LEQUAL", "value": 3},
179    {"name": "FRAG_GREATER", "value": 4},
180    {"name": "FRAG_NOTEQUAL", "value": 5},
181    {"name": "FRAG_GEQUAL", "value": 6},
182    {"name": "FRAG_ALWAYS", "value": 7}
183   ]
184  },
185  "ConservativeZExport": {
186   "entries": [
187    {"name": "EXPORT_ANY_Z", "value": 0},
188    {"name": "EXPORT_LESS_THAN_Z", "value": 1},
189    {"name": "EXPORT_GREATER_THAN_Z", "value": 2},
190    {"name": "EXPORT_RESERVED", "value": 3}
191   ]
192  },
193  "CovToShaderSel": {
194   "entries": [
195    {"name": "INPUT_COVERAGE", "value": 0},
196    {"name": "INPUT_INNER_COVERAGE", "value": 1},
197    {"name": "INPUT_DEPTH_COVERAGE", "value": 2},
198    {"name": "RAW", "value": 3}
199   ]
200  },
201  "DbPRTFaultBehavior": {
202   "entries": [
203    {"name": "FAULT_ZERO", "value": 0},
204    {"name": "FAULT_ONE", "value": 1},
205    {"name": "FAULT_FAIL", "value": 2},
206    {"name": "FAULT_PASS", "value": 3}
207   ]
208  },
209  "DbPSLControl": {
210   "entries": [
211    {"name": "PSLC_AUTO", "value": 0},
212    {"name": "PSLC_ON_HANG_ONLY", "value": 1},
213    {"name": "PSLC_ASAP", "value": 2},
214    {"name": "PSLC_COUNTDOWN", "value": 3}
215   ]
216  },
217  "EXCP_EN": {
218   "entries": [
219    {"name": "INVALID", "value": 1},
220    {"name": "INPUT_DENORMAL", "value": 2},
221    {"name": "DIVIDE_BY_ZERO", "value": 4},
222    {"name": "OVERFLOW", "value": 8},
223    {"name": "UNDERFLOW", "value": 16},
224    {"name": "INEXACT", "value": 32},
225    {"name": "INT_DIVIDE_BY_ZERO", "value": 64},
226    {"name": "ADDRESS_WATCH", "value": 128},
227    {"name": "MEMORY_VIOLATION", "value": 256}
228   ]
229  },
230  "FLOAT_MODE": {
231   "entries": [
232    {"name": "FP_32_ROUND_TOWARDS_ZERO", "value": 3},
233    {"name": "FP_16_64_ROUND_TOWARDS_ZERO", "value": 12},
234    {"name": "FP_32_DENORMS", "value": 48},
235    {"name": "FP_16_64_DENORMS", "value": 192}
236   ]
237  },
238  "ForceControl": {
239   "entries": [
240    {"name": "FORCE_OFF", "value": 0},
241    {"name": "FORCE_ENABLE", "value": 1},
242    {"name": "FORCE_DISABLE", "value": 2},
243    {"name": "FORCE_RESERVED", "value": 3}
244   ]
245  },
246  "OreoMode": {
247   "entries": [
248    {"name": "OMODE_BLEND", "value": 0},
249    {"name": "OMODE_O_THEN_B", "value": 1},
250    {"name": "OMODE_P_THEN_O_THEN_B", "value": 2},
251    {"name": "OMODE_RESERVED_3", "value": 3}
252   ]
253  },
254  "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": {
255   "entries": [
256    {"name": "X_DRAW_POINTS", "value": 0},
257    {"name": "X_DRAW_LINES", "value": 1},
258    {"name": "X_DRAW_TRIANGLES", "value": 2}
259   ]
260  },
261  "PA_SU_SC_MODE_CNTL__POLY_MODE": {
262   "entries": [
263    {"name": "X_DISABLE_POLY_MODE", "value": 0},
264    {"name": "X_DUAL_MODE", "value": 1}
265   ]
266  },
267  "PA_SU_VTX_CNTL__ROUND_MODE": {
268   "entries": [
269    {"name": "X_TRUNCATE", "value": 0},
270    {"name": "X_ROUND", "value": 1},
271    {"name": "X_ROUND_TO_EVEN", "value": 2},
272    {"name": "X_ROUND_TO_ODD", "value": 3}
273   ]
274  },
275  "PkrMap": {
276   "entries": [
277    {"name": "RASTER_CONFIG_PKR_MAP_0", "value": 0},
278    {"name": "RASTER_CONFIG_PKR_MAP_1", "value": 1},
279    {"name": "RASTER_CONFIG_PKR_MAP_2", "value": 2},
280    {"name": "RASTER_CONFIG_PKR_MAP_3", "value": 3}
281   ]
282  },
283  "PkrXsel": {
284   "entries": [
285    {"name": "RASTER_CONFIG_PKR_XSEL_0", "value": 0},
286    {"name": "RASTER_CONFIG_PKR_XSEL_1", "value": 1},
287    {"name": "RASTER_CONFIG_PKR_XSEL_2", "value": 2},
288    {"name": "RASTER_CONFIG_PKR_XSEL_3", "value": 3}
289   ]
290  },
291  "PkrXsel2": {
292   "entries": [
293    {"name": "RASTER_CONFIG_PKR_XSEL2_0", "value": 0},
294    {"name": "RASTER_CONFIG_PKR_XSEL2_1", "value": 1},
295    {"name": "RASTER_CONFIG_PKR_XSEL2_2", "value": 2},
296    {"name": "RASTER_CONFIG_PKR_XSEL2_3", "value": 3}
297   ]
298  },
299  "PkrYsel": {
300   "entries": [
301    {"name": "RASTER_CONFIG_PKR_YSEL_0", "value": 0},
302    {"name": "RASTER_CONFIG_PKR_YSEL_1", "value": 1},
303    {"name": "RASTER_CONFIG_PKR_YSEL_2", "value": 2},
304    {"name": "RASTER_CONFIG_PKR_YSEL_3", "value": 3}
305   ]
306  },
307  "QUANT_MODE": {
308   "entries": [
309    {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0},
310    {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1},
311    {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2},
312    {"name": "X_16_8_FIXED_POINT_1_2", "value": 3},
313    {"name": "X_16_8_FIXED_POINT_1", "value": 4},
314    {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5},
315    {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6},
316    {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7}
317   ]
318  },
319  "ROP3": {
320   "entries": [
321    {"name": "ROP3_CLEAR", "value": 0},
322    {"name": "X_0X05", "value": 5},
323    {"name": "X_0X0A", "value": 10},
324    {"name": "X_0X0F", "value": 15},
325    {"name": "ROP3_NOR", "value": 17},
326    {"name": "ROP3_AND_INVERTED", "value": 34},
327    {"name": "ROP3_COPY_INVERTED", "value": 51},
328    {"name": "ROP3_AND_REVERSE", "value": 68},
329    {"name": "X_0X50", "value": 80},
330    {"name": "ROP3_INVERT", "value": 85},
331    {"name": "X_0X5A", "value": 90},
332    {"name": "X_0X5F", "value": 95},
333    {"name": "ROP3_XOR", "value": 102},
334    {"name": "ROP3_NAND", "value": 119},
335    {"name": "ROP3_AND", "value": 136},
336    {"name": "ROP3_EQUIVALENT", "value": 153},
337    {"name": "X_0XA0", "value": 160},
338    {"name": "X_0XA5", "value": 165},
339    {"name": "ROP3_NO_OP", "value": 170},
340    {"name": "X_0XAF", "value": 175},
341    {"name": "ROP3_OR_INVERTED", "value": 187},
342    {"name": "ROP3_COPY", "value": 204},
343    {"name": "ROP3_OR_REVERSE", "value": 221},
344    {"name": "ROP3_OR", "value": 238},
345    {"name": "X_0XF0", "value": 240},
346    {"name": "X_0XF5", "value": 245},
347    {"name": "X_0XFA", "value": 250},
348    {"name": "ROP3_SET", "value": 255}
349   ]
350  },
351  "RbMap": {
352   "entries": [
353    {"name": "RASTER_CONFIG_RB_MAP_0", "value": 0},
354    {"name": "RASTER_CONFIG_RB_MAP_1", "value": 1},
355    {"name": "RASTER_CONFIG_RB_MAP_2", "value": 2},
356    {"name": "RASTER_CONFIG_RB_MAP_3", "value": 3}
357   ]
358  },
359  "RbXsel": {
360   "entries": [
361    {"name": "RASTER_CONFIG_RB_XSEL_0", "value": 0},
362    {"name": "RASTER_CONFIG_RB_XSEL_1", "value": 1}
363   ]
364  },
365  "RbXsel2": {
366   "entries": [
367    {"name": "RASTER_CONFIG_RB_XSEL2_0", "value": 0},
368    {"name": "RASTER_CONFIG_RB_XSEL2_1", "value": 1},
369    {"name": "RASTER_CONFIG_RB_XSEL2_2", "value": 2},
370    {"name": "RASTER_CONFIG_RB_XSEL2_3", "value": 3}
371   ]
372  },
373  "RbYsel": {
374   "entries": [
375    {"name": "RASTER_CONFIG_RB_YSEL_0", "value": 0},
376    {"name": "RASTER_CONFIG_RB_YSEL_1", "value": 1}
377   ]
378  },
379  "ReadPolicy": {
380   "entries": [
381    {"name": "CACHE_LRU_RD", "value": 0},
382    {"name": "CACHE_STREAM_RD", "value": 1},
383    {"name": "CACHE_NOA", "value": 2},
384    {"name": "RESERVED_RDPOLICY", "value": 3}
385   ]
386  },
387  "SPI_PNT_SPRITE_OVERRIDE": {
388   "entries": [
389    {"name": "SPI_PNT_SPRITE_SEL_0", "value": 0},
390    {"name": "SPI_PNT_SPRITE_SEL_1", "value": 1},
391    {"name": "SPI_PNT_SPRITE_SEL_S", "value": 2},
392    {"name": "SPI_PNT_SPRITE_SEL_T", "value": 3},
393    {"name": "SPI_PNT_SPRITE_SEL_NONE", "value": 4}
394   ]
395  },
396  "SPI_SHADER_EX_FORMAT": {
397   "entries": [
398    {"name": "SPI_SHADER_ZERO", "value": 0},
399    {"name": "SPI_SHADER_32_R", "value": 1},
400    {"name": "SPI_SHADER_32_GR", "value": 2},
401    {"name": "SPI_SHADER_32_AR", "value": 3},
402    {"name": "SPI_SHADER_FP16_ABGR", "value": 4},
403    {"name": "SPI_SHADER_UNORM16_ABGR", "value": 5},
404    {"name": "SPI_SHADER_SNORM16_ABGR", "value": 6},
405    {"name": "SPI_SHADER_UINT16_ABGR", "value": 7},
406    {"name": "SPI_SHADER_SINT16_ABGR", "value": 8},
407    {"name": "SPI_SHADER_32_ABGR", "value": 9}
408   ]
409  },
410  "SPI_SHADER_FORMAT": {
411   "entries": [
412    {"name": "SPI_SHADER_NONE", "value": 0},
413    {"name": "SPI_SHADER_1COMP", "value": 1},
414    {"name": "SPI_SHADER_2COMP", "value": 2},
415    {"name": "SPI_SHADER_4COMPRESS", "value": 3},
416    {"name": "SPI_SHADER_4COMP", "value": 4}
417   ]
418  },
419  "SPM_PERFMON_STATE": {
420   "entries": [
421    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET", "value": 0},
422    {"name": "STRM_PERFMON_STATE_START_COUNTING", "value": 1},
423    {"name": "STRM_PERFMON_STATE_STOP_COUNTING", "value": 2},
424    {"name": "STRM_PERFMON_STATE_RESERVED_3", "value": 3},
425    {"name": "STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM", "value": 4},
426    {"name": "STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM", "value": 5}
427   ]
428  },
429  "SX_BLEND_OPT": {
430   "entries": [
431    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_ALL", "value": 0},
432    {"name": "BLEND_OPT_PRESERVE_ALL_IGNORE_NONE", "value": 1},
433    {"name": "BLEND_OPT_PRESERVE_C1_IGNORE_C0", "value": 2},
434    {"name": "BLEND_OPT_PRESERVE_C0_IGNORE_C1", "value": 3},
435    {"name": "BLEND_OPT_PRESERVE_A1_IGNORE_A0", "value": 4},
436    {"name": "BLEND_OPT_PRESERVE_A0_IGNORE_A1", "value": 5},
437    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_A0", "value": 6},
438    {"name": "BLEND_OPT_PRESERVE_NONE_IGNORE_NONE", "value": 7}
439   ]
440  },
441  "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": {
442   "entries": [
443    {"name": "EXACT", "value": 0},
444    {"name": "11BIT_FORMAT", "value": 1},
445    {"name": "10BIT_FORMAT", "value": 3},
446    {"name": "8BIT_FORMAT", "value": 6},
447    {"name": "6BIT_FORMAT", "value": 11},
448    {"name": "5BIT_FORMAT", "value": 13},
449    {"name": "4BIT_FORMAT", "value": 15}
450   ]
451  },
452  "SX_DOWNCONVERT_FORMAT": {
453   "entries": [
454    {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0},
455    {"name": "SX_RT_EXPORT_32_R", "value": 1},
456    {"name": "SX_RT_EXPORT_32_A", "value": 2},
457    {"name": "SX_RT_EXPORT_10_11_11", "value": 3},
458    {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4},
459    {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5},
460    {"name": "SX_RT_EXPORT_5_6_5", "value": 6},
461    {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7},
462    {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8},
463    {"name": "SX_RT_EXPORT_16_16_GR", "value": 9},
464    {"name": "SX_RT_EXPORT_16_16_AR", "value": 10},
465    {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11},
466    {"name": "SX_RT_EXPORT_2_10_10_10_7E3", "value": 12},
467    {"name": "SX_RT_EXPORT_2_10_10_10_6E4", "value": 13}
468   ]
469  },
470  "SX_OPT_COMB_FCN": {
471   "entries": [
472    {"name": "OPT_COMB_NONE", "value": 0},
473    {"name": "OPT_COMB_ADD", "value": 1},
474    {"name": "OPT_COMB_SUBTRACT", "value": 2},
475    {"name": "OPT_COMB_MIN", "value": 3},
476    {"name": "OPT_COMB_MAX", "value": 4},
477    {"name": "OPT_COMB_REVSUBTRACT", "value": 5},
478    {"name": "OPT_COMB_BLEND_DISABLED", "value": 6},
479    {"name": "OPT_COMB_SAFE_ADD", "value": 7}
480   ]
481  },
482  "ScMap": {
483   "entries": [
484    {"name": "RASTER_CONFIG_SC_MAP_0", "value": 0},
485    {"name": "RASTER_CONFIG_SC_MAP_1", "value": 1},
486    {"name": "RASTER_CONFIG_SC_MAP_2", "value": 2},
487    {"name": "RASTER_CONFIG_SC_MAP_3", "value": 3}
488   ]
489  },
490  "ScUncertaintyRegionMode": {
491   "entries": [
492    {"name": "SC_HALF_LSB", "value": 0},
493    {"name": "SC_LSB_ONE_SIDED", "value": 1},
494    {"name": "SC_LSB_TWO_SIDED", "value": 2}
495   ]
496  },
497  "ScXsel": {
498   "entries": [
499    {"name": "RASTER_CONFIG_SC_XSEL_8_WIDE_TILE", "value": 0},
500    {"name": "RASTER_CONFIG_SC_XSEL_16_WIDE_TILE", "value": 1},
501    {"name": "RASTER_CONFIG_SC_XSEL_32_WIDE_TILE", "value": 2},
502    {"name": "RASTER_CONFIG_SC_XSEL_64_WIDE_TILE", "value": 3}
503   ]
504  },
505  "ScYsel": {
506   "entries": [
507    {"name": "RASTER_CONFIG_SC_YSEL_8_WIDE_TILE", "value": 0},
508    {"name": "RASTER_CONFIG_SC_YSEL_16_WIDE_TILE", "value": 1},
509    {"name": "RASTER_CONFIG_SC_YSEL_32_WIDE_TILE", "value": 2},
510    {"name": "RASTER_CONFIG_SC_YSEL_64_WIDE_TILE", "value": 3}
511   ]
512  },
513  "SeMap": {
514   "entries": [
515    {"name": "RASTER_CONFIG_SE_MAP_0", "value": 0},
516    {"name": "RASTER_CONFIG_SE_MAP_1", "value": 1},
517    {"name": "RASTER_CONFIG_SE_MAP_2", "value": 2},
518    {"name": "RASTER_CONFIG_SE_MAP_3", "value": 3}
519   ]
520  },
521  "SePairMap": {
522   "entries": [
523    {"name": "RASTER_CONFIG_SE_PAIR_MAP_0", "value": 0},
524    {"name": "RASTER_CONFIG_SE_PAIR_MAP_1", "value": 1},
525    {"name": "RASTER_CONFIG_SE_PAIR_MAP_2", "value": 2},
526    {"name": "RASTER_CONFIG_SE_PAIR_MAP_3", "value": 3}
527   ]
528  },
529  "SePairXsel": {
530   "entries": [
531    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE", "value": 0},
532    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE", "value": 1},
533    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE", "value": 2},
534    {"name": "RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE", "value": 3}
535   ]
536  },
537  "SePairYsel": {
538   "entries": [
539    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE", "value": 0},
540    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE", "value": 1},
541    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE", "value": 2},
542    {"name": "RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE", "value": 3}
543   ]
544  },
545  "SeXsel": {
546   "entries": [
547    {"name": "RASTER_CONFIG_SE_XSEL_8_WIDE_TILE", "value": 0},
548    {"name": "RASTER_CONFIG_SE_XSEL_16_WIDE_TILE", "value": 1},
549    {"name": "RASTER_CONFIG_SE_XSEL_32_WIDE_TILE", "value": 2},
550    {"name": "RASTER_CONFIG_SE_XSEL_64_WIDE_TILE", "value": 3}
551   ]
552  },
553  "SeYsel": {
554   "entries": [
555    {"name": "RASTER_CONFIG_SE_YSEL_8_WIDE_TILE", "value": 0},
556    {"name": "RASTER_CONFIG_SE_YSEL_16_WIDE_TILE", "value": 1},
557    {"name": "RASTER_CONFIG_SE_YSEL_32_WIDE_TILE", "value": 2},
558    {"name": "RASTER_CONFIG_SE_YSEL_64_WIDE_TILE", "value": 3}
559   ]
560  },
561  "StencilFormat": {
562   "entries": [
563    {"name": "STENCIL_INVALID", "value": 0},
564    {"name": "STENCIL_8", "value": 1}
565   ]
566  },
567  "StencilOp": {
568   "entries": [
569    {"name": "STENCIL_KEEP", "value": 0},
570    {"name": "STENCIL_ZERO", "value": 1},
571    {"name": "STENCIL_ONES", "value": 2},
572    {"name": "STENCIL_REPLACE_TEST", "value": 3},
573    {"name": "STENCIL_REPLACE_OP", "value": 4},
574    {"name": "STENCIL_ADD_CLAMP", "value": 5},
575    {"name": "STENCIL_SUB_CLAMP", "value": 6},
576    {"name": "STENCIL_INVERT", "value": 7},
577    {"name": "STENCIL_ADD_WRAP", "value": 8},
578    {"name": "STENCIL_SUB_WRAP", "value": 9},
579    {"name": "STENCIL_AND", "value": 10},
580    {"name": "STENCIL_OR", "value": 11},
581    {"name": "STENCIL_XOR", "value": 12},
582    {"name": "STENCIL_NAND", "value": 13},
583    {"name": "STENCIL_NOR", "value": 14},
584    {"name": "STENCIL_XNOR", "value": 15}
585   ]
586  },
587  "SurfaceNumber": {
588   "entries": [
589    {"name": "NUMBER_UNORM", "value": 0},
590    {"name": "NUMBER_SNORM", "value": 1},
591    {"name": "NUMBER_USCALED", "value": 2},
592    {"name": "NUMBER_SSCALED", "value": 3},
593    {"name": "NUMBER_UINT", "value": 4},
594    {"name": "NUMBER_SINT", "value": 5},
595    {"name": "NUMBER_SRGB", "value": 6},
596    {"name": "NUMBER_FLOAT", "value": 7}
597   ]
598  },
599  "SurfaceSwap": {
600   "entries": [
601    {"name": "SWAP_STD", "value": 0},
602    {"name": "SWAP_ALT", "value": 1},
603    {"name": "SWAP_STD_REV", "value": 2},
604    {"name": "SWAP_ALT_REV", "value": 3}
605   ]
606  },
607  "ThreadTraceRegInclude": {
608   "entries": [
609    {"name": "REG_INCLUDE_SQDEC", "value": 1},
610    {"name": "REG_INCLUDE_SHDEC", "value": 2},
611    {"name": "REG_INCLUDE_GFXUDEC", "value": 4},
612    {"name": "REG_INCLUDE_COMP", "value": 8},
613    {"name": "REG_INCLUDE_CONTEXT", "value": 16},
614    {"name": "REG_INCLUDE_CONFIG", "value": 32},
615    {"name": "REG_INCLUDE_OTHER", "value": 64},
616    {"name": "REG_INCLUDE_READS", "value": 128}
617   ]
618  },
619  "ThreadTraceTokenExclude": {
620   "entries": [
621    {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1},
622    {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2},
623    {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4},
624    {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8},
625    {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16},
626    {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32},
627    {"name": "TOKEN_EXCLUDE_REG", "value": 64},
628    {"name": "TOKEN_EXCLUDE_EVENT", "value": 128},
629    {"name": "TOKEN_EXCLUDE_INST", "value": 256},
630    {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512},
631    {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024},
632    {"name": "TOKEN_EXCLUDE_PERF", "value": 2048}
633   ]
634  },
635  "VGT_DETECT_ONE": {
636   "entries": [
637    {"name": "ENABLE_TF1_OPT", "value": 0},
638    {"name": "DISABLE_TF1_OPT", "value": 1}
639   ]
640  },
641  "VGT_DETECT_ZERO": {
642   "entries": [
643    {"name": "ENABLE_TF0_OPT", "value": 0},
644    {"name": "DISABLE_TF0_OPT", "value": 1}
645   ]
646  },
647  "VGT_DIST_MODE": {
648   "entries": [
649    {"name": "NO_DIST", "value": 0},
650    {"name": "PATCHES", "value": 1},
651    {"name": "DONUTS", "value": 2},
652    {"name": "TRAPEZOIDS", "value": 3}
653   ]
654  },
655  "VGT_DI_MAJOR_MODE_SELECT": {
656   "entries": [
657    {"name": "DI_MAJOR_MODE_0", "value": 0},
658    {"name": "DI_MAJOR_MODE_1", "value": 1}
659   ]
660  },
661  "VGT_DI_PRIM_TYPE": {
662   "entries": [
663    {"name": "DI_PT_NONE", "value": 0},
664    {"name": "DI_PT_POINTLIST", "value": 1},
665    {"name": "DI_PT_LINELIST", "value": 2},
666    {"name": "DI_PT_LINESTRIP", "value": 3},
667    {"name": "DI_PT_TRILIST", "value": 4},
668    {"name": "DI_PT_TRIFAN", "value": 5},
669    {"name": "DI_PT_TRISTRIP", "value": 6},
670    {"name": "DI_PT_2D_RECTANGLE", "value": 7},
671    {"name": "DI_PT_UNUSED_1", "value": 8},
672    {"name": "DI_PT_PATCH", "value": 9},
673    {"name": "DI_PT_LINELIST_ADJ", "value": 10},
674    {"name": "DI_PT_LINESTRIP_ADJ", "value": 11},
675    {"name": "DI_PT_TRILIST_ADJ", "value": 12},
676    {"name": "DI_PT_TRISTRIP_ADJ", "value": 13},
677    {"name": "DI_PT_UNUSED_3", "value": 14},
678    {"name": "DI_PT_UNUSED_4", "value": 15},
679    {"name": "DI_PT_UNUSED_5", "value": 16},
680    {"name": "DI_PT_RECTLIST", "value": 17},
681    {"name": "DI_PT_LINELOOP", "value": 18},
682    {"name": "DI_PT_QUADLIST", "value": 19},
683    {"name": "DI_PT_QUADSTRIP", "value": 20},
684    {"name": "DI_PT_POLYGON", "value": 21}
685   ]
686  },
687  "VGT_DI_SOURCE_SELECT": {
688   "entries": [
689    {"name": "DI_SRC_SEL_DMA", "value": 0},
690    {"name": "DI_SRC_SEL_IMMEDIATE", "value": 1},
691    {"name": "DI_SRC_SEL_AUTO_INDEX", "value": 2},
692    {"name": "DI_SRC_SEL_RESERVED", "value": 3}
693   ]
694  },
695  "VGT_DMA_BUF_TYPE": {
696   "entries": [
697    {"name": "VGT_DMA_BUF_MEM", "value": 0},
698    {"name": "VGT_DMA_BUF_RING", "value": 1},
699    {"name": "VGT_DMA_BUF_SETUP", "value": 2},
700    {"name": "VGT_DMA_PTR_UPDATE", "value": 3}
701   ]
702  },
703  "VGT_DMA_SWAP_MODE": {
704   "entries": [
705    {"name": "VGT_DMA_SWAP_NONE", "value": 0},
706    {"name": "VGT_DMA_SWAP_16_BIT", "value": 1},
707    {"name": "VGT_DMA_SWAP_32_BIT", "value": 2},
708    {"name": "VGT_DMA_SWAP_WORD", "value": 3}
709   ]
710  },
711  "VGT_EVENT_TYPE": {
712   "entries": [
713    {"name": "Reserved_0x00", "value": 0},
714    {"name": "SAMPLE_STREAMOUTSTATS1", "value": 1},
715    {"name": "SAMPLE_STREAMOUTSTATS2", "value": 2},
716    {"name": "SAMPLE_STREAMOUTSTATS3", "value": 3},
717    {"name": "CACHE_FLUSH_TS", "value": 4},
718    {"name": "CONTEXT_DONE", "value": 5},
719    {"name": "CACHE_FLUSH", "value": 6},
720    {"name": "CS_PARTIAL_FLUSH", "value": 7},
721    {"name": "VGT_STREAMOUT_SYNC", "value": 8},
722    {"name": "Reserved_0x09", "value": 9},
723    {"name": "VGT_STREAMOUT_RESET", "value": 10},
724    {"name": "END_OF_PIPE_INCR_DE", "value": 11},
725    {"name": "END_OF_PIPE_IB_END", "value": 12},
726    {"name": "RST_PIX_CNT", "value": 13},
727    {"name": "BREAK_BATCH", "value": 14},
728    {"name": "VS_PARTIAL_FLUSH", "value": 15},
729    {"name": "PS_PARTIAL_FLUSH", "value": 16},
730    {"name": "FLUSH_HS_OUTPUT", "value": 17},
731    {"name": "FLUSH_DFSM", "value": 18},
732    {"name": "RESET_TO_LOWEST_VGT", "value": 19},
733    {"name": "CACHE_FLUSH_AND_INV_TS_EVENT", "value": 20},
734    {"name": "WAIT_SYNC", "value": 21},
735    {"name": "CACHE_FLUSH_AND_INV_EVENT", "value": 22},
736    {"name": "PERFCOUNTER_START", "value": 23},
737    {"name": "PERFCOUNTER_STOP", "value": 24},
738    {"name": "PIPELINESTAT_START", "value": 25},
739    {"name": "PIPELINESTAT_STOP", "value": 26},
740    {"name": "PERFCOUNTER_SAMPLE", "value": 27},
741    {"name": "FLUSH_ES_OUTPUT", "value": 28},
742    {"name": "BIN_CONF_OVERRIDE_CHECK", "value": 29},
743    {"name": "SAMPLE_PIPELINESTAT", "value": 30},
744    {"name": "SO_VGTSTREAMOUT_FLUSH", "value": 31},
745    {"name": "SAMPLE_STREAMOUTSTATS", "value": 32},
746    {"name": "RESET_VTX_CNT", "value": 33},
747    {"name": "BLOCK_CONTEXT_DONE", "value": 34},
748    {"name": "CS_CONTEXT_DONE", "value": 35},
749    {"name": "VGT_FLUSH", "value": 36},
750    {"name": "TGID_ROLLOVER", "value": 37},
751    {"name": "SQ_NON_EVENT", "value": 38},
752    {"name": "SC_SEND_DB_VPZ", "value": 39},
753    {"name": "BOTTOM_OF_PIPE_TS", "value": 40},
754    {"name": "FLUSH_SX_TS", "value": 41},
755    {"name": "DB_CACHE_FLUSH_AND_INV", "value": 42},
756    {"name": "FLUSH_AND_INV_DB_DATA_TS", "value": 43},
757    {"name": "FLUSH_AND_INV_DB_META", "value": 44},
758    {"name": "FLUSH_AND_INV_CB_DATA_TS", "value": 45},
759    {"name": "FLUSH_AND_INV_CB_META", "value": 46},
760    {"name": "CS_DONE", "value": 47},
761    {"name": "PS_DONE", "value": 48},
762    {"name": "FLUSH_AND_INV_CB_PIXEL_DATA", "value": 49},
763    {"name": "SX_CB_RAT_ACK_REQUEST", "value": 50},
764    {"name": "THREAD_TRACE_START", "value": 51},
765    {"name": "THREAD_TRACE_STOP", "value": 52},
766    {"name": "THREAD_TRACE_MARKER", "value": 53},
767    {"name": "THREAD_TRACE_DRAW", "value": 54},
768    {"name": "THREAD_TRACE_FINISH", "value": 55},
769    {"name": "PIXEL_PIPE_STAT_CONTROL", "value": 56},
770    {"name": "PIXEL_PIPE_STAT_DUMP", "value": 57},
771    {"name": "PIXEL_PIPE_STAT_RESET", "value": 58},
772    {"name": "CONTEXT_SUSPEND", "value": 59},
773    {"name": "OFFCHIP_HS_DEALLOC", "value": 60},
774    {"name": "ENABLE_NGG_PIPELINE", "value": 61},
775    {"name": "ENABLE_LEGACY_PIPELINE", "value": 62},
776    {"name": "DRAW_DONE", "value": 63}
777   ]
778  },
779  "VGT_GS_OUTPRIM_TYPE": {
780   "entries": [
781    {"name": "POINTLIST", "value": 0},
782    {"name": "LINESTRIP", "value": 1},
783    {"name": "TRISTRIP", "value": 2},
784    {"name": "RECT_2D", "value": 3},
785    {"name": "RECTLIST", "value": 4}
786   ]
787  },
788  "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY": {
789   "entries": [
790    {"name": "X_8K_DWORDS", "value": 0},
791    {"name": "X_4K_DWORDS", "value": 1},
792    {"name": "X_2K_DWORDS", "value": 2},
793    {"name": "X_1K_DWORDS", "value": 3}
794   ]
795  },
796  "VGT_INDEX_TYPE_MODE": {
797   "entries": [
798    {"name": "VGT_INDEX_16", "value": 0},
799    {"name": "VGT_INDEX_32", "value": 1},
800    {"name": "VGT_INDEX_8", "value": 2}
801   ]
802  },
803  "VGT_RDREQ_POLICY": {
804   "entries": [
805    {"name": "VGT_POLICY_LRU", "value": 0},
806    {"name": "VGT_POLICY_STREAM", "value": 1},
807    {"name": "VGT_POLICY_BYPASS", "value": 2}
808   ]
809  },
810  "VGT_STAGES_ES_EN": {
811   "entries": [
812    {"name": "ES_STAGE_OFF", "value": 0},
813    {"name": "ES_STAGE_DS", "value": 1},
814    {"name": "ES_STAGE_REAL", "value": 2},
815    {"name": "RESERVED_ES", "value": 3}
816   ]
817  },
818  "VGT_STAGES_GS_EN": {
819   "entries": [
820    {"name": "GS_STAGE_OFF", "value": 0},
821    {"name": "GS_STAGE_ON", "value": 1}
822   ]
823  },
824  "VGT_STAGES_HS_EN": {
825   "entries": [
826    {"name": "HS_STAGE_OFF", "value": 0},
827    {"name": "HS_STAGE_ON", "value": 1}
828   ]
829  },
830  "VGT_STAGES_LS_EN": {
831   "entries": [
832    {"name": "LS_STAGE_OFF", "value": 0},
833    {"name": "LS_STAGE_ON", "value": 1},
834    {"name": "CS_STAGE_ON", "value": 2},
835    {"name": "RESERVED_LS", "value": 3}
836   ]
837  },
838  "VGT_STAGES_VS_EN": {
839   "entries": [
840    {"name": "VS_STAGE_REAL", "value": 0},
841    {"name": "VS_STAGE_DS", "value": 1},
842    {"name": "VS_STAGE_COPY_SHADER", "value": 2},
843    {"name": "RESERVED_VS", "value": 3}
844   ]
845  },
846  "VGT_TESS_PARTITION": {
847   "entries": [
848    {"name": "PART_INTEGER", "value": 0},
849    {"name": "PART_POW2", "value": 1},
850    {"name": "PART_FRAC_ODD", "value": 2},
851    {"name": "PART_FRAC_EVEN", "value": 3}
852   ]
853  },
854  "VGT_TESS_TOPOLOGY": {
855   "entries": [
856    {"name": "OUTPUT_POINT", "value": 0},
857    {"name": "OUTPUT_LINE", "value": 1},
858    {"name": "OUTPUT_TRIANGLE_CW", "value": 2},
859    {"name": "OUTPUT_TRIANGLE_CCW", "value": 3}
860   ]
861  },
862  "VGT_TESS_TYPE": {
863   "entries": [
864    {"name": "TESS_ISOLINE", "value": 0},
865    {"name": "TESS_TRIANGLE", "value": 1},
866    {"name": "TESS_QUAD", "value": 2}
867   ]
868  },
869  "VRSCombinerModeSC": {
870   "entries": [
871    {"name": "SC_VRS_COMB_MODE_PASSTHRU", "value": 0},
872    {"name": "SC_VRS_COMB_MODE_OVERRIDE", "value": 1},
873    {"name": "SC_VRS_COMB_MODE_MIN", "value": 2},
874    {"name": "SC_VRS_COMB_MODE_MAX", "value": 3},
875    {"name": "SC_VRS_COMB_MODE_SATURATE", "value": 4}
876   ]
877  },
878  "VRSrate": {
879   "entries": [
880    {"name": "VRS_SHADING_RATE_1X1", "value": 0},
881    {"name": "VRS_SHADING_RATE_1X2", "value": 1},
882    {"name": "VRS_SHADING_RATE_UNDEFINED0", "value": 2},
883    {"name": "VRS_SHADING_RATE_UNDEFINED1", "value": 3},
884    {"name": "VRS_SHADING_RATE_2X1", "value": 4},
885    {"name": "VRS_SHADING_RATE_2X2", "value": 5},
886    {"name": "VRS_SHADING_RATE_2X4", "value": 6},
887    {"name": "VRS_SHADING_RATE_UNDEFINED2", "value": 7},
888    {"name": "VRS_SHADING_RATE_UNDEFINED3", "value": 8},
889    {"name": "VRS_SHADING_RATE_4X2", "value": 9},
890    {"name": "VRS_SHADING_RATE_4X4", "value": 10},
891    {"name": "VRS_SHADING_RATE_UNDEFINED4", "value": 11},
892    {"name": "VRS_SHADING_RATE_16X_SSAA", "value": 12},
893    {"name": "VRS_SHADING_RATE_8X_SSAA", "value": 13},
894    {"name": "VRS_SHADING_RATE_4X_SSAA", "value": 14},
895    {"name": "VRS_SHADING_RATE_2X_SSAA", "value": 15}
896   ]
897  },
898  "WritePolicy": {
899   "entries": [
900    {"name": "CACHE_LRU_WR", "value": 0},
901    {"name": "CACHE_STREAM", "value": 1},
902    {"name": "CACHE_NOA_WR", "value": 2},
903    {"name": "CACHE_BYPASS", "value": 3}
904   ]
905  },
906  "ZFormat": {
907   "entries": [
908    {"name": "Z_INVALID", "value": 0},
909    {"name": "Z_16", "value": 1},
910    {"name": "Z_24", "value": 2},
911    {"name": "Z_32_FLOAT", "value": 3}
912   ]
913  },
914  "ZLimitSumm": {
915   "entries": [
916    {"name": "FORCE_SUMM_OFF", "value": 0},
917    {"name": "FORCE_SUMM_MINZ", "value": 1},
918    {"name": "FORCE_SUMM_MAXZ", "value": 2},
919    {"name": "FORCE_SUMM_BOTH", "value": 3}
920   ]
921  },
922  "ZOrder": {
923   "entries": [
924    {"name": "LATE_Z", "value": 0},
925    {"name": "EARLY_Z_THEN_LATE_Z", "value": 1},
926    {"name": "RE_Z", "value": 2},
927    {"name": "EARLY_Z_THEN_RE_Z", "value": 3}
928   ]
929  }
930 },
931 "register_mappings": [
932  {
933   "chips": ["gfx11"],
934   "map": {"at": 40, "to": "mm"},
935   "name": "SQ_WAVE_ACTIVE",
936   "type_ref": "SQ_WAVE_ACTIVE"
937  },
938  {
939   "chips": ["gfx11"],
940   "map": {"at": 44, "to": "mm"},
941   "name": "SQ_WAVE_VALID_AND_IDLE",
942   "type_ref": "SQ_WAVE_ACTIVE"
943  },
944  {
945   "chips": ["gfx11"],
946   "map": {"at": 1028, "to": "mm"},
947   "name": "SQ_WAVE_MODE",
948   "type_ref": "SQ_WAVE_MODE"
949  },
950  {
951   "chips": ["gfx11"],
952   "map": {"at": 1032, "to": "mm"},
953   "name": "SQ_WAVE_STATUS",
954   "type_ref": "SQ_WAVE_STATUS"
955  },
956  {
957   "chips": ["gfx11"],
958   "map": {"at": 1036, "to": "mm"},
959   "name": "SQ_WAVE_TRAPSTS",
960   "type_ref": "SQ_WAVE_TRAPSTS"
961  },
962  {
963   "chips": ["gfx11"],
964   "map": {"at": 1044, "to": "mm"},
965   "name": "SQ_WAVE_GPR_ALLOC",
966   "type_ref": "SQ_WAVE_GPR_ALLOC"
967  },
968  {
969   "chips": ["gfx11"],
970   "map": {"at": 1048, "to": "mm"},
971   "name": "SQ_WAVE_LDS_ALLOC",
972   "type_ref": "SQ_WAVE_LDS_ALLOC"
973  },
974  {
975   "chips": ["gfx11"],
976   "map": {"at": 1052, "to": "mm"},
977   "name": "SQ_WAVE_IB_STS",
978   "type_ref": "SQ_WAVE_IB_STS"
979  },
980  {
981   "chips": ["gfx11"],
982   "map": {"at": 1056, "to": "mm"},
983   "name": "SQ_WAVE_PC_LO"
984  },
985  {
986   "chips": ["gfx11"],
987   "map": {"at": 1060, "to": "mm"},
988   "name": "SQ_WAVE_PC_HI",
989   "type_ref": "SQ_WAVE_PC_HI"
990  },
991  {
992   "chips": ["gfx11"],
993   "map": {"at": 1076, "to": "mm"},
994   "name": "SQ_WAVE_IB_DBG1",
995   "type_ref": "SQ_WAVE_IB_DBG1"
996  },
997  {
998   "chips": ["gfx11"],
999   "map": {"at": 1080, "to": "mm"},
1000   "name": "SQ_WAVE_FLUSH_IB"
1001  },
1002  {
1003   "chips": ["gfx11"],
1004   "map": {"at": 1104, "to": "mm"},
1005   "name": "SQ_WAVE_FLAT_SCRATCH_LO"
1006  },
1007  {
1008   "chips": ["gfx11"],
1009   "map": {"at": 1108, "to": "mm"},
1010   "name": "SQ_WAVE_FLAT_SCRATCH_HI"
1011  },
1012  {
1013   "chips": ["gfx11"],
1014   "map": {"at": 1116, "to": "mm"},
1015   "name": "SQ_WAVE_HW_ID1",
1016   "type_ref": "SQ_WAVE_HW_ID1"
1017  },
1018  {
1019   "chips": ["gfx11"],
1020   "map": {"at": 1120, "to": "mm"},
1021   "name": "SQ_WAVE_HW_ID2",
1022   "type_ref": "SQ_WAVE_HW_ID2"
1023  },
1024  {
1025   "chips": ["gfx11"],
1026   "map": {"at": 1124, "to": "mm"},
1027   "name": "SQ_WAVE_POPS_PACKER",
1028   "type_ref": "SQ_WAVE_POPS_PACKER"
1029  },
1030  {
1031   "chips": ["gfx11"],
1032   "map": {"at": 1128, "to": "mm"},
1033   "name": "SQ_WAVE_SCHED_MODE",
1034   "type_ref": "SQ_WAVE_SCHED_MODE"
1035  },
1036  {
1037   "chips": ["gfx11"],
1038   "map": {"at": 1136, "to": "mm"},
1039   "name": "SQ_WAVE_IB_STS2",
1040   "type_ref": "SQ_WAVE_IB_STS2"
1041  },
1042  {
1043   "chips": ["gfx11"],
1044   "map": {"at": 1140, "to": "mm"},
1045   "name": "SQ_WAVE_SHADER_CYCLES",
1046   "type_ref": "SQ_WAVE_SHADER_CYCLES"
1047  },
1048  {
1049   "chips": ["gfx11"],
1050   "map": {"at": 2480, "to": "mm"},
1051   "name": "SQ_WAVE_TTMP0"
1052  },
1053  {
1054   "chips": ["gfx11"],
1055   "map": {"at": 2484, "to": "mm"},
1056   "name": "SQ_WAVE_TTMP1"
1057  },
1058  {
1059   "chips": ["gfx11"],
1060   "map": {"at": 2492, "to": "mm"},
1061   "name": "SQ_WAVE_TTMP3"
1062  },
1063  {
1064   "chips": ["gfx11"],
1065   "map": {"at": 2496, "to": "mm"},
1066   "name": "SQ_WAVE_TTMP4"
1067  },
1068  {
1069   "chips": ["gfx11"],
1070   "map": {"at": 2500, "to": "mm"},
1071   "name": "SQ_WAVE_TTMP5"
1072  },
1073  {
1074   "chips": ["gfx11"],
1075   "map": {"at": 2504, "to": "mm"},
1076   "name": "SQ_WAVE_TTMP6"
1077  },
1078  {
1079   "chips": ["gfx11"],
1080   "map": {"at": 2508, "to": "mm"},
1081   "name": "SQ_WAVE_TTMP7"
1082  },
1083  {
1084   "chips": ["gfx11"],
1085   "map": {"at": 2512, "to": "mm"},
1086   "name": "SQ_WAVE_TTMP8"
1087  },
1088  {
1089   "chips": ["gfx11"],
1090   "map": {"at": 2516, "to": "mm"},
1091   "name": "SQ_WAVE_TTMP9"
1092  },
1093  {
1094   "chips": ["gfx11"],
1095   "map": {"at": 2520, "to": "mm"},
1096   "name": "SQ_WAVE_TTMP10"
1097  },
1098  {
1099   "chips": ["gfx11"],
1100   "map": {"at": 2524, "to": "mm"},
1101   "name": "SQ_WAVE_TTMP11"
1102  },
1103  {
1104   "chips": ["gfx11"],
1105   "map": {"at": 2528, "to": "mm"},
1106   "name": "SQ_WAVE_TTMP12"
1107  },
1108  {
1109   "chips": ["gfx11"],
1110   "map": {"at": 2532, "to": "mm"},
1111   "name": "SQ_WAVE_TTMP13"
1112  },
1113  {
1114   "chips": ["gfx11"],
1115   "map": {"at": 2536, "to": "mm"},
1116   "name": "SQ_WAVE_TTMP14"
1117  },
1118  {
1119   "chips": ["gfx11"],
1120   "map": {"at": 2540, "to": "mm"},
1121   "name": "SQ_WAVE_TTMP15"
1122  },
1123  {
1124   "chips": ["gfx11"],
1125   "map": {"at": 2548, "to": "mm"},
1126   "name": "SQ_WAVE_M0"
1127  },
1128  {
1129   "chips": ["gfx11"],
1130   "map": {"at": 2552, "to": "mm"},
1131   "name": "SQ_WAVE_EXEC_LO"
1132  },
1133  {
1134   "chips": ["gfx11"],
1135   "map": {"at": 2556, "to": "mm"},
1136   "name": "SQ_WAVE_EXEC_HI"
1137  },
1138  {
1139   "chips": ["gfx11"],
1140   "map": {"at": 32776, "to": "mm"},
1141   "name": "GRBM_STATUS2",
1142   "type_ref": "GRBM_STATUS2"
1143  },
1144  {
1145   "chips": ["gfx11"],
1146   "map": {"at": 32784, "to": "mm"},
1147   "name": "GRBM_STATUS",
1148   "type_ref": "GRBM_STATUS"
1149  },
1150  {
1151   "chips": ["gfx11"],
1152   "map": {"at": 32788, "to": "mm"},
1153   "name": "GRBM_STATUS_SE0",
1154   "type_ref": "GRBM_STATUS_SE0"
1155  },
1156  {
1157   "chips": ["gfx11"],
1158   "map": {"at": 32792, "to": "mm"},
1159   "name": "GRBM_STATUS_SE1",
1160   "type_ref": "GRBM_STATUS_SE0"
1161  },
1162  {
1163   "chips": ["gfx11"],
1164   "map": {"at": 32796, "to": "mm"},
1165   "name": "GRBM_STATUS3",
1166   "type_ref": "GRBM_STATUS3"
1167  },
1168  {
1169   "chips": ["gfx11"],
1170   "map": {"at": 32824, "to": "mm"},
1171   "name": "GRBM_STATUS_SE2",
1172   "type_ref": "GRBM_STATUS_SE0"
1173  },
1174  {
1175   "chips": ["gfx11"],
1176   "map": {"at": 32828, "to": "mm"},
1177   "name": "GRBM_STATUS_SE3",
1178   "type_ref": "GRBM_STATUS_SE0"
1179  },
1180  {
1181   "chips": ["gfx11"],
1182   "map": {"at": 32832, "to": "mm"},
1183   "name": "GRBM_STATUS_SE4",
1184   "type_ref": "GRBM_STATUS_SE0"
1185  },
1186  {
1187   "chips": ["gfx11"],
1188   "map": {"at": 32836, "to": "mm"},
1189   "name": "GRBM_STATUS_SE5",
1190   "type_ref": "GRBM_STATUS_SE0"
1191  },
1192  {
1193   "chips": ["gfx11"],
1194   "map": {"at": 33280, "to": "mm"},
1195   "name": "CP_CPC_DEBUG_CNTL",
1196   "type_ref": "CP_CPC_DEBUG_CNTL"
1197  },
1198  {
1199   "chips": ["gfx11"],
1200   "map": {"at": 33284, "to": "mm"},
1201   "name": "CP_CPC_DEBUG_DATA"
1202  },
1203  {
1204   "chips": ["gfx11"],
1205   "map": {"at": 33296, "to": "mm"},
1206   "name": "CP_CPC_STATUS",
1207   "type_ref": "CP_CPC_STATUS"
1208  },
1209  {
1210   "chips": ["gfx11"],
1211   "map": {"at": 33300, "to": "mm"},
1212   "name": "CP_CPC_BUSY_STAT",
1213   "type_ref": "CP_CPC_BUSY_STAT"
1214  },
1215  {
1216   "chips": ["gfx11"],
1217   "map": {"at": 33304, "to": "mm"},
1218   "name": "CP_CPC_STALLED_STAT1",
1219   "type_ref": "CP_CPC_STALLED_STAT1"
1220  },
1221  {
1222   "chips": ["gfx11"],
1223   "map": {"at": 33308, "to": "mm"},
1224   "name": "CP_CPF_STATUS",
1225   "type_ref": "CP_CPF_STATUS"
1226  },
1227  {
1228   "chips": ["gfx11"],
1229   "map": {"at": 33312, "to": "mm"},
1230   "name": "CP_CPF_BUSY_STAT",
1231   "type_ref": "CP_CPF_BUSY_STAT"
1232  },
1233  {
1234   "chips": ["gfx11"],
1235   "map": {"at": 33316, "to": "mm"},
1236   "name": "CP_CPF_STALLED_STAT1",
1237   "type_ref": "CP_CPF_STALLED_STAT1"
1238  },
1239  {
1240   "chips": ["gfx11"],
1241   "map": {"at": 33320, "to": "mm"},
1242   "name": "CP_CPC_BUSY_STAT2",
1243   "type_ref": "CP_CPC_BUSY_STAT2"
1244  },
1245  {
1246   "chips": ["gfx11"],
1247   "map": {"at": 33324, "to": "mm"},
1248   "name": "CP_CPC_GRBM_FREE_COUNT",
1249   "type_ref": "CP_CPC_GRBM_FREE_COUNT"
1250  },
1251  {
1252   "chips": ["gfx11"],
1253   "map": {"at": 33328, "to": "mm"},
1254   "name": "CP_CPC_PRIV_VIOLATION_ADDR",
1255   "type_ref": "CP_CPC_PRIV_VIOLATION_ADDR"
1256  },
1257  {
1258   "chips": ["gfx11"],
1259   "map": {"at": 33344, "to": "mm"},
1260   "name": "CP_CPC_SCRATCH_INDEX",
1261   "type_ref": "CP_CPC_SCRATCH_INDEX"
1262  },
1263  {
1264   "chips": ["gfx11"],
1265   "map": {"at": 33348, "to": "mm"},
1266   "name": "CP_CPC_SCRATCH_DATA"
1267  },
1268  {
1269   "chips": ["gfx11"],
1270   "map": {"at": 33352, "to": "mm"},
1271   "name": "CP_CPF_GRBM_FREE_COUNT",
1272   "type_ref": "CP_CPF_GRBM_FREE_COUNT"
1273  },
1274  {
1275   "chips": ["gfx11"],
1276   "map": {"at": 33356, "to": "mm"},
1277   "name": "CP_CPF_BUSY_STAT2",
1278   "type_ref": "CP_CPF_BUSY_STAT2"
1279  },
1280  {
1281   "chips": ["gfx11"],
1282   "map": {"at": 33436, "to": "mm"},
1283   "name": "CP_CPC_HALT_HYST_COUNT",
1284   "type_ref": "CP_CPC_HALT_HYST_COUNT"
1285  },
1286  {
1287   "chips": ["gfx11"],
1288   "map": {"at": 39160, "to": "mm"},
1289   "name": "GB_ADDR_CONFIG",
1290   "type_ref": "GB_ADDR_CONFIG"
1291  },
1292  {
1293   "chips": ["gfx11"],
1294   "map": {"at": 45056, "to": "mm"},
1295   "name": "GUS_IO_RD_COMBINE_FLUSH",
1296   "type_ref": "GUS_IO_RD_COMBINE_FLUSH"
1297  },
1298  {
1299   "chips": ["gfx11"],
1300   "map": {"at": 45060, "to": "mm"},
1301   "name": "SPI_SHADER_PGM_RSRC4_PS",
1302   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
1303  },
1304  {
1305   "chips": ["gfx11"],
1306   "map": {"at": 45064, "to": "mm"},
1307   "name": "GUS_IO_RD_PRI_AGE_RATE",
1308   "type_ref": "GUS_IO_RD_PRI_AGE_RATE"
1309  },
1310  {
1311   "chips": ["gfx11"],
1312   "map": {"at": 45068, "to": "mm"},
1313   "name": "GUS_IO_WR_PRI_AGE_RATE",
1314   "type_ref": "GUS_IO_RD_PRI_AGE_RATE"
1315  },
1316  {
1317   "chips": ["gfx11"],
1318   "map": {"at": 45072, "to": "mm"},
1319   "name": "GUS_IO_RD_PRI_AGE_COEFF",
1320   "type_ref": "GUS_IO_RD_PRI_AGE_COEFF"
1321  },
1322  {
1323   "chips": ["gfx11"],
1324   "map": {"at": 45076, "to": "mm"},
1325   "name": "GUS_IO_WR_PRI_AGE_COEFF",
1326   "type_ref": "GUS_IO_RD_PRI_AGE_COEFF"
1327  },
1328  {
1329   "chips": ["gfx11"],
1330   "map": {"at": 45080, "to": "mm"},
1331   "name": "SPI_SHADER_PGM_CHKSUM_PS"
1332  },
1333  {
1334   "chips": ["gfx11"],
1335   "map": {"at": 45084, "to": "mm"},
1336   "name": "SPI_SHADER_PGM_RSRC3_PS",
1337   "type_ref": "SPI_SHADER_PGM_RSRC3_PS"
1338  },
1339  {
1340   "chips": ["gfx11"],
1341   "map": {"at": 45088, "to": "mm"},
1342   "name": "SPI_SHADER_PGM_LO_PS"
1343  },
1344  {
1345   "chips": ["gfx11"],
1346   "map": {"at": 45092, "to": "mm"},
1347   "name": "SPI_SHADER_PGM_HI_PS",
1348   "type_ref": "SPI_SHADER_PGM_HI_PS"
1349  },
1350  {
1351   "chips": ["gfx11"],
1352   "map": {"at": 45096, "to": "mm"},
1353   "name": "SPI_SHADER_PGM_RSRC1_PS",
1354   "type_ref": "SPI_SHADER_PGM_RSRC1_PS"
1355  },
1356  {
1357   "chips": ["gfx11"],
1358   "map": {"at": 45100, "to": "mm"},
1359   "name": "SPI_SHADER_PGM_RSRC2_PS",
1360   "type_ref": "SPI_SHADER_PGM_RSRC2_PS"
1361  },
1362  {
1363   "chips": ["gfx11"],
1364   "map": {"at": 45104, "to": "mm"},
1365   "name": "SPI_SHADER_USER_DATA_PS_0"
1366  },
1367  {
1368   "chips": ["gfx11"],
1369   "map": {"at": 45108, "to": "mm"},
1370   "name": "SPI_SHADER_USER_DATA_PS_1"
1371  },
1372  {
1373   "chips": ["gfx11"],
1374   "map": {"at": 45112, "to": "mm"},
1375   "name": "SPI_SHADER_USER_DATA_PS_2"
1376  },
1377  {
1378   "chips": ["gfx11"],
1379   "map": {"at": 45116, "to": "mm"},
1380   "name": "SPI_SHADER_USER_DATA_PS_3"
1381  },
1382  {
1383   "chips": ["gfx11"],
1384   "map": {"at": 45120, "to": "mm"},
1385   "name": "SPI_SHADER_USER_DATA_PS_4"
1386  },
1387  {
1388   "chips": ["gfx11"],
1389   "map": {"at": 45124, "to": "mm"},
1390   "name": "SPI_SHADER_USER_DATA_PS_5"
1391  },
1392  {
1393   "chips": ["gfx11"],
1394   "map": {"at": 45128, "to": "mm"},
1395   "name": "SPI_SHADER_USER_DATA_PS_6"
1396  },
1397  {
1398   "chips": ["gfx11"],
1399   "map": {"at": 45132, "to": "mm"},
1400   "name": "SPI_SHADER_USER_DATA_PS_7"
1401  },
1402  {
1403   "chips": ["gfx11"],
1404   "map": {"at": 45136, "to": "mm"},
1405   "name": "SPI_SHADER_USER_DATA_PS_8"
1406  },
1407  {
1408   "chips": ["gfx11"],
1409   "map": {"at": 45140, "to": "mm"},
1410   "name": "SPI_SHADER_USER_DATA_PS_9"
1411  },
1412  {
1413   "chips": ["gfx11"],
1414   "map": {"at": 45144, "to": "mm"},
1415   "name": "SPI_SHADER_USER_DATA_PS_10"
1416  },
1417  {
1418   "chips": ["gfx11"],
1419   "map": {"at": 45148, "to": "mm"},
1420   "name": "SPI_SHADER_USER_DATA_PS_11"
1421  },
1422  {
1423   "chips": ["gfx11"],
1424   "map": {"at": 45152, "to": "mm"},
1425   "name": "SPI_SHADER_USER_DATA_PS_12"
1426  },
1427  {
1428   "chips": ["gfx11"],
1429   "map": {"at": 45156, "to": "mm"},
1430   "name": "SPI_SHADER_USER_DATA_PS_13"
1431  },
1432  {
1433   "chips": ["gfx11"],
1434   "map": {"at": 45160, "to": "mm"},
1435   "name": "SPI_SHADER_USER_DATA_PS_14"
1436  },
1437  {
1438   "chips": ["gfx11"],
1439   "map": {"at": 45164, "to": "mm"},
1440   "name": "SPI_SHADER_USER_DATA_PS_15"
1441  },
1442  {
1443   "chips": ["gfx11"],
1444   "map": {"at": 45168, "to": "mm"},
1445   "name": "SPI_SHADER_USER_DATA_PS_16"
1446  },
1447  {
1448   "chips": ["gfx11"],
1449   "map": {"at": 45172, "to": "mm"},
1450   "name": "SPI_SHADER_USER_DATA_PS_17"
1451  },
1452  {
1453   "chips": ["gfx11"],
1454   "map": {"at": 45176, "to": "mm"},
1455   "name": "SPI_SHADER_USER_DATA_PS_18"
1456  },
1457  {
1458   "chips": ["gfx11"],
1459   "map": {"at": 45180, "to": "mm"},
1460   "name": "SPI_SHADER_USER_DATA_PS_19"
1461  },
1462  {
1463   "chips": ["gfx11"],
1464   "map": {"at": 45184, "to": "mm"},
1465   "name": "SPI_SHADER_USER_DATA_PS_20"
1466  },
1467  {
1468   "chips": ["gfx11"],
1469   "map": {"at": 45188, "to": "mm"},
1470   "name": "SPI_SHADER_USER_DATA_PS_21"
1471  },
1472  {
1473   "chips": ["gfx11"],
1474   "map": {"at": 45192, "to": "mm"},
1475   "name": "SPI_SHADER_USER_DATA_PS_22"
1476  },
1477  {
1478   "chips": ["gfx11"],
1479   "map": {"at": 45196, "to": "mm"},
1480   "name": "SPI_SHADER_USER_DATA_PS_23"
1481  },
1482  {
1483   "chips": ["gfx11"],
1484   "map": {"at": 45200, "to": "mm"},
1485   "name": "SPI_SHADER_USER_DATA_PS_24"
1486  },
1487  {
1488   "chips": ["gfx11"],
1489   "map": {"at": 45204, "to": "mm"},
1490   "name": "SPI_SHADER_USER_DATA_PS_25"
1491  },
1492  {
1493   "chips": ["gfx11"],
1494   "map": {"at": 45208, "to": "mm"},
1495   "name": "SPI_SHADER_USER_DATA_PS_26"
1496  },
1497  {
1498   "chips": ["gfx11"],
1499   "map": {"at": 45212, "to": "mm"},
1500   "name": "SPI_SHADER_USER_DATA_PS_27"
1501  },
1502  {
1503   "chips": ["gfx11"],
1504   "map": {"at": 45216, "to": "mm"},
1505   "name": "SPI_SHADER_USER_DATA_PS_28"
1506  },
1507  {
1508   "chips": ["gfx11"],
1509   "map": {"at": 45220, "to": "mm"},
1510   "name": "SPI_SHADER_USER_DATA_PS_29"
1511  },
1512  {
1513   "chips": ["gfx11"],
1514   "map": {"at": 45224, "to": "mm"},
1515   "name": "SPI_SHADER_USER_DATA_PS_30"
1516  },
1517  {
1518   "chips": ["gfx11"],
1519   "map": {"at": 45228, "to": "mm"},
1520   "name": "SPI_SHADER_USER_DATA_PS_31"
1521  },
1522  {
1523   "chips": ["gfx11"],
1524   "map": {"at": 45232, "to": "mm"},
1525   "name": "GUS_DRAM_PRI_QUANT1_PRI2",
1526   "type_ref": "GUS_DRAM_PRI_QUANT1_PRI2"
1527  },
1528  {
1529   "chips": ["gfx11"],
1530   "map": {"at": 45236, "to": "mm"},
1531   "name": "GUS_DRAM_PRI_QUANT1_PRI3",
1532   "type_ref": "GUS_DRAM_PRI_QUANT1_PRI2"
1533  },
1534  {
1535   "chips": ["gfx11"],
1536   "map": {"at": 45240, "to": "mm"},
1537   "name": "GUS_DRAM_PRI_QUANT1_PRI4",
1538   "type_ref": "GUS_DRAM_PRI_QUANT1_PRI2"
1539  },
1540  {
1541   "chips": ["gfx11"],
1542   "map": {"at": 45244, "to": "mm"},
1543   "name": "GUS_DRAM_PRI_QUANT1_PRI5",
1544   "type_ref": "GUS_DRAM_PRI_QUANT1_PRI2"
1545  },
1546  {
1547   "chips": ["gfx11"],
1548   "map": {"at": 45248, "to": "mm"},
1549   "name": "SPI_SHADER_REQ_CTRL_PS",
1550   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
1551  },
1552  {
1553   "chips": ["gfx11"],
1554   "map": {"at": 45252, "to": "mm"},
1555   "name": "GUS_DRAM_GROUP_BURST",
1556   "type_ref": "GUS_DRAM_GROUP_BURST"
1557  },
1558  {
1559   "chips": ["gfx11"],
1560   "map": {"at": 45256, "to": "mm"},
1561   "name": "SPI_SHADER_USER_ACCUM_PS_0",
1562   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1563  },
1564  {
1565   "chips": ["gfx11"],
1566   "map": {"at": 45260, "to": "mm"},
1567   "name": "SPI_SHADER_USER_ACCUM_PS_1",
1568   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1569  },
1570  {
1571   "chips": ["gfx11"],
1572   "map": {"at": 45264, "to": "mm"},
1573   "name": "SPI_SHADER_USER_ACCUM_PS_2",
1574   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1575  },
1576  {
1577   "chips": ["gfx11"],
1578   "map": {"at": 45268, "to": "mm"},
1579   "name": "SPI_SHADER_USER_ACCUM_PS_3",
1580   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
1581  },
1582  {
1583   "chips": ["gfx11"],
1584   "map": {"at": 45272, "to": "mm"},
1585   "name": "GUS_SDP_TAG_RESERVE1",
1586   "type_ref": "GUS_SDP_TAG_RESERVE1"
1587  },
1588  {
1589   "chips": ["gfx11"],
1590   "map": {"at": 45276, "to": "mm"},
1591   "name": "GUS_SDP_VCC_RESERVE0",
1592   "type_ref": "GUS_SDP_VCC_RESERVE0"
1593  },
1594  {
1595   "chips": ["gfx11"],
1596   "map": {"at": 45280, "to": "mm"},
1597   "name": "GUS_SDP_VCC_RESERVE1",
1598   "type_ref": "GUS_SDP_VCC_RESERVE1"
1599  },
1600  {
1601   "chips": ["gfx11"],
1602   "map": {"at": 45284, "to": "mm"},
1603   "name": "GUS_SDP_VCD_RESERVE0",
1604   "type_ref": "GUS_SDP_VCC_RESERVE0"
1605  },
1606  {
1607   "chips": ["gfx11"],
1608   "map": {"at": 45288, "to": "mm"},
1609   "name": "GUS_SDP_VCD_RESERVE1",
1610   "type_ref": "GUS_SDP_VCC_RESERVE1"
1611  },
1612  {
1613   "chips": ["gfx11"],
1614   "map": {"at": 45292, "to": "mm"},
1615   "name": "GUS_SDP_REQ_CNTL",
1616   "type_ref": "GUS_SDP_REQ_CNTL"
1617  },
1618  {
1619   "chips": ["gfx11"],
1620   "map": {"at": 45296, "to": "mm"},
1621   "name": "GUS_MISC",
1622   "type_ref": "GUS_MISC"
1623  },
1624  {
1625   "chips": ["gfx11"],
1626   "map": {"at": 45300, "to": "mm"},
1627   "name": "GUS_LATENCY_SAMPLING",
1628   "type_ref": "GUS_LATENCY_SAMPLING"
1629  },
1630  {
1631   "chips": ["gfx11"],
1632   "map": {"at": 45304, "to": "mm"},
1633   "name": "GUS_ERR_STATUS",
1634   "type_ref": "GUS_ERR_STATUS"
1635  },
1636  {
1637   "chips": ["gfx11"],
1638   "map": {"at": 45308, "to": "mm"},
1639   "name": "GUS_MISC2",
1640   "type_ref": "GUS_MISC2"
1641  },
1642  {
1643   "chips": ["gfx11"],
1644   "map": {"at": 45332, "to": "mm"},
1645   "name": "GUS_SDP_ENABLE",
1646   "type_ref": "GUS_SDP_ENABLE"
1647  },
1648  {
1649   "chips": ["gfx11"],
1650   "map": {"at": 45336, "to": "mm"},
1651   "name": "GUS_L1_CH0_CMD_IN"
1652  },
1653  {
1654   "chips": ["gfx11"],
1655   "map": {"at": 45340, "to": "mm"},
1656   "name": "GUS_L1_CH0_CMD_OUT"
1657  },
1658  {
1659   "chips": ["gfx11"],
1660   "map": {"at": 45344, "to": "mm"},
1661   "name": "GUS_L1_CH0_DATA_IN"
1662  },
1663  {
1664   "chips": ["gfx11"],
1665   "map": {"at": 45348, "to": "mm"},
1666   "name": "GUS_L1_CH0_DATA_OUT"
1667  },
1668  {
1669   "chips": ["gfx11"],
1670   "map": {"at": 45352, "to": "mm"},
1671   "name": "GUS_L1_CH0_DATA_U_IN"
1672  },
1673  {
1674   "chips": ["gfx11"],
1675   "map": {"at": 45356, "to": "mm"},
1676   "name": "GUS_L1_CH0_DATA_U_OUT"
1677  },
1678  {
1679   "chips": ["gfx11"],
1680   "map": {"at": 45360, "to": "mm"},
1681   "name": "GUS_L1_CH1_CMD_IN"
1682  },
1683  {
1684   "chips": ["gfx11"],
1685   "map": {"at": 45364, "to": "mm"},
1686   "name": "GUS_L1_CH1_CMD_OUT"
1687  },
1688  {
1689   "chips": ["gfx11"],
1690   "map": {"at": 45368, "to": "mm"},
1691   "name": "GUS_L1_CH1_DATA_IN"
1692  },
1693  {
1694   "chips": ["gfx11"],
1695   "map": {"at": 45372, "to": "mm"},
1696   "name": "GUS_L1_CH1_DATA_OUT"
1697  },
1698  {
1699   "chips": ["gfx11"],
1700   "map": {"at": 45376, "to": "mm"},
1701   "name": "GUS_L1_CH1_DATA_U_IN"
1702  },
1703  {
1704   "chips": ["gfx11"],
1705   "map": {"at": 45380, "to": "mm"},
1706   "name": "GUS_L1_CH1_DATA_U_OUT"
1707  },
1708  {
1709   "chips": ["gfx11"],
1710   "map": {"at": 45384, "to": "mm"},
1711   "name": "GUS_L1_SA0_CMD_IN"
1712  },
1713  {
1714   "chips": ["gfx11"],
1715   "map": {"at": 45388, "to": "mm"},
1716   "name": "GUS_L1_SA0_CMD_OUT"
1717  },
1718  {
1719   "chips": ["gfx11"],
1720   "map": {"at": 45392, "to": "mm"},
1721   "name": "GUS_L1_SA0_DATA_IN"
1722  },
1723  {
1724   "chips": ["gfx11"],
1725   "map": {"at": 45396, "to": "mm"},
1726   "name": "GUS_L1_SA0_DATA_OUT"
1727  },
1728  {
1729   "chips": ["gfx11"],
1730   "map": {"at": 45400, "to": "mm"},
1731   "name": "GUS_L1_SA0_DATA_U_IN"
1732  },
1733  {
1734   "chips": ["gfx11"],
1735   "map": {"at": 45404, "to": "mm"},
1736   "name": "GUS_L1_SA0_DATA_U_OUT"
1737  },
1738  {
1739   "chips": ["gfx11"],
1740   "map": {"at": 45408, "to": "mm"},
1741   "name": "GUS_L1_SA1_CMD_IN"
1742  },
1743  {
1744   "chips": ["gfx11"],
1745   "map": {"at": 45412, "to": "mm"},
1746   "name": "GUS_L1_SA1_CMD_OUT"
1747  },
1748  {
1749   "chips": ["gfx11"],
1750   "map": {"at": 45416, "to": "mm"},
1751   "name": "GUS_L1_SA1_DATA_IN"
1752  },
1753  {
1754   "chips": ["gfx11"],
1755   "map": {"at": 45420, "to": "mm"},
1756   "name": "GUS_L1_SA1_DATA_OUT"
1757  },
1758  {
1759   "chips": ["gfx11"],
1760   "map": {"at": 45424, "to": "mm"},
1761   "name": "GUS_L1_SA1_DATA_U_IN"
1762  },
1763  {
1764   "chips": ["gfx11"],
1765   "map": {"at": 45428, "to": "mm"},
1766   "name": "GUS_L1_SA1_DATA_U_OUT"
1767  },
1768  {
1769   "chips": ["gfx11"],
1770   "map": {"at": 45432, "to": "mm"},
1771   "name": "GUS_L1_SA2_CMD_IN"
1772  },
1773  {
1774   "chips": ["gfx11"],
1775   "map": {"at": 45436, "to": "mm"},
1776   "name": "GUS_L1_SA2_CMD_OUT"
1777  },
1778  {
1779   "chips": ["gfx11"],
1780   "map": {"at": 45440, "to": "mm"},
1781   "name": "GUS_L1_SA2_DATA_IN"
1782  },
1783  {
1784   "chips": ["gfx11"],
1785   "map": {"at": 45444, "to": "mm"},
1786   "name": "GUS_L1_SA2_DATA_OUT"
1787  },
1788  {
1789   "chips": ["gfx11"],
1790   "map": {"at": 45448, "to": "mm"},
1791   "name": "GUS_L1_SA2_DATA_U_IN"
1792  },
1793  {
1794   "chips": ["gfx11"],
1795   "map": {"at": 45452, "to": "mm"},
1796   "name": "GUS_L1_SA2_DATA_U_OUT"
1797  },
1798  {
1799   "chips": ["gfx11"],
1800   "map": {"at": 45456, "to": "mm"},
1801   "name": "GUS_L1_SA3_CMD_IN"
1802  },
1803  {
1804   "chips": ["gfx11"],
1805   "map": {"at": 45460, "to": "mm"},
1806   "name": "GUS_L1_SA3_CMD_OUT"
1807  },
1808  {
1809   "chips": ["gfx11"],
1810   "map": {"at": 45464, "to": "mm"},
1811   "name": "GUS_L1_SA3_DATA_IN"
1812  },
1813  {
1814   "chips": ["gfx11"],
1815   "map": {"at": 45468, "to": "mm"},
1816   "name": "GUS_L1_SA3_DATA_OUT"
1817  },
1818  {
1819   "chips": ["gfx11"],
1820   "map": {"at": 45472, "to": "mm"},
1821   "name": "GUS_L1_SA3_DATA_U_IN"
1822  },
1823  {
1824   "chips": ["gfx11"],
1825   "map": {"at": 45476, "to": "mm"},
1826   "name": "GUS_L1_SA3_DATA_U_OUT"
1827  },
1828  {
1829   "chips": ["gfx11"],
1830   "map": {"at": 45480, "to": "mm"},
1831   "name": "GUS_MISC3",
1832   "type_ref": "GUS_MISC3"
1833  },
1834  {
1835   "chips": ["gfx11"],
1836   "map": {"at": 45484, "to": "mm"},
1837   "name": "GUS_WRRSP_FIFO_CNTL",
1838   "type_ref": "GUS_WRRSP_FIFO_CNTL"
1839  },
1840  {
1841   "chips": ["gfx11"],
1842   "map": {"at": 45568, "to": "mm"},
1843   "name": "SPI_SHADER_PGM_CHKSUM_GS"
1844  },
1845  {
1846   "chips": ["gfx11"],
1847   "map": {"at": 45572, "to": "mm"},
1848   "name": "SPI_SHADER_PGM_RSRC4_GS",
1849   "type_ref": "SPI_SHADER_PGM_RSRC4_GS"
1850  },
1851  {
1852   "chips": ["gfx11"],
1853   "map": {"at": 45576, "to": "mm"},
1854   "name": "SPI_SHADER_USER_DATA_ADDR_LO_GS"
1855  },
1856  {
1857   "chips": ["gfx11"],
1858   "map": {"at": 45580, "to": "mm"},
1859   "name": "SPI_SHADER_USER_DATA_ADDR_HI_GS"
1860  },
1861  {
1862   "chips": ["gfx11"],
1863   "map": {"at": 45584, "to": "mm"},
1864   "name": "SPI_SHADER_PGM_LO_ES_GS"
1865  },
1866  {
1867   "chips": ["gfx11"],
1868   "map": {"at": 45588, "to": "mm"},
1869   "name": "SPI_SHADER_PGM_HI_ES_GS",
1870   "type_ref": "SPI_SHADER_PGM_HI_PS"
1871  },
1872  {
1873   "chips": ["gfx11"],
1874   "map": {"at": 45596, "to": "mm"},
1875   "name": "SPI_SHADER_PGM_RSRC3_GS",
1876   "type_ref": "SPI_SHADER_PGM_RSRC3_GS"
1877  },
1878  {
1879   "chips": ["gfx11"],
1880   "map": {"at": 45600, "to": "mm"},
1881   "name": "SPI_SHADER_PGM_LO_GS"
1882  },
1883  {
1884   "chips": ["gfx11"],
1885   "map": {"at": 45604, "to": "mm"},
1886   "name": "SPI_SHADER_PGM_HI_GS"
1887  },
1888  {
1889   "chips": ["gfx11"],
1890   "map": {"at": 45608, "to": "mm"},
1891   "name": "SPI_SHADER_PGM_RSRC1_GS",
1892   "type_ref": "SPI_SHADER_PGM_RSRC1_GS"
1893  },
1894  {
1895   "chips": ["gfx11"],
1896   "map": {"at": 45612, "to": "mm"},
1897   "name": "SPI_SHADER_PGM_RSRC2_GS",
1898   "type_ref": "SPI_SHADER_PGM_RSRC2_GS"
1899  },
1900  {
1901   "chips": ["gfx11"],
1902   "map": {"at": 45616, "to": "mm"},
1903   "name": "SPI_SHADER_USER_DATA_GS_0"
1904  },
1905  {
1906   "chips": ["gfx11"],
1907   "map": {"at": 45620, "to": "mm"},
1908   "name": "SPI_SHADER_USER_DATA_GS_1"
1909  },
1910  {
1911   "chips": ["gfx11"],
1912   "map": {"at": 45624, "to": "mm"},
1913   "name": "SPI_SHADER_USER_DATA_GS_2"
1914  },
1915  {
1916   "chips": ["gfx11"],
1917   "map": {"at": 45628, "to": "mm"},
1918   "name": "SPI_SHADER_USER_DATA_GS_3"
1919  },
1920  {
1921   "chips": ["gfx11"],
1922   "map": {"at": 45632, "to": "mm"},
1923   "name": "SPI_SHADER_USER_DATA_GS_4"
1924  },
1925  {
1926   "chips": ["gfx11"],
1927   "map": {"at": 45636, "to": "mm"},
1928   "name": "SPI_SHADER_USER_DATA_GS_5"
1929  },
1930  {
1931   "chips": ["gfx11"],
1932   "map": {"at": 45640, "to": "mm"},
1933   "name": "SPI_SHADER_USER_DATA_GS_6"
1934  },
1935  {
1936   "chips": ["gfx11"],
1937   "map": {"at": 45644, "to": "mm"},
1938   "name": "SPI_SHADER_USER_DATA_GS_7"
1939  },
1940  {
1941   "chips": ["gfx11"],
1942   "map": {"at": 45648, "to": "mm"},
1943   "name": "SPI_SHADER_USER_DATA_GS_8"
1944  },
1945  {
1946   "chips": ["gfx11"],
1947   "map": {"at": 45652, "to": "mm"},
1948   "name": "SPI_SHADER_USER_DATA_GS_9"
1949  },
1950  {
1951   "chips": ["gfx11"],
1952   "map": {"at": 45656, "to": "mm"},
1953   "name": "SPI_SHADER_USER_DATA_GS_10"
1954  },
1955  {
1956   "chips": ["gfx11"],
1957   "map": {"at": 45660, "to": "mm"},
1958   "name": "SPI_SHADER_USER_DATA_GS_11"
1959  },
1960  {
1961   "chips": ["gfx11"],
1962   "map": {"at": 45664, "to": "mm"},
1963   "name": "SPI_SHADER_USER_DATA_GS_12"
1964  },
1965  {
1966   "chips": ["gfx11"],
1967   "map": {"at": 45668, "to": "mm"},
1968   "name": "SPI_SHADER_USER_DATA_GS_13"
1969  },
1970  {
1971   "chips": ["gfx11"],
1972   "map": {"at": 45672, "to": "mm"},
1973   "name": "SPI_SHADER_USER_DATA_GS_14"
1974  },
1975  {
1976   "chips": ["gfx11"],
1977   "map": {"at": 45676, "to": "mm"},
1978   "name": "SPI_SHADER_USER_DATA_GS_15"
1979  },
1980  {
1981   "chips": ["gfx11"],
1982   "map": {"at": 45680, "to": "mm"},
1983   "name": "SPI_SHADER_USER_DATA_GS_16"
1984  },
1985  {
1986   "chips": ["gfx11"],
1987   "map": {"at": 45684, "to": "mm"},
1988   "name": "SPI_SHADER_USER_DATA_GS_17"
1989  },
1990  {
1991   "chips": ["gfx11"],
1992   "map": {"at": 45688, "to": "mm"},
1993   "name": "SPI_SHADER_USER_DATA_GS_18"
1994  },
1995  {
1996   "chips": ["gfx11"],
1997   "map": {"at": 45692, "to": "mm"},
1998   "name": "SPI_SHADER_USER_DATA_GS_19"
1999  },
2000  {
2001   "chips": ["gfx11"],
2002   "map": {"at": 45696, "to": "mm"},
2003   "name": "SPI_SHADER_USER_DATA_GS_20"
2004  },
2005  {
2006   "chips": ["gfx11"],
2007   "map": {"at": 45700, "to": "mm"},
2008   "name": "SPI_SHADER_USER_DATA_GS_21"
2009  },
2010  {
2011   "chips": ["gfx11"],
2012   "map": {"at": 45704, "to": "mm"},
2013   "name": "SPI_SHADER_USER_DATA_GS_22"
2014  },
2015  {
2016   "chips": ["gfx11"],
2017   "map": {"at": 45708, "to": "mm"},
2018   "name": "SPI_SHADER_USER_DATA_GS_23"
2019  },
2020  {
2021   "chips": ["gfx11"],
2022   "map": {"at": 45712, "to": "mm"},
2023   "name": "SPI_SHADER_USER_DATA_GS_24"
2024  },
2025  {
2026   "chips": ["gfx11"],
2027   "map": {"at": 45716, "to": "mm"},
2028   "name": "SPI_SHADER_USER_DATA_GS_25"
2029  },
2030  {
2031   "chips": ["gfx11"],
2032   "map": {"at": 45720, "to": "mm"},
2033   "name": "SPI_SHADER_USER_DATA_GS_26"
2034  },
2035  {
2036   "chips": ["gfx11"],
2037   "map": {"at": 45724, "to": "mm"},
2038   "name": "SPI_SHADER_USER_DATA_GS_27"
2039  },
2040  {
2041   "chips": ["gfx11"],
2042   "map": {"at": 45728, "to": "mm"},
2043   "name": "SPI_SHADER_USER_DATA_GS_28"
2044  },
2045  {
2046   "chips": ["gfx11"],
2047   "map": {"at": 45732, "to": "mm"},
2048   "name": "SPI_SHADER_USER_DATA_GS_29"
2049  },
2050  {
2051   "chips": ["gfx11"],
2052   "map": {"at": 45736, "to": "mm"},
2053   "name": "SPI_SHADER_USER_DATA_GS_30"
2054  },
2055  {
2056   "chips": ["gfx11"],
2057   "map": {"at": 45740, "to": "mm"},
2058   "name": "SPI_SHADER_USER_DATA_GS_31"
2059  },
2060  {
2061   "chips": ["gfx11"],
2062   "map": {"at": 45744, "to": "mm"},
2063   "name": "SPI_SHADER_GS_MESHLET_DIM",
2064   "type_ref": "SPI_SHADER_GS_MESHLET_DIM"
2065  },
2066  {
2067   "chips": ["gfx11"],
2068   "map": {"at": 45748, "to": "mm"},
2069   "name": "SPI_SHADER_GS_MESHLET_EXP_ALLOC",
2070   "type_ref": "SPI_SHADER_GS_MESHLET_EXP_ALLOC"
2071  },
2072  {
2073   "chips": ["gfx11"],
2074   "map": {"at": 45760, "to": "mm"},
2075   "name": "SPI_SHADER_REQ_CTRL_ESGS",
2076   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2077  },
2078  {
2079   "chips": ["gfx11"],
2080   "map": {"at": 45768, "to": "mm"},
2081   "name": "SPI_SHADER_USER_ACCUM_ESGS_0",
2082   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2083  },
2084  {
2085   "chips": ["gfx11"],
2086   "map": {"at": 45772, "to": "mm"},
2087   "name": "SPI_SHADER_USER_ACCUM_ESGS_1",
2088   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2089  },
2090  {
2091   "chips": ["gfx11"],
2092   "map": {"at": 45776, "to": "mm"},
2093   "name": "SPI_SHADER_USER_ACCUM_ESGS_2",
2094   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2095  },
2096  {
2097   "chips": ["gfx11"],
2098   "map": {"at": 45780, "to": "mm"},
2099   "name": "SPI_SHADER_USER_ACCUM_ESGS_3",
2100   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2101  },
2102  {
2103   "chips": ["gfx11"],
2104   "map": {"at": 45856, "to": "mm"},
2105   "name": "SPI_SHADER_PGM_LO_ES"
2106  },
2107  {
2108   "chips": ["gfx11"],
2109   "map": {"at": 45860, "to": "mm"},
2110   "name": "SPI_SHADER_PGM_HI_ES",
2111   "type_ref": "SPI_SHADER_PGM_HI_PS"
2112  },
2113  {
2114   "chips": ["gfx11"],
2115   "map": {"at": 46080, "to": "mm"},
2116   "name": "SPI_SHADER_PGM_CHKSUM_HS"
2117  },
2118  {
2119   "chips": ["gfx11"],
2120   "map": {"at": 46084, "to": "mm"},
2121   "name": "SPI_SHADER_PGM_RSRC4_HS",
2122   "type_ref": "SPI_SHADER_PGM_RSRC4_PS"
2123  },
2124  {
2125   "chips": ["gfx11"],
2126   "map": {"at": 46088, "to": "mm"},
2127   "name": "SPI_SHADER_USER_DATA_ADDR_LO_HS"
2128  },
2129  {
2130   "chips": ["gfx11"],
2131   "map": {"at": 46092, "to": "mm"},
2132   "name": "SPI_SHADER_USER_DATA_ADDR_HI_HS"
2133  },
2134  {
2135   "chips": ["gfx11"],
2136   "map": {"at": 46096, "to": "mm"},
2137   "name": "SPI_SHADER_PGM_LO_LS_HS"
2138  },
2139  {
2140   "chips": ["gfx11"],
2141   "map": {"at": 46100, "to": "mm"},
2142   "name": "SPI_SHADER_PGM_HI_LS_HS",
2143   "type_ref": "SPI_SHADER_PGM_HI_PS"
2144  },
2145  {
2146   "chips": ["gfx11"],
2147   "map": {"at": 46108, "to": "mm"},
2148   "name": "SPI_SHADER_PGM_RSRC3_HS",
2149   "type_ref": "SPI_SHADER_PGM_RSRC3_HS"
2150  },
2151  {
2152   "chips": ["gfx11"],
2153   "map": {"at": 46112, "to": "mm"},
2154   "name": "SPI_SHADER_PGM_LO_HS"
2155  },
2156  {
2157   "chips": ["gfx11"],
2158   "map": {"at": 46116, "to": "mm"},
2159   "name": "SPI_SHADER_PGM_HI_HS"
2160  },
2161  {
2162   "chips": ["gfx11"],
2163   "map": {"at": 46120, "to": "mm"},
2164   "name": "SPI_SHADER_PGM_RSRC1_HS",
2165   "type_ref": "SPI_SHADER_PGM_RSRC1_HS"
2166  },
2167  {
2168   "chips": ["gfx11"],
2169   "map": {"at": 46124, "to": "mm"},
2170   "name": "SPI_SHADER_PGM_RSRC2_HS",
2171   "type_ref": "SPI_SHADER_PGM_RSRC2_HS"
2172  },
2173  {
2174   "chips": ["gfx11"],
2175   "map": {"at": 46128, "to": "mm"},
2176   "name": "SPI_SHADER_USER_DATA_HS_0"
2177  },
2178  {
2179   "chips": ["gfx11"],
2180   "map": {"at": 46132, "to": "mm"},
2181   "name": "SPI_SHADER_USER_DATA_HS_1"
2182  },
2183  {
2184   "chips": ["gfx11"],
2185   "map": {"at": 46136, "to": "mm"},
2186   "name": "SPI_SHADER_USER_DATA_HS_2"
2187  },
2188  {
2189   "chips": ["gfx11"],
2190   "map": {"at": 46140, "to": "mm"},
2191   "name": "SPI_SHADER_USER_DATA_HS_3"
2192  },
2193  {
2194   "chips": ["gfx11"],
2195   "map": {"at": 46144, "to": "mm"},
2196   "name": "SPI_SHADER_USER_DATA_HS_4"
2197  },
2198  {
2199   "chips": ["gfx11"],
2200   "map": {"at": 46148, "to": "mm"},
2201   "name": "SPI_SHADER_USER_DATA_HS_5"
2202  },
2203  {
2204   "chips": ["gfx11"],
2205   "map": {"at": 46152, "to": "mm"},
2206   "name": "SPI_SHADER_USER_DATA_HS_6"
2207  },
2208  {
2209   "chips": ["gfx11"],
2210   "map": {"at": 46156, "to": "mm"},
2211   "name": "SPI_SHADER_USER_DATA_HS_7"
2212  },
2213  {
2214   "chips": ["gfx11"],
2215   "map": {"at": 46160, "to": "mm"},
2216   "name": "SPI_SHADER_USER_DATA_HS_8"
2217  },
2218  {
2219   "chips": ["gfx11"],
2220   "map": {"at": 46164, "to": "mm"},
2221   "name": "SPI_SHADER_USER_DATA_HS_9"
2222  },
2223  {
2224   "chips": ["gfx11"],
2225   "map": {"at": 46168, "to": "mm"},
2226   "name": "SPI_SHADER_USER_DATA_HS_10"
2227  },
2228  {
2229   "chips": ["gfx11"],
2230   "map": {"at": 46172, "to": "mm"},
2231   "name": "SPI_SHADER_USER_DATA_HS_11"
2232  },
2233  {
2234   "chips": ["gfx11"],
2235   "map": {"at": 46176, "to": "mm"},
2236   "name": "SPI_SHADER_USER_DATA_HS_12"
2237  },
2238  {
2239   "chips": ["gfx11"],
2240   "map": {"at": 46180, "to": "mm"},
2241   "name": "SPI_SHADER_USER_DATA_HS_13"
2242  },
2243  {
2244   "chips": ["gfx11"],
2245   "map": {"at": 46184, "to": "mm"},
2246   "name": "SPI_SHADER_USER_DATA_HS_14"
2247  },
2248  {
2249   "chips": ["gfx11"],
2250   "map": {"at": 46188, "to": "mm"},
2251   "name": "SPI_SHADER_USER_DATA_HS_15"
2252  },
2253  {
2254   "chips": ["gfx11"],
2255   "map": {"at": 46192, "to": "mm"},
2256   "name": "SPI_SHADER_USER_DATA_HS_16"
2257  },
2258  {
2259   "chips": ["gfx11"],
2260   "map": {"at": 46196, "to": "mm"},
2261   "name": "SPI_SHADER_USER_DATA_HS_17"
2262  },
2263  {
2264   "chips": ["gfx11"],
2265   "map": {"at": 46200, "to": "mm"},
2266   "name": "SPI_SHADER_USER_DATA_HS_18"
2267  },
2268  {
2269   "chips": ["gfx11"],
2270   "map": {"at": 46204, "to": "mm"},
2271   "name": "SPI_SHADER_USER_DATA_HS_19"
2272  },
2273  {
2274   "chips": ["gfx11"],
2275   "map": {"at": 46208, "to": "mm"},
2276   "name": "SPI_SHADER_USER_DATA_HS_20"
2277  },
2278  {
2279   "chips": ["gfx11"],
2280   "map": {"at": 46212, "to": "mm"},
2281   "name": "SPI_SHADER_USER_DATA_HS_21"
2282  },
2283  {
2284   "chips": ["gfx11"],
2285   "map": {"at": 46216, "to": "mm"},
2286   "name": "SPI_SHADER_USER_DATA_HS_22"
2287  },
2288  {
2289   "chips": ["gfx11"],
2290   "map": {"at": 46220, "to": "mm"},
2291   "name": "SPI_SHADER_USER_DATA_HS_23"
2292  },
2293  {
2294   "chips": ["gfx11"],
2295   "map": {"at": 46224, "to": "mm"},
2296   "name": "SPI_SHADER_USER_DATA_HS_24"
2297  },
2298  {
2299   "chips": ["gfx11"],
2300   "map": {"at": 46228, "to": "mm"},
2301   "name": "SPI_SHADER_USER_DATA_HS_25"
2302  },
2303  {
2304   "chips": ["gfx11"],
2305   "map": {"at": 46232, "to": "mm"},
2306   "name": "SPI_SHADER_USER_DATA_HS_26"
2307  },
2308  {
2309   "chips": ["gfx11"],
2310   "map": {"at": 46236, "to": "mm"},
2311   "name": "SPI_SHADER_USER_DATA_HS_27"
2312  },
2313  {
2314   "chips": ["gfx11"],
2315   "map": {"at": 46240, "to": "mm"},
2316   "name": "SPI_SHADER_USER_DATA_HS_28"
2317  },
2318  {
2319   "chips": ["gfx11"],
2320   "map": {"at": 46244, "to": "mm"},
2321   "name": "SPI_SHADER_USER_DATA_HS_29"
2322  },
2323  {
2324   "chips": ["gfx11"],
2325   "map": {"at": 46248, "to": "mm"},
2326   "name": "SPI_SHADER_USER_DATA_HS_30"
2327  },
2328  {
2329   "chips": ["gfx11"],
2330   "map": {"at": 46252, "to": "mm"},
2331   "name": "SPI_SHADER_USER_DATA_HS_31"
2332  },
2333  {
2334   "chips": ["gfx11"],
2335   "map": {"at": 46272, "to": "mm"},
2336   "name": "SPI_SHADER_REQ_CTRL_LSHS",
2337   "type_ref": "SPI_SHADER_REQ_CTRL_PS"
2338  },
2339  {
2340   "chips": ["gfx11"],
2341   "map": {"at": 46280, "to": "mm"},
2342   "name": "SPI_SHADER_USER_ACCUM_LSHS_0",
2343   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2344  },
2345  {
2346   "chips": ["gfx11"],
2347   "map": {"at": 46284, "to": "mm"},
2348   "name": "SPI_SHADER_USER_ACCUM_LSHS_1",
2349   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2350  },
2351  {
2352   "chips": ["gfx11"],
2353   "map": {"at": 46288, "to": "mm"},
2354   "name": "SPI_SHADER_USER_ACCUM_LSHS_2",
2355   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2356  },
2357  {
2358   "chips": ["gfx11"],
2359   "map": {"at": 46292, "to": "mm"},
2360   "name": "SPI_SHADER_USER_ACCUM_LSHS_3",
2361   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2362  },
2363  {
2364   "chips": ["gfx11"],
2365   "map": {"at": 46340, "to": "mm"},
2366   "name": "GL1C_STATUS",
2367   "type_ref": "GL1C_STATUS"
2368  },
2369  {
2370   "chips": ["gfx11"],
2371   "map": {"at": 46348, "to": "mm"},
2372   "name": "GL1C_UTCL0_CNTL2",
2373   "type_ref": "GL1C_UTCL0_CNTL2"
2374  },
2375  {
2376   "chips": ["gfx11"],
2377   "map": {"at": 46352, "to": "mm"},
2378   "name": "GL1C_UTCL0_STATUS",
2379   "type_ref": "GL1C_UTCL0_STATUS"
2380  },
2381  {
2382   "chips": ["gfx11"],
2383   "map": {"at": 46356, "to": "mm"},
2384   "name": "GL1C_UTCL0_RETRY",
2385   "type_ref": "GL1C_UTCL0_RETRY"
2386  },
2387  {
2388   "chips": ["gfx11"],
2389   "map": {"at": 46368, "to": "mm"},
2390   "name": "SPI_SHADER_PGM_LO_LS"
2391  },
2392  {
2393   "chips": ["gfx11"],
2394   "map": {"at": 46372, "to": "mm"},
2395   "name": "SPI_SHADER_PGM_HI_LS",
2396   "type_ref": "SPI_SHADER_PGM_HI_PS"
2397  },
2398  {
2399   "chips": ["gfx11"],
2400   "map": {"at": 46592, "to": "mm"},
2401   "name": "CH_ARB_CTRL",
2402   "type_ref": "CH_ARB_CTRL"
2403  },
2404  {
2405   "chips": ["gfx11"],
2406   "map": {"at": 46600, "to": "mm"},
2407   "name": "CH_DRAM_BURST_MASK",
2408   "type_ref": "CH_DRAM_BURST_MASK"
2409  },
2410  {
2411   "chips": ["gfx11"],
2412   "map": {"at": 46604, "to": "mm"},
2413   "name": "CH_ARB_STATUS",
2414   "type_ref": "CH_ARB_STATUS"
2415  },
2416  {
2417   "chips": ["gfx11"],
2418   "map": {"at": 46608, "to": "mm"},
2419   "name": "CH_DRAM_BURST_CTRL",
2420   "type_ref": "CH_DRAM_BURST_CTRL"
2421  },
2422  {
2423   "chips": ["gfx11"],
2424   "map": {"at": 46624, "to": "mm"},
2425   "name": "CHA_CHC_CREDITS",
2426   "type_ref": "CHA_CHC_CREDITS"
2427  },
2428  {
2429   "chips": ["gfx11"],
2430   "map": {"at": 46628, "to": "mm"},
2431   "name": "CHA_CLIENT_FREE_DELAY",
2432   "type_ref": "CHA_CLIENT_FREE_DELAY"
2433  },
2434  {
2435   "chips": ["gfx11"],
2436   "map": {"at": 46640, "to": "mm"},
2437   "name": "CHI_CHR_REP_FGCG_OVERRIDE",
2438   "type_ref": "CHI_CHR_REP_FGCG_OVERRIDE"
2439  },
2440  {
2441   "chips": ["gfx11"],
2442   "map": {"at": 46672, "to": "mm"},
2443   "name": "CH_VC5_ENABLE",
2444   "type_ref": "CH_VC5_ENABLE"
2445  },
2446  {
2447   "chips": ["gfx11"],
2448   "map": {"at": 46848, "to": "mm"},
2449   "name": "CHC_CTRL",
2450   "type_ref": "CHC_CTRL"
2451  },
2452  {
2453   "chips": ["gfx11"],
2454   "map": {"at": 46852, "to": "mm"},
2455   "name": "CHC_STATUS",
2456   "type_ref": "CHC_STATUS"
2457  },
2458  {
2459   "chips": ["gfx11"],
2460   "map": {"at": 46856, "to": "mm"},
2461   "name": "CHCG_CTRL",
2462   "type_ref": "CHCG_CTRL"
2463  },
2464  {
2465   "chips": ["gfx11"],
2466   "map": {"at": 46860, "to": "mm"},
2467   "name": "CHCG_STATUS",
2468   "type_ref": "CHCG_STATUS"
2469  },
2470  {
2471   "chips": ["gfx11"],
2472   "map": {"at": 47104, "to": "mm"},
2473   "name": "COMPUTE_DISPATCH_INITIATOR",
2474   "type_ref": "COMPUTE_DISPATCH_INITIATOR"
2475  },
2476  {
2477   "chips": ["gfx11"],
2478   "map": {"at": 47108, "to": "mm"},
2479   "name": "COMPUTE_DIM_X"
2480  },
2481  {
2482   "chips": ["gfx11"],
2483   "map": {"at": 47112, "to": "mm"},
2484   "name": "COMPUTE_DIM_Y"
2485  },
2486  {
2487   "chips": ["gfx11"],
2488   "map": {"at": 47116, "to": "mm"},
2489   "name": "COMPUTE_DIM_Z"
2490  },
2491  {
2492   "chips": ["gfx11"],
2493   "map": {"at": 47120, "to": "mm"},
2494   "name": "COMPUTE_START_X"
2495  },
2496  {
2497   "chips": ["gfx11"],
2498   "map": {"at": 47124, "to": "mm"},
2499   "name": "COMPUTE_START_Y"
2500  },
2501  {
2502   "chips": ["gfx11"],
2503   "map": {"at": 47128, "to": "mm"},
2504   "name": "COMPUTE_START_Z"
2505  },
2506  {
2507   "chips": ["gfx11"],
2508   "map": {"at": 47132, "to": "mm"},
2509   "name": "COMPUTE_NUM_THREAD_X",
2510   "type_ref": "COMPUTE_NUM_THREAD_X"
2511  },
2512  {
2513   "chips": ["gfx11"],
2514   "map": {"at": 47136, "to": "mm"},
2515   "name": "COMPUTE_NUM_THREAD_Y",
2516   "type_ref": "COMPUTE_NUM_THREAD_X"
2517  },
2518  {
2519   "chips": ["gfx11"],
2520   "map": {"at": 47140, "to": "mm"},
2521   "name": "COMPUTE_NUM_THREAD_Z",
2522   "type_ref": "COMPUTE_NUM_THREAD_X"
2523  },
2524  {
2525   "chips": ["gfx11"],
2526   "map": {"at": 47144, "to": "mm"},
2527   "name": "COMPUTE_PIPELINESTAT_ENABLE",
2528   "type_ref": "COMPUTE_PIPELINESTAT_ENABLE"
2529  },
2530  {
2531   "chips": ["gfx11"],
2532   "map": {"at": 47148, "to": "mm"},
2533   "name": "COMPUTE_PERFCOUNT_ENABLE",
2534   "type_ref": "COMPUTE_PERFCOUNT_ENABLE"
2535  },
2536  {
2537   "chips": ["gfx11"],
2538   "map": {"at": 47152, "to": "mm"},
2539   "name": "COMPUTE_PGM_LO"
2540  },
2541  {
2542   "chips": ["gfx11"],
2543   "map": {"at": 47156, "to": "mm"},
2544   "name": "COMPUTE_PGM_HI",
2545   "type_ref": "COMPUTE_PGM_HI"
2546  },
2547  {
2548   "chips": ["gfx11"],
2549   "map": {"at": 47160, "to": "mm"},
2550   "name": "COMPUTE_DISPATCH_PKT_ADDR_LO"
2551  },
2552  {
2553   "chips": ["gfx11"],
2554   "map": {"at": 47164, "to": "mm"},
2555   "name": "COMPUTE_DISPATCH_PKT_ADDR_HI",
2556   "type_ref": "COMPUTE_PGM_HI"
2557  },
2558  {
2559   "chips": ["gfx11"],
2560   "map": {"at": 47168, "to": "mm"},
2561   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_LO"
2562  },
2563  {
2564   "chips": ["gfx11"],
2565   "map": {"at": 47172, "to": "mm"},
2566   "name": "COMPUTE_DISPATCH_SCRATCH_BASE_HI",
2567   "type_ref": "COMPUTE_PGM_HI"
2568  },
2569  {
2570   "chips": ["gfx11"],
2571   "map": {"at": 47176, "to": "mm"},
2572   "name": "COMPUTE_PGM_RSRC1",
2573   "type_ref": "COMPUTE_PGM_RSRC1"
2574  },
2575  {
2576   "chips": ["gfx11"],
2577   "map": {"at": 47180, "to": "mm"},
2578   "name": "COMPUTE_PGM_RSRC2",
2579   "type_ref": "COMPUTE_PGM_RSRC2"
2580  },
2581  {
2582   "chips": ["gfx11"],
2583   "map": {"at": 47184, "to": "mm"},
2584   "name": "COMPUTE_VMID",
2585   "type_ref": "COMPUTE_VMID"
2586  },
2587  {
2588   "chips": ["gfx11"],
2589   "map": {"at": 47188, "to": "mm"},
2590   "name": "COMPUTE_RESOURCE_LIMITS",
2591   "type_ref": "COMPUTE_RESOURCE_LIMITS"
2592  },
2593  {
2594   "chips": ["gfx11"],
2595   "map": {"at": 47192, "to": "mm"},
2596   "name": "COMPUTE_DESTINATION_EN_SE0"
2597  },
2598  {
2599   "chips": ["gfx11"],
2600   "map": {"at": 47196, "to": "mm"},
2601   "name": "COMPUTE_DESTINATION_EN_SE1"
2602  },
2603  {
2604   "chips": ["gfx11"],
2605   "map": {"at": 47200, "to": "mm"},
2606   "name": "COMPUTE_TMPRING_SIZE",
2607   "type_ref": "COMPUTE_TMPRING_SIZE"
2608  },
2609  {
2610   "chips": ["gfx11"],
2611   "map": {"at": 47204, "to": "mm"},
2612   "name": "COMPUTE_DESTINATION_EN_SE2"
2613  },
2614  {
2615   "chips": ["gfx11"],
2616   "map": {"at": 47208, "to": "mm"},
2617   "name": "COMPUTE_DESTINATION_EN_SE3"
2618  },
2619  {
2620   "chips": ["gfx11"],
2621   "map": {"at": 47212, "to": "mm"},
2622   "name": "COMPUTE_RESTART_X"
2623  },
2624  {
2625   "chips": ["gfx11"],
2626   "map": {"at": 47216, "to": "mm"},
2627   "name": "COMPUTE_RESTART_Y"
2628  },
2629  {
2630   "chips": ["gfx11"],
2631   "map": {"at": 47220, "to": "mm"},
2632   "name": "COMPUTE_RESTART_Z"
2633  },
2634  {
2635   "chips": ["gfx11"],
2636   "map": {"at": 47224, "to": "mm"},
2637   "name": "COMPUTE_THREAD_TRACE_ENABLE",
2638   "type_ref": "COMPUTE_THREAD_TRACE_ENABLE"
2639  },
2640  {
2641   "chips": ["gfx11"],
2642   "map": {"at": 47228, "to": "mm"},
2643   "name": "COMPUTE_MISC_RESERVED",
2644   "type_ref": "COMPUTE_MISC_RESERVED"
2645  },
2646  {
2647   "chips": ["gfx11"],
2648   "map": {"at": 47232, "to": "mm"},
2649   "name": "COMPUTE_DISPATCH_ID"
2650  },
2651  {
2652   "chips": ["gfx11"],
2653   "map": {"at": 47236, "to": "mm"},
2654   "name": "COMPUTE_THREADGROUP_ID"
2655  },
2656  {
2657   "chips": ["gfx11"],
2658   "map": {"at": 47240, "to": "mm"},
2659   "name": "COMPUTE_REQ_CTRL",
2660   "type_ref": "COMPUTE_REQ_CTRL"
2661  },
2662  {
2663   "chips": ["gfx11"],
2664   "map": {"at": 47244, "to": "mm"},
2665   "name": "GL2A_PRIORITY_CTRL"
2666  },
2667  {
2668   "chips": ["gfx11"],
2669   "map": {"at": 47248, "to": "mm"},
2670   "name": "COMPUTE_USER_ACCUM_0",
2671   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2672  },
2673  {
2674   "chips": ["gfx11"],
2675   "map": {"at": 47252, "to": "mm"},
2676   "name": "COMPUTE_USER_ACCUM_1",
2677   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2678  },
2679  {
2680   "chips": ["gfx11"],
2681   "map": {"at": 47256, "to": "mm"},
2682   "name": "COMPUTE_USER_ACCUM_2",
2683   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2684  },
2685  {
2686   "chips": ["gfx11"],
2687   "map": {"at": 47260, "to": "mm"},
2688   "name": "COMPUTE_USER_ACCUM_3",
2689   "type_ref": "SPI_SHADER_USER_ACCUM_PS_0"
2690  },
2691  {
2692   "chips": ["gfx11"],
2693   "map": {"at": 47264, "to": "mm"},
2694   "name": "COMPUTE_PGM_RSRC3",
2695   "type_ref": "COMPUTE_PGM_RSRC3"
2696  },
2697  {
2698   "chips": ["gfx11"],
2699   "map": {"at": 47268, "to": "mm"},
2700   "name": "COMPUTE_DDID_INDEX",
2701   "type_ref": "COMPUTE_DDID_INDEX"
2702  },
2703  {
2704   "chips": ["gfx11"],
2705   "map": {"at": 47272, "to": "mm"},
2706   "name": "COMPUTE_SHADER_CHKSUM"
2707  },
2708  {
2709   "chips": ["gfx11"],
2710   "map": {"at": 47276, "to": "mm"},
2711   "name": "COMPUTE_STATIC_THREAD_MGMT_SE4",
2712   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE4"
2713  },
2714  {
2715   "chips": ["gfx11"],
2716   "map": {"at": 47280, "to": "mm"},
2717   "name": "COMPUTE_STATIC_THREAD_MGMT_SE5",
2718   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE4"
2719  },
2720  {
2721   "chips": ["gfx11"],
2722   "map": {"at": 47284, "to": "mm"},
2723   "name": "COMPUTE_STATIC_THREAD_MGMT_SE6",
2724   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE4"
2725  },
2726  {
2727   "chips": ["gfx11"],
2728   "map": {"at": 47288, "to": "mm"},
2729   "name": "COMPUTE_STATIC_THREAD_MGMT_SE7",
2730   "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE4"
2731  },
2732  {
2733   "chips": ["gfx11"],
2734   "map": {"at": 47292, "to": "mm"},
2735   "name": "COMPUTE_DISPATCH_INTERLEAVE",
2736   "type_ref": "COMPUTE_DISPATCH_INTERLEAVE"
2737  },
2738  {
2739   "chips": ["gfx11"],
2740   "map": {"at": 47296, "to": "mm"},
2741   "name": "COMPUTE_RELAUNCH",
2742   "type_ref": "COMPUTE_RELAUNCH"
2743  },
2744  {
2745   "chips": ["gfx11"],
2746   "map": {"at": 47300, "to": "mm"},
2747   "name": "COMPUTE_WAVE_RESTORE_ADDR_LO"
2748  },
2749  {
2750   "chips": ["gfx11"],
2751   "map": {"at": 47304, "to": "mm"},
2752   "name": "COMPUTE_WAVE_RESTORE_ADDR_HI",
2753   "type_ref": "COMPUTE_WAVE_RESTORE_ADDR_HI"
2754  },
2755  {
2756   "chips": ["gfx11"],
2757   "map": {"at": 47308, "to": "mm"},
2758   "name": "COMPUTE_RELAUNCH2",
2759   "type_ref": "COMPUTE_RELAUNCH"
2760  },
2761  {
2762   "chips": ["gfx11"],
2763   "map": {"at": 47360, "to": "mm"},
2764   "name": "COMPUTE_USER_DATA_0"
2765  },
2766  {
2767   "chips": ["gfx11"],
2768   "map": {"at": 47364, "to": "mm"},
2769   "name": "COMPUTE_USER_DATA_1"
2770  },
2771  {
2772   "chips": ["gfx11"],
2773   "map": {"at": 47368, "to": "mm"},
2774   "name": "COMPUTE_USER_DATA_2"
2775  },
2776  {
2777   "chips": ["gfx11"],
2778   "map": {"at": 47372, "to": "mm"},
2779   "name": "COMPUTE_USER_DATA_3"
2780  },
2781  {
2782   "chips": ["gfx11"],
2783   "map": {"at": 47376, "to": "mm"},
2784   "name": "COMPUTE_USER_DATA_4"
2785  },
2786  {
2787   "chips": ["gfx11"],
2788   "map": {"at": 47380, "to": "mm"},
2789   "name": "COMPUTE_USER_DATA_5"
2790  },
2791  {
2792   "chips": ["gfx11"],
2793   "map": {"at": 47384, "to": "mm"},
2794   "name": "COMPUTE_USER_DATA_6"
2795  },
2796  {
2797   "chips": ["gfx11"],
2798   "map": {"at": 47388, "to": "mm"},
2799   "name": "COMPUTE_USER_DATA_7"
2800  },
2801  {
2802   "chips": ["gfx11"],
2803   "map": {"at": 47392, "to": "mm"},
2804   "name": "COMPUTE_USER_DATA_8"
2805  },
2806  {
2807   "chips": ["gfx11"],
2808   "map": {"at": 47396, "to": "mm"},
2809   "name": "COMPUTE_USER_DATA_9"
2810  },
2811  {
2812   "chips": ["gfx11"],
2813   "map": {"at": 47400, "to": "mm"},
2814   "name": "COMPUTE_USER_DATA_10"
2815  },
2816  {
2817   "chips": ["gfx11"],
2818   "map": {"at": 47404, "to": "mm"},
2819   "name": "COMPUTE_USER_DATA_11"
2820  },
2821  {
2822   "chips": ["gfx11"],
2823   "map": {"at": 47408, "to": "mm"},
2824   "name": "COMPUTE_USER_DATA_12"
2825  },
2826  {
2827   "chips": ["gfx11"],
2828   "map": {"at": 47412, "to": "mm"},
2829   "name": "COMPUTE_USER_DATA_13"
2830  },
2831  {
2832   "chips": ["gfx11"],
2833   "map": {"at": 47416, "to": "mm"},
2834   "name": "COMPUTE_USER_DATA_14"
2835  },
2836  {
2837   "chips": ["gfx11"],
2838   "map": {"at": 47420, "to": "mm"},
2839   "name": "COMPUTE_USER_DATA_15"
2840  },
2841  {
2842   "chips": ["gfx11"],
2843   "map": {"at": 47604, "to": "mm"},
2844   "name": "COMPUTE_DISPATCH_TUNNEL",
2845   "type_ref": "COMPUTE_DISPATCH_TUNNEL"
2846  },
2847  {
2848   "chips": ["gfx11"],
2849   "map": {"at": 47608, "to": "mm"},
2850   "name": "COMPUTE_DISPATCH_END"
2851  },
2852  {
2853   "chips": ["gfx11"],
2854   "map": {"at": 47612, "to": "mm"},
2855   "name": "COMPUTE_NOWHERE"
2856  },
2857  {
2858   "chips": ["gfx11"],
2859   "map": {"at": 47616, "to": "mm"},
2860   "name": "SH_RESERVED_REG0"
2861  },
2862  {
2863   "chips": ["gfx11"],
2864   "map": {"at": 47620, "to": "mm"},
2865   "name": "SH_RESERVED_REG1"
2866  },
2867  {
2868   "chips": ["gfx11"],
2869   "map": {"at": 163840, "to": "mm"},
2870   "name": "DB_RENDER_CONTROL",
2871   "type_ref": "DB_RENDER_CONTROL"
2872  },
2873  {
2874   "chips": ["gfx11"],
2875   "map": {"at": 163844, "to": "mm"},
2876   "name": "DB_COUNT_CONTROL",
2877   "type_ref": "DB_COUNT_CONTROL"
2878  },
2879  {
2880   "chips": ["gfx11"],
2881   "map": {"at": 163848, "to": "mm"},
2882   "name": "DB_DEPTH_VIEW",
2883   "type_ref": "DB_DEPTH_VIEW"
2884  },
2885  {
2886   "chips": ["gfx11"],
2887   "map": {"at": 163852, "to": "mm"},
2888   "name": "DB_RENDER_OVERRIDE",
2889   "type_ref": "DB_RENDER_OVERRIDE"
2890  },
2891  {
2892   "chips": ["gfx11"],
2893   "map": {"at": 163856, "to": "mm"},
2894   "name": "DB_RENDER_OVERRIDE2",
2895   "type_ref": "DB_RENDER_OVERRIDE2"
2896  },
2897  {
2898   "chips": ["gfx11"],
2899   "map": {"at": 163860, "to": "mm"},
2900   "name": "DB_HTILE_DATA_BASE"
2901  },
2902  {
2903   "chips": ["gfx11"],
2904   "map": {"at": 163868, "to": "mm"},
2905   "name": "DB_DEPTH_SIZE_XY",
2906   "type_ref": "DB_DEPTH_SIZE_XY"
2907  },
2908  {
2909   "chips": ["gfx11"],
2910   "map": {"at": 163872, "to": "mm"},
2911   "name": "DB_DEPTH_BOUNDS_MIN"
2912  },
2913  {
2914   "chips": ["gfx11"],
2915   "map": {"at": 163876, "to": "mm"},
2916   "name": "DB_DEPTH_BOUNDS_MAX"
2917  },
2918  {
2919   "chips": ["gfx11"],
2920   "map": {"at": 163880, "to": "mm"},
2921   "name": "DB_STENCIL_CLEAR",
2922   "type_ref": "DB_STENCIL_CLEAR"
2923  },
2924  {
2925   "chips": ["gfx11"],
2926   "map": {"at": 163884, "to": "mm"},
2927   "name": "DB_DEPTH_CLEAR"
2928  },
2929  {
2930   "chips": ["gfx11"],
2931   "map": {"at": 163888, "to": "mm"},
2932   "name": "PA_SC_SCREEN_SCISSOR_TL",
2933   "type_ref": "PA_SC_SCREEN_SCISSOR_TL"
2934  },
2935  {
2936   "chips": ["gfx11"],
2937   "map": {"at": 163892, "to": "mm"},
2938   "name": "PA_SC_SCREEN_SCISSOR_BR",
2939   "type_ref": "PA_SC_SCREEN_SCISSOR_BR"
2940  },
2941  {
2942   "chips": ["gfx11"],
2943   "map": {"at": 163900, "to": "mm"},
2944   "name": "DB_RESERVED_REG_2",
2945   "type_ref": "DB_RESERVED_REG_2"
2946  },
2947  {
2948   "chips": ["gfx11"],
2949   "map": {"at": 163904, "to": "mm"},
2950   "name": "DB_Z_INFO",
2951   "type_ref": "DB_Z_INFO"
2952  },
2953  {
2954   "chips": ["gfx11"],
2955   "map": {"at": 163908, "to": "mm"},
2956   "name": "DB_STENCIL_INFO",
2957   "type_ref": "DB_STENCIL_INFO"
2958  },
2959  {
2960   "chips": ["gfx11"],
2961   "map": {"at": 163912, "to": "mm"},
2962   "name": "DB_Z_READ_BASE"
2963  },
2964  {
2965   "chips": ["gfx11"],
2966   "map": {"at": 163916, "to": "mm"},
2967   "name": "DB_STENCIL_READ_BASE"
2968  },
2969  {
2970   "chips": ["gfx11"],
2971   "map": {"at": 163920, "to": "mm"},
2972   "name": "DB_Z_WRITE_BASE"
2973  },
2974  {
2975   "chips": ["gfx11"],
2976   "map": {"at": 163924, "to": "mm"},
2977   "name": "DB_STENCIL_WRITE_BASE"
2978  },
2979  {
2980   "chips": ["gfx11"],
2981   "map": {"at": 163928, "to": "mm"},
2982   "name": "DB_RESERVED_REG_1",
2983   "type_ref": "DB_RESERVED_REG_1"
2984  },
2985  {
2986   "chips": ["gfx11"],
2987   "map": {"at": 163932, "to": "mm"},
2988   "name": "DB_RESERVED_REG_3",
2989   "type_ref": "DB_RESERVED_REG_3"
2990  },
2991  {
2992   "chips": ["gfx11"],
2993   "map": {"at": 163944, "to": "mm"},
2994   "name": "DB_Z_READ_BASE_HI",
2995   "type_ref": "DB_Z_READ_BASE_HI"
2996  },
2997  {
2998   "chips": ["gfx11"],
2999   "map": {"at": 163948, "to": "mm"},
3000   "name": "DB_STENCIL_READ_BASE_HI",
3001   "type_ref": "DB_Z_READ_BASE_HI"
3002  },
3003  {
3004   "chips": ["gfx11"],
3005   "map": {"at": 163952, "to": "mm"},
3006   "name": "DB_Z_WRITE_BASE_HI",
3007   "type_ref": "DB_Z_READ_BASE_HI"
3008  },
3009  {
3010   "chips": ["gfx11"],
3011   "map": {"at": 163956, "to": "mm"},
3012   "name": "DB_STENCIL_WRITE_BASE_HI",
3013   "type_ref": "DB_Z_READ_BASE_HI"
3014  },
3015  {
3016   "chips": ["gfx11"],
3017   "map": {"at": 163960, "to": "mm"},
3018   "name": "DB_HTILE_DATA_BASE_HI",
3019   "type_ref": "DB_Z_READ_BASE_HI"
3020  },
3021  {
3022   "chips": ["gfx11"],
3023   "map": {"at": 163964, "to": "mm"},
3024   "name": "DB_RMI_L2_CACHE_CONTROL",
3025   "type_ref": "DB_RMI_L2_CACHE_CONTROL"
3026  },
3027  {
3028   "chips": ["gfx11"],
3029   "map": {"at": 163968, "to": "mm"},
3030   "name": "TA_BC_BASE_ADDR"
3031  },
3032  {
3033   "chips": ["gfx11"],
3034   "map": {"at": 163972, "to": "mm"},
3035   "name": "TA_BC_BASE_ADDR_HI",
3036   "type_ref": "TA_BC_BASE_ADDR_HI"
3037  },
3038  {
3039   "chips": ["gfx11"],
3040   "map": {"at": 164328, "to": "mm"},
3041   "name": "COHER_DEST_BASE_HI_0",
3042   "type_ref": "COHER_DEST_BASE_HI_0"
3043  },
3044  {
3045   "chips": ["gfx11"],
3046   "map": {"at": 164332, "to": "mm"},
3047   "name": "COHER_DEST_BASE_HI_1",
3048   "type_ref": "COHER_DEST_BASE_HI_0"
3049  },
3050  {
3051   "chips": ["gfx11"],
3052   "map": {"at": 164336, "to": "mm"},
3053   "name": "COHER_DEST_BASE_HI_2",
3054   "type_ref": "COHER_DEST_BASE_HI_0"
3055  },
3056  {
3057   "chips": ["gfx11"],
3058   "map": {"at": 164340, "to": "mm"},
3059   "name": "COHER_DEST_BASE_HI_3",
3060   "type_ref": "COHER_DEST_BASE_HI_0"
3061  },
3062  {
3063   "chips": ["gfx11"],
3064   "map": {"at": 164344, "to": "mm"},
3065   "name": "COHER_DEST_BASE_2"
3066  },
3067  {
3068   "chips": ["gfx11"],
3069   "map": {"at": 164348, "to": "mm"},
3070   "name": "COHER_DEST_BASE_3"
3071  },
3072  {
3073   "chips": ["gfx11"],
3074   "map": {"at": 164352, "to": "mm"},
3075   "name": "PA_SC_WINDOW_OFFSET",
3076   "type_ref": "PA_SC_WINDOW_OFFSET"
3077  },
3078  {
3079   "chips": ["gfx11"],
3080   "map": {"at": 164356, "to": "mm"},
3081   "name": "PA_SC_WINDOW_SCISSOR_TL",
3082   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3083  },
3084  {
3085   "chips": ["gfx11"],
3086   "map": {"at": 164360, "to": "mm"},
3087   "name": "PA_SC_WINDOW_SCISSOR_BR",
3088   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3089  },
3090  {
3091   "chips": ["gfx11"],
3092   "map": {"at": 164364, "to": "mm"},
3093   "name": "PA_SC_CLIPRECT_RULE",
3094   "type_ref": "PA_SC_CLIPRECT_RULE"
3095  },
3096  {
3097   "chips": ["gfx11"],
3098   "map": {"at": 164368, "to": "mm"},
3099   "name": "PA_SC_CLIPRECT_0_TL",
3100   "type_ref": "PA_SC_CLIPRECT_0_TL"
3101  },
3102  {
3103   "chips": ["gfx11"],
3104   "map": {"at": 164372, "to": "mm"},
3105   "name": "PA_SC_CLIPRECT_0_BR",
3106   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3107  },
3108  {
3109   "chips": ["gfx11"],
3110   "map": {"at": 164376, "to": "mm"},
3111   "name": "PA_SC_CLIPRECT_1_TL",
3112   "type_ref": "PA_SC_CLIPRECT_0_TL"
3113  },
3114  {
3115   "chips": ["gfx11"],
3116   "map": {"at": 164380, "to": "mm"},
3117   "name": "PA_SC_CLIPRECT_1_BR",
3118   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3119  },
3120  {
3121   "chips": ["gfx11"],
3122   "map": {"at": 164384, "to": "mm"},
3123   "name": "PA_SC_CLIPRECT_2_TL",
3124   "type_ref": "PA_SC_CLIPRECT_0_TL"
3125  },
3126  {
3127   "chips": ["gfx11"],
3128   "map": {"at": 164388, "to": "mm"},
3129   "name": "PA_SC_CLIPRECT_2_BR",
3130   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3131  },
3132  {
3133   "chips": ["gfx11"],
3134   "map": {"at": 164392, "to": "mm"},
3135   "name": "PA_SC_CLIPRECT_3_TL",
3136   "type_ref": "PA_SC_CLIPRECT_0_TL"
3137  },
3138  {
3139   "chips": ["gfx11"],
3140   "map": {"at": 164396, "to": "mm"},
3141   "name": "PA_SC_CLIPRECT_3_BR",
3142   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3143  },
3144  {
3145   "chips": ["gfx11"],
3146   "map": {"at": 164400, "to": "mm"},
3147   "name": "PA_SC_EDGERULE",
3148   "type_ref": "PA_SC_EDGERULE"
3149  },
3150  {
3151   "chips": ["gfx11"],
3152   "map": {"at": 164404, "to": "mm"},
3153   "name": "PA_SU_HARDWARE_SCREEN_OFFSET",
3154   "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET"
3155  },
3156  {
3157   "chips": ["gfx11"],
3158   "map": {"at": 164408, "to": "mm"},
3159   "name": "CB_TARGET_MASK",
3160   "type_ref": "CB_TARGET_MASK"
3161  },
3162  {
3163   "chips": ["gfx11"],
3164   "map": {"at": 164412, "to": "mm"},
3165   "name": "CB_SHADER_MASK",
3166   "type_ref": "CB_SHADER_MASK"
3167  },
3168  {
3169   "chips": ["gfx11"],
3170   "map": {"at": 164416, "to": "mm"},
3171   "name": "PA_SC_GENERIC_SCISSOR_TL",
3172   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3173  },
3174  {
3175   "chips": ["gfx11"],
3176   "map": {"at": 164420, "to": "mm"},
3177   "name": "PA_SC_GENERIC_SCISSOR_BR",
3178   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3179  },
3180  {
3181   "chips": ["gfx11"],
3182   "map": {"at": 164424, "to": "mm"},
3183   "name": "COHER_DEST_BASE_0"
3184  },
3185  {
3186   "chips": ["gfx11"],
3187   "map": {"at": 164428, "to": "mm"},
3188   "name": "COHER_DEST_BASE_1"
3189  },
3190  {
3191   "chips": ["gfx11"],
3192   "map": {"at": 164432, "to": "mm"},
3193   "name": "PA_SC_VPORT_SCISSOR_0_TL",
3194   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3195  },
3196  {
3197   "chips": ["gfx11"],
3198   "map": {"at": 164436, "to": "mm"},
3199   "name": "PA_SC_VPORT_SCISSOR_0_BR",
3200   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3201  },
3202  {
3203   "chips": ["gfx11"],
3204   "map": {"at": 164440, "to": "mm"},
3205   "name": "PA_SC_VPORT_SCISSOR_1_TL",
3206   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3207  },
3208  {
3209   "chips": ["gfx11"],
3210   "map": {"at": 164444, "to": "mm"},
3211   "name": "PA_SC_VPORT_SCISSOR_1_BR",
3212   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3213  },
3214  {
3215   "chips": ["gfx11"],
3216   "map": {"at": 164448, "to": "mm"},
3217   "name": "PA_SC_VPORT_SCISSOR_2_TL",
3218   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3219  },
3220  {
3221   "chips": ["gfx11"],
3222   "map": {"at": 164452, "to": "mm"},
3223   "name": "PA_SC_VPORT_SCISSOR_2_BR",
3224   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3225  },
3226  {
3227   "chips": ["gfx11"],
3228   "map": {"at": 164456, "to": "mm"},
3229   "name": "PA_SC_VPORT_SCISSOR_3_TL",
3230   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3231  },
3232  {
3233   "chips": ["gfx11"],
3234   "map": {"at": 164460, "to": "mm"},
3235   "name": "PA_SC_VPORT_SCISSOR_3_BR",
3236   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3237  },
3238  {
3239   "chips": ["gfx11"],
3240   "map": {"at": 164464, "to": "mm"},
3241   "name": "PA_SC_VPORT_SCISSOR_4_TL",
3242   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3243  },
3244  {
3245   "chips": ["gfx11"],
3246   "map": {"at": 164468, "to": "mm"},
3247   "name": "PA_SC_VPORT_SCISSOR_4_BR",
3248   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3249  },
3250  {
3251   "chips": ["gfx11"],
3252   "map": {"at": 164472, "to": "mm"},
3253   "name": "PA_SC_VPORT_SCISSOR_5_TL",
3254   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3255  },
3256  {
3257   "chips": ["gfx11"],
3258   "map": {"at": 164476, "to": "mm"},
3259   "name": "PA_SC_VPORT_SCISSOR_5_BR",
3260   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3261  },
3262  {
3263   "chips": ["gfx11"],
3264   "map": {"at": 164480, "to": "mm"},
3265   "name": "PA_SC_VPORT_SCISSOR_6_TL",
3266   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3267  },
3268  {
3269   "chips": ["gfx11"],
3270   "map": {"at": 164484, "to": "mm"},
3271   "name": "PA_SC_VPORT_SCISSOR_6_BR",
3272   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3273  },
3274  {
3275   "chips": ["gfx11"],
3276   "map": {"at": 164488, "to": "mm"},
3277   "name": "PA_SC_VPORT_SCISSOR_7_TL",
3278   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3279  },
3280  {
3281   "chips": ["gfx11"],
3282   "map": {"at": 164492, "to": "mm"},
3283   "name": "PA_SC_VPORT_SCISSOR_7_BR",
3284   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3285  },
3286  {
3287   "chips": ["gfx11"],
3288   "map": {"at": 164496, "to": "mm"},
3289   "name": "PA_SC_VPORT_SCISSOR_8_TL",
3290   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3291  },
3292  {
3293   "chips": ["gfx11"],
3294   "map": {"at": 164500, "to": "mm"},
3295   "name": "PA_SC_VPORT_SCISSOR_8_BR",
3296   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3297  },
3298  {
3299   "chips": ["gfx11"],
3300   "map": {"at": 164504, "to": "mm"},
3301   "name": "PA_SC_VPORT_SCISSOR_9_TL",
3302   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3303  },
3304  {
3305   "chips": ["gfx11"],
3306   "map": {"at": 164508, "to": "mm"},
3307   "name": "PA_SC_VPORT_SCISSOR_9_BR",
3308   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3309  },
3310  {
3311   "chips": ["gfx11"],
3312   "map": {"at": 164512, "to": "mm"},
3313   "name": "PA_SC_VPORT_SCISSOR_10_TL",
3314   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3315  },
3316  {
3317   "chips": ["gfx11"],
3318   "map": {"at": 164516, "to": "mm"},
3319   "name": "PA_SC_VPORT_SCISSOR_10_BR",
3320   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3321  },
3322  {
3323   "chips": ["gfx11"],
3324   "map": {"at": 164520, "to": "mm"},
3325   "name": "PA_SC_VPORT_SCISSOR_11_TL",
3326   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3327  },
3328  {
3329   "chips": ["gfx11"],
3330   "map": {"at": 164524, "to": "mm"},
3331   "name": "PA_SC_VPORT_SCISSOR_11_BR",
3332   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3333  },
3334  {
3335   "chips": ["gfx11"],
3336   "map": {"at": 164528, "to": "mm"},
3337   "name": "PA_SC_VPORT_SCISSOR_12_TL",
3338   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3339  },
3340  {
3341   "chips": ["gfx11"],
3342   "map": {"at": 164532, "to": "mm"},
3343   "name": "PA_SC_VPORT_SCISSOR_12_BR",
3344   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3345  },
3346  {
3347   "chips": ["gfx11"],
3348   "map": {"at": 164536, "to": "mm"},
3349   "name": "PA_SC_VPORT_SCISSOR_13_TL",
3350   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3351  },
3352  {
3353   "chips": ["gfx11"],
3354   "map": {"at": 164540, "to": "mm"},
3355   "name": "PA_SC_VPORT_SCISSOR_13_BR",
3356   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3357  },
3358  {
3359   "chips": ["gfx11"],
3360   "map": {"at": 164544, "to": "mm"},
3361   "name": "PA_SC_VPORT_SCISSOR_14_TL",
3362   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3363  },
3364  {
3365   "chips": ["gfx11"],
3366   "map": {"at": 164548, "to": "mm"},
3367   "name": "PA_SC_VPORT_SCISSOR_14_BR",
3368   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3369  },
3370  {
3371   "chips": ["gfx11"],
3372   "map": {"at": 164552, "to": "mm"},
3373   "name": "PA_SC_VPORT_SCISSOR_15_TL",
3374   "type_ref": "PA_SC_WINDOW_SCISSOR_TL"
3375  },
3376  {
3377   "chips": ["gfx11"],
3378   "map": {"at": 164556, "to": "mm"},
3379   "name": "PA_SC_VPORT_SCISSOR_15_BR",
3380   "type_ref": "PA_SC_WINDOW_SCISSOR_BR"
3381  },
3382  {
3383   "chips": ["gfx11"],
3384   "map": {"at": 164560, "to": "mm"},
3385   "name": "PA_SC_VPORT_ZMIN_0"
3386  },
3387  {
3388   "chips": ["gfx11"],
3389   "map": {"at": 164564, "to": "mm"},
3390   "name": "PA_SC_VPORT_ZMAX_0"
3391  },
3392  {
3393   "chips": ["gfx11"],
3394   "map": {"at": 164568, "to": "mm"},
3395   "name": "PA_SC_VPORT_ZMIN_1"
3396  },
3397  {
3398   "chips": ["gfx11"],
3399   "map": {"at": 164572, "to": "mm"},
3400   "name": "PA_SC_VPORT_ZMAX_1"
3401  },
3402  {
3403   "chips": ["gfx11"],
3404   "map": {"at": 164576, "to": "mm"},
3405   "name": "PA_SC_VPORT_ZMIN_2"
3406  },
3407  {
3408   "chips": ["gfx11"],
3409   "map": {"at": 164580, "to": "mm"},
3410   "name": "PA_SC_VPORT_ZMAX_2"
3411  },
3412  {
3413   "chips": ["gfx11"],
3414   "map": {"at": 164584, "to": "mm"},
3415   "name": "PA_SC_VPORT_ZMIN_3"
3416  },
3417  {
3418   "chips": ["gfx11"],
3419   "map": {"at": 164588, "to": "mm"},
3420   "name": "PA_SC_VPORT_ZMAX_3"
3421  },
3422  {
3423   "chips": ["gfx11"],
3424   "map": {"at": 164592, "to": "mm"},
3425   "name": "PA_SC_VPORT_ZMIN_4"
3426  },
3427  {
3428   "chips": ["gfx11"],
3429   "map": {"at": 164596, "to": "mm"},
3430   "name": "PA_SC_VPORT_ZMAX_4"
3431  },
3432  {
3433   "chips": ["gfx11"],
3434   "map": {"at": 164600, "to": "mm"},
3435   "name": "PA_SC_VPORT_ZMIN_5"
3436  },
3437  {
3438   "chips": ["gfx11"],
3439   "map": {"at": 164604, "to": "mm"},
3440   "name": "PA_SC_VPORT_ZMAX_5"
3441  },
3442  {
3443   "chips": ["gfx11"],
3444   "map": {"at": 164608, "to": "mm"},
3445   "name": "PA_SC_VPORT_ZMIN_6"
3446  },
3447  {
3448   "chips": ["gfx11"],
3449   "map": {"at": 164612, "to": "mm"},
3450   "name": "PA_SC_VPORT_ZMAX_6"
3451  },
3452  {
3453   "chips": ["gfx11"],
3454   "map": {"at": 164616, "to": "mm"},
3455   "name": "PA_SC_VPORT_ZMIN_7"
3456  },
3457  {
3458   "chips": ["gfx11"],
3459   "map": {"at": 164620, "to": "mm"},
3460   "name": "PA_SC_VPORT_ZMAX_7"
3461  },
3462  {
3463   "chips": ["gfx11"],
3464   "map": {"at": 164624, "to": "mm"},
3465   "name": "PA_SC_VPORT_ZMIN_8"
3466  },
3467  {
3468   "chips": ["gfx11"],
3469   "map": {"at": 164628, "to": "mm"},
3470   "name": "PA_SC_VPORT_ZMAX_8"
3471  },
3472  {
3473   "chips": ["gfx11"],
3474   "map": {"at": 164632, "to": "mm"},
3475   "name": "PA_SC_VPORT_ZMIN_9"
3476  },
3477  {
3478   "chips": ["gfx11"],
3479   "map": {"at": 164636, "to": "mm"},
3480   "name": "PA_SC_VPORT_ZMAX_9"
3481  },
3482  {
3483   "chips": ["gfx11"],
3484   "map": {"at": 164640, "to": "mm"},
3485   "name": "PA_SC_VPORT_ZMIN_10"
3486  },
3487  {
3488   "chips": ["gfx11"],
3489   "map": {"at": 164644, "to": "mm"},
3490   "name": "PA_SC_VPORT_ZMAX_10"
3491  },
3492  {
3493   "chips": ["gfx11"],
3494   "map": {"at": 164648, "to": "mm"},
3495   "name": "PA_SC_VPORT_ZMIN_11"
3496  },
3497  {
3498   "chips": ["gfx11"],
3499   "map": {"at": 164652, "to": "mm"},
3500   "name": "PA_SC_VPORT_ZMAX_11"
3501  },
3502  {
3503   "chips": ["gfx11"],
3504   "map": {"at": 164656, "to": "mm"},
3505   "name": "PA_SC_VPORT_ZMIN_12"
3506  },
3507  {
3508   "chips": ["gfx11"],
3509   "map": {"at": 164660, "to": "mm"},
3510   "name": "PA_SC_VPORT_ZMAX_12"
3511  },
3512  {
3513   "chips": ["gfx11"],
3514   "map": {"at": 164664, "to": "mm"},
3515   "name": "PA_SC_VPORT_ZMIN_13"
3516  },
3517  {
3518   "chips": ["gfx11"],
3519   "map": {"at": 164668, "to": "mm"},
3520   "name": "PA_SC_VPORT_ZMAX_13"
3521  },
3522  {
3523   "chips": ["gfx11"],
3524   "map": {"at": 164672, "to": "mm"},
3525   "name": "PA_SC_VPORT_ZMIN_14"
3526  },
3527  {
3528   "chips": ["gfx11"],
3529   "map": {"at": 164676, "to": "mm"},
3530   "name": "PA_SC_VPORT_ZMAX_14"
3531  },
3532  {
3533   "chips": ["gfx11"],
3534   "map": {"at": 164680, "to": "mm"},
3535   "name": "PA_SC_VPORT_ZMIN_15"
3536  },
3537  {
3538   "chips": ["gfx11"],
3539   "map": {"at": 164684, "to": "mm"},
3540   "name": "PA_SC_VPORT_ZMAX_15"
3541  },
3542  {
3543   "chips": ["gfx11"],
3544   "map": {"at": 164688, "to": "mm"},
3545   "name": "PA_SC_RASTER_CONFIG",
3546   "type_ref": "PA_SC_RASTER_CONFIG"
3547  },
3548  {
3549   "chips": ["gfx11"],
3550   "map": {"at": 164692, "to": "mm"},
3551   "name": "PA_SC_RASTER_CONFIG_1",
3552   "type_ref": "PA_SC_RASTER_CONFIG_1"
3553  },
3554  {
3555   "chips": ["gfx11"],
3556   "map": {"at": 164696, "to": "mm"},
3557   "name": "PA_SC_SCREEN_EXTENT_CONTROL",
3558   "type_ref": "PA_SC_SCREEN_EXTENT_CONTROL"
3559  },
3560  {
3561   "chips": ["gfx11"],
3562   "map": {"at": 164700, "to": "mm"},
3563   "name": "PA_SC_TILE_STEERING_OVERRIDE",
3564   "type_ref": "PA_SC_TILE_STEERING_OVERRIDE"
3565  },
3566  {
3567   "chips": ["gfx11"],
3568   "map": {"at": 164704, "to": "mm"},
3569   "name": "CP_PERFMON_CNTX_CNTL",
3570   "type_ref": "CP_PERFMON_CNTX_CNTL"
3571  },
3572  {
3573   "chips": ["gfx11"],
3574   "map": {"at": 164708, "to": "mm"},
3575   "name": "CP_PIPEID",
3576   "type_ref": "CP_PIPEID"
3577  },
3578  {
3579   "chips": ["gfx11"],
3580   "map": {"at": 164712, "to": "mm"},
3581   "name": "CP_VMID",
3582   "type_ref": "CP_VMID"
3583  },
3584  {
3585   "chips": ["gfx11"],
3586   "map": {"at": 164716, "to": "mm"},
3587   "name": "CONTEXT_RESERVED_REG0"
3588  },
3589  {
3590   "chips": ["gfx11"],
3591   "map": {"at": 164720, "to": "mm"},
3592   "name": "CONTEXT_RESERVED_REG1"
3593  },
3594  {
3595   "chips": ["gfx11"],
3596   "map": {"at": 164816, "to": "mm"},
3597   "name": "PA_SC_VRS_OVERRIDE_CNTL",
3598   "type_ref": "PA_SC_VRS_OVERRIDE_CNTL"
3599  },
3600  {
3601   "chips": ["gfx11"],
3602   "map": {"at": 164820, "to": "mm"},
3603   "name": "PA_SC_VRS_RATE_FEEDBACK_BASE"
3604  },
3605  {
3606   "chips": ["gfx11"],
3607   "map": {"at": 164824, "to": "mm"},
3608   "name": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT",
3609   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
3610  },
3611  {
3612   "chips": ["gfx11"],
3613   "map": {"at": 164828, "to": "mm"},
3614   "name": "PA_SC_VRS_RATE_FEEDBACK_SIZE_XY",
3615   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_SIZE_XY"
3616  },
3617  {
3618   "chips": ["gfx11"],
3619   "map": {"at": 164836, "to": "mm"},
3620   "name": "PA_SC_VRS_RATE_CACHE_CNTL",
3621   "type_ref": "PA_SC_VRS_RATE_CACHE_CNTL"
3622  },
3623  {
3624   "chips": ["gfx11"],
3625   "map": {"at": 164848, "to": "mm"},
3626   "name": "PA_SC_VRS_RATE_BASE"
3627  },
3628  {
3629   "chips": ["gfx11"],
3630   "map": {"at": 164852, "to": "mm"},
3631   "name": "PA_SC_VRS_RATE_BASE_EXT",
3632   "type_ref": "PA_SC_VRS_RATE_BASE_EXT"
3633  },
3634  {
3635   "chips": ["gfx11"],
3636   "map": {"at": 164856, "to": "mm"},
3637   "name": "PA_SC_VRS_RATE_SIZE_XY",
3638   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_SIZE_XY"
3639  },
3640  {
3641   "chips": ["gfx11"],
3642   "map": {"at": 164876, "to": "mm"},
3643   "name": "VGT_MULTI_PRIM_IB_RESET_INDX"
3644  },
3645  {
3646   "chips": ["gfx11"],
3647   "map": {"at": 164880, "to": "mm"},
3648   "name": "CB_RMI_GL2_CACHE_CONTROL",
3649   "type_ref": "CB_RMI_GL2_CACHE_CONTROL"
3650  },
3651  {
3652   "chips": ["gfx11"],
3653   "map": {"at": 164884, "to": "mm"},
3654   "name": "CB_BLEND_RED"
3655  },
3656  {
3657   "chips": ["gfx11"],
3658   "map": {"at": 164888, "to": "mm"},
3659   "name": "CB_BLEND_GREEN"
3660  },
3661  {
3662   "chips": ["gfx11"],
3663   "map": {"at": 164892, "to": "mm"},
3664   "name": "CB_BLEND_BLUE"
3665  },
3666  {
3667   "chips": ["gfx11"],
3668   "map": {"at": 164896, "to": "mm"},
3669   "name": "CB_BLEND_ALPHA"
3670  },
3671  {
3672   "chips": ["gfx11"],
3673   "map": {"at": 164900, "to": "mm"},
3674   "name": "CB_FDCC_CONTROL",
3675   "type_ref": "CB_FDCC_CONTROL"
3676  },
3677  {
3678   "chips": ["gfx11"],
3679   "map": {"at": 164904, "to": "mm"},
3680   "name": "CB_COVERAGE_OUT_CONTROL",
3681   "type_ref": "CB_COVERAGE_OUT_CONTROL"
3682  },
3683  {
3684   "chips": ["gfx11"],
3685   "map": {"at": 164908, "to": "mm"},
3686   "name": "DB_STENCIL_CONTROL",
3687   "type_ref": "DB_STENCIL_CONTROL"
3688  },
3689  {
3690   "chips": ["gfx11"],
3691   "map": {"at": 164912, "to": "mm"},
3692   "name": "DB_STENCILREFMASK",
3693   "type_ref": "DB_STENCILREFMASK"
3694  },
3695  {
3696   "chips": ["gfx11"],
3697   "map": {"at": 164916, "to": "mm"},
3698   "name": "DB_STENCILREFMASK_BF",
3699   "type_ref": "DB_STENCILREFMASK_BF"
3700  },
3701  {
3702   "chips": ["gfx11"],
3703   "map": {"at": 164924, "to": "mm"},
3704   "name": "PA_CL_VPORT_XSCALE"
3705  },
3706  {
3707   "chips": ["gfx11"],
3708   "map": {"at": 164928, "to": "mm"},
3709   "name": "PA_CL_VPORT_XOFFSET"
3710  },
3711  {
3712   "chips": ["gfx11"],
3713   "map": {"at": 164932, "to": "mm"},
3714   "name": "PA_CL_VPORT_YSCALE"
3715  },
3716  {
3717   "chips": ["gfx11"],
3718   "map": {"at": 164936, "to": "mm"},
3719   "name": "PA_CL_VPORT_YOFFSET"
3720  },
3721  {
3722   "chips": ["gfx11"],
3723   "map": {"at": 164940, "to": "mm"},
3724   "name": "PA_CL_VPORT_ZSCALE"
3725  },
3726  {
3727   "chips": ["gfx11"],
3728   "map": {"at": 164944, "to": "mm"},
3729   "name": "PA_CL_VPORT_ZOFFSET"
3730  },
3731  {
3732   "chips": ["gfx11"],
3733   "map": {"at": 164948, "to": "mm"},
3734   "name": "PA_CL_VPORT_XSCALE_1"
3735  },
3736  {
3737   "chips": ["gfx11"],
3738   "map": {"at": 164952, "to": "mm"},
3739   "name": "PA_CL_VPORT_XOFFSET_1"
3740  },
3741  {
3742   "chips": ["gfx11"],
3743   "map": {"at": 164956, "to": "mm"},
3744   "name": "PA_CL_VPORT_YSCALE_1"
3745  },
3746  {
3747   "chips": ["gfx11"],
3748   "map": {"at": 164960, "to": "mm"},
3749   "name": "PA_CL_VPORT_YOFFSET_1"
3750  },
3751  {
3752   "chips": ["gfx11"],
3753   "map": {"at": 164964, "to": "mm"},
3754   "name": "PA_CL_VPORT_ZSCALE_1"
3755  },
3756  {
3757   "chips": ["gfx11"],
3758   "map": {"at": 164968, "to": "mm"},
3759   "name": "PA_CL_VPORT_ZOFFSET_1"
3760  },
3761  {
3762   "chips": ["gfx11"],
3763   "map": {"at": 164972, "to": "mm"},
3764   "name": "PA_CL_VPORT_XSCALE_2"
3765  },
3766  {
3767   "chips": ["gfx11"],
3768   "map": {"at": 164976, "to": "mm"},
3769   "name": "PA_CL_VPORT_XOFFSET_2"
3770  },
3771  {
3772   "chips": ["gfx11"],
3773   "map": {"at": 164980, "to": "mm"},
3774   "name": "PA_CL_VPORT_YSCALE_2"
3775  },
3776  {
3777   "chips": ["gfx11"],
3778   "map": {"at": 164984, "to": "mm"},
3779   "name": "PA_CL_VPORT_YOFFSET_2"
3780  },
3781  {
3782   "chips": ["gfx11"],
3783   "map": {"at": 164988, "to": "mm"},
3784   "name": "PA_CL_VPORT_ZSCALE_2"
3785  },
3786  {
3787   "chips": ["gfx11"],
3788   "map": {"at": 164992, "to": "mm"},
3789   "name": "PA_CL_VPORT_ZOFFSET_2"
3790  },
3791  {
3792   "chips": ["gfx11"],
3793   "map": {"at": 164996, "to": "mm"},
3794   "name": "PA_CL_VPORT_XSCALE_3"
3795  },
3796  {
3797   "chips": ["gfx11"],
3798   "map": {"at": 165000, "to": "mm"},
3799   "name": "PA_CL_VPORT_XOFFSET_3"
3800  },
3801  {
3802   "chips": ["gfx11"],
3803   "map": {"at": 165004, "to": "mm"},
3804   "name": "PA_CL_VPORT_YSCALE_3"
3805  },
3806  {
3807   "chips": ["gfx11"],
3808   "map": {"at": 165008, "to": "mm"},
3809   "name": "PA_CL_VPORT_YOFFSET_3"
3810  },
3811  {
3812   "chips": ["gfx11"],
3813   "map": {"at": 165012, "to": "mm"},
3814   "name": "PA_CL_VPORT_ZSCALE_3"
3815  },
3816  {
3817   "chips": ["gfx11"],
3818   "map": {"at": 165016, "to": "mm"},
3819   "name": "PA_CL_VPORT_ZOFFSET_3"
3820  },
3821  {
3822   "chips": ["gfx11"],
3823   "map": {"at": 165020, "to": "mm"},
3824   "name": "PA_CL_VPORT_XSCALE_4"
3825  },
3826  {
3827   "chips": ["gfx11"],
3828   "map": {"at": 165024, "to": "mm"},
3829   "name": "PA_CL_VPORT_XOFFSET_4"
3830  },
3831  {
3832   "chips": ["gfx11"],
3833   "map": {"at": 165028, "to": "mm"},
3834   "name": "PA_CL_VPORT_YSCALE_4"
3835  },
3836  {
3837   "chips": ["gfx11"],
3838   "map": {"at": 165032, "to": "mm"},
3839   "name": "PA_CL_VPORT_YOFFSET_4"
3840  },
3841  {
3842   "chips": ["gfx11"],
3843   "map": {"at": 165036, "to": "mm"},
3844   "name": "PA_CL_VPORT_ZSCALE_4"
3845  },
3846  {
3847   "chips": ["gfx11"],
3848   "map": {"at": 165040, "to": "mm"},
3849   "name": "PA_CL_VPORT_ZOFFSET_4"
3850  },
3851  {
3852   "chips": ["gfx11"],
3853   "map": {"at": 165044, "to": "mm"},
3854   "name": "PA_CL_VPORT_XSCALE_5"
3855  },
3856  {
3857   "chips": ["gfx11"],
3858   "map": {"at": 165048, "to": "mm"},
3859   "name": "PA_CL_VPORT_XOFFSET_5"
3860  },
3861  {
3862   "chips": ["gfx11"],
3863   "map": {"at": 165052, "to": "mm"},
3864   "name": "PA_CL_VPORT_YSCALE_5"
3865  },
3866  {
3867   "chips": ["gfx11"],
3868   "map": {"at": 165056, "to": "mm"},
3869   "name": "PA_CL_VPORT_YOFFSET_5"
3870  },
3871  {
3872   "chips": ["gfx11"],
3873   "map": {"at": 165060, "to": "mm"},
3874   "name": "PA_CL_VPORT_ZSCALE_5"
3875  },
3876  {
3877   "chips": ["gfx11"],
3878   "map": {"at": 165064, "to": "mm"},
3879   "name": "PA_CL_VPORT_ZOFFSET_5"
3880  },
3881  {
3882   "chips": ["gfx11"],
3883   "map": {"at": 165068, "to": "mm"},
3884   "name": "PA_CL_VPORT_XSCALE_6"
3885  },
3886  {
3887   "chips": ["gfx11"],
3888   "map": {"at": 165072, "to": "mm"},
3889   "name": "PA_CL_VPORT_XOFFSET_6"
3890  },
3891  {
3892   "chips": ["gfx11"],
3893   "map": {"at": 165076, "to": "mm"},
3894   "name": "PA_CL_VPORT_YSCALE_6"
3895  },
3896  {
3897   "chips": ["gfx11"],
3898   "map": {"at": 165080, "to": "mm"},
3899   "name": "PA_CL_VPORT_YOFFSET_6"
3900  },
3901  {
3902   "chips": ["gfx11"],
3903   "map": {"at": 165084, "to": "mm"},
3904   "name": "PA_CL_VPORT_ZSCALE_6"
3905  },
3906  {
3907   "chips": ["gfx11"],
3908   "map": {"at": 165088, "to": "mm"},
3909   "name": "PA_CL_VPORT_ZOFFSET_6"
3910  },
3911  {
3912   "chips": ["gfx11"],
3913   "map": {"at": 165092, "to": "mm"},
3914   "name": "PA_CL_VPORT_XSCALE_7"
3915  },
3916  {
3917   "chips": ["gfx11"],
3918   "map": {"at": 165096, "to": "mm"},
3919   "name": "PA_CL_VPORT_XOFFSET_7"
3920  },
3921  {
3922   "chips": ["gfx11"],
3923   "map": {"at": 165100, "to": "mm"},
3924   "name": "PA_CL_VPORT_YSCALE_7"
3925  },
3926  {
3927   "chips": ["gfx11"],
3928   "map": {"at": 165104, "to": "mm"},
3929   "name": "PA_CL_VPORT_YOFFSET_7"
3930  },
3931  {
3932   "chips": ["gfx11"],
3933   "map": {"at": 165108, "to": "mm"},
3934   "name": "PA_CL_VPORT_ZSCALE_7"
3935  },
3936  {
3937   "chips": ["gfx11"],
3938   "map": {"at": 165112, "to": "mm"},
3939   "name": "PA_CL_VPORT_ZOFFSET_7"
3940  },
3941  {
3942   "chips": ["gfx11"],
3943   "map": {"at": 165116, "to": "mm"},
3944   "name": "PA_CL_VPORT_XSCALE_8"
3945  },
3946  {
3947   "chips": ["gfx11"],
3948   "map": {"at": 165120, "to": "mm"},
3949   "name": "PA_CL_VPORT_XOFFSET_8"
3950  },
3951  {
3952   "chips": ["gfx11"],
3953   "map": {"at": 165124, "to": "mm"},
3954   "name": "PA_CL_VPORT_YSCALE_8"
3955  },
3956  {
3957   "chips": ["gfx11"],
3958   "map": {"at": 165128, "to": "mm"},
3959   "name": "PA_CL_VPORT_YOFFSET_8"
3960  },
3961  {
3962   "chips": ["gfx11"],
3963   "map": {"at": 165132, "to": "mm"},
3964   "name": "PA_CL_VPORT_ZSCALE_8"
3965  },
3966  {
3967   "chips": ["gfx11"],
3968   "map": {"at": 165136, "to": "mm"},
3969   "name": "PA_CL_VPORT_ZOFFSET_8"
3970  },
3971  {
3972   "chips": ["gfx11"],
3973   "map": {"at": 165140, "to": "mm"},
3974   "name": "PA_CL_VPORT_XSCALE_9"
3975  },
3976  {
3977   "chips": ["gfx11"],
3978   "map": {"at": 165144, "to": "mm"},
3979   "name": "PA_CL_VPORT_XOFFSET_9"
3980  },
3981  {
3982   "chips": ["gfx11"],
3983   "map": {"at": 165148, "to": "mm"},
3984   "name": "PA_CL_VPORT_YSCALE_9"
3985  },
3986  {
3987   "chips": ["gfx11"],
3988   "map": {"at": 165152, "to": "mm"},
3989   "name": "PA_CL_VPORT_YOFFSET_9"
3990  },
3991  {
3992   "chips": ["gfx11"],
3993   "map": {"at": 165156, "to": "mm"},
3994   "name": "PA_CL_VPORT_ZSCALE_9"
3995  },
3996  {
3997   "chips": ["gfx11"],
3998   "map": {"at": 165160, "to": "mm"},
3999   "name": "PA_CL_VPORT_ZOFFSET_9"
4000  },
4001  {
4002   "chips": ["gfx11"],
4003   "map": {"at": 165164, "to": "mm"},
4004   "name": "PA_CL_VPORT_XSCALE_10"
4005  },
4006  {
4007   "chips": ["gfx11"],
4008   "map": {"at": 165168, "to": "mm"},
4009   "name": "PA_CL_VPORT_XOFFSET_10"
4010  },
4011  {
4012   "chips": ["gfx11"],
4013   "map": {"at": 165172, "to": "mm"},
4014   "name": "PA_CL_VPORT_YSCALE_10"
4015  },
4016  {
4017   "chips": ["gfx11"],
4018   "map": {"at": 165176, "to": "mm"},
4019   "name": "PA_CL_VPORT_YOFFSET_10"
4020  },
4021  {
4022   "chips": ["gfx11"],
4023   "map": {"at": 165180, "to": "mm"},
4024   "name": "PA_CL_VPORT_ZSCALE_10"
4025  },
4026  {
4027   "chips": ["gfx11"],
4028   "map": {"at": 165184, "to": "mm"},
4029   "name": "PA_CL_VPORT_ZOFFSET_10"
4030  },
4031  {
4032   "chips": ["gfx11"],
4033   "map": {"at": 165188, "to": "mm"},
4034   "name": "PA_CL_VPORT_XSCALE_11"
4035  },
4036  {
4037   "chips": ["gfx11"],
4038   "map": {"at": 165192, "to": "mm"},
4039   "name": "PA_CL_VPORT_XOFFSET_11"
4040  },
4041  {
4042   "chips": ["gfx11"],
4043   "map": {"at": 165196, "to": "mm"},
4044   "name": "PA_CL_VPORT_YSCALE_11"
4045  },
4046  {
4047   "chips": ["gfx11"],
4048   "map": {"at": 165200, "to": "mm"},
4049   "name": "PA_CL_VPORT_YOFFSET_11"
4050  },
4051  {
4052   "chips": ["gfx11"],
4053   "map": {"at": 165204, "to": "mm"},
4054   "name": "PA_CL_VPORT_ZSCALE_11"
4055  },
4056  {
4057   "chips": ["gfx11"],
4058   "map": {"at": 165208, "to": "mm"},
4059   "name": "PA_CL_VPORT_ZOFFSET_11"
4060  },
4061  {
4062   "chips": ["gfx11"],
4063   "map": {"at": 165212, "to": "mm"},
4064   "name": "PA_CL_VPORT_XSCALE_12"
4065  },
4066  {
4067   "chips": ["gfx11"],
4068   "map": {"at": 165216, "to": "mm"},
4069   "name": "PA_CL_VPORT_XOFFSET_12"
4070  },
4071  {
4072   "chips": ["gfx11"],
4073   "map": {"at": 165220, "to": "mm"},
4074   "name": "PA_CL_VPORT_YSCALE_12"
4075  },
4076  {
4077   "chips": ["gfx11"],
4078   "map": {"at": 165224, "to": "mm"},
4079   "name": "PA_CL_VPORT_YOFFSET_12"
4080  },
4081  {
4082   "chips": ["gfx11"],
4083   "map": {"at": 165228, "to": "mm"},
4084   "name": "PA_CL_VPORT_ZSCALE_12"
4085  },
4086  {
4087   "chips": ["gfx11"],
4088   "map": {"at": 165232, "to": "mm"},
4089   "name": "PA_CL_VPORT_ZOFFSET_12"
4090  },
4091  {
4092   "chips": ["gfx11"],
4093   "map": {"at": 165236, "to": "mm"},
4094   "name": "PA_CL_VPORT_XSCALE_13"
4095  },
4096  {
4097   "chips": ["gfx11"],
4098   "map": {"at": 165240, "to": "mm"},
4099   "name": "PA_CL_VPORT_XOFFSET_13"
4100  },
4101  {
4102   "chips": ["gfx11"],
4103   "map": {"at": 165244, "to": "mm"},
4104   "name": "PA_CL_VPORT_YSCALE_13"
4105  },
4106  {
4107   "chips": ["gfx11"],
4108   "map": {"at": 165248, "to": "mm"},
4109   "name": "PA_CL_VPORT_YOFFSET_13"
4110  },
4111  {
4112   "chips": ["gfx11"],
4113   "map": {"at": 165252, "to": "mm"},
4114   "name": "PA_CL_VPORT_ZSCALE_13"
4115  },
4116  {
4117   "chips": ["gfx11"],
4118   "map": {"at": 165256, "to": "mm"},
4119   "name": "PA_CL_VPORT_ZOFFSET_13"
4120  },
4121  {
4122   "chips": ["gfx11"],
4123   "map": {"at": 165260, "to": "mm"},
4124   "name": "PA_CL_VPORT_XSCALE_14"
4125  },
4126  {
4127   "chips": ["gfx11"],
4128   "map": {"at": 165264, "to": "mm"},
4129   "name": "PA_CL_VPORT_XOFFSET_14"
4130  },
4131  {
4132   "chips": ["gfx11"],
4133   "map": {"at": 165268, "to": "mm"},
4134   "name": "PA_CL_VPORT_YSCALE_14"
4135  },
4136  {
4137   "chips": ["gfx11"],
4138   "map": {"at": 165272, "to": "mm"},
4139   "name": "PA_CL_VPORT_YOFFSET_14"
4140  },
4141  {
4142   "chips": ["gfx11"],
4143   "map": {"at": 165276, "to": "mm"},
4144   "name": "PA_CL_VPORT_ZSCALE_14"
4145  },
4146  {
4147   "chips": ["gfx11"],
4148   "map": {"at": 165280, "to": "mm"},
4149   "name": "PA_CL_VPORT_ZOFFSET_14"
4150  },
4151  {
4152   "chips": ["gfx11"],
4153   "map": {"at": 165284, "to": "mm"},
4154   "name": "PA_CL_VPORT_XSCALE_15"
4155  },
4156  {
4157   "chips": ["gfx11"],
4158   "map": {"at": 165288, "to": "mm"},
4159   "name": "PA_CL_VPORT_XOFFSET_15"
4160  },
4161  {
4162   "chips": ["gfx11"],
4163   "map": {"at": 165292, "to": "mm"},
4164   "name": "PA_CL_VPORT_YSCALE_15"
4165  },
4166  {
4167   "chips": ["gfx11"],
4168   "map": {"at": 165296, "to": "mm"},
4169   "name": "PA_CL_VPORT_YOFFSET_15"
4170  },
4171  {
4172   "chips": ["gfx11"],
4173   "map": {"at": 165300, "to": "mm"},
4174   "name": "PA_CL_VPORT_ZSCALE_15"
4175  },
4176  {
4177   "chips": ["gfx11"],
4178   "map": {"at": 165304, "to": "mm"},
4179   "name": "PA_CL_VPORT_ZOFFSET_15"
4180  },
4181  {
4182   "chips": ["gfx11"],
4183   "map": {"at": 165308, "to": "mm"},
4184   "name": "PA_CL_UCP_0_X"
4185  },
4186  {
4187   "chips": ["gfx11"],
4188   "map": {"at": 165312, "to": "mm"},
4189   "name": "PA_CL_UCP_0_Y"
4190  },
4191  {
4192   "chips": ["gfx11"],
4193   "map": {"at": 165316, "to": "mm"},
4194   "name": "PA_CL_UCP_0_Z"
4195  },
4196  {
4197   "chips": ["gfx11"],
4198   "map": {"at": 165320, "to": "mm"},
4199   "name": "PA_CL_UCP_0_W"
4200  },
4201  {
4202   "chips": ["gfx11"],
4203   "map": {"at": 165324, "to": "mm"},
4204   "name": "PA_CL_UCP_1_X"
4205  },
4206  {
4207   "chips": ["gfx11"],
4208   "map": {"at": 165328, "to": "mm"},
4209   "name": "PA_CL_UCP_1_Y"
4210  },
4211  {
4212   "chips": ["gfx11"],
4213   "map": {"at": 165332, "to": "mm"},
4214   "name": "PA_CL_UCP_1_Z"
4215  },
4216  {
4217   "chips": ["gfx11"],
4218   "map": {"at": 165336, "to": "mm"},
4219   "name": "PA_CL_UCP_1_W"
4220  },
4221  {
4222   "chips": ["gfx11"],
4223   "map": {"at": 165340, "to": "mm"},
4224   "name": "PA_CL_UCP_2_X"
4225  },
4226  {
4227   "chips": ["gfx11"],
4228   "map": {"at": 165344, "to": "mm"},
4229   "name": "PA_CL_UCP_2_Y"
4230  },
4231  {
4232   "chips": ["gfx11"],
4233   "map": {"at": 165348, "to": "mm"},
4234   "name": "PA_CL_UCP_2_Z"
4235  },
4236  {
4237   "chips": ["gfx11"],
4238   "map": {"at": 165352, "to": "mm"},
4239   "name": "PA_CL_UCP_2_W"
4240  },
4241  {
4242   "chips": ["gfx11"],
4243   "map": {"at": 165356, "to": "mm"},
4244   "name": "PA_CL_UCP_3_X"
4245  },
4246  {
4247   "chips": ["gfx11"],
4248   "map": {"at": 165360, "to": "mm"},
4249   "name": "PA_CL_UCP_3_Y"
4250  },
4251  {
4252   "chips": ["gfx11"],
4253   "map": {"at": 165364, "to": "mm"},
4254   "name": "PA_CL_UCP_3_Z"
4255  },
4256  {
4257   "chips": ["gfx11"],
4258   "map": {"at": 165368, "to": "mm"},
4259   "name": "PA_CL_UCP_3_W"
4260  },
4261  {
4262   "chips": ["gfx11"],
4263   "map": {"at": 165372, "to": "mm"},
4264   "name": "PA_CL_UCP_4_X"
4265  },
4266  {
4267   "chips": ["gfx11"],
4268   "map": {"at": 165376, "to": "mm"},
4269   "name": "PA_CL_UCP_4_Y"
4270  },
4271  {
4272   "chips": ["gfx11"],
4273   "map": {"at": 165380, "to": "mm"},
4274   "name": "PA_CL_UCP_4_Z"
4275  },
4276  {
4277   "chips": ["gfx11"],
4278   "map": {"at": 165384, "to": "mm"},
4279   "name": "PA_CL_UCP_4_W"
4280  },
4281  {
4282   "chips": ["gfx11"],
4283   "map": {"at": 165388, "to": "mm"},
4284   "name": "PA_CL_UCP_5_X"
4285  },
4286  {
4287   "chips": ["gfx11"],
4288   "map": {"at": 165392, "to": "mm"},
4289   "name": "PA_CL_UCP_5_Y"
4290  },
4291  {
4292   "chips": ["gfx11"],
4293   "map": {"at": 165396, "to": "mm"},
4294   "name": "PA_CL_UCP_5_Z"
4295  },
4296  {
4297   "chips": ["gfx11"],
4298   "map": {"at": 165400, "to": "mm"},
4299   "name": "PA_CL_UCP_5_W"
4300  },
4301  {
4302   "chips": ["gfx11"],
4303   "map": {"at": 165404, "to": "mm"},
4304   "name": "PA_CL_PROG_NEAR_CLIP_Z"
4305  },
4306  {
4307   "chips": ["gfx11"],
4308   "map": {"at": 165408, "to": "mm"},
4309   "name": "PA_RATE_CNTL",
4310   "type_ref": "PA_RATE_CNTL"
4311  },
4312  {
4313   "chips": ["gfx11"],
4314   "map": {"at": 165444, "to": "mm"},
4315   "name": "SPI_PS_INPUT_CNTL_0",
4316   "type_ref": "SPI_PS_INPUT_CNTL_0"
4317  },
4318  {
4319   "chips": ["gfx11"],
4320   "map": {"at": 165448, "to": "mm"},
4321   "name": "SPI_PS_INPUT_CNTL_1",
4322   "type_ref": "SPI_PS_INPUT_CNTL_0"
4323  },
4324  {
4325   "chips": ["gfx11"],
4326   "map": {"at": 165452, "to": "mm"},
4327   "name": "SPI_PS_INPUT_CNTL_2",
4328   "type_ref": "SPI_PS_INPUT_CNTL_0"
4329  },
4330  {
4331   "chips": ["gfx11"],
4332   "map": {"at": 165456, "to": "mm"},
4333   "name": "SPI_PS_INPUT_CNTL_3",
4334   "type_ref": "SPI_PS_INPUT_CNTL_0"
4335  },
4336  {
4337   "chips": ["gfx11"],
4338   "map": {"at": 165460, "to": "mm"},
4339   "name": "SPI_PS_INPUT_CNTL_4",
4340   "type_ref": "SPI_PS_INPUT_CNTL_0"
4341  },
4342  {
4343   "chips": ["gfx11"],
4344   "map": {"at": 165464, "to": "mm"},
4345   "name": "SPI_PS_INPUT_CNTL_5",
4346   "type_ref": "SPI_PS_INPUT_CNTL_0"
4347  },
4348  {
4349   "chips": ["gfx11"],
4350   "map": {"at": 165468, "to": "mm"},
4351   "name": "SPI_PS_INPUT_CNTL_6",
4352   "type_ref": "SPI_PS_INPUT_CNTL_0"
4353  },
4354  {
4355   "chips": ["gfx11"],
4356   "map": {"at": 165472, "to": "mm"},
4357   "name": "SPI_PS_INPUT_CNTL_7",
4358   "type_ref": "SPI_PS_INPUT_CNTL_0"
4359  },
4360  {
4361   "chips": ["gfx11"],
4362   "map": {"at": 165476, "to": "mm"},
4363   "name": "SPI_PS_INPUT_CNTL_8",
4364   "type_ref": "SPI_PS_INPUT_CNTL_0"
4365  },
4366  {
4367   "chips": ["gfx11"],
4368   "map": {"at": 165480, "to": "mm"},
4369   "name": "SPI_PS_INPUT_CNTL_9",
4370   "type_ref": "SPI_PS_INPUT_CNTL_0"
4371  },
4372  {
4373   "chips": ["gfx11"],
4374   "map": {"at": 165484, "to": "mm"},
4375   "name": "SPI_PS_INPUT_CNTL_10",
4376   "type_ref": "SPI_PS_INPUT_CNTL_0"
4377  },
4378  {
4379   "chips": ["gfx11"],
4380   "map": {"at": 165488, "to": "mm"},
4381   "name": "SPI_PS_INPUT_CNTL_11",
4382   "type_ref": "SPI_PS_INPUT_CNTL_0"
4383  },
4384  {
4385   "chips": ["gfx11"],
4386   "map": {"at": 165492, "to": "mm"},
4387   "name": "SPI_PS_INPUT_CNTL_12",
4388   "type_ref": "SPI_PS_INPUT_CNTL_0"
4389  },
4390  {
4391   "chips": ["gfx11"],
4392   "map": {"at": 165496, "to": "mm"},
4393   "name": "SPI_PS_INPUT_CNTL_13",
4394   "type_ref": "SPI_PS_INPUT_CNTL_0"
4395  },
4396  {
4397   "chips": ["gfx11"],
4398   "map": {"at": 165500, "to": "mm"},
4399   "name": "SPI_PS_INPUT_CNTL_14",
4400   "type_ref": "SPI_PS_INPUT_CNTL_0"
4401  },
4402  {
4403   "chips": ["gfx11"],
4404   "map": {"at": 165504, "to": "mm"},
4405   "name": "SPI_PS_INPUT_CNTL_15",
4406   "type_ref": "SPI_PS_INPUT_CNTL_0"
4407  },
4408  {
4409   "chips": ["gfx11"],
4410   "map": {"at": 165508, "to": "mm"},
4411   "name": "SPI_PS_INPUT_CNTL_16",
4412   "type_ref": "SPI_PS_INPUT_CNTL_0"
4413  },
4414  {
4415   "chips": ["gfx11"],
4416   "map": {"at": 165512, "to": "mm"},
4417   "name": "SPI_PS_INPUT_CNTL_17",
4418   "type_ref": "SPI_PS_INPUT_CNTL_0"
4419  },
4420  {
4421   "chips": ["gfx11"],
4422   "map": {"at": 165516, "to": "mm"},
4423   "name": "SPI_PS_INPUT_CNTL_18",
4424   "type_ref": "SPI_PS_INPUT_CNTL_0"
4425  },
4426  {
4427   "chips": ["gfx11"],
4428   "map": {"at": 165520, "to": "mm"},
4429   "name": "SPI_PS_INPUT_CNTL_19",
4430   "type_ref": "SPI_PS_INPUT_CNTL_0"
4431  },
4432  {
4433   "chips": ["gfx11"],
4434   "map": {"at": 165524, "to": "mm"},
4435   "name": "SPI_PS_INPUT_CNTL_20",
4436   "type_ref": "SPI_PS_INPUT_CNTL_20"
4437  },
4438  {
4439   "chips": ["gfx11"],
4440   "map": {"at": 165528, "to": "mm"},
4441   "name": "SPI_PS_INPUT_CNTL_21",
4442   "type_ref": "SPI_PS_INPUT_CNTL_20"
4443  },
4444  {
4445   "chips": ["gfx11"],
4446   "map": {"at": 165532, "to": "mm"},
4447   "name": "SPI_PS_INPUT_CNTL_22",
4448   "type_ref": "SPI_PS_INPUT_CNTL_20"
4449  },
4450  {
4451   "chips": ["gfx11"],
4452   "map": {"at": 165536, "to": "mm"},
4453   "name": "SPI_PS_INPUT_CNTL_23",
4454   "type_ref": "SPI_PS_INPUT_CNTL_20"
4455  },
4456  {
4457   "chips": ["gfx11"],
4458   "map": {"at": 165540, "to": "mm"},
4459   "name": "SPI_PS_INPUT_CNTL_24",
4460   "type_ref": "SPI_PS_INPUT_CNTL_20"
4461  },
4462  {
4463   "chips": ["gfx11"],
4464   "map": {"at": 165544, "to": "mm"},
4465   "name": "SPI_PS_INPUT_CNTL_25",
4466   "type_ref": "SPI_PS_INPUT_CNTL_20"
4467  },
4468  {
4469   "chips": ["gfx11"],
4470   "map": {"at": 165548, "to": "mm"},
4471   "name": "SPI_PS_INPUT_CNTL_26",
4472   "type_ref": "SPI_PS_INPUT_CNTL_20"
4473  },
4474  {
4475   "chips": ["gfx11"],
4476   "map": {"at": 165552, "to": "mm"},
4477   "name": "SPI_PS_INPUT_CNTL_27",
4478   "type_ref": "SPI_PS_INPUT_CNTL_20"
4479  },
4480  {
4481   "chips": ["gfx11"],
4482   "map": {"at": 165556, "to": "mm"},
4483   "name": "SPI_PS_INPUT_CNTL_28",
4484   "type_ref": "SPI_PS_INPUT_CNTL_20"
4485  },
4486  {
4487   "chips": ["gfx11"],
4488   "map": {"at": 165560, "to": "mm"},
4489   "name": "SPI_PS_INPUT_CNTL_29",
4490   "type_ref": "SPI_PS_INPUT_CNTL_20"
4491  },
4492  {
4493   "chips": ["gfx11"],
4494   "map": {"at": 165564, "to": "mm"},
4495   "name": "SPI_PS_INPUT_CNTL_30",
4496   "type_ref": "SPI_PS_INPUT_CNTL_20"
4497  },
4498  {
4499   "chips": ["gfx11"],
4500   "map": {"at": 165568, "to": "mm"},
4501   "name": "SPI_PS_INPUT_CNTL_31",
4502   "type_ref": "SPI_PS_INPUT_CNTL_20"
4503  },
4504  {
4505   "chips": ["gfx11"],
4506   "map": {"at": 165572, "to": "mm"},
4507   "name": "SPI_VS_OUT_CONFIG",
4508   "type_ref": "SPI_VS_OUT_CONFIG"
4509  },
4510  {
4511   "chips": ["gfx11"],
4512   "map": {"at": 165580, "to": "mm"},
4513   "name": "SPI_PS_INPUT_ENA",
4514   "type_ref": "SPI_PS_INPUT_ENA"
4515  },
4516  {
4517   "chips": ["gfx11"],
4518   "map": {"at": 165584, "to": "mm"},
4519   "name": "SPI_PS_INPUT_ADDR",
4520   "type_ref": "SPI_PS_INPUT_ENA"
4521  },
4522  {
4523   "chips": ["gfx11"],
4524   "map": {"at": 165588, "to": "mm"},
4525   "name": "SPI_INTERP_CONTROL_0",
4526   "type_ref": "SPI_INTERP_CONTROL_0"
4527  },
4528  {
4529   "chips": ["gfx11"],
4530   "map": {"at": 165592, "to": "mm"},
4531   "name": "SPI_PS_IN_CONTROL",
4532   "type_ref": "SPI_PS_IN_CONTROL"
4533  },
4534  {
4535   "chips": ["gfx11"],
4536   "map": {"at": 165600, "to": "mm"},
4537   "name": "SPI_BARYC_CNTL",
4538   "type_ref": "SPI_BARYC_CNTL"
4539  },
4540  {
4541   "chips": ["gfx11"],
4542   "map": {"at": 165608, "to": "mm"},
4543   "name": "SPI_TMPRING_SIZE",
4544   "type_ref": "COMPUTE_TMPRING_SIZE"
4545  },
4546  {
4547   "chips": ["gfx11"],
4548   "map": {"at": 165612, "to": "mm"},
4549   "name": "SPI_GFX_SCRATCH_BASE_LO"
4550  },
4551  {
4552   "chips": ["gfx11"],
4553   "map": {"at": 165616, "to": "mm"},
4554   "name": "SPI_GFX_SCRATCH_BASE_HI",
4555   "type_ref": "COMPUTE_PGM_HI"
4556  },
4557  {
4558   "chips": ["gfx11"],
4559   "map": {"at": 165640, "to": "mm"},
4560   "name": "SPI_SHADER_IDX_FORMAT",
4561   "type_ref": "SPI_SHADER_IDX_FORMAT"
4562  },
4563  {
4564   "chips": ["gfx11"],
4565   "map": {"at": 165644, "to": "mm"},
4566   "name": "SPI_SHADER_POS_FORMAT",
4567   "type_ref": "SPI_SHADER_POS_FORMAT"
4568  },
4569  {
4570   "chips": ["gfx11"],
4571   "map": {"at": 165648, "to": "mm"},
4572   "name": "SPI_SHADER_Z_FORMAT",
4573   "type_ref": "SPI_SHADER_Z_FORMAT"
4574  },
4575  {
4576   "chips": ["gfx11"],
4577   "map": {"at": 165652, "to": "mm"},
4578   "name": "SPI_SHADER_COL_FORMAT",
4579   "type_ref": "SPI_SHADER_COL_FORMAT"
4580  },
4581  {
4582   "chips": ["gfx11"],
4583   "map": {"at": 165712, "to": "mm"},
4584   "name": "SX_PS_DOWNCONVERT_CONTROL",
4585   "type_ref": "SX_PS_DOWNCONVERT_CONTROL"
4586  },
4587  {
4588   "chips": ["gfx11"],
4589   "map": {"at": 165716, "to": "mm"},
4590   "name": "SX_PS_DOWNCONVERT",
4591   "type_ref": "SX_PS_DOWNCONVERT"
4592  },
4593  {
4594   "chips": ["gfx11"],
4595   "map": {"at": 165720, "to": "mm"},
4596   "name": "SX_BLEND_OPT_EPSILON",
4597   "type_ref": "SX_BLEND_OPT_EPSILON"
4598  },
4599  {
4600   "chips": ["gfx11"],
4601   "map": {"at": 165724, "to": "mm"},
4602   "name": "SX_BLEND_OPT_CONTROL",
4603   "type_ref": "SX_BLEND_OPT_CONTROL"
4604  },
4605  {
4606   "chips": ["gfx11"],
4607   "map": {"at": 165728, "to": "mm"},
4608   "name": "SX_MRT0_BLEND_OPT",
4609   "type_ref": "SX_MRT0_BLEND_OPT"
4610  },
4611  {
4612   "chips": ["gfx11"],
4613   "map": {"at": 165732, "to": "mm"},
4614   "name": "SX_MRT1_BLEND_OPT",
4615   "type_ref": "SX_MRT0_BLEND_OPT"
4616  },
4617  {
4618   "chips": ["gfx11"],
4619   "map": {"at": 165736, "to": "mm"},
4620   "name": "SX_MRT2_BLEND_OPT",
4621   "type_ref": "SX_MRT0_BLEND_OPT"
4622  },
4623  {
4624   "chips": ["gfx11"],
4625   "map": {"at": 165740, "to": "mm"},
4626   "name": "SX_MRT3_BLEND_OPT",
4627   "type_ref": "SX_MRT0_BLEND_OPT"
4628  },
4629  {
4630   "chips": ["gfx11"],
4631   "map": {"at": 165744, "to": "mm"},
4632   "name": "SX_MRT4_BLEND_OPT",
4633   "type_ref": "SX_MRT0_BLEND_OPT"
4634  },
4635  {
4636   "chips": ["gfx11"],
4637   "map": {"at": 165748, "to": "mm"},
4638   "name": "SX_MRT5_BLEND_OPT",
4639   "type_ref": "SX_MRT0_BLEND_OPT"
4640  },
4641  {
4642   "chips": ["gfx11"],
4643   "map": {"at": 165752, "to": "mm"},
4644   "name": "SX_MRT6_BLEND_OPT",
4645   "type_ref": "SX_MRT0_BLEND_OPT"
4646  },
4647  {
4648   "chips": ["gfx11"],
4649   "map": {"at": 165756, "to": "mm"},
4650   "name": "SX_MRT7_BLEND_OPT",
4651   "type_ref": "SX_MRT0_BLEND_OPT"
4652  },
4653  {
4654   "chips": ["gfx11"],
4655   "map": {"at": 165760, "to": "mm"},
4656   "name": "CB_BLEND0_CONTROL",
4657   "type_ref": "CB_BLEND0_CONTROL"
4658  },
4659  {
4660   "chips": ["gfx11"],
4661   "map": {"at": 165764, "to": "mm"},
4662   "name": "CB_BLEND1_CONTROL",
4663   "type_ref": "CB_BLEND0_CONTROL"
4664  },
4665  {
4666   "chips": ["gfx11"],
4667   "map": {"at": 165768, "to": "mm"},
4668   "name": "CB_BLEND2_CONTROL",
4669   "type_ref": "CB_BLEND0_CONTROL"
4670  },
4671  {
4672   "chips": ["gfx11"],
4673   "map": {"at": 165772, "to": "mm"},
4674   "name": "CB_BLEND3_CONTROL",
4675   "type_ref": "CB_BLEND0_CONTROL"
4676  },
4677  {
4678   "chips": ["gfx11"],
4679   "map": {"at": 165776, "to": "mm"},
4680   "name": "CB_BLEND4_CONTROL",
4681   "type_ref": "CB_BLEND0_CONTROL"
4682  },
4683  {
4684   "chips": ["gfx11"],
4685   "map": {"at": 165780, "to": "mm"},
4686   "name": "CB_BLEND5_CONTROL",
4687   "type_ref": "CB_BLEND0_CONTROL"
4688  },
4689  {
4690   "chips": ["gfx11"],
4691   "map": {"at": 165784, "to": "mm"},
4692   "name": "CB_BLEND6_CONTROL",
4693   "type_ref": "CB_BLEND0_CONTROL"
4694  },
4695  {
4696   "chips": ["gfx11"],
4697   "map": {"at": 165788, "to": "mm"},
4698   "name": "CB_BLEND7_CONTROL",
4699   "type_ref": "CB_BLEND0_CONTROL"
4700  },
4701  {
4702   "chips": ["gfx11"],
4703   "map": {"at": 165840, "to": "mm"},
4704   "name": "GFX_COPY_STATE",
4705   "type_ref": "GFX_COPY_STATE"
4706  },
4707  {
4708   "chips": ["gfx11"],
4709   "map": {"at": 165844, "to": "mm"},
4710   "name": "PA_CL_POINT_X_RAD"
4711  },
4712  {
4713   "chips": ["gfx11"],
4714   "map": {"at": 165848, "to": "mm"},
4715   "name": "PA_CL_POINT_Y_RAD"
4716  },
4717  {
4718   "chips": ["gfx11"],
4719   "map": {"at": 165852, "to": "mm"},
4720   "name": "PA_CL_POINT_SIZE"
4721  },
4722  {
4723   "chips": ["gfx11"],
4724   "map": {"at": 165856, "to": "mm"},
4725   "name": "PA_CL_POINT_CULL_RAD"
4726  },
4727  {
4728   "chips": ["gfx11"],
4729   "map": {"at": 165860, "to": "mm"},
4730   "name": "VGT_DMA_BASE_HI",
4731   "type_ref": "VGT_DMA_BASE_HI"
4732  },
4733  {
4734   "chips": ["gfx11"],
4735   "map": {"at": 165864, "to": "mm"},
4736   "name": "VGT_DMA_BASE"
4737  },
4738  {
4739   "chips": ["gfx11"],
4740   "map": {"at": 165872, "to": "mm"},
4741   "name": "VGT_DRAW_INITIATOR",
4742   "type_ref": "VGT_DRAW_INITIATOR"
4743  },
4744  {
4745   "chips": ["gfx11"],
4746   "map": {"at": 165880, "to": "mm"},
4747   "name": "VGT_EVENT_ADDRESS_REG",
4748   "type_ref": "VGT_EVENT_ADDRESS_REG"
4749  },
4750  {
4751   "chips": ["gfx11"],
4752   "map": {"at": 165884, "to": "mm"},
4753   "name": "GE_MAX_OUTPUT_PER_SUBGROUP",
4754   "type_ref": "GE_MAX_OUTPUT_PER_SUBGROUP"
4755  },
4756  {
4757   "chips": ["gfx11"],
4758   "map": {"at": 165888, "to": "mm"},
4759   "name": "DB_DEPTH_CONTROL",
4760   "type_ref": "DB_DEPTH_CONTROL"
4761  },
4762  {
4763   "chips": ["gfx11"],
4764   "map": {"at": 165892, "to": "mm"},
4765   "name": "DB_EQAA",
4766   "type_ref": "DB_EQAA"
4767  },
4768  {
4769   "chips": ["gfx11"],
4770   "map": {"at": 165896, "to": "mm"},
4771   "name": "CB_COLOR_CONTROL",
4772   "type_ref": "CB_COLOR_CONTROL"
4773  },
4774  {
4775   "chips": ["gfx11"],
4776   "map": {"at": 165900, "to": "mm"},
4777   "name": "DB_SHADER_CONTROL",
4778   "type_ref": "DB_SHADER_CONTROL"
4779  },
4780  {
4781   "chips": ["gfx11"],
4782   "map": {"at": 165904, "to": "mm"},
4783   "name": "PA_CL_CLIP_CNTL",
4784   "type_ref": "PA_CL_CLIP_CNTL"
4785  },
4786  {
4787   "chips": ["gfx11"],
4788   "map": {"at": 165908, "to": "mm"},
4789   "name": "PA_SU_SC_MODE_CNTL",
4790   "type_ref": "PA_SU_SC_MODE_CNTL"
4791  },
4792  {
4793   "chips": ["gfx11"],
4794   "map": {"at": 165912, "to": "mm"},
4795   "name": "PA_CL_VTE_CNTL",
4796   "type_ref": "PA_CL_VTE_CNTL"
4797  },
4798  {
4799   "chips": ["gfx11"],
4800   "map": {"at": 165916, "to": "mm"},
4801   "name": "PA_CL_VS_OUT_CNTL",
4802   "type_ref": "PA_CL_VS_OUT_CNTL"
4803  },
4804  {
4805   "chips": ["gfx11"],
4806   "map": {"at": 165920, "to": "mm"},
4807   "name": "PA_CL_NANINF_CNTL",
4808   "type_ref": "PA_CL_NANINF_CNTL"
4809  },
4810  {
4811   "chips": ["gfx11"],
4812   "map": {"at": 165924, "to": "mm"},
4813   "name": "PA_SU_LINE_STIPPLE_CNTL",
4814   "type_ref": "PA_SU_LINE_STIPPLE_CNTL"
4815  },
4816  {
4817   "chips": ["gfx11"],
4818   "map": {"at": 165928, "to": "mm"},
4819   "name": "PA_SU_LINE_STIPPLE_SCALE"
4820  },
4821  {
4822   "chips": ["gfx11"],
4823   "map": {"at": 165932, "to": "mm"},
4824   "name": "PA_SU_PRIM_FILTER_CNTL",
4825   "type_ref": "PA_SU_PRIM_FILTER_CNTL"
4826  },
4827  {
4828   "chips": ["gfx11"],
4829   "map": {"at": 165936, "to": "mm"},
4830   "name": "PA_SU_SMALL_PRIM_FILTER_CNTL",
4831   "type_ref": "PA_SU_SMALL_PRIM_FILTER_CNTL"
4832  },
4833  {
4834   "chips": ["gfx11"],
4835   "map": {"at": 165944, "to": "mm"},
4836   "name": "PA_CL_NGG_CNTL",
4837   "type_ref": "PA_CL_NGG_CNTL"
4838  },
4839  {
4840   "chips": ["gfx11"],
4841   "map": {"at": 165948, "to": "mm"},
4842   "name": "PA_SU_OVER_RASTERIZATION_CNTL",
4843   "type_ref": "PA_SU_OVER_RASTERIZATION_CNTL"
4844  },
4845  {
4846   "chips": ["gfx11"],
4847   "map": {"at": 165952, "to": "mm"},
4848   "name": "PA_STEREO_CNTL",
4849   "type_ref": "PA_STEREO_CNTL"
4850  },
4851  {
4852   "chips": ["gfx11"],
4853   "map": {"at": 165956, "to": "mm"},
4854   "name": "PA_STATE_STEREO_X"
4855  },
4856  {
4857   "chips": ["gfx11"],
4858   "map": {"at": 165960, "to": "mm"},
4859   "name": "PA_CL_VRS_CNTL",
4860   "type_ref": "PA_CL_VRS_CNTL"
4861  },
4862  {
4863   "chips": ["gfx11"],
4864   "map": {"at": 166400, "to": "mm"},
4865   "name": "PA_SU_POINT_SIZE",
4866   "type_ref": "PA_SU_POINT_SIZE"
4867  },
4868  {
4869   "chips": ["gfx11"],
4870   "map": {"at": 166404, "to": "mm"},
4871   "name": "PA_SU_POINT_MINMAX",
4872   "type_ref": "PA_SU_POINT_MINMAX"
4873  },
4874  {
4875   "chips": ["gfx11"],
4876   "map": {"at": 166408, "to": "mm"},
4877   "name": "PA_SU_LINE_CNTL",
4878   "type_ref": "PA_SU_LINE_CNTL"
4879  },
4880  {
4881   "chips": ["gfx11"],
4882   "map": {"at": 166412, "to": "mm"},
4883   "name": "PA_SC_LINE_STIPPLE",
4884   "type_ref": "PA_SC_LINE_STIPPLE"
4885  },
4886  {
4887   "chips": ["gfx11"],
4888   "map": {"at": 166424, "to": "mm"},
4889   "name": "VGT_HOS_MAX_TESS_LEVEL"
4890  },
4891  {
4892   "chips": ["gfx11"],
4893   "map": {"at": 166428, "to": "mm"},
4894   "name": "VGT_HOS_MIN_TESS_LEVEL"
4895  },
4896  {
4897   "chips": ["gfx11"],
4898   "map": {"at": 166472, "to": "mm"},
4899   "name": "PA_SC_MODE_CNTL_0",
4900   "type_ref": "PA_SC_MODE_CNTL_0"
4901  },
4902  {
4903   "chips": ["gfx11"],
4904   "map": {"at": 166476, "to": "mm"},
4905   "name": "PA_SC_MODE_CNTL_1",
4906   "type_ref": "PA_SC_MODE_CNTL_1"
4907  },
4908  {
4909   "chips": ["gfx11"],
4910   "map": {"at": 166480, "to": "mm"},
4911   "name": "VGT_ENHANCE"
4912  },
4913  {
4914   "chips": ["gfx11"],
4915   "map": {"at": 166512, "to": "mm"},
4916   "name": "IA_ENHANCE"
4917  },
4918  {
4919   "chips": ["gfx11"],
4920   "map": {"at": 166516, "to": "mm"},
4921   "name": "VGT_DMA_SIZE"
4922  },
4923  {
4924   "chips": ["gfx11"],
4925   "map": {"at": 166520, "to": "mm"},
4926   "name": "VGT_DMA_MAX_SIZE"
4927  },
4928  {
4929   "chips": ["gfx11"],
4930   "map": {"at": 166524, "to": "mm"},
4931   "name": "VGT_DMA_INDEX_TYPE",
4932   "type_ref": "VGT_DMA_INDEX_TYPE"
4933  },
4934  {
4935   "chips": ["gfx11"],
4936   "map": {"at": 166528, "to": "mm"},
4937   "name": "WD_ENHANCE"
4938  },
4939  {
4940   "chips": ["gfx11"],
4941   "map": {"at": 166532, "to": "mm"},
4942   "name": "VGT_PRIMITIVEID_EN",
4943   "type_ref": "VGT_PRIMITIVEID_EN"
4944  },
4945  {
4946   "chips": ["gfx11"],
4947   "map": {"at": 166536, "to": "mm"},
4948   "name": "VGT_DMA_NUM_INSTANCES"
4949  },
4950  {
4951   "chips": ["gfx11"],
4952   "map": {"at": 166540, "to": "mm"},
4953   "name": "VGT_PRIMITIVEID_RESET"
4954  },
4955  {
4956   "chips": ["gfx11"],
4957   "map": {"at": 166544, "to": "mm"},
4958   "name": "VGT_EVENT_INITIATOR",
4959   "type_ref": "VGT_EVENT_INITIATOR"
4960  },
4961  {
4962   "chips": ["gfx11"],
4963   "map": {"at": 166552, "to": "mm"},
4964   "name": "VGT_DRAW_PAYLOAD_CNTL",
4965   "type_ref": "VGT_DRAW_PAYLOAD_CNTL"
4966  },
4967  {
4968   "chips": ["gfx11"],
4969   "map": {"at": 166572, "to": "mm"},
4970   "name": "VGT_ESGS_RING_ITEMSIZE",
4971   "type_ref": "VGT_ESGS_RING_ITEMSIZE"
4972  },
4973  {
4974   "chips": ["gfx11"],
4975   "map": {"at": 166580, "to": "mm"},
4976   "name": "VGT_REUSE_OFF",
4977   "type_ref": "VGT_REUSE_OFF"
4978  },
4979  {
4980   "chips": ["gfx11"],
4981   "map": {"at": 166588, "to": "mm"},
4982   "name": "DB_HTILE_SURFACE",
4983   "type_ref": "DB_HTILE_SURFACE"
4984  },
4985  {
4986   "chips": ["gfx11"],
4987   "map": {"at": 166592, "to": "mm"},
4988   "name": "DB_SRESULTS_COMPARE_STATE0",
4989   "type_ref": "DB_SRESULTS_COMPARE_STATE0"
4990  },
4991  {
4992   "chips": ["gfx11"],
4993   "map": {"at": 166596, "to": "mm"},
4994   "name": "DB_SRESULTS_COMPARE_STATE1",
4995   "type_ref": "DB_SRESULTS_COMPARE_STATE1"
4996  },
4997  {
4998   "chips": ["gfx11"],
4999   "map": {"at": 166600, "to": "mm"},
5000   "name": "DB_PRELOAD_CONTROL",
5001   "type_ref": "DB_PRELOAD_CONTROL"
5002  },
5003  {
5004   "chips": ["gfx11"],
5005   "map": {"at": 166696, "to": "mm"},
5006   "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET"
5007  },
5008  {
5009   "chips": ["gfx11"],
5010   "map": {"at": 166700, "to": "mm"},
5011   "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE"
5012  },
5013  {
5014   "chips": ["gfx11"],
5015   "map": {"at": 166704, "to": "mm"},
5016   "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE",
5017   "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE"
5018  },
5019  {
5020   "chips": ["gfx11"],
5021   "map": {"at": 166712, "to": "mm"},
5022   "name": "VGT_GS_MAX_VERT_OUT",
5023   "type_ref": "VGT_GS_MAX_VERT_OUT"
5024  },
5025  {
5026   "chips": ["gfx11"],
5027   "map": {"at": 166732, "to": "mm"},
5028   "name": "GE_NGG_SUBGRP_CNTL",
5029   "type_ref": "GE_NGG_SUBGRP_CNTL"
5030  },
5031  {
5032   "chips": ["gfx11"],
5033   "map": {"at": 166736, "to": "mm"},
5034   "name": "VGT_TESS_DISTRIBUTION",
5035   "type_ref": "VGT_TESS_DISTRIBUTION"
5036  },
5037  {
5038   "chips": ["gfx11"],
5039   "map": {"at": 166740, "to": "mm"},
5040   "name": "VGT_SHADER_STAGES_EN",
5041   "type_ref": "VGT_SHADER_STAGES_EN"
5042  },
5043  {
5044   "chips": ["gfx11"],
5045   "map": {"at": 166744, "to": "mm"},
5046   "name": "VGT_LS_HS_CONFIG",
5047   "type_ref": "VGT_LS_HS_CONFIG"
5048  },
5049  {
5050   "chips": ["gfx11"],
5051   "map": {"at": 166764, "to": "mm"},
5052   "name": "VGT_TF_PARAM",
5053   "type_ref": "VGT_TF_PARAM"
5054  },
5055  {
5056   "chips": ["gfx11"],
5057   "map": {"at": 166768, "to": "mm"},
5058   "name": "DB_ALPHA_TO_MASK",
5059   "type_ref": "DB_ALPHA_TO_MASK"
5060  },
5061  {
5062   "chips": ["gfx11"],
5063   "map": {"at": 166776, "to": "mm"},
5064   "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL",
5065   "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL"
5066  },
5067  {
5068   "chips": ["gfx11"],
5069   "map": {"at": 166780, "to": "mm"},
5070   "name": "PA_SU_POLY_OFFSET_CLAMP"
5071  },
5072  {
5073   "chips": ["gfx11"],
5074   "map": {"at": 166784, "to": "mm"},
5075   "name": "PA_SU_POLY_OFFSET_FRONT_SCALE"
5076  },
5077  {
5078   "chips": ["gfx11"],
5079   "map": {"at": 166788, "to": "mm"},
5080   "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET"
5081  },
5082  {
5083   "chips": ["gfx11"],
5084   "map": {"at": 166792, "to": "mm"},
5085   "name": "PA_SU_POLY_OFFSET_BACK_SCALE"
5086  },
5087  {
5088   "chips": ["gfx11"],
5089   "map": {"at": 166796, "to": "mm"},
5090   "name": "PA_SU_POLY_OFFSET_BACK_OFFSET"
5091  },
5092  {
5093   "chips": ["gfx11"],
5094   "map": {"at": 166800, "to": "mm"},
5095   "name": "VGT_GS_INSTANCE_CNT",
5096   "type_ref": "VGT_GS_INSTANCE_CNT"
5097  },
5098  {
5099   "chips": ["gfx11"],
5100   "map": {"at": 166868, "to": "mm"},
5101   "name": "PA_SC_CENTROID_PRIORITY_0",
5102   "type_ref": "PA_SC_CENTROID_PRIORITY_0"
5103  },
5104  {
5105   "chips": ["gfx11"],
5106   "map": {"at": 166872, "to": "mm"},
5107   "name": "PA_SC_CENTROID_PRIORITY_1",
5108   "type_ref": "PA_SC_CENTROID_PRIORITY_1"
5109  },
5110  {
5111   "chips": ["gfx11"],
5112   "map": {"at": 166876, "to": "mm"},
5113   "name": "PA_SC_LINE_CNTL",
5114   "type_ref": "PA_SC_LINE_CNTL"
5115  },
5116  {
5117   "chips": ["gfx11"],
5118   "map": {"at": 166880, "to": "mm"},
5119   "name": "PA_SC_AA_CONFIG",
5120   "type_ref": "PA_SC_AA_CONFIG"
5121  },
5122  {
5123   "chips": ["gfx11"],
5124   "map": {"at": 166884, "to": "mm"},
5125   "name": "PA_SU_VTX_CNTL",
5126   "type_ref": "PA_SU_VTX_CNTL"
5127  },
5128  {
5129   "chips": ["gfx11"],
5130   "map": {"at": 166888, "to": "mm"},
5131   "name": "PA_CL_GB_VERT_CLIP_ADJ"
5132  },
5133  {
5134   "chips": ["gfx11"],
5135   "map": {"at": 166892, "to": "mm"},
5136   "name": "PA_CL_GB_VERT_DISC_ADJ"
5137  },
5138  {
5139   "chips": ["gfx11"],
5140   "map": {"at": 166896, "to": "mm"},
5141   "name": "PA_CL_GB_HORZ_CLIP_ADJ"
5142  },
5143  {
5144   "chips": ["gfx11"],
5145   "map": {"at": 166900, "to": "mm"},
5146   "name": "PA_CL_GB_HORZ_DISC_ADJ"
5147  },
5148  {
5149   "chips": ["gfx11"],
5150   "map": {"at": 166904, "to": "mm"},
5151   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0",
5152   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5153  },
5154  {
5155   "chips": ["gfx11"],
5156   "map": {"at": 166908, "to": "mm"},
5157   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1",
5158   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5159  },
5160  {
5161   "chips": ["gfx11"],
5162   "map": {"at": 166912, "to": "mm"},
5163   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2",
5164   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5165  },
5166  {
5167   "chips": ["gfx11"],
5168   "map": {"at": 166916, "to": "mm"},
5169   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3",
5170   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5171  },
5172  {
5173   "chips": ["gfx11"],
5174   "map": {"at": 166920, "to": "mm"},
5175   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0",
5176   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5177  },
5178  {
5179   "chips": ["gfx11"],
5180   "map": {"at": 166924, "to": "mm"},
5181   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1",
5182   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5183  },
5184  {
5185   "chips": ["gfx11"],
5186   "map": {"at": 166928, "to": "mm"},
5187   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2",
5188   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5189  },
5190  {
5191   "chips": ["gfx11"],
5192   "map": {"at": 166932, "to": "mm"},
5193   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3",
5194   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5195  },
5196  {
5197   "chips": ["gfx11"],
5198   "map": {"at": 166936, "to": "mm"},
5199   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0",
5200   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5201  },
5202  {
5203   "chips": ["gfx11"],
5204   "map": {"at": 166940, "to": "mm"},
5205   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1",
5206   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5207  },
5208  {
5209   "chips": ["gfx11"],
5210   "map": {"at": 166944, "to": "mm"},
5211   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2",
5212   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5213  },
5214  {
5215   "chips": ["gfx11"],
5216   "map": {"at": 166948, "to": "mm"},
5217   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3",
5218   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5219  },
5220  {
5221   "chips": ["gfx11"],
5222   "map": {"at": 166952, "to": "mm"},
5223   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0",
5224   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
5225  },
5226  {
5227   "chips": ["gfx11"],
5228   "map": {"at": 166956, "to": "mm"},
5229   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1",
5230   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1"
5231  },
5232  {
5233   "chips": ["gfx11"],
5234   "map": {"at": 166960, "to": "mm"},
5235   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2",
5236   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2"
5237  },
5238  {
5239   "chips": ["gfx11"],
5240   "map": {"at": 166964, "to": "mm"},
5241   "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3",
5242   "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3"
5243  },
5244  {
5245   "chips": ["gfx11"],
5246   "map": {"at": 166968, "to": "mm"},
5247   "name": "PA_SC_AA_MASK_X0Y0_X1Y0",
5248   "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0"
5249  },
5250  {
5251   "chips": ["gfx11"],
5252   "map": {"at": 166972, "to": "mm"},
5253   "name": "PA_SC_AA_MASK_X0Y1_X1Y1",
5254   "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1"
5255  },
5256  {
5257   "chips": ["gfx11"],
5258   "map": {"at": 166976, "to": "mm"},
5259   "name": "PA_SC_SHADER_CONTROL",
5260   "type_ref": "PA_SC_SHADER_CONTROL"
5261  },
5262  {
5263   "chips": ["gfx11"],
5264   "map": {"at": 166980, "to": "mm"},
5265   "name": "PA_SC_BINNER_CNTL_0",
5266   "type_ref": "PA_SC_BINNER_CNTL_0"
5267  },
5268  {
5269   "chips": ["gfx11"],
5270   "map": {"at": 166984, "to": "mm"},
5271   "name": "PA_SC_BINNER_CNTL_1",
5272   "type_ref": "PA_SC_BINNER_CNTL_1"
5273  },
5274  {
5275   "chips": ["gfx11"],
5276   "map": {"at": 166988, "to": "mm"},
5277   "name": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL",
5278   "type_ref": "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
5279  },
5280  {
5281   "chips": ["gfx11"],
5282   "map": {"at": 166992, "to": "mm"},
5283   "name": "PA_SC_NGG_MODE_CNTL",
5284   "type_ref": "PA_SC_NGG_MODE_CNTL"
5285  },
5286  {
5287   "chips": ["gfx11"],
5288   "map": {"at": 166996, "to": "mm"},
5289   "name": "PA_SC_BINNER_CNTL_2",
5290   "type_ref": "PA_SC_BINNER_CNTL_2"
5291  },
5292  {
5293   "chips": ["gfx11"],
5294   "map": {"at": 167008, "to": "mm"},
5295   "name": "CB_COLOR0_BASE"
5296  },
5297  {
5298   "chips": ["gfx11"],
5299   "map": {"at": 167020, "to": "mm"},
5300   "name": "CB_COLOR0_VIEW",
5301   "type_ref": "CB_COLOR0_VIEW"
5302  },
5303  {
5304   "chips": ["gfx11"],
5305   "map": {"at": 167024, "to": "mm"},
5306   "name": "CB_COLOR0_INFO",
5307   "type_ref": "CB_COLOR0_INFO"
5308  },
5309  {
5310   "chips": ["gfx11"],
5311   "map": {"at": 167028, "to": "mm"},
5312   "name": "CB_COLOR0_ATTRIB",
5313   "type_ref": "CB_COLOR0_ATTRIB"
5314  },
5315  {
5316   "chips": ["gfx11"],
5317   "map": {"at": 167032, "to": "mm"},
5318   "name": "CB_COLOR0_FDCC_CONTROL",
5319   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5320  },
5321  {
5322   "chips": ["gfx11"],
5323   "map": {"at": 167060, "to": "mm"},
5324   "name": "CB_COLOR0_DCC_BASE"
5325  },
5326  {
5327   "chips": ["gfx11"],
5328   "map": {"at": 167068, "to": "mm"},
5329   "name": "CB_COLOR1_BASE"
5330  },
5331  {
5332   "chips": ["gfx11"],
5333   "map": {"at": 167080, "to": "mm"},
5334   "name": "CB_COLOR1_VIEW",
5335   "type_ref": "CB_COLOR0_VIEW"
5336  },
5337  {
5338   "chips": ["gfx11"],
5339   "map": {"at": 167084, "to": "mm"},
5340   "name": "CB_COLOR1_INFO",
5341   "type_ref": "CB_COLOR0_INFO"
5342  },
5343  {
5344   "chips": ["gfx11"],
5345   "map": {"at": 167088, "to": "mm"},
5346   "name": "CB_COLOR1_ATTRIB",
5347   "type_ref": "CB_COLOR0_ATTRIB"
5348  },
5349  {
5350   "chips": ["gfx11"],
5351   "map": {"at": 167092, "to": "mm"},
5352   "name": "CB_COLOR1_FDCC_CONTROL",
5353   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5354  },
5355  {
5356   "chips": ["gfx11"],
5357   "map": {"at": 167120, "to": "mm"},
5358   "name": "CB_COLOR1_DCC_BASE"
5359  },
5360  {
5361   "chips": ["gfx11"],
5362   "map": {"at": 167128, "to": "mm"},
5363   "name": "CB_COLOR2_BASE"
5364  },
5365  {
5366   "chips": ["gfx11"],
5367   "map": {"at": 167140, "to": "mm"},
5368   "name": "CB_COLOR2_VIEW",
5369   "type_ref": "CB_COLOR0_VIEW"
5370  },
5371  {
5372   "chips": ["gfx11"],
5373   "map": {"at": 167144, "to": "mm"},
5374   "name": "CB_COLOR2_INFO",
5375   "type_ref": "CB_COLOR0_INFO"
5376  },
5377  {
5378   "chips": ["gfx11"],
5379   "map": {"at": 167148, "to": "mm"},
5380   "name": "CB_COLOR2_ATTRIB",
5381   "type_ref": "CB_COLOR0_ATTRIB"
5382  },
5383  {
5384   "chips": ["gfx11"],
5385   "map": {"at": 167152, "to": "mm"},
5386   "name": "CB_COLOR2_FDCC_CONTROL",
5387   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5388  },
5389  {
5390   "chips": ["gfx11"],
5391   "map": {"at": 167180, "to": "mm"},
5392   "name": "CB_COLOR2_DCC_BASE"
5393  },
5394  {
5395   "chips": ["gfx11"],
5396   "map": {"at": 167188, "to": "mm"},
5397   "name": "CB_COLOR3_BASE"
5398  },
5399  {
5400   "chips": ["gfx11"],
5401   "map": {"at": 167200, "to": "mm"},
5402   "name": "CB_COLOR3_VIEW",
5403   "type_ref": "CB_COLOR0_VIEW"
5404  },
5405  {
5406   "chips": ["gfx11"],
5407   "map": {"at": 167204, "to": "mm"},
5408   "name": "CB_COLOR3_INFO",
5409   "type_ref": "CB_COLOR0_INFO"
5410  },
5411  {
5412   "chips": ["gfx11"],
5413   "map": {"at": 167208, "to": "mm"},
5414   "name": "CB_COLOR3_ATTRIB",
5415   "type_ref": "CB_COLOR0_ATTRIB"
5416  },
5417  {
5418   "chips": ["gfx11"],
5419   "map": {"at": 167212, "to": "mm"},
5420   "name": "CB_COLOR3_FDCC_CONTROL",
5421   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5422  },
5423  {
5424   "chips": ["gfx11"],
5425   "map": {"at": 167240, "to": "mm"},
5426   "name": "CB_COLOR3_DCC_BASE"
5427  },
5428  {
5429   "chips": ["gfx11"],
5430   "map": {"at": 167248, "to": "mm"},
5431   "name": "CB_COLOR4_BASE"
5432  },
5433  {
5434   "chips": ["gfx11"],
5435   "map": {"at": 167260, "to": "mm"},
5436   "name": "CB_COLOR4_VIEW",
5437   "type_ref": "CB_COLOR0_VIEW"
5438  },
5439  {
5440   "chips": ["gfx11"],
5441   "map": {"at": 167264, "to": "mm"},
5442   "name": "CB_COLOR4_INFO",
5443   "type_ref": "CB_COLOR0_INFO"
5444  },
5445  {
5446   "chips": ["gfx11"],
5447   "map": {"at": 167268, "to": "mm"},
5448   "name": "CB_COLOR4_ATTRIB",
5449   "type_ref": "CB_COLOR0_ATTRIB"
5450  },
5451  {
5452   "chips": ["gfx11"],
5453   "map": {"at": 167272, "to": "mm"},
5454   "name": "CB_COLOR4_FDCC_CONTROL",
5455   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5456  },
5457  {
5458   "chips": ["gfx11"],
5459   "map": {"at": 167300, "to": "mm"},
5460   "name": "CB_COLOR4_DCC_BASE"
5461  },
5462  {
5463   "chips": ["gfx11"],
5464   "map": {"at": 167308, "to": "mm"},
5465   "name": "CB_COLOR5_BASE"
5466  },
5467  {
5468   "chips": ["gfx11"],
5469   "map": {"at": 167320, "to": "mm"},
5470   "name": "CB_COLOR5_VIEW",
5471   "type_ref": "CB_COLOR0_VIEW"
5472  },
5473  {
5474   "chips": ["gfx11"],
5475   "map": {"at": 167324, "to": "mm"},
5476   "name": "CB_COLOR5_INFO",
5477   "type_ref": "CB_COLOR0_INFO"
5478  },
5479  {
5480   "chips": ["gfx11"],
5481   "map": {"at": 167328, "to": "mm"},
5482   "name": "CB_COLOR5_ATTRIB",
5483   "type_ref": "CB_COLOR0_ATTRIB"
5484  },
5485  {
5486   "chips": ["gfx11"],
5487   "map": {"at": 167332, "to": "mm"},
5488   "name": "CB_COLOR5_FDCC_CONTROL",
5489   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5490  },
5491  {
5492   "chips": ["gfx11"],
5493   "map": {"at": 167360, "to": "mm"},
5494   "name": "CB_COLOR5_DCC_BASE"
5495  },
5496  {
5497   "chips": ["gfx11"],
5498   "map": {"at": 167368, "to": "mm"},
5499   "name": "CB_COLOR6_BASE"
5500  },
5501  {
5502   "chips": ["gfx11"],
5503   "map": {"at": 167380, "to": "mm"},
5504   "name": "CB_COLOR6_VIEW",
5505   "type_ref": "CB_COLOR0_VIEW"
5506  },
5507  {
5508   "chips": ["gfx11"],
5509   "map": {"at": 167384, "to": "mm"},
5510   "name": "CB_COLOR6_INFO",
5511   "type_ref": "CB_COLOR0_INFO"
5512  },
5513  {
5514   "chips": ["gfx11"],
5515   "map": {"at": 167388, "to": "mm"},
5516   "name": "CB_COLOR6_ATTRIB",
5517   "type_ref": "CB_COLOR0_ATTRIB"
5518  },
5519  {
5520   "chips": ["gfx11"],
5521   "map": {"at": 167392, "to": "mm"},
5522   "name": "CB_COLOR6_FDCC_CONTROL",
5523   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5524  },
5525  {
5526   "chips": ["gfx11"],
5527   "map": {"at": 167420, "to": "mm"},
5528   "name": "CB_COLOR6_DCC_BASE"
5529  },
5530  {
5531   "chips": ["gfx11"],
5532   "map": {"at": 167428, "to": "mm"},
5533   "name": "CB_COLOR7_BASE"
5534  },
5535  {
5536   "chips": ["gfx11"],
5537   "map": {"at": 167440, "to": "mm"},
5538   "name": "CB_COLOR7_VIEW",
5539   "type_ref": "CB_COLOR0_VIEW"
5540  },
5541  {
5542   "chips": ["gfx11"],
5543   "map": {"at": 167444, "to": "mm"},
5544   "name": "CB_COLOR7_INFO",
5545   "type_ref": "CB_COLOR0_INFO"
5546  },
5547  {
5548   "chips": ["gfx11"],
5549   "map": {"at": 167448, "to": "mm"},
5550   "name": "CB_COLOR7_ATTRIB",
5551   "type_ref": "CB_COLOR0_ATTRIB"
5552  },
5553  {
5554   "chips": ["gfx11"],
5555   "map": {"at": 167452, "to": "mm"},
5556   "name": "CB_COLOR7_FDCC_CONTROL",
5557   "type_ref": "CB_COLOR0_FDCC_CONTROL"
5558  },
5559  {
5560   "chips": ["gfx11"],
5561   "map": {"at": 167480, "to": "mm"},
5562   "name": "CB_COLOR7_DCC_BASE"
5563  },
5564  {
5565   "chips": ["gfx11"],
5566   "map": {"at": 167488, "to": "mm"},
5567   "name": "CB_COLOR0_BASE_EXT",
5568   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5569  },
5570  {
5571   "chips": ["gfx11"],
5572   "map": {"at": 167492, "to": "mm"},
5573   "name": "CB_COLOR1_BASE_EXT",
5574   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5575  },
5576  {
5577   "chips": ["gfx11"],
5578   "map": {"at": 167496, "to": "mm"},
5579   "name": "CB_COLOR2_BASE_EXT",
5580   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5581  },
5582  {
5583   "chips": ["gfx11"],
5584   "map": {"at": 167500, "to": "mm"},
5585   "name": "CB_COLOR3_BASE_EXT",
5586   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5587  },
5588  {
5589   "chips": ["gfx11"],
5590   "map": {"at": 167504, "to": "mm"},
5591   "name": "CB_COLOR4_BASE_EXT",
5592   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5593  },
5594  {
5595   "chips": ["gfx11"],
5596   "map": {"at": 167508, "to": "mm"},
5597   "name": "CB_COLOR5_BASE_EXT",
5598   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5599  },
5600  {
5601   "chips": ["gfx11"],
5602   "map": {"at": 167512, "to": "mm"},
5603   "name": "CB_COLOR6_BASE_EXT",
5604   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5605  },
5606  {
5607   "chips": ["gfx11"],
5608   "map": {"at": 167516, "to": "mm"},
5609   "name": "CB_COLOR7_BASE_EXT",
5610   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5611  },
5612  {
5613   "chips": ["gfx11"],
5614   "map": {"at": 167584, "to": "mm"},
5615   "name": "CB_COLOR0_DCC_BASE_EXT",
5616   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5617  },
5618  {
5619   "chips": ["gfx11"],
5620   "map": {"at": 167588, "to": "mm"},
5621   "name": "CB_COLOR1_DCC_BASE_EXT",
5622   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5623  },
5624  {
5625   "chips": ["gfx11"],
5626   "map": {"at": 167592, "to": "mm"},
5627   "name": "CB_COLOR2_DCC_BASE_EXT",
5628   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5629  },
5630  {
5631   "chips": ["gfx11"],
5632   "map": {"at": 167596, "to": "mm"},
5633   "name": "CB_COLOR3_DCC_BASE_EXT",
5634   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5635  },
5636  {
5637   "chips": ["gfx11"],
5638   "map": {"at": 167600, "to": "mm"},
5639   "name": "CB_COLOR4_DCC_BASE_EXT",
5640   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5641  },
5642  {
5643   "chips": ["gfx11"],
5644   "map": {"at": 167604, "to": "mm"},
5645   "name": "CB_COLOR5_DCC_BASE_EXT",
5646   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5647  },
5648  {
5649   "chips": ["gfx11"],
5650   "map": {"at": 167608, "to": "mm"},
5651   "name": "CB_COLOR6_DCC_BASE_EXT",
5652   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5653  },
5654  {
5655   "chips": ["gfx11"],
5656   "map": {"at": 167612, "to": "mm"},
5657   "name": "CB_COLOR7_DCC_BASE_EXT",
5658   "type_ref": "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT"
5659  },
5660  {
5661   "chips": ["gfx11"],
5662   "map": {"at": 167616, "to": "mm"},
5663   "name": "CB_COLOR0_ATTRIB2",
5664   "type_ref": "CB_COLOR0_ATTRIB2"
5665  },
5666  {
5667   "chips": ["gfx11"],
5668   "map": {"at": 167620, "to": "mm"},
5669   "name": "CB_COLOR1_ATTRIB2",
5670   "type_ref": "CB_COLOR0_ATTRIB2"
5671  },
5672  {
5673   "chips": ["gfx11"],
5674   "map": {"at": 167624, "to": "mm"},
5675   "name": "CB_COLOR2_ATTRIB2",
5676   "type_ref": "CB_COLOR0_ATTRIB2"
5677  },
5678  {
5679   "chips": ["gfx11"],
5680   "map": {"at": 167628, "to": "mm"},
5681   "name": "CB_COLOR3_ATTRIB2",
5682   "type_ref": "CB_COLOR0_ATTRIB2"
5683  },
5684  {
5685   "chips": ["gfx11"],
5686   "map": {"at": 167632, "to": "mm"},
5687   "name": "CB_COLOR4_ATTRIB2",
5688   "type_ref": "CB_COLOR0_ATTRIB2"
5689  },
5690  {
5691   "chips": ["gfx11"],
5692   "map": {"at": 167636, "to": "mm"},
5693   "name": "CB_COLOR5_ATTRIB2",
5694   "type_ref": "CB_COLOR0_ATTRIB2"
5695  },
5696  {
5697   "chips": ["gfx11"],
5698   "map": {"at": 167640, "to": "mm"},
5699   "name": "CB_COLOR6_ATTRIB2",
5700   "type_ref": "CB_COLOR0_ATTRIB2"
5701  },
5702  {
5703   "chips": ["gfx11"],
5704   "map": {"at": 167644, "to": "mm"},
5705   "name": "CB_COLOR7_ATTRIB2",
5706   "type_ref": "CB_COLOR0_ATTRIB2"
5707  },
5708  {
5709   "chips": ["gfx11"],
5710   "map": {"at": 167648, "to": "mm"},
5711   "name": "CB_COLOR0_ATTRIB3",
5712   "type_ref": "CB_COLOR0_ATTRIB3"
5713  },
5714  {
5715   "chips": ["gfx11"],
5716   "map": {"at": 167652, "to": "mm"},
5717   "name": "CB_COLOR1_ATTRIB3",
5718   "type_ref": "CB_COLOR0_ATTRIB3"
5719  },
5720  {
5721   "chips": ["gfx11"],
5722   "map": {"at": 167656, "to": "mm"},
5723   "name": "CB_COLOR2_ATTRIB3",
5724   "type_ref": "CB_COLOR0_ATTRIB3"
5725  },
5726  {
5727   "chips": ["gfx11"],
5728   "map": {"at": 167660, "to": "mm"},
5729   "name": "CB_COLOR3_ATTRIB3",
5730   "type_ref": "CB_COLOR0_ATTRIB3"
5731  },
5732  {
5733   "chips": ["gfx11"],
5734   "map": {"at": 167664, "to": "mm"},
5735   "name": "CB_COLOR4_ATTRIB3",
5736   "type_ref": "CB_COLOR0_ATTRIB3"
5737  },
5738  {
5739   "chips": ["gfx11"],
5740   "map": {"at": 167668, "to": "mm"},
5741   "name": "CB_COLOR5_ATTRIB3",
5742   "type_ref": "CB_COLOR0_ATTRIB3"
5743  },
5744  {
5745   "chips": ["gfx11"],
5746   "map": {"at": 167672, "to": "mm"},
5747   "name": "CB_COLOR6_ATTRIB3",
5748   "type_ref": "CB_COLOR0_ATTRIB3"
5749  },
5750  {
5751   "chips": ["gfx11"],
5752   "map": {"at": 167676, "to": "mm"},
5753   "name": "CB_COLOR7_ATTRIB3",
5754   "type_ref": "CB_COLOR0_ATTRIB3"
5755  },
5756  {
5757   "chips": ["gfx11"],
5758   "map": {"at": 196608, "to": "mm"},
5759   "name": "CP_EOP_DONE_ADDR_LO",
5760   "type_ref": "CP_EOP_DONE_ADDR_LO"
5761  },
5762  {
5763   "chips": ["gfx11"],
5764   "map": {"at": 196612, "to": "mm"},
5765   "name": "CP_EOP_DONE_ADDR_HI",
5766   "type_ref": "CP_EOP_DONE_ADDR_HI"
5767  },
5768  {
5769   "chips": ["gfx11"],
5770   "map": {"at": 196616, "to": "mm"},
5771   "name": "CP_EOP_DONE_DATA_LO"
5772  },
5773  {
5774   "chips": ["gfx11"],
5775   "map": {"at": 196620, "to": "mm"},
5776   "name": "CP_EOP_DONE_DATA_HI"
5777  },
5778  {
5779   "chips": ["gfx11"],
5780   "map": {"at": 196624, "to": "mm"},
5781   "name": "CP_EOP_LAST_FENCE_LO"
5782  },
5783  {
5784   "chips": ["gfx11"],
5785   "map": {"at": 196628, "to": "mm"},
5786   "name": "CP_EOP_LAST_FENCE_HI"
5787  },
5788  {
5789   "chips": ["gfx11"],
5790   "map": {"at": 196704, "to": "mm"},
5791   "name": "CP_PIPE_STATS_ADDR_LO",
5792   "type_ref": "CP_PIPE_STATS_ADDR_LO"
5793  },
5794  {
5795   "chips": ["gfx11"],
5796   "map": {"at": 196708, "to": "mm"},
5797   "name": "CP_PIPE_STATS_ADDR_HI",
5798   "type_ref": "CP_PIPE_STATS_ADDR_HI"
5799  },
5800  {
5801   "chips": ["gfx11"],
5802   "map": {"at": 196712, "to": "mm"},
5803   "name": "CP_VGT_IAVERT_COUNT_LO"
5804  },
5805  {
5806   "chips": ["gfx11"],
5807   "map": {"at": 196716, "to": "mm"},
5808   "name": "CP_VGT_IAVERT_COUNT_HI"
5809  },
5810  {
5811   "chips": ["gfx11"],
5812   "map": {"at": 196720, "to": "mm"},
5813   "name": "CP_VGT_IAPRIM_COUNT_LO"
5814  },
5815  {
5816   "chips": ["gfx11"],
5817   "map": {"at": 196724, "to": "mm"},
5818   "name": "CP_VGT_IAPRIM_COUNT_HI"
5819  },
5820  {
5821   "chips": ["gfx11"],
5822   "map": {"at": 196728, "to": "mm"},
5823   "name": "CP_VGT_GSPRIM_COUNT_LO"
5824  },
5825  {
5826   "chips": ["gfx11"],
5827   "map": {"at": 196732, "to": "mm"},
5828   "name": "CP_VGT_GSPRIM_COUNT_HI"
5829  },
5830  {
5831   "chips": ["gfx11"],
5832   "map": {"at": 196736, "to": "mm"},
5833   "name": "CP_VGT_VSINVOC_COUNT_LO"
5834  },
5835  {
5836   "chips": ["gfx11"],
5837   "map": {"at": 196740, "to": "mm"},
5838   "name": "CP_VGT_VSINVOC_COUNT_HI"
5839  },
5840  {
5841   "chips": ["gfx11"],
5842   "map": {"at": 196744, "to": "mm"},
5843   "name": "CP_VGT_GSINVOC_COUNT_LO"
5844  },
5845  {
5846   "chips": ["gfx11"],
5847   "map": {"at": 196748, "to": "mm"},
5848   "name": "CP_VGT_GSINVOC_COUNT_HI"
5849  },
5850  {
5851   "chips": ["gfx11"],
5852   "map": {"at": 196752, "to": "mm"},
5853   "name": "CP_VGT_HSINVOC_COUNT_LO"
5854  },
5855  {
5856   "chips": ["gfx11"],
5857   "map": {"at": 196756, "to": "mm"},
5858   "name": "CP_VGT_HSINVOC_COUNT_HI"
5859  },
5860  {
5861   "chips": ["gfx11"],
5862   "map": {"at": 196760, "to": "mm"},
5863   "name": "CP_VGT_DSINVOC_COUNT_LO"
5864  },
5865  {
5866   "chips": ["gfx11"],
5867   "map": {"at": 196764, "to": "mm"},
5868   "name": "CP_VGT_DSINVOC_COUNT_HI"
5869  },
5870  {
5871   "chips": ["gfx11"],
5872   "map": {"at": 196768, "to": "mm"},
5873   "name": "CP_PA_CINVOC_COUNT_LO"
5874  },
5875  {
5876   "chips": ["gfx11"],
5877   "map": {"at": 196772, "to": "mm"},
5878   "name": "CP_PA_CINVOC_COUNT_HI"
5879  },
5880  {
5881   "chips": ["gfx11"],
5882   "map": {"at": 196776, "to": "mm"},
5883   "name": "CP_PA_CPRIM_COUNT_LO"
5884  },
5885  {
5886   "chips": ["gfx11"],
5887   "map": {"at": 196780, "to": "mm"},
5888   "name": "CP_PA_CPRIM_COUNT_HI"
5889  },
5890  {
5891   "chips": ["gfx11"],
5892   "map": {"at": 196784, "to": "mm"},
5893   "name": "CP_SC_PSINVOC_COUNT0_LO"
5894  },
5895  {
5896   "chips": ["gfx11"],
5897   "map": {"at": 196788, "to": "mm"},
5898   "name": "CP_SC_PSINVOC_COUNT0_HI"
5899  },
5900  {
5901   "chips": ["gfx11"],
5902   "map": {"at": 196792, "to": "mm"},
5903   "name": "CP_SC_PSINVOC_COUNT1_LO"
5904  },
5905  {
5906   "chips": ["gfx11"],
5907   "map": {"at": 196796, "to": "mm"},
5908   "name": "CP_SC_PSINVOC_COUNT1_HI"
5909  },
5910  {
5911   "chips": ["gfx11"],
5912   "map": {"at": 196800, "to": "mm"},
5913   "name": "CP_VGT_CSINVOC_COUNT_LO"
5914  },
5915  {
5916   "chips": ["gfx11"],
5917   "map": {"at": 196804, "to": "mm"},
5918   "name": "CP_VGT_CSINVOC_COUNT_HI"
5919  },
5920  {
5921   "chips": ["gfx11"],
5922   "map": {"at": 196808, "to": "mm"},
5923   "name": "CP_VGT_ASINVOC_COUNT_LO"
5924  },
5925  {
5926   "chips": ["gfx11"],
5927   "map": {"at": 196812, "to": "mm"},
5928   "name": "CP_VGT_ASINVOC_COUNT_HI"
5929  },
5930  {
5931   "chips": ["gfx11"],
5932   "map": {"at": 196852, "to": "mm"},
5933   "name": "CP_PIPE_STATS_CONTROL",
5934   "type_ref": "CP_PIPE_STATS_CONTROL"
5935  },
5936  {
5937   "chips": ["gfx11"],
5938   "map": {"at": 196864, "to": "mm"},
5939   "name": "SCRATCH_REG0"
5940  },
5941  {
5942   "chips": ["gfx11"],
5943   "map": {"at": 196868, "to": "mm"},
5944   "name": "SCRATCH_REG1"
5945  },
5946  {
5947   "chips": ["gfx11"],
5948   "map": {"at": 196872, "to": "mm"},
5949   "name": "SCRATCH_REG2"
5950  },
5951  {
5952   "chips": ["gfx11"],
5953   "map": {"at": 196876, "to": "mm"},
5954   "name": "SCRATCH_REG3"
5955  },
5956  {
5957   "chips": ["gfx11"],
5958   "map": {"at": 196880, "to": "mm"},
5959   "name": "SCRATCH_REG4"
5960  },
5961  {
5962   "chips": ["gfx11"],
5963   "map": {"at": 196884, "to": "mm"},
5964   "name": "SCRATCH_REG5"
5965  },
5966  {
5967   "chips": ["gfx11"],
5968   "map": {"at": 196888, "to": "mm"},
5969   "name": "SCRATCH_REG6"
5970  },
5971  {
5972   "chips": ["gfx11"],
5973   "map": {"at": 196892, "to": "mm"},
5974   "name": "SCRATCH_REG7"
5975  },
5976  {
5977   "chips": ["gfx11"],
5978   "map": {"at": 196896, "to": "mm"},
5979   "name": "SCRATCH_REG_ATOMIC",
5980   "type_ref": "SCRATCH_REG_ATOMIC"
5981  },
5982  {
5983   "chips": ["gfx11"],
5984   "map": {"at": 196908, "to": "mm"},
5985   "name": "CP_APPEND_DDID_CNT",
5986   "type_ref": "COMPUTE_PGM_HI"
5987  },
5988  {
5989   "chips": ["gfx11"],
5990   "map": {"at": 196912, "to": "mm"},
5991   "name": "CP_APPEND_DATA_HI"
5992  },
5993  {
5994   "chips": ["gfx11"],
5995   "map": {"at": 196916, "to": "mm"},
5996   "name": "CP_APPEND_LAST_CS_FENCE_HI"
5997  },
5998  {
5999   "chips": ["gfx11"],
6000   "map": {"at": 196920, "to": "mm"},
6001   "name": "CP_APPEND_LAST_PS_FENCE_HI"
6002  },
6003  {
6004   "chips": ["gfx11"],
6005   "map": {"at": 196936, "to": "mm"},
6006   "name": "CP_PFP_ATOMIC_PREOP_LO"
6007  },
6008  {
6009   "chips": ["gfx11"],
6010   "map": {"at": 196940, "to": "mm"},
6011   "name": "CP_PFP_ATOMIC_PREOP_HI"
6012  },
6013  {
6014   "chips": ["gfx11"],
6015   "map": {"at": 196944, "to": "mm"},
6016   "name": "CP_PFP_GDS_ATOMIC0_PREOP_LO"
6017  },
6018  {
6019   "chips": ["gfx11"],
6020   "map": {"at": 196948, "to": "mm"},
6021   "name": "CP_PFP_GDS_ATOMIC0_PREOP_HI"
6022  },
6023  {
6024   "chips": ["gfx11"],
6025   "map": {"at": 196952, "to": "mm"},
6026   "name": "CP_PFP_GDS_ATOMIC1_PREOP_LO"
6027  },
6028  {
6029   "chips": ["gfx11"],
6030   "map": {"at": 196956, "to": "mm"},
6031   "name": "CP_PFP_GDS_ATOMIC1_PREOP_HI"
6032  },
6033  {
6034   "chips": ["gfx11"],
6035   "map": {"at": 196960, "to": "mm"},
6036   "name": "CP_APPEND_ADDR_LO",
6037   "type_ref": "CP_APPEND_ADDR_LO"
6038  },
6039  {
6040   "chips": ["gfx11"],
6041   "map": {"at": 196964, "to": "mm"},
6042   "name": "CP_APPEND_ADDR_HI",
6043   "type_ref": "CP_APPEND_ADDR_HI"
6044  },
6045  {
6046   "chips": ["gfx11"],
6047   "map": {"at": 196968, "to": "mm"},
6048   "name": "CP_APPEND_DATA"
6049  },
6050  {
6051   "chips": ["gfx11"],
6052   "map": {"at": 196972, "to": "mm"},
6053   "name": "CP_APPEND_LAST_CS_FENCE"
6054  },
6055  {
6056   "chips": ["gfx11"],
6057   "map": {"at": 196976, "to": "mm"},
6058   "name": "CP_APPEND_LAST_PS_FENCE"
6059  },
6060  {
6061   "chips": ["gfx11"],
6062   "map": {"at": 196980, "to": "mm"},
6063   "name": "CP_ATOMIC_PREOP_LO"
6064  },
6065  {
6066   "chips": ["gfx11"],
6067   "map": {"at": 196984, "to": "mm"},
6068   "name": "CP_ATOMIC_PREOP_HI"
6069  },
6070  {
6071   "chips": ["gfx11"],
6072   "map": {"at": 196988, "to": "mm"},
6073   "name": "CP_GDS_ATOMIC0_PREOP_LO"
6074  },
6075  {
6076   "chips": ["gfx11"],
6077   "map": {"at": 196992, "to": "mm"},
6078   "name": "CP_GDS_ATOMIC0_PREOP_HI"
6079  },
6080  {
6081   "chips": ["gfx11"],
6082   "map": {"at": 196996, "to": "mm"},
6083   "name": "CP_GDS_ATOMIC1_PREOP_LO"
6084  },
6085  {
6086   "chips": ["gfx11"],
6087   "map": {"at": 197000, "to": "mm"},
6088   "name": "CP_GDS_ATOMIC1_PREOP_HI"
6089  },
6090  {
6091   "chips": ["gfx11"],
6092   "map": {"at": 197028, "to": "mm"},
6093   "name": "CP_ME_MC_WADDR_LO",
6094   "type_ref": "CP_ME_MC_WADDR_LO"
6095  },
6096  {
6097   "chips": ["gfx11"],
6098   "map": {"at": 197032, "to": "mm"},
6099   "name": "CP_ME_MC_WADDR_HI",
6100   "type_ref": "CP_ME_MC_WADDR_HI"
6101  },
6102  {
6103   "chips": ["gfx11"],
6104   "map": {"at": 197036, "to": "mm"},
6105   "name": "CP_ME_MC_WDATA_LO"
6106  },
6107  {
6108   "chips": ["gfx11"],
6109   "map": {"at": 197040, "to": "mm"},
6110   "name": "CP_ME_MC_WDATA_HI"
6111  },
6112  {
6113   "chips": ["gfx11"],
6114   "map": {"at": 197044, "to": "mm"},
6115   "name": "CP_ME_MC_RADDR_LO",
6116   "type_ref": "CP_ME_MC_RADDR_LO"
6117  },
6118  {
6119   "chips": ["gfx11"],
6120   "map": {"at": 197048, "to": "mm"},
6121   "name": "CP_ME_MC_RADDR_HI",
6122   "type_ref": "CP_ME_MC_RADDR_HI"
6123  },
6124  {
6125   "chips": ["gfx11"],
6126   "map": {"at": 197052, "to": "mm"},
6127   "name": "CP_SEM_WAIT_TIMER"
6128  },
6129  {
6130   "chips": ["gfx11"],
6131   "map": {"at": 197056, "to": "mm"},
6132   "name": "CP_SIG_SEM_ADDR_LO",
6133   "type_ref": "CP_SIG_SEM_ADDR_LO"
6134  },
6135  {
6136   "chips": ["gfx11"],
6137   "map": {"at": 197060, "to": "mm"},
6138   "name": "CP_SIG_SEM_ADDR_HI",
6139   "type_ref": "CP_SIG_SEM_ADDR_HI"
6140  },
6141  {
6142   "chips": ["gfx11"],
6143   "map": {"at": 197072, "to": "mm"},
6144   "name": "CP_WAIT_REG_MEM_TIMEOUT"
6145  },
6146  {
6147   "chips": ["gfx11"],
6148   "map": {"at": 197076, "to": "mm"},
6149   "name": "CP_WAIT_SEM_ADDR_LO",
6150   "type_ref": "CP_SIG_SEM_ADDR_LO"
6151  },
6152  {
6153   "chips": ["gfx11"],
6154   "map": {"at": 197080, "to": "mm"},
6155   "name": "CP_WAIT_SEM_ADDR_HI",
6156   "type_ref": "CP_SIG_SEM_ADDR_HI"
6157  },
6158  {
6159   "chips": ["gfx11"],
6160   "map": {"at": 197084, "to": "mm"},
6161   "name": "CP_DMA_PFP_CONTROL",
6162   "type_ref": "CP_DMA_PFP_CONTROL"
6163  },
6164  {
6165   "chips": ["gfx11"],
6166   "map": {"at": 197088, "to": "mm"},
6167   "name": "CP_DMA_ME_CONTROL",
6168   "type_ref": "CP_DMA_PFP_CONTROL"
6169  },
6170  {
6171   "chips": ["gfx11"],
6172   "map": {"at": 197120, "to": "mm"},
6173   "name": "CP_DMA_ME_SRC_ADDR"
6174  },
6175  {
6176   "chips": ["gfx11"],
6177   "map": {"at": 197124, "to": "mm"},
6178   "name": "CP_DMA_ME_SRC_ADDR_HI",
6179   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6180  },
6181  {
6182   "chips": ["gfx11"],
6183   "map": {"at": 197128, "to": "mm"},
6184   "name": "CP_DMA_ME_DST_ADDR"
6185  },
6186  {
6187   "chips": ["gfx11"],
6188   "map": {"at": 197132, "to": "mm"},
6189   "name": "CP_DMA_ME_DST_ADDR_HI",
6190   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6191  },
6192  {
6193   "chips": ["gfx11"],
6194   "map": {"at": 197136, "to": "mm"},
6195   "name": "CP_DMA_ME_COMMAND",
6196   "type_ref": "CP_DMA_ME_COMMAND"
6197  },
6198  {
6199   "chips": ["gfx11"],
6200   "map": {"at": 197140, "to": "mm"},
6201   "name": "CP_DMA_PFP_SRC_ADDR"
6202  },
6203  {
6204   "chips": ["gfx11"],
6205   "map": {"at": 197144, "to": "mm"},
6206   "name": "CP_DMA_PFP_SRC_ADDR_HI",
6207   "type_ref": "CP_DMA_ME_SRC_ADDR_HI"
6208  },
6209  {
6210   "chips": ["gfx11"],
6211   "map": {"at": 197148, "to": "mm"},
6212   "name": "CP_DMA_PFP_DST_ADDR"
6213  },
6214  {
6215   "chips": ["gfx11"],
6216   "map": {"at": 197152, "to": "mm"},
6217   "name": "CP_DMA_PFP_DST_ADDR_HI",
6218   "type_ref": "CP_DMA_ME_DST_ADDR_HI"
6219  },
6220  {
6221   "chips": ["gfx11"],
6222   "map": {"at": 197156, "to": "mm"},
6223   "name": "CP_DMA_PFP_COMMAND",
6224   "type_ref": "CP_DMA_ME_COMMAND"
6225  },
6226  {
6227   "chips": ["gfx11"],
6228   "map": {"at": 197160, "to": "mm"},
6229   "name": "CP_DMA_CNTL",
6230   "type_ref": "CP_DMA_CNTL"
6231  },
6232  {
6233   "chips": ["gfx11"],
6234   "map": {"at": 197164, "to": "mm"},
6235   "name": "CP_DMA_READ_TAGS",
6236   "type_ref": "CP_DMA_READ_TAGS"
6237  },
6238  {
6239   "chips": ["gfx11"],
6240   "map": {"at": 197172, "to": "mm"},
6241   "name": "CP_PFP_IB_CONTROL",
6242   "type_ref": "CP_PFP_IB_CONTROL"
6243  },
6244  {
6245   "chips": ["gfx11"],
6246   "map": {"at": 197176, "to": "mm"},
6247   "name": "CP_PFP_LOAD_CONTROL",
6248   "type_ref": "CP_PFP_LOAD_CONTROL"
6249  },
6250  {
6251   "chips": ["gfx11"],
6252   "map": {"at": 197180, "to": "mm"},
6253   "name": "CP_SCRATCH_INDEX",
6254   "type_ref": "CP_CPC_SCRATCH_INDEX"
6255  },
6256  {
6257   "chips": ["gfx11"],
6258   "map": {"at": 197184, "to": "mm"},
6259   "name": "CP_SCRATCH_DATA"
6260  },
6261  {
6262   "chips": ["gfx11"],
6263   "map": {"at": 197188, "to": "mm"},
6264   "name": "CP_RB_OFFSET",
6265   "type_ref": "CP_RB_OFFSET"
6266  },
6267  {
6268   "chips": ["gfx11"],
6269   "map": {"at": 197196, "to": "mm"},
6270   "name": "CP_IB2_OFFSET",
6271   "type_ref": "CP_IB2_OFFSET"
6272  },
6273  {
6274   "chips": ["gfx11"],
6275   "map": {"at": 197208, "to": "mm"},
6276   "name": "CP_IB2_PREAMBLE_BEGIN",
6277   "type_ref": "CP_IB2_PREAMBLE_BEGIN"
6278  },
6279  {
6280   "chips": ["gfx11"],
6281   "map": {"at": 197212, "to": "mm"},
6282   "name": "CP_IB2_PREAMBLE_END",
6283   "type_ref": "CP_IB2_PREAMBLE_END"
6284  },
6285  {
6286   "chips": ["gfx11"],
6287   "map": {"at": 197232, "to": "mm"},
6288   "name": "CP_DMA_ME_CMD_ADDR_LO",
6289   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
6290  },
6291  {
6292   "chips": ["gfx11"],
6293   "map": {"at": 197236, "to": "mm"},
6294   "name": "CP_DMA_ME_CMD_ADDR_HI",
6295   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
6296  },
6297  {
6298   "chips": ["gfx11"],
6299   "map": {"at": 197240, "to": "mm"},
6300   "name": "CP_DMA_PFP_CMD_ADDR_LO",
6301   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
6302  },
6303  {
6304   "chips": ["gfx11"],
6305   "map": {"at": 197244, "to": "mm"},
6306   "name": "CP_DMA_PFP_CMD_ADDR_HI",
6307   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
6308  },
6309  {
6310   "chips": ["gfx11"],
6311   "map": {"at": 197248, "to": "mm"},
6312   "name": "CP_APPEND_CMD_ADDR_LO",
6313   "type_ref": "CP_DMA_ME_CMD_ADDR_LO"
6314  },
6315  {
6316   "chips": ["gfx11"],
6317   "map": {"at": 197252, "to": "mm"},
6318   "name": "CP_APPEND_CMD_ADDR_HI",
6319   "type_ref": "CP_DMA_ME_CMD_ADDR_HI"
6320  },
6321  {
6322   "chips": ["gfx11"],
6323   "map": {"at": 197256, "to": "mm"},
6324   "name": "UCONFIG_RESERVED_REG0"
6325  },
6326  {
6327   "chips": ["gfx11"],
6328   "map": {"at": 197260, "to": "mm"},
6329   "name": "UCONFIG_RESERVED_REG1"
6330  },
6331  {
6332   "chips": ["gfx11"],
6333   "map": {"at": 197264, "to": "mm"},
6334   "name": "CP_PA_MSPRIM_COUNT_LO"
6335  },
6336  {
6337   "chips": ["gfx11"],
6338   "map": {"at": 197268, "to": "mm"},
6339   "name": "CP_PA_MSPRIM_COUNT_HI"
6340  },
6341  {
6342   "chips": ["gfx11"],
6343   "map": {"at": 197272, "to": "mm"},
6344   "name": "CP_GE_MSINVOC_COUNT_LO"
6345  },
6346  {
6347   "chips": ["gfx11"],
6348   "map": {"at": 197276, "to": "mm"},
6349   "name": "CP_GE_MSINVOC_COUNT_HI"
6350  },
6351  {
6352   "chips": ["gfx11"],
6353   "map": {"at": 197380, "to": "mm"},
6354   "name": "CP_IB2_CMD_BUFSZ",
6355   "type_ref": "CP_IB2_CMD_BUFSZ"
6356  },
6357  {
6358   "chips": ["gfx11"],
6359   "map": {"at": 197384, "to": "mm"},
6360   "name": "CP_ST_CMD_BUFSZ",
6361   "type_ref": "CP_ST_CMD_BUFSZ"
6362  },
6363  {
6364   "chips": ["gfx11"],
6365   "map": {"at": 197436, "to": "mm"},
6366   "name": "CP_IB2_BASE_LO",
6367   "type_ref": "CP_IB2_BASE_LO"
6368  },
6369  {
6370   "chips": ["gfx11"],
6371   "map": {"at": 197440, "to": "mm"},
6372   "name": "CP_IB2_BASE_HI",
6373   "type_ref": "CP_IB2_BASE_HI"
6374  },
6375  {
6376   "chips": ["gfx11"],
6377   "map": {"at": 197444, "to": "mm"},
6378   "name": "CP_IB2_BUFSZ",
6379   "type_ref": "CP_IB2_BUFSZ"
6380  },
6381  {
6382   "chips": ["gfx11"],
6383   "map": {"at": 197448, "to": "mm"},
6384   "name": "CP_ST_BASE_LO",
6385   "type_ref": "CP_ST_BASE_LO"
6386  },
6387  {
6388   "chips": ["gfx11"],
6389   "map": {"at": 197452, "to": "mm"},
6390   "name": "CP_ST_BASE_HI",
6391   "type_ref": "CP_ST_BASE_HI"
6392  },
6393  {
6394   "chips": ["gfx11"],
6395   "map": {"at": 197456, "to": "mm"},
6396   "name": "CP_ST_BUFSZ",
6397   "type_ref": "CP_ST_BUFSZ"
6398  },
6399  {
6400   "chips": ["gfx11"],
6401   "map": {"at": 197460, "to": "mm"},
6402   "name": "CP_EOP_DONE_EVENT_CNTL",
6403   "type_ref": "CP_EOP_DONE_EVENT_CNTL"
6404  },
6405  {
6406   "chips": ["gfx11"],
6407   "map": {"at": 197464, "to": "mm"},
6408   "name": "CP_EOP_DONE_DATA_CNTL",
6409   "type_ref": "CP_EOP_DONE_DATA_CNTL"
6410  },
6411  {
6412   "chips": ["gfx11"],
6413   "map": {"at": 197468, "to": "mm"},
6414   "name": "CP_EOP_DONE_CNTX_ID"
6415  },
6416  {
6417   "chips": ["gfx11"],
6418   "map": {"at": 197472, "to": "mm"},
6419   "name": "CP_DB_BASE_LO",
6420   "type_ref": "CP_DB_BASE_LO"
6421  },
6422  {
6423   "chips": ["gfx11"],
6424   "map": {"at": 197476, "to": "mm"},
6425   "name": "CP_DB_BASE_HI",
6426   "type_ref": "CP_DB_BASE_HI"
6427  },
6428  {
6429   "chips": ["gfx11"],
6430   "map": {"at": 197480, "to": "mm"},
6431   "name": "CP_DB_BUFSZ",
6432   "type_ref": "CP_DB_BUFSZ"
6433  },
6434  {
6435   "chips": ["gfx11"],
6436   "map": {"at": 197484, "to": "mm"},
6437   "name": "CP_DB_CMD_BUFSZ",
6438   "type_ref": "CP_DB_CMD_BUFSZ"
6439  },
6440  {
6441   "chips": ["gfx11"],
6442   "map": {"at": 197552, "to": "mm"},
6443   "name": "CP_PFP_COMPLETION_STATUS",
6444   "type_ref": "CP_PFP_COMPLETION_STATUS"
6445  },
6446  {
6447   "chips": ["gfx11"],
6448   "map": {"at": 197560, "to": "mm"},
6449   "name": "CP_PRED_NOT_VISIBLE",
6450   "type_ref": "CP_PRED_NOT_VISIBLE"
6451  },
6452  {
6453   "chips": ["gfx11"],
6454   "map": {"at": 197568, "to": "mm"},
6455   "name": "CP_PFP_METADATA_BASE_ADDR"
6456  },
6457  {
6458   "chips": ["gfx11"],
6459   "map": {"at": 197572, "to": "mm"},
6460   "name": "CP_PFP_METADATA_BASE_ADDR_HI",
6461   "type_ref": "CP_EOP_DONE_ADDR_HI"
6462  },
6463  {
6464   "chips": ["gfx11"],
6465   "map": {"at": 197584, "to": "mm"},
6466   "name": "CP_DRAW_INDX_INDR_ADDR"
6467  },
6468  {
6469   "chips": ["gfx11"],
6470   "map": {"at": 197588, "to": "mm"},
6471   "name": "CP_DRAW_INDX_INDR_ADDR_HI",
6472   "type_ref": "CP_EOP_DONE_ADDR_HI"
6473  },
6474  {
6475   "chips": ["gfx11"],
6476   "map": {"at": 197592, "to": "mm"},
6477   "name": "CP_DISPATCH_INDR_ADDR"
6478  },
6479  {
6480   "chips": ["gfx11"],
6481   "map": {"at": 197596, "to": "mm"},
6482   "name": "CP_DISPATCH_INDR_ADDR_HI",
6483   "type_ref": "CP_EOP_DONE_ADDR_HI"
6484  },
6485  {
6486   "chips": ["gfx11"],
6487   "map": {"at": 197600, "to": "mm"},
6488   "name": "CP_INDEX_BASE_ADDR"
6489  },
6490  {
6491   "chips": ["gfx11"],
6492   "map": {"at": 197604, "to": "mm"},
6493   "name": "CP_INDEX_BASE_ADDR_HI",
6494   "type_ref": "CP_EOP_DONE_ADDR_HI"
6495  },
6496  {
6497   "chips": ["gfx11"],
6498   "map": {"at": 197608, "to": "mm"},
6499   "name": "CP_INDEX_TYPE",
6500   "type_ref": "CP_INDEX_TYPE"
6501  },
6502  {
6503   "chips": ["gfx11"],
6504   "map": {"at": 197612, "to": "mm"},
6505   "name": "CP_GDS_BKUP_ADDR"
6506  },
6507  {
6508   "chips": ["gfx11"],
6509   "map": {"at": 197616, "to": "mm"},
6510   "name": "CP_GDS_BKUP_ADDR_HI",
6511   "type_ref": "CP_EOP_DONE_ADDR_HI"
6512  },
6513  {
6514   "chips": ["gfx11"],
6515   "map": {"at": 197620, "to": "mm"},
6516   "name": "CP_SAMPLE_STATUS",
6517   "type_ref": "CP_SAMPLE_STATUS"
6518  },
6519  {
6520   "chips": ["gfx11"],
6521   "map": {"at": 197624, "to": "mm"},
6522   "name": "CP_ME_COHER_CNTL",
6523   "type_ref": "CP_ME_COHER_CNTL"
6524  },
6525  {
6526   "chips": ["gfx11"],
6527   "map": {"at": 197628, "to": "mm"},
6528   "name": "CP_ME_COHER_SIZE"
6529  },
6530  {
6531   "chips": ["gfx11"],
6532   "map": {"at": 197632, "to": "mm"},
6533   "name": "CP_ME_COHER_SIZE_HI",
6534   "type_ref": "CP_ME_COHER_SIZE_HI"
6535  },
6536  {
6537   "chips": ["gfx11"],
6538   "map": {"at": 197636, "to": "mm"},
6539   "name": "CP_ME_COHER_BASE"
6540  },
6541  {
6542   "chips": ["gfx11"],
6543   "map": {"at": 197640, "to": "mm"},
6544   "name": "CP_ME_COHER_BASE_HI",
6545   "type_ref": "CP_ME_COHER_BASE_HI"
6546  },
6547  {
6548   "chips": ["gfx11"],
6549   "map": {"at": 197644, "to": "mm"},
6550   "name": "CP_ME_COHER_STATUS",
6551   "type_ref": "CP_ME_COHER_STATUS"
6552  },
6553  {
6554   "chips": ["gfx11"],
6555   "map": {"at": 197888, "to": "mm"},
6556   "name": "RLC_GPM_PERF_COUNT_0",
6557   "type_ref": "RLC_GPM_PERF_COUNT_0"
6558  },
6559  {
6560   "chips": ["gfx11"],
6561   "map": {"at": 197892, "to": "mm"},
6562   "name": "RLC_GPM_PERF_COUNT_1",
6563   "type_ref": "RLC_GPM_PERF_COUNT_0"
6564  },
6565  {
6566   "chips": ["gfx11"],
6567   "map": {"at": 198656, "to": "mm"},
6568   "name": "GRBM_GFX_INDEX",
6569   "type_ref": "GRBM_GFX_INDEX"
6570  },
6571  {
6572   "chips": ["gfx11"],
6573   "map": {"at": 198920, "to": "mm"},
6574   "name": "VGT_PRIMITIVE_TYPE",
6575   "type_ref": "VGT_PRIMITIVE_TYPE"
6576  },
6577  {
6578   "chips": ["gfx11"],
6579   "map": {"at": 198924, "to": "mm"},
6580   "name": "VGT_INDEX_TYPE",
6581   "type_ref": "VGT_INDEX_TYPE"
6582  },
6583  {
6584   "chips": ["gfx11"],
6585   "map": {"at": 198948, "to": "mm"},
6586   "name": "GE_MIN_VTX_INDX"
6587  },
6588  {
6589   "chips": ["gfx11"],
6590   "map": {"at": 198952, "to": "mm"},
6591   "name": "GE_INDX_OFFSET"
6592  },
6593  {
6594   "chips": ["gfx11"],
6595   "map": {"at": 198956, "to": "mm"},
6596   "name": "GE_MULTI_PRIM_IB_RESET_EN",
6597   "type_ref": "GE_MULTI_PRIM_IB_RESET_EN"
6598  },
6599  {
6600   "chips": ["gfx11"],
6601   "map": {"at": 198960, "to": "mm"},
6602   "name": "VGT_NUM_INDICES"
6603  },
6604  {
6605   "chips": ["gfx11"],
6606   "map": {"at": 198964, "to": "mm"},
6607   "name": "VGT_NUM_INSTANCES"
6608  },
6609  {
6610   "chips": ["gfx11"],
6611   "map": {"at": 198968, "to": "mm"},
6612   "name": "VGT_TF_RING_SIZE",
6613   "type_ref": "VGT_TF_RING_SIZE"
6614  },
6615  {
6616   "chips": ["gfx11"],
6617   "map": {"at": 198972, "to": "mm"},
6618   "name": "VGT_HS_OFFCHIP_PARAM",
6619   "type_ref": "VGT_HS_OFFCHIP_PARAM"
6620  },
6621  {
6622   "chips": ["gfx11"],
6623   "map": {"at": 198976, "to": "mm"},
6624   "name": "VGT_TF_MEMORY_BASE"
6625  },
6626  {
6627   "chips": ["gfx11"],
6628   "map": {"at": 199012, "to": "mm"},
6629   "name": "GE_MAX_VTX_INDX"
6630  },
6631  {
6632   "chips": ["gfx11"],
6633   "map": {"at": 199016, "to": "mm"},
6634   "name": "VGT_INSTANCE_BASE_ID"
6635  },
6636  {
6637   "chips": ["gfx11"],
6638   "map": {"at": 199020, "to": "mm"},
6639   "name": "GE_CNTL",
6640   "type_ref": "GE_CNTL"
6641  },
6642  {
6643   "chips": ["gfx11"],
6644   "map": {"at": 199024, "to": "mm"},
6645   "name": "GE_USER_VGPR1"
6646  },
6647  {
6648   "chips": ["gfx11"],
6649   "map": {"at": 199028, "to": "mm"},
6650   "name": "GE_USER_VGPR2"
6651  },
6652  {
6653   "chips": ["gfx11"],
6654   "map": {"at": 199032, "to": "mm"},
6655   "name": "GE_USER_VGPR3"
6656  },
6657  {
6658   "chips": ["gfx11"],
6659   "map": {"at": 199036, "to": "mm"},
6660   "name": "GE_STEREO_CNTL",
6661   "type_ref": "GE_STEREO_CNTL"
6662  },
6663  {
6664   "chips": ["gfx11"],
6665   "map": {"at": 199040, "to": "mm"},
6666   "name": "GE_PC_ALLOC",
6667   "type_ref": "GE_PC_ALLOC"
6668  },
6669  {
6670   "chips": ["gfx11"],
6671   "map": {"at": 199044, "to": "mm"},
6672   "name": "VGT_TF_MEMORY_BASE_HI",
6673   "type_ref": "DB_Z_READ_BASE_HI"
6674  },
6675  {
6676   "chips": ["gfx11"],
6677   "map": {"at": 199048, "to": "mm"},
6678   "name": "GE_USER_VGPR_EN",
6679   "type_ref": "GE_USER_VGPR_EN"
6680  },
6681  {
6682   "chips": ["gfx11"],
6683   "map": {"at": 199056, "to": "mm"},
6684   "name": "GE_GS_FAST_LAUNCH_WG_DIM",
6685   "type_ref": "GE_GS_FAST_LAUNCH_WG_DIM"
6686  },
6687  {
6688   "chips": ["gfx11"],
6689   "map": {"at": 199060, "to": "mm"},
6690   "name": "GE_GS_FAST_LAUNCH_WG_DIM_1",
6691   "type_ref": "GE_GS_FAST_LAUNCH_WG_DIM_1"
6692  },
6693  {
6694   "chips": ["gfx11"],
6695   "map": {"at": 199064, "to": "mm"},
6696   "name": "VGT_GS_OUT_PRIM_TYPE",
6697   "type_ref": "VGT_GS_OUT_PRIM_TYPE"
6698  },
6699  {
6700   "chips": ["gfx11"],
6701   "map": {"at": 199168, "to": "mm"},
6702   "name": "PA_SU_LINE_STIPPLE_VALUE",
6703   "type_ref": "PA_SU_LINE_STIPPLE_VALUE"
6704  },
6705  {
6706   "chips": ["gfx11"],
6707   "map": {"at": 199172, "to": "mm"},
6708   "name": "PA_SC_LINE_STIPPLE_STATE",
6709   "type_ref": "PA_SC_LINE_STIPPLE_STATE"
6710  },
6711  {
6712   "chips": ["gfx11"],
6713   "map": {"at": 199184, "to": "mm"},
6714   "name": "PA_SC_SCREEN_EXTENT_MIN_0",
6715   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
6716  },
6717  {
6718   "chips": ["gfx11"],
6719   "map": {"at": 199188, "to": "mm"},
6720   "name": "PA_SC_SCREEN_EXTENT_MAX_0",
6721   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
6722  },
6723  {
6724   "chips": ["gfx11"],
6725   "map": {"at": 199192, "to": "mm"},
6726   "name": "PA_SC_SCREEN_EXTENT_MIN_1",
6727   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
6728  },
6729  {
6730   "chips": ["gfx11"],
6731   "map": {"at": 199212, "to": "mm"},
6732   "name": "PA_SC_SCREEN_EXTENT_MAX_1",
6733   "type_ref": "PA_SC_SCREEN_EXTENT_MIN_0"
6734  },
6735  {
6736   "chips": ["gfx11"],
6737   "map": {"at": 199296, "to": "mm"},
6738   "name": "PA_SC_P3D_TRAP_SCREEN_HV_EN",
6739   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
6740  },
6741  {
6742   "chips": ["gfx11"],
6743   "map": {"at": 199300, "to": "mm"},
6744   "name": "PA_SC_P3D_TRAP_SCREEN_H",
6745   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
6746  },
6747  {
6748   "chips": ["gfx11"],
6749   "map": {"at": 199304, "to": "mm"},
6750   "name": "PA_SC_P3D_TRAP_SCREEN_V",
6751   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
6752  },
6753  {
6754   "chips": ["gfx11"],
6755   "map": {"at": 199308, "to": "mm"},
6756   "name": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE",
6757   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
6758  },
6759  {
6760   "chips": ["gfx11"],
6761   "map": {"at": 199312, "to": "mm"},
6762   "name": "PA_SC_P3D_TRAP_SCREEN_COUNT",
6763   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
6764  },
6765  {
6766   "chips": ["gfx11"],
6767   "map": {"at": 199328, "to": "mm"},
6768   "name": "PA_SC_HP3D_TRAP_SCREEN_HV_EN",
6769   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
6770  },
6771  {
6772   "chips": ["gfx11"],
6773   "map": {"at": 199332, "to": "mm"},
6774   "name": "PA_SC_HP3D_TRAP_SCREEN_H",
6775   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
6776  },
6777  {
6778   "chips": ["gfx11"],
6779   "map": {"at": 199336, "to": "mm"},
6780   "name": "PA_SC_HP3D_TRAP_SCREEN_V",
6781   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
6782  },
6783  {
6784   "chips": ["gfx11"],
6785   "map": {"at": 199340, "to": "mm"},
6786   "name": "PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE",
6787   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
6788  },
6789  {
6790   "chips": ["gfx11"],
6791   "map": {"at": 199344, "to": "mm"},
6792   "name": "PA_SC_HP3D_TRAP_SCREEN_COUNT",
6793   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
6794  },
6795  {
6796   "chips": ["gfx11"],
6797   "map": {"at": 199360, "to": "mm"},
6798   "name": "PA_SC_TRAP_SCREEN_HV_EN",
6799   "type_ref": "PA_SC_P3D_TRAP_SCREEN_HV_EN"
6800  },
6801  {
6802   "chips": ["gfx11"],
6803   "map": {"at": 199364, "to": "mm"},
6804   "name": "PA_SC_TRAP_SCREEN_H",
6805   "type_ref": "PA_SC_P3D_TRAP_SCREEN_H"
6806  },
6807  {
6808   "chips": ["gfx11"],
6809   "map": {"at": 199368, "to": "mm"},
6810   "name": "PA_SC_TRAP_SCREEN_V",
6811   "type_ref": "PA_SC_P3D_TRAP_SCREEN_V"
6812  },
6813  {
6814   "chips": ["gfx11"],
6815   "map": {"at": 199372, "to": "mm"},
6816   "name": "PA_SC_TRAP_SCREEN_OCCURRENCE",
6817   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
6818  },
6819  {
6820   "chips": ["gfx11"],
6821   "map": {"at": 199376, "to": "mm"},
6822   "name": "PA_SC_TRAP_SCREEN_COUNT",
6823   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
6824  },
6825  {
6826   "chips": ["gfx11"],
6827   "map": {"at": 199936, "to": "mm"},
6828   "name": "SQ_THREAD_TRACE_USERDATA_0"
6829  },
6830  {
6831   "chips": ["gfx11"],
6832   "map": {"at": 199940, "to": "mm"},
6833   "name": "SQ_THREAD_TRACE_USERDATA_1"
6834  },
6835  {
6836   "chips": ["gfx11"],
6837   "map": {"at": 199944, "to": "mm"},
6838   "name": "SQ_THREAD_TRACE_USERDATA_2"
6839  },
6840  {
6841   "chips": ["gfx11"],
6842   "map": {"at": 199948, "to": "mm"},
6843   "name": "SQ_THREAD_TRACE_USERDATA_3"
6844  },
6845  {
6846   "chips": ["gfx11"],
6847   "map": {"at": 199952, "to": "mm"},
6848   "name": "SQ_THREAD_TRACE_USERDATA_4"
6849  },
6850  {
6851   "chips": ["gfx11"],
6852   "map": {"at": 199956, "to": "mm"},
6853   "name": "SQ_THREAD_TRACE_USERDATA_5"
6854  },
6855  {
6856   "chips": ["gfx11"],
6857   "map": {"at": 199960, "to": "mm"},
6858   "name": "SQ_THREAD_TRACE_USERDATA_6"
6859  },
6860  {
6861   "chips": ["gfx11"],
6862   "map": {"at": 199964, "to": "mm"},
6863   "name": "SQ_THREAD_TRACE_USERDATA_7"
6864  },
6865  {
6866   "chips": ["gfx11"],
6867   "map": {"at": 199968, "to": "mm"},
6868   "name": "SQC_CACHES",
6869   "type_ref": "SQC_CACHES"
6870  },
6871  {
6872   "chips": ["gfx11"],
6873   "map": {"at": 200192, "to": "mm"},
6874   "name": "TA_CS_BC_BASE_ADDR"
6875  },
6876  {
6877   "chips": ["gfx11"],
6878   "map": {"at": 200196, "to": "mm"},
6879   "name": "TA_CS_BC_BASE_ADDR_HI",
6880   "type_ref": "TA_BC_BASE_ADDR_HI"
6881  },
6882  {
6883   "chips": ["gfx11"],
6884   "map": {"at": 200448, "to": "mm"},
6885   "name": "DB_OCCLUSION_COUNT0_LOW"
6886  },
6887  {
6888   "chips": ["gfx11"],
6889   "map": {"at": 200452, "to": "mm"},
6890   "name": "DB_OCCLUSION_COUNT0_HI",
6891   "type_ref": "DB_OCCLUSION_COUNT0_HI"
6892  },
6893  {
6894   "chips": ["gfx11"],
6895   "map": {"at": 200456, "to": "mm"},
6896   "name": "DB_OCCLUSION_COUNT1_LOW"
6897  },
6898  {
6899   "chips": ["gfx11"],
6900   "map": {"at": 200460, "to": "mm"},
6901   "name": "DB_OCCLUSION_COUNT1_HI",
6902   "type_ref": "DB_OCCLUSION_COUNT0_HI"
6903  },
6904  {
6905   "chips": ["gfx11"],
6906   "map": {"at": 200464, "to": "mm"},
6907   "name": "DB_OCCLUSION_COUNT2_LOW"
6908  },
6909  {
6910   "chips": ["gfx11"],
6911   "map": {"at": 200468, "to": "mm"},
6912   "name": "DB_OCCLUSION_COUNT2_HI",
6913   "type_ref": "DB_OCCLUSION_COUNT0_HI"
6914  },
6915  {
6916   "chips": ["gfx11"],
6917   "map": {"at": 200472, "to": "mm"},
6918   "name": "DB_OCCLUSION_COUNT3_LOW"
6919  },
6920  {
6921   "chips": ["gfx11"],
6922   "map": {"at": 200476, "to": "mm"},
6923   "name": "DB_OCCLUSION_COUNT3_HI",
6924   "type_ref": "DB_OCCLUSION_COUNT0_HI"
6925  },
6926  {
6927   "chips": ["gfx11"],
6928   "map": {"at": 200704, "to": "mm"},
6929   "name": "GDS_RD_ADDR"
6930  },
6931  {
6932   "chips": ["gfx11"],
6933   "map": {"at": 200708, "to": "mm"},
6934   "name": "GDS_RD_DATA"
6935  },
6936  {
6937   "chips": ["gfx11"],
6938   "map": {"at": 200712, "to": "mm"},
6939   "name": "GDS_RD_BURST_ADDR"
6940  },
6941  {
6942   "chips": ["gfx11"],
6943   "map": {"at": 200716, "to": "mm"},
6944   "name": "GDS_RD_BURST_COUNT"
6945  },
6946  {
6947   "chips": ["gfx11"],
6948   "map": {"at": 200720, "to": "mm"},
6949   "name": "GDS_RD_BURST_DATA"
6950  },
6951  {
6952   "chips": ["gfx11"],
6953   "map": {"at": 200724, "to": "mm"},
6954   "name": "GDS_WR_ADDR"
6955  },
6956  {
6957   "chips": ["gfx11"],
6958   "map": {"at": 200728, "to": "mm"},
6959   "name": "GDS_WR_DATA"
6960  },
6961  {
6962   "chips": ["gfx11"],
6963   "map": {"at": 200732, "to": "mm"},
6964   "name": "GDS_WR_BURST_ADDR"
6965  },
6966  {
6967   "chips": ["gfx11"],
6968   "map": {"at": 200736, "to": "mm"},
6969   "name": "GDS_WR_BURST_DATA"
6970  },
6971  {
6972   "chips": ["gfx11"],
6973   "map": {"at": 200740, "to": "mm"},
6974   "name": "GDS_WRITE_COMPLETE"
6975  },
6976  {
6977   "chips": ["gfx11"],
6978   "map": {"at": 200744, "to": "mm"},
6979   "name": "GDS_ATOM_CNTL",
6980   "type_ref": "GDS_ATOM_CNTL"
6981  },
6982  {
6983   "chips": ["gfx11"],
6984   "map": {"at": 200748, "to": "mm"},
6985   "name": "GDS_ATOM_COMPLETE",
6986   "type_ref": "GDS_ATOM_COMPLETE"
6987  },
6988  {
6989   "chips": ["gfx11"],
6990   "map": {"at": 200752, "to": "mm"},
6991   "name": "GDS_ATOM_BASE",
6992   "type_ref": "GDS_ATOM_BASE"
6993  },
6994  {
6995   "chips": ["gfx11"],
6996   "map": {"at": 200756, "to": "mm"},
6997   "name": "GDS_ATOM_SIZE",
6998   "type_ref": "GDS_ATOM_SIZE"
6999  },
7000  {
7001   "chips": ["gfx11"],
7002   "map": {"at": 200760, "to": "mm"},
7003   "name": "GDS_ATOM_OFFSET0",
7004   "type_ref": "GDS_ATOM_OFFSET0"
7005  },
7006  {
7007   "chips": ["gfx11"],
7008   "map": {"at": 200764, "to": "mm"},
7009   "name": "GDS_ATOM_OFFSET1",
7010   "type_ref": "GDS_ATOM_OFFSET1"
7011  },
7012  {
7013   "chips": ["gfx11"],
7014   "map": {"at": 200768, "to": "mm"},
7015   "name": "GDS_ATOM_DST"
7016  },
7017  {
7018   "chips": ["gfx11"],
7019   "map": {"at": 200772, "to": "mm"},
7020   "name": "GDS_ATOM_OP",
7021   "type_ref": "GDS_ATOM_OP"
7022  },
7023  {
7024   "chips": ["gfx11"],
7025   "map": {"at": 200776, "to": "mm"},
7026   "name": "GDS_ATOM_SRC0"
7027  },
7028  {
7029   "chips": ["gfx11"],
7030   "map": {"at": 200780, "to": "mm"},
7031   "name": "GDS_ATOM_SRC0_U"
7032  },
7033  {
7034   "chips": ["gfx11"],
7035   "map": {"at": 200784, "to": "mm"},
7036   "name": "GDS_ATOM_SRC1"
7037  },
7038  {
7039   "chips": ["gfx11"],
7040   "map": {"at": 200788, "to": "mm"},
7041   "name": "GDS_ATOM_SRC1_U"
7042  },
7043  {
7044   "chips": ["gfx11"],
7045   "map": {"at": 200792, "to": "mm"},
7046   "name": "GDS_ATOM_READ0"
7047  },
7048  {
7049   "chips": ["gfx11"],
7050   "map": {"at": 200796, "to": "mm"},
7051   "name": "GDS_ATOM_READ0_U"
7052  },
7053  {
7054   "chips": ["gfx11"],
7055   "map": {"at": 200800, "to": "mm"},
7056   "name": "GDS_ATOM_READ1"
7057  },
7058  {
7059   "chips": ["gfx11"],
7060   "map": {"at": 200804, "to": "mm"},
7061   "name": "GDS_ATOM_READ1_U"
7062  },
7063  {
7064   "chips": ["gfx11"],
7065   "map": {"at": 200808, "to": "mm"},
7066   "name": "GDS_GWS_RESOURCE_CNTL",
7067   "type_ref": "GDS_GWS_RESOURCE_CNTL"
7068  },
7069  {
7070   "chips": ["gfx11"],
7071   "map": {"at": 200812, "to": "mm"},
7072   "name": "GDS_GWS_RESOURCE",
7073   "type_ref": "GDS_GWS_RESOURCE"
7074  },
7075  {
7076   "chips": ["gfx11"],
7077   "map": {"at": 200816, "to": "mm"},
7078   "name": "GDS_GWS_RESOURCE_CNT",
7079   "type_ref": "GDS_GWS_RESOURCE_CNT"
7080  },
7081  {
7082   "chips": ["gfx11"],
7083   "map": {"at": 200820, "to": "mm"},
7084   "name": "GDS_OA_CNTL",
7085   "type_ref": "GDS_OA_CNTL"
7086  },
7087  {
7088   "chips": ["gfx11"],
7089   "map": {"at": 200824, "to": "mm"},
7090   "name": "GDS_OA_COUNTER"
7091  },
7092  {
7093   "chips": ["gfx11"],
7094   "map": {"at": 200828, "to": "mm"},
7095   "name": "GDS_OA_ADDRESS",
7096   "type_ref": "GDS_OA_ADDRESS"
7097  },
7098  {
7099   "chips": ["gfx11"],
7100   "map": {"at": 200832, "to": "mm"},
7101   "name": "GDS_OA_INCDEC",
7102   "type_ref": "GDS_OA_INCDEC"
7103  },
7104  {
7105   "chips": ["gfx11"],
7106   "map": {"at": 200836, "to": "mm"},
7107   "name": "GDS_OA_RING_SIZE"
7108  },
7109  {
7110   "chips": ["gfx11"],
7111   "map": {"at": 200840, "to": "mm"},
7112   "name": "GDS_STRMOUT_DWORDS_WRITTEN_0"
7113  },
7114  {
7115   "chips": ["gfx11"],
7116   "map": {"at": 200844, "to": "mm"},
7117   "name": "GDS_STRMOUT_DWORDS_WRITTEN_1"
7118  },
7119  {
7120   "chips": ["gfx11"],
7121   "map": {"at": 200848, "to": "mm"},
7122   "name": "GDS_STRMOUT_DWORDS_WRITTEN_2"
7123  },
7124  {
7125   "chips": ["gfx11"],
7126   "map": {"at": 200852, "to": "mm"},
7127   "name": "GDS_STRMOUT_DWORDS_WRITTEN_3"
7128  },
7129  {
7130   "chips": ["gfx11"],
7131   "map": {"at": 200856, "to": "mm"},
7132   "name": "GDS_GS_0"
7133  },
7134  {
7135   "chips": ["gfx11"],
7136   "map": {"at": 200860, "to": "mm"},
7137   "name": "GDS_GS_1"
7138  },
7139  {
7140   "chips": ["gfx11"],
7141   "map": {"at": 200864, "to": "mm"},
7142   "name": "GDS_GS_2"
7143  },
7144  {
7145   "chips": ["gfx11"],
7146   "map": {"at": 200868, "to": "mm"},
7147   "name": "GDS_GS_3"
7148  },
7149  {
7150   "chips": ["gfx11"],
7151   "map": {"at": 200872, "to": "mm"},
7152   "name": "GDS_STRMOUT_PRIMS_NEEDED_0_LO"
7153  },
7154  {
7155   "chips": ["gfx11"],
7156   "map": {"at": 200876, "to": "mm"},
7157   "name": "GDS_STRMOUT_PRIMS_NEEDED_0_HI"
7158  },
7159  {
7160   "chips": ["gfx11"],
7161   "map": {"at": 200880, "to": "mm"},
7162   "name": "GDS_STRMOUT_PRIMS_WRITTEN_0_LO"
7163  },
7164  {
7165   "chips": ["gfx11"],
7166   "map": {"at": 200884, "to": "mm"},
7167   "name": "GDS_STRMOUT_PRIMS_WRITTEN_0_HI"
7168  },
7169  {
7170   "chips": ["gfx11"],
7171   "map": {"at": 200888, "to": "mm"},
7172   "name": "GDS_STRMOUT_PRIMS_NEEDED_1_LO"
7173  },
7174  {
7175   "chips": ["gfx11"],
7176   "map": {"at": 200892, "to": "mm"},
7177   "name": "GDS_STRMOUT_PRIMS_NEEDED_1_HI"
7178  },
7179  {
7180   "chips": ["gfx11"],
7181   "map": {"at": 200896, "to": "mm"},
7182   "name": "GDS_STRMOUT_PRIMS_WRITTEN_1_LO"
7183  },
7184  {
7185   "chips": ["gfx11"],
7186   "map": {"at": 200900, "to": "mm"},
7187   "name": "GDS_STRMOUT_PRIMS_WRITTEN_1_HI"
7188  },
7189  {
7190   "chips": ["gfx11"],
7191   "map": {"at": 200904, "to": "mm"},
7192   "name": "GDS_STRMOUT_PRIMS_NEEDED_2_LO"
7193  },
7194  {
7195   "chips": ["gfx11"],
7196   "map": {"at": 200908, "to": "mm"},
7197   "name": "GDS_STRMOUT_PRIMS_NEEDED_2_HI"
7198  },
7199  {
7200   "chips": ["gfx11"],
7201   "map": {"at": 200912, "to": "mm"},
7202   "name": "GDS_STRMOUT_PRIMS_WRITTEN_2_LO"
7203  },
7204  {
7205   "chips": ["gfx11"],
7206   "map": {"at": 200916, "to": "mm"},
7207   "name": "GDS_STRMOUT_PRIMS_WRITTEN_2_HI"
7208  },
7209  {
7210   "chips": ["gfx11"],
7211   "map": {"at": 200920, "to": "mm"},
7212   "name": "GDS_STRMOUT_PRIMS_NEEDED_3_LO"
7213  },
7214  {
7215   "chips": ["gfx11"],
7216   "map": {"at": 200924, "to": "mm"},
7217   "name": "GDS_STRMOUT_PRIMS_NEEDED_3_HI"
7218  },
7219  {
7220   "chips": ["gfx11"],
7221   "map": {"at": 200928, "to": "mm"},
7222   "name": "GDS_STRMOUT_PRIMS_WRITTEN_3_LO"
7223  },
7224  {
7225   "chips": ["gfx11"],
7226   "map": {"at": 200932, "to": "mm"},
7227   "name": "GDS_STRMOUT_PRIMS_WRITTEN_3_HI"
7228  },
7229  {
7230   "chips": ["gfx11"],
7231   "map": {"at": 200960, "to": "mm"},
7232   "name": "SPI_CONFIG_CNTL",
7233   "type_ref": "SPI_CONFIG_CNTL"
7234  },
7235  {
7236   "chips": ["gfx11"],
7237   "map": {"at": 200964, "to": "mm"},
7238   "name": "SPI_CONFIG_CNTL_1",
7239   "type_ref": "SPI_CONFIG_CNTL_1"
7240  },
7241  {
7242   "chips": ["gfx11"],
7243   "map": {"at": 200968, "to": "mm"},
7244   "name": "SPI_CONFIG_CNTL_2",
7245   "type_ref": "SPI_CONFIG_CNTL_2"
7246  },
7247  {
7248   "chips": ["gfx11"],
7249   "map": {"at": 200972, "to": "mm"},
7250   "name": "SPI_WAVE_LIMIT_CNTL",
7251   "type_ref": "SPI_WAVE_LIMIT_CNTL"
7252  },
7253  {
7254   "chips": ["gfx11"],
7255   "map": {"at": 200976, "to": "mm"},
7256   "name": "SPI_GS_THROTTLE_CNTL1",
7257   "type_ref": "SPI_GS_THROTTLE_CNTL1"
7258  },
7259  {
7260   "chips": ["gfx11"],
7261   "map": {"at": 200980, "to": "mm"},
7262   "name": "SPI_GS_THROTTLE_CNTL2",
7263   "type_ref": "SPI_GS_THROTTLE_CNTL2"
7264  },
7265  {
7266   "chips": ["gfx11"],
7267   "map": {"at": 200984, "to": "mm"},
7268   "name": "SPI_ATTRIBUTE_RING_BASE"
7269  },
7270  {
7271   "chips": ["gfx11"],
7272   "map": {"at": 200988, "to": "mm"},
7273   "name": "SPI_ATTRIBUTE_RING_SIZE",
7274   "type_ref": "SPI_ATTRIBUTE_RING_SIZE"
7275  },
7276  {
7277   "chips": ["gfx11"],
7278   "map": {"at": 212992, "to": "mm"},
7279   "name": "CPG_PERFCOUNTER1_LO"
7280  },
7281  {
7282   "chips": ["gfx11"],
7283   "map": {"at": 212996, "to": "mm"},
7284   "name": "CPG_PERFCOUNTER1_HI"
7285  },
7286  {
7287   "chips": ["gfx11"],
7288   "map": {"at": 213000, "to": "mm"},
7289   "name": "CPG_PERFCOUNTER0_LO"
7290  },
7291  {
7292   "chips": ["gfx11"],
7293   "map": {"at": 213004, "to": "mm"},
7294   "name": "CPG_PERFCOUNTER0_HI"
7295  },
7296  {
7297   "chips": ["gfx11"],
7298   "map": {"at": 213008, "to": "mm"},
7299   "name": "CPC_PERFCOUNTER1_LO"
7300  },
7301  {
7302   "chips": ["gfx11"],
7303   "map": {"at": 213012, "to": "mm"},
7304   "name": "CPC_PERFCOUNTER1_HI"
7305  },
7306  {
7307   "chips": ["gfx11"],
7308   "map": {"at": 213016, "to": "mm"},
7309   "name": "CPC_PERFCOUNTER0_LO"
7310  },
7311  {
7312   "chips": ["gfx11"],
7313   "map": {"at": 213020, "to": "mm"},
7314   "name": "CPC_PERFCOUNTER0_HI"
7315  },
7316  {
7317   "chips": ["gfx11"],
7318   "map": {"at": 213024, "to": "mm"},
7319   "name": "CPF_PERFCOUNTER1_LO"
7320  },
7321  {
7322   "chips": ["gfx11"],
7323   "map": {"at": 213028, "to": "mm"},
7324   "name": "CPF_PERFCOUNTER1_HI"
7325  },
7326  {
7327   "chips": ["gfx11"],
7328   "map": {"at": 213032, "to": "mm"},
7329   "name": "CPF_PERFCOUNTER0_LO"
7330  },
7331  {
7332   "chips": ["gfx11"],
7333   "map": {"at": 213036, "to": "mm"},
7334   "name": "CPF_PERFCOUNTER0_HI"
7335  },
7336  {
7337   "chips": ["gfx11"],
7338   "map": {"at": 213040, "to": "mm"},
7339   "name": "CPF_LATENCY_STATS_DATA"
7340  },
7341  {
7342   "chips": ["gfx11"],
7343   "map": {"at": 213044, "to": "mm"},
7344   "name": "CPG_LATENCY_STATS_DATA"
7345  },
7346  {
7347   "chips": ["gfx11"],
7348   "map": {"at": 213048, "to": "mm"},
7349   "name": "CPC_LATENCY_STATS_DATA"
7350  },
7351  {
7352   "chips": ["gfx11"],
7353   "map": {"at": 213248, "to": "mm"},
7354   "name": "GRBM_PERFCOUNTER0_LO"
7355  },
7356  {
7357   "chips": ["gfx11"],
7358   "map": {"at": 213252, "to": "mm"},
7359   "name": "GRBM_PERFCOUNTER0_HI"
7360  },
7361  {
7362   "chips": ["gfx11"],
7363   "map": {"at": 213260, "to": "mm"},
7364   "name": "GRBM_PERFCOUNTER1_LO"
7365  },
7366  {
7367   "chips": ["gfx11"],
7368   "map": {"at": 213264, "to": "mm"},
7369   "name": "GRBM_PERFCOUNTER1_HI"
7370  },
7371  {
7372   "chips": ["gfx11"],
7373   "map": {"at": 213268, "to": "mm"},
7374   "name": "GRBM_SE0_PERFCOUNTER_LO"
7375  },
7376  {
7377   "chips": ["gfx11"],
7378   "map": {"at": 213272, "to": "mm"},
7379   "name": "GRBM_SE0_PERFCOUNTER_HI"
7380  },
7381  {
7382   "chips": ["gfx11"],
7383   "map": {"at": 213276, "to": "mm"},
7384   "name": "GRBM_SE1_PERFCOUNTER_LO"
7385  },
7386  {
7387   "chips": ["gfx11"],
7388   "map": {"at": 213280, "to": "mm"},
7389   "name": "GRBM_SE1_PERFCOUNTER_HI"
7390  },
7391  {
7392   "chips": ["gfx11"],
7393   "map": {"at": 213284, "to": "mm"},
7394   "name": "GRBM_SE2_PERFCOUNTER_LO"
7395  },
7396  {
7397   "chips": ["gfx11"],
7398   "map": {"at": 213288, "to": "mm"},
7399   "name": "GRBM_SE2_PERFCOUNTER_HI"
7400  },
7401  {
7402   "chips": ["gfx11"],
7403   "map": {"at": 213292, "to": "mm"},
7404   "name": "GRBM_SE3_PERFCOUNTER_LO"
7405  },
7406  {
7407   "chips": ["gfx11"],
7408   "map": {"at": 213296, "to": "mm"},
7409   "name": "GRBM_SE3_PERFCOUNTER_HI"
7410  },
7411  {
7412   "chips": ["gfx11"],
7413   "map": {"at": 213300, "to": "mm"},
7414   "name": "GRBM_SE4_PERFCOUNTER_LO"
7415  },
7416  {
7417   "chips": ["gfx11"],
7418   "map": {"at": 213304, "to": "mm"},
7419   "name": "GRBM_SE4_PERFCOUNTER_HI"
7420  },
7421  {
7422   "chips": ["gfx11"],
7423   "map": {"at": 213308, "to": "mm"},
7424   "name": "GRBM_SE5_PERFCOUNTER_LO"
7425  },
7426  {
7427   "chips": ["gfx11"],
7428   "map": {"at": 213312, "to": "mm"},
7429   "name": "GRBM_SE5_PERFCOUNTER_HI"
7430  },
7431  {
7432   "chips": ["gfx11"],
7433   "map": {"at": 213316, "to": "mm"},
7434   "name": "GRBM_SE6_PERFCOUNTER_LO"
7435  },
7436  {
7437   "chips": ["gfx11"],
7438   "map": {"at": 213320, "to": "mm"},
7439   "name": "GRBM_SE6_PERFCOUNTER_HI"
7440  },
7441  {
7442   "chips": ["gfx11"],
7443   "map": {"at": 213648, "to": "mm"},
7444   "name": "GE1_PERFCOUNTER0_LO"
7445  },
7446  {
7447   "chips": ["gfx11"],
7448   "map": {"at": 213652, "to": "mm"},
7449   "name": "GE1_PERFCOUNTER0_HI"
7450  },
7451  {
7452   "chips": ["gfx11"],
7453   "map": {"at": 213656, "to": "mm"},
7454   "name": "GE1_PERFCOUNTER1_LO"
7455  },
7456  {
7457   "chips": ["gfx11"],
7458   "map": {"at": 213660, "to": "mm"},
7459   "name": "GE1_PERFCOUNTER1_HI"
7460  },
7461  {
7462   "chips": ["gfx11"],
7463   "map": {"at": 213664, "to": "mm"},
7464   "name": "GE1_PERFCOUNTER2_LO"
7465  },
7466  {
7467   "chips": ["gfx11"],
7468   "map": {"at": 213668, "to": "mm"},
7469   "name": "GE1_PERFCOUNTER2_HI"
7470  },
7471  {
7472   "chips": ["gfx11"],
7473   "map": {"at": 213672, "to": "mm"},
7474   "name": "GE1_PERFCOUNTER3_LO"
7475  },
7476  {
7477   "chips": ["gfx11"],
7478   "map": {"at": 213676, "to": "mm"},
7479   "name": "GE1_PERFCOUNTER3_HI"
7480  },
7481  {
7482   "chips": ["gfx11"],
7483   "map": {"at": 213680, "to": "mm"},
7484   "name": "GE2_DIST_PERFCOUNTER0_LO"
7485  },
7486  {
7487   "chips": ["gfx11"],
7488   "map": {"at": 213684, "to": "mm"},
7489   "name": "GE2_DIST_PERFCOUNTER0_HI"
7490  },
7491  {
7492   "chips": ["gfx11"],
7493   "map": {"at": 213688, "to": "mm"},
7494   "name": "GE2_DIST_PERFCOUNTER1_LO"
7495  },
7496  {
7497   "chips": ["gfx11"],
7498   "map": {"at": 213692, "to": "mm"},
7499   "name": "GE2_DIST_PERFCOUNTER1_HI"
7500  },
7501  {
7502   "chips": ["gfx11"],
7503   "map": {"at": 213696, "to": "mm"},
7504   "name": "GE2_DIST_PERFCOUNTER2_LO"
7505  },
7506  {
7507   "chips": ["gfx11"],
7508   "map": {"at": 213700, "to": "mm"},
7509   "name": "GE2_DIST_PERFCOUNTER2_HI"
7510  },
7511  {
7512   "chips": ["gfx11"],
7513   "map": {"at": 213704, "to": "mm"},
7514   "name": "GE2_DIST_PERFCOUNTER3_LO"
7515  },
7516  {
7517   "chips": ["gfx11"],
7518   "map": {"at": 213708, "to": "mm"},
7519   "name": "GE2_DIST_PERFCOUNTER3_HI"
7520  },
7521  {
7522   "chips": ["gfx11"],
7523   "map": {"at": 213712, "to": "mm"},
7524   "name": "GE2_SE_PERFCOUNTER0_LO"
7525  },
7526  {
7527   "chips": ["gfx11"],
7528   "map": {"at": 213716, "to": "mm"},
7529   "name": "GE2_SE_PERFCOUNTER0_HI"
7530  },
7531  {
7532   "chips": ["gfx11"],
7533   "map": {"at": 213720, "to": "mm"},
7534   "name": "GE2_SE_PERFCOUNTER1_LO"
7535  },
7536  {
7537   "chips": ["gfx11"],
7538   "map": {"at": 213724, "to": "mm"},
7539   "name": "GE2_SE_PERFCOUNTER1_HI"
7540  },
7541  {
7542   "chips": ["gfx11"],
7543   "map": {"at": 213728, "to": "mm"},
7544   "name": "GE2_SE_PERFCOUNTER2_LO"
7545  },
7546  {
7547   "chips": ["gfx11"],
7548   "map": {"at": 213732, "to": "mm"},
7549   "name": "GE2_SE_PERFCOUNTER2_HI"
7550  },
7551  {
7552   "chips": ["gfx11"],
7553   "map": {"at": 213736, "to": "mm"},
7554   "name": "GE2_SE_PERFCOUNTER3_LO"
7555  },
7556  {
7557   "chips": ["gfx11"],
7558   "map": {"at": 213740, "to": "mm"},
7559   "name": "GE2_SE_PERFCOUNTER3_HI"
7560  },
7561  {
7562   "chips": ["gfx11"],
7563   "map": {"at": 214016, "to": "mm"},
7564   "name": "PA_SU_PERFCOUNTER0_LO"
7565  },
7566  {
7567   "chips": ["gfx11"],
7568   "map": {"at": 214020, "to": "mm"},
7569   "name": "PA_SU_PERFCOUNTER0_HI"
7570  },
7571  {
7572   "chips": ["gfx11"],
7573   "map": {"at": 214024, "to": "mm"},
7574   "name": "PA_SU_PERFCOUNTER1_LO"
7575  },
7576  {
7577   "chips": ["gfx11"],
7578   "map": {"at": 214028, "to": "mm"},
7579   "name": "PA_SU_PERFCOUNTER1_HI"
7580  },
7581  {
7582   "chips": ["gfx11"],
7583   "map": {"at": 214032, "to": "mm"},
7584   "name": "PA_SU_PERFCOUNTER2_LO"
7585  },
7586  {
7587   "chips": ["gfx11"],
7588   "map": {"at": 214036, "to": "mm"},
7589   "name": "PA_SU_PERFCOUNTER2_HI"
7590  },
7591  {
7592   "chips": ["gfx11"],
7593   "map": {"at": 214040, "to": "mm"},
7594   "name": "PA_SU_PERFCOUNTER3_LO"
7595  },
7596  {
7597   "chips": ["gfx11"],
7598   "map": {"at": 214044, "to": "mm"},
7599   "name": "PA_SU_PERFCOUNTER3_HI"
7600  },
7601  {
7602   "chips": ["gfx11"],
7603   "map": {"at": 214272, "to": "mm"},
7604   "name": "PA_SC_PERFCOUNTER0_LO"
7605  },
7606  {
7607   "chips": ["gfx11"],
7608   "map": {"at": 214276, "to": "mm"},
7609   "name": "PA_SC_PERFCOUNTER0_HI"
7610  },
7611  {
7612   "chips": ["gfx11"],
7613   "map": {"at": 214280, "to": "mm"},
7614   "name": "PA_SC_PERFCOUNTER1_LO"
7615  },
7616  {
7617   "chips": ["gfx11"],
7618   "map": {"at": 214284, "to": "mm"},
7619   "name": "PA_SC_PERFCOUNTER1_HI"
7620  },
7621  {
7622   "chips": ["gfx11"],
7623   "map": {"at": 214288, "to": "mm"},
7624   "name": "PA_SC_PERFCOUNTER2_LO"
7625  },
7626  {
7627   "chips": ["gfx11"],
7628   "map": {"at": 214292, "to": "mm"},
7629   "name": "PA_SC_PERFCOUNTER2_HI"
7630  },
7631  {
7632   "chips": ["gfx11"],
7633   "map": {"at": 214296, "to": "mm"},
7634   "name": "PA_SC_PERFCOUNTER3_LO"
7635  },
7636  {
7637   "chips": ["gfx11"],
7638   "map": {"at": 214300, "to": "mm"},
7639   "name": "PA_SC_PERFCOUNTER3_HI"
7640  },
7641  {
7642   "chips": ["gfx11"],
7643   "map": {"at": 214304, "to": "mm"},
7644   "name": "PA_SC_PERFCOUNTER4_LO"
7645  },
7646  {
7647   "chips": ["gfx11"],
7648   "map": {"at": 214308, "to": "mm"},
7649   "name": "PA_SC_PERFCOUNTER4_HI"
7650  },
7651  {
7652   "chips": ["gfx11"],
7653   "map": {"at": 214312, "to": "mm"},
7654   "name": "PA_SC_PERFCOUNTER5_LO"
7655  },
7656  {
7657   "chips": ["gfx11"],
7658   "map": {"at": 214316, "to": "mm"},
7659   "name": "PA_SC_PERFCOUNTER5_HI"
7660  },
7661  {
7662   "chips": ["gfx11"],
7663   "map": {"at": 214320, "to": "mm"},
7664   "name": "PA_SC_PERFCOUNTER6_LO"
7665  },
7666  {
7667   "chips": ["gfx11"],
7668   "map": {"at": 214324, "to": "mm"},
7669   "name": "PA_SC_PERFCOUNTER6_HI"
7670  },
7671  {
7672   "chips": ["gfx11"],
7673   "map": {"at": 214328, "to": "mm"},
7674   "name": "PA_SC_PERFCOUNTER7_LO"
7675  },
7676  {
7677   "chips": ["gfx11"],
7678   "map": {"at": 214332, "to": "mm"},
7679   "name": "PA_SC_PERFCOUNTER7_HI"
7680  },
7681  {
7682   "chips": ["gfx11"],
7683   "map": {"at": 214528, "to": "mm"},
7684   "name": "SPI_PERFCOUNTER0_HI"
7685  },
7686  {
7687   "chips": ["gfx11"],
7688   "map": {"at": 214532, "to": "mm"},
7689   "name": "SPI_PERFCOUNTER0_LO"
7690  },
7691  {
7692   "chips": ["gfx11"],
7693   "map": {"at": 214536, "to": "mm"},
7694   "name": "SPI_PERFCOUNTER1_HI"
7695  },
7696  {
7697   "chips": ["gfx11"],
7698   "map": {"at": 214540, "to": "mm"},
7699   "name": "SPI_PERFCOUNTER1_LO"
7700  },
7701  {
7702   "chips": ["gfx11"],
7703   "map": {"at": 214544, "to": "mm"},
7704   "name": "SPI_PERFCOUNTER2_HI"
7705  },
7706  {
7707   "chips": ["gfx11"],
7708   "map": {"at": 214548, "to": "mm"},
7709   "name": "SPI_PERFCOUNTER2_LO"
7710  },
7711  {
7712   "chips": ["gfx11"],
7713   "map": {"at": 214552, "to": "mm"},
7714   "name": "SPI_PERFCOUNTER3_HI"
7715  },
7716  {
7717   "chips": ["gfx11"],
7718   "map": {"at": 214556, "to": "mm"},
7719   "name": "SPI_PERFCOUNTER3_LO"
7720  },
7721  {
7722   "chips": ["gfx11"],
7723   "map": {"at": 214560, "to": "mm"},
7724   "name": "SPI_PERFCOUNTER4_HI"
7725  },
7726  {
7727   "chips": ["gfx11"],
7728   "map": {"at": 214564, "to": "mm"},
7729   "name": "SPI_PERFCOUNTER4_LO"
7730  },
7731  {
7732   "chips": ["gfx11"],
7733   "map": {"at": 214568, "to": "mm"},
7734   "name": "SPI_PERFCOUNTER5_HI"
7735  },
7736  {
7737   "chips": ["gfx11"],
7738   "map": {"at": 214572, "to": "mm"},
7739   "name": "SPI_PERFCOUNTER5_LO"
7740  },
7741  {
7742   "chips": ["gfx11"],
7743   "map": {"at": 214576, "to": "mm"},
7744   "name": "PC_PERFCOUNTER0_HI"
7745  },
7746  {
7747   "chips": ["gfx11"],
7748   "map": {"at": 214580, "to": "mm"},
7749   "name": "PC_PERFCOUNTER0_LO"
7750  },
7751  {
7752   "chips": ["gfx11"],
7753   "map": {"at": 214584, "to": "mm"},
7754   "name": "PC_PERFCOUNTER1_HI"
7755  },
7756  {
7757   "chips": ["gfx11"],
7758   "map": {"at": 214588, "to": "mm"},
7759   "name": "PC_PERFCOUNTER1_LO"
7760  },
7761  {
7762   "chips": ["gfx11"],
7763   "map": {"at": 214592, "to": "mm"},
7764   "name": "PC_PERFCOUNTER2_HI"
7765  },
7766  {
7767   "chips": ["gfx11"],
7768   "map": {"at": 214596, "to": "mm"},
7769   "name": "PC_PERFCOUNTER2_LO"
7770  },
7771  {
7772   "chips": ["gfx11"],
7773   "map": {"at": 214600, "to": "mm"},
7774   "name": "PC_PERFCOUNTER3_HI"
7775  },
7776  {
7777   "chips": ["gfx11"],
7778   "map": {"at": 214604, "to": "mm"},
7779   "name": "PC_PERFCOUNTER3_LO"
7780  },
7781  {
7782   "chips": ["gfx11"],
7783   "map": {"at": 214784, "to": "mm"},
7784   "name": "SQ_PERFCOUNTER0_LO"
7785  },
7786  {
7787   "chips": ["gfx11"],
7788   "map": {"at": 214792, "to": "mm"},
7789   "name": "SQ_PERFCOUNTER1_LO"
7790  },
7791  {
7792   "chips": ["gfx11"],
7793   "map": {"at": 214800, "to": "mm"},
7794   "name": "SQ_PERFCOUNTER2_LO"
7795  },
7796  {
7797   "chips": ["gfx11"],
7798   "map": {"at": 214808, "to": "mm"},
7799   "name": "SQ_PERFCOUNTER3_LO"
7800  },
7801  {
7802   "chips": ["gfx11"],
7803   "map": {"at": 214816, "to": "mm"},
7804   "name": "SQ_PERFCOUNTER4_LO"
7805  },
7806  {
7807   "chips": ["gfx11"],
7808   "map": {"at": 214824, "to": "mm"},
7809   "name": "SQ_PERFCOUNTER5_LO"
7810  },
7811  {
7812   "chips": ["gfx11"],
7813   "map": {"at": 214832, "to": "mm"},
7814   "name": "SQ_PERFCOUNTER6_LO"
7815  },
7816  {
7817   "chips": ["gfx11"],
7818   "map": {"at": 214840, "to": "mm"},
7819   "name": "SQ_PERFCOUNTER7_LO"
7820  },
7821  {
7822   "chips": ["gfx11"],
7823   "map": {"at": 214928, "to": "mm"},
7824   "name": "SQG_PERFCOUNTER0_LO"
7825  },
7826  {
7827   "chips": ["gfx11"],
7828   "map": {"at": 214932, "to": "mm"},
7829   "name": "SQG_PERFCOUNTER0_HI"
7830  },
7831  {
7832   "chips": ["gfx11"],
7833   "map": {"at": 214936, "to": "mm"},
7834   "name": "SQG_PERFCOUNTER1_LO"
7835  },
7836  {
7837   "chips": ["gfx11"],
7838   "map": {"at": 214940, "to": "mm"},
7839   "name": "SQG_PERFCOUNTER1_HI"
7840  },
7841  {
7842   "chips": ["gfx11"],
7843   "map": {"at": 214944, "to": "mm"},
7844   "name": "SQG_PERFCOUNTER2_LO"
7845  },
7846  {
7847   "chips": ["gfx11"],
7848   "map": {"at": 214948, "to": "mm"},
7849   "name": "SQG_PERFCOUNTER2_HI"
7850  },
7851  {
7852   "chips": ["gfx11"],
7853   "map": {"at": 214952, "to": "mm"},
7854   "name": "SQG_PERFCOUNTER3_LO"
7855  },
7856  {
7857   "chips": ["gfx11"],
7858   "map": {"at": 214956, "to": "mm"},
7859   "name": "SQG_PERFCOUNTER3_HI"
7860  },
7861  {
7862   "chips": ["gfx11"],
7863   "map": {"at": 214960, "to": "mm"},
7864   "name": "SQG_PERFCOUNTER4_LO"
7865  },
7866  {
7867   "chips": ["gfx11"],
7868   "map": {"at": 214964, "to": "mm"},
7869   "name": "SQG_PERFCOUNTER4_HI"
7870  },
7871  {
7872   "chips": ["gfx11"],
7873   "map": {"at": 214968, "to": "mm"},
7874   "name": "SQG_PERFCOUNTER5_LO"
7875  },
7876  {
7877   "chips": ["gfx11"],
7878   "map": {"at": 214972, "to": "mm"},
7879   "name": "SQG_PERFCOUNTER5_HI"
7880  },
7881  {
7882   "chips": ["gfx11"],
7883   "map": {"at": 214976, "to": "mm"},
7884   "name": "SQG_PERFCOUNTER6_LO"
7885  },
7886  {
7887   "chips": ["gfx11"],
7888   "map": {"at": 214980, "to": "mm"},
7889   "name": "SQG_PERFCOUNTER6_HI"
7890  },
7891  {
7892   "chips": ["gfx11"],
7893   "map": {"at": 214984, "to": "mm"},
7894   "name": "SQG_PERFCOUNTER7_LO"
7895  },
7896  {
7897   "chips": ["gfx11"],
7898   "map": {"at": 214988, "to": "mm"},
7899   "name": "SQG_PERFCOUNTER7_HI"
7900  },
7901  {
7902   "chips": ["gfx11"],
7903   "map": {"at": 215296, "to": "mm"},
7904   "name": "SX_PERFCOUNTER0_LO"
7905  },
7906  {
7907   "chips": ["gfx11"],
7908   "map": {"at": 215300, "to": "mm"},
7909   "name": "SX_PERFCOUNTER0_HI"
7910  },
7911  {
7912   "chips": ["gfx11"],
7913   "map": {"at": 215304, "to": "mm"},
7914   "name": "SX_PERFCOUNTER1_LO"
7915  },
7916  {
7917   "chips": ["gfx11"],
7918   "map": {"at": 215308, "to": "mm"},
7919   "name": "SX_PERFCOUNTER1_HI"
7920  },
7921  {
7922   "chips": ["gfx11"],
7923   "map": {"at": 215312, "to": "mm"},
7924   "name": "SX_PERFCOUNTER2_LO"
7925  },
7926  {
7927   "chips": ["gfx11"],
7928   "map": {"at": 215316, "to": "mm"},
7929   "name": "SX_PERFCOUNTER2_HI"
7930  },
7931  {
7932   "chips": ["gfx11"],
7933   "map": {"at": 215320, "to": "mm"},
7934   "name": "SX_PERFCOUNTER3_LO"
7935  },
7936  {
7937   "chips": ["gfx11"],
7938   "map": {"at": 215324, "to": "mm"},
7939   "name": "SX_PERFCOUNTER3_HI"
7940  },
7941  {
7942   "chips": ["gfx11"],
7943   "map": {"at": 215424, "to": "mm"},
7944   "name": "GCEA_PERFCOUNTER2_LO"
7945  },
7946  {
7947   "chips": ["gfx11"],
7948   "map": {"at": 215428, "to": "mm"},
7949   "name": "GCEA_PERFCOUNTER2_HI"
7950  },
7951  {
7952   "chips": ["gfx11"],
7953   "map": {"at": 215432, "to": "mm"},
7954   "name": "GCEA_PERFCOUNTER_LO"
7955  },
7956  {
7957   "chips": ["gfx11"],
7958   "map": {"at": 215436, "to": "mm"},
7959   "name": "GCEA_PERFCOUNTER_HI",
7960   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_HI"
7961  },
7962  {
7963   "chips": ["gfx11"],
7964   "map": {"at": 215552, "to": "mm"},
7965   "name": "GDS_PERFCOUNTER0_LO"
7966  },
7967  {
7968   "chips": ["gfx11"],
7969   "map": {"at": 215556, "to": "mm"},
7970   "name": "GDS_PERFCOUNTER0_HI"
7971  },
7972  {
7973   "chips": ["gfx11"],
7974   "map": {"at": 215560, "to": "mm"},
7975   "name": "GDS_PERFCOUNTER1_LO"
7976  },
7977  {
7978   "chips": ["gfx11"],
7979   "map": {"at": 215564, "to": "mm"},
7980   "name": "GDS_PERFCOUNTER1_HI"
7981  },
7982  {
7983   "chips": ["gfx11"],
7984   "map": {"at": 215568, "to": "mm"},
7985   "name": "GDS_PERFCOUNTER2_LO"
7986  },
7987  {
7988   "chips": ["gfx11"],
7989   "map": {"at": 215572, "to": "mm"},
7990   "name": "GDS_PERFCOUNTER2_HI"
7991  },
7992  {
7993   "chips": ["gfx11"],
7994   "map": {"at": 215576, "to": "mm"},
7995   "name": "GDS_PERFCOUNTER3_LO"
7996  },
7997  {
7998   "chips": ["gfx11"],
7999   "map": {"at": 215580, "to": "mm"},
8000   "name": "GDS_PERFCOUNTER3_HI"
8001  },
8002  {
8003   "chips": ["gfx11"],
8004   "map": {"at": 215808, "to": "mm"},
8005   "name": "TA_PERFCOUNTER0_LO"
8006  },
8007  {
8008   "chips": ["gfx11"],
8009   "map": {"at": 215812, "to": "mm"},
8010   "name": "TA_PERFCOUNTER0_HI"
8011  },
8012  {
8013   "chips": ["gfx11"],
8014   "map": {"at": 215816, "to": "mm"},
8015   "name": "TA_PERFCOUNTER1_LO"
8016  },
8017  {
8018   "chips": ["gfx11"],
8019   "map": {"at": 215820, "to": "mm"},
8020   "name": "TA_PERFCOUNTER1_HI"
8021  },
8022  {
8023   "chips": ["gfx11"],
8024   "map": {"at": 216064, "to": "mm"},
8025   "name": "TD_PERFCOUNTER0_LO"
8026  },
8027  {
8028   "chips": ["gfx11"],
8029   "map": {"at": 216068, "to": "mm"},
8030   "name": "TD_PERFCOUNTER0_HI"
8031  },
8032  {
8033   "chips": ["gfx11"],
8034   "map": {"at": 216072, "to": "mm"},
8035   "name": "TD_PERFCOUNTER1_LO"
8036  },
8037  {
8038   "chips": ["gfx11"],
8039   "map": {"at": 216076, "to": "mm"},
8040   "name": "TD_PERFCOUNTER1_HI"
8041  },
8042  {
8043   "chips": ["gfx11"],
8044   "map": {"at": 216320, "to": "mm"},
8045   "name": "TCP_PERFCOUNTER0_LO"
8046  },
8047  {
8048   "chips": ["gfx11"],
8049   "map": {"at": 216324, "to": "mm"},
8050   "name": "TCP_PERFCOUNTER0_HI"
8051  },
8052  {
8053   "chips": ["gfx11"],
8054   "map": {"at": 216328, "to": "mm"},
8055   "name": "TCP_PERFCOUNTER1_LO"
8056  },
8057  {
8058   "chips": ["gfx11"],
8059   "map": {"at": 216332, "to": "mm"},
8060   "name": "TCP_PERFCOUNTER1_HI"
8061  },
8062  {
8063   "chips": ["gfx11"],
8064   "map": {"at": 216336, "to": "mm"},
8065   "name": "TCP_PERFCOUNTER2_LO"
8066  },
8067  {
8068   "chips": ["gfx11"],
8069   "map": {"at": 216340, "to": "mm"},
8070   "name": "TCP_PERFCOUNTER2_HI"
8071  },
8072  {
8073   "chips": ["gfx11"],
8074   "map": {"at": 216344, "to": "mm"},
8075   "name": "TCP_PERFCOUNTER3_LO"
8076  },
8077  {
8078   "chips": ["gfx11"],
8079   "map": {"at": 216348, "to": "mm"},
8080   "name": "TCP_PERFCOUNTER3_HI"
8081  },
8082  {
8083   "chips": ["gfx11"],
8084   "map": {"at": 216352, "to": "mm"},
8085   "name": "TCP_PERFCOUNTER_FILTER",
8086   "type_ref": "TCP_PERFCOUNTER_FILTER"
8087  },
8088  {
8089   "chips": ["gfx11"],
8090   "map": {"at": 216356, "to": "mm"},
8091   "name": "TCP_PERFCOUNTER_FILTER2",
8092   "type_ref": "TCP_PERFCOUNTER_FILTER2"
8093  },
8094  {
8095   "chips": ["gfx11"],
8096   "map": {"at": 216360, "to": "mm"},
8097   "name": "TCP_PERFCOUNTER_FILTER_EN",
8098   "type_ref": "TCP_PERFCOUNTER_FILTER_EN"
8099  },
8100  {
8101   "chips": ["gfx11"],
8102   "map": {"at": 216576, "to": "mm"},
8103   "name": "GL2C_PERFCOUNTER0_LO"
8104  },
8105  {
8106   "chips": ["gfx11"],
8107   "map": {"at": 216580, "to": "mm"},
8108   "name": "GL2C_PERFCOUNTER0_HI"
8109  },
8110  {
8111   "chips": ["gfx11"],
8112   "map": {"at": 216584, "to": "mm"},
8113   "name": "GL2C_PERFCOUNTER1_LO"
8114  },
8115  {
8116   "chips": ["gfx11"],
8117   "map": {"at": 216588, "to": "mm"},
8118   "name": "GL2C_PERFCOUNTER1_HI"
8119  },
8120  {
8121   "chips": ["gfx11"],
8122   "map": {"at": 216592, "to": "mm"},
8123   "name": "GL2C_PERFCOUNTER2_LO"
8124  },
8125  {
8126   "chips": ["gfx11"],
8127   "map": {"at": 216596, "to": "mm"},
8128   "name": "GL2C_PERFCOUNTER2_HI"
8129  },
8130  {
8131   "chips": ["gfx11"],
8132   "map": {"at": 216600, "to": "mm"},
8133   "name": "GL2C_PERFCOUNTER3_LO"
8134  },
8135  {
8136   "chips": ["gfx11"],
8137   "map": {"at": 216604, "to": "mm"},
8138   "name": "GL2C_PERFCOUNTER3_HI"
8139  },
8140  {
8141   "chips": ["gfx11"],
8142   "map": {"at": 216640, "to": "mm"},
8143   "name": "GL2A_PERFCOUNTER0_LO"
8144  },
8145  {
8146   "chips": ["gfx11"],
8147   "map": {"at": 216644, "to": "mm"},
8148   "name": "GL2A_PERFCOUNTER0_HI"
8149  },
8150  {
8151   "chips": ["gfx11"],
8152   "map": {"at": 216648, "to": "mm"},
8153   "name": "GL2A_PERFCOUNTER1_LO"
8154  },
8155  {
8156   "chips": ["gfx11"],
8157   "map": {"at": 216652, "to": "mm"},
8158   "name": "GL2A_PERFCOUNTER1_HI"
8159  },
8160  {
8161   "chips": ["gfx11"],
8162   "map": {"at": 216656, "to": "mm"},
8163   "name": "GL2A_PERFCOUNTER2_LO"
8164  },
8165  {
8166   "chips": ["gfx11"],
8167   "map": {"at": 216660, "to": "mm"},
8168   "name": "GL2A_PERFCOUNTER2_HI"
8169  },
8170  {
8171   "chips": ["gfx11"],
8172   "map": {"at": 216664, "to": "mm"},
8173   "name": "GL2A_PERFCOUNTER3_LO"
8174  },
8175  {
8176   "chips": ["gfx11"],
8177   "map": {"at": 216668, "to": "mm"},
8178   "name": "GL2A_PERFCOUNTER3_HI"
8179  },
8180  {
8181   "chips": ["gfx11"],
8182   "map": {"at": 216704, "to": "mm"},
8183   "name": "GL1C_PERFCOUNTER0_LO"
8184  },
8185  {
8186   "chips": ["gfx11"],
8187   "map": {"at": 216708, "to": "mm"},
8188   "name": "GL1C_PERFCOUNTER0_HI"
8189  },
8190  {
8191   "chips": ["gfx11"],
8192   "map": {"at": 216712, "to": "mm"},
8193   "name": "GL1C_PERFCOUNTER1_LO"
8194  },
8195  {
8196   "chips": ["gfx11"],
8197   "map": {"at": 216716, "to": "mm"},
8198   "name": "GL1C_PERFCOUNTER1_HI"
8199  },
8200  {
8201   "chips": ["gfx11"],
8202   "map": {"at": 216720, "to": "mm"},
8203   "name": "GL1C_PERFCOUNTER2_LO"
8204  },
8205  {
8206   "chips": ["gfx11"],
8207   "map": {"at": 216724, "to": "mm"},
8208   "name": "GL1C_PERFCOUNTER2_HI"
8209  },
8210  {
8211   "chips": ["gfx11"],
8212   "map": {"at": 216728, "to": "mm"},
8213   "name": "GL1C_PERFCOUNTER3_LO"
8214  },
8215  {
8216   "chips": ["gfx11"],
8217   "map": {"at": 216732, "to": "mm"},
8218   "name": "GL1C_PERFCOUNTER3_HI"
8219  },
8220  {
8221   "chips": ["gfx11"],
8222   "map": {"at": 216832, "to": "mm"},
8223   "name": "CHC_PERFCOUNTER0_LO"
8224  },
8225  {
8226   "chips": ["gfx11"],
8227   "map": {"at": 216836, "to": "mm"},
8228   "name": "CHC_PERFCOUNTER0_HI"
8229  },
8230  {
8231   "chips": ["gfx11"],
8232   "map": {"at": 216840, "to": "mm"},
8233   "name": "CHC_PERFCOUNTER1_LO"
8234  },
8235  {
8236   "chips": ["gfx11"],
8237   "map": {"at": 216844, "to": "mm"},
8238   "name": "CHC_PERFCOUNTER1_HI"
8239  },
8240  {
8241   "chips": ["gfx11"],
8242   "map": {"at": 216848, "to": "mm"},
8243   "name": "CHC_PERFCOUNTER2_LO"
8244  },
8245  {
8246   "chips": ["gfx11"],
8247   "map": {"at": 216852, "to": "mm"},
8248   "name": "CHC_PERFCOUNTER2_HI"
8249  },
8250  {
8251   "chips": ["gfx11"],
8252   "map": {"at": 216856, "to": "mm"},
8253   "name": "CHC_PERFCOUNTER3_LO"
8254  },
8255  {
8256   "chips": ["gfx11"],
8257   "map": {"at": 216860, "to": "mm"},
8258   "name": "CHC_PERFCOUNTER3_HI"
8259  },
8260  {
8261   "chips": ["gfx11"],
8262   "map": {"at": 216864, "to": "mm"},
8263   "name": "CHCG_PERFCOUNTER0_LO"
8264  },
8265  {
8266   "chips": ["gfx11"],
8267   "map": {"at": 216868, "to": "mm"},
8268   "name": "CHCG_PERFCOUNTER0_HI"
8269  },
8270  {
8271   "chips": ["gfx11"],
8272   "map": {"at": 216872, "to": "mm"},
8273   "name": "CHCG_PERFCOUNTER1_LO"
8274  },
8275  {
8276   "chips": ["gfx11"],
8277   "map": {"at": 216876, "to": "mm"},
8278   "name": "CHCG_PERFCOUNTER1_HI"
8279  },
8280  {
8281   "chips": ["gfx11"],
8282   "map": {"at": 216880, "to": "mm"},
8283   "name": "CHCG_PERFCOUNTER2_LO"
8284  },
8285  {
8286   "chips": ["gfx11"],
8287   "map": {"at": 216884, "to": "mm"},
8288   "name": "CHCG_PERFCOUNTER2_HI"
8289  },
8290  {
8291   "chips": ["gfx11"],
8292   "map": {"at": 216888, "to": "mm"},
8293   "name": "CHCG_PERFCOUNTER3_LO"
8294  },
8295  {
8296   "chips": ["gfx11"],
8297   "map": {"at": 216892, "to": "mm"},
8298   "name": "CHCG_PERFCOUNTER3_HI"
8299  },
8300  {
8301   "chips": ["gfx11"],
8302   "map": {"at": 217112, "to": "mm"},
8303   "name": "CB_PERFCOUNTER0_LO"
8304  },
8305  {
8306   "chips": ["gfx11"],
8307   "map": {"at": 217116, "to": "mm"},
8308   "name": "CB_PERFCOUNTER0_HI"
8309  },
8310  {
8311   "chips": ["gfx11"],
8312   "map": {"at": 217120, "to": "mm"},
8313   "name": "CB_PERFCOUNTER1_LO"
8314  },
8315  {
8316   "chips": ["gfx11"],
8317   "map": {"at": 217124, "to": "mm"},
8318   "name": "CB_PERFCOUNTER1_HI"
8319  },
8320  {
8321   "chips": ["gfx11"],
8322   "map": {"at": 217128, "to": "mm"},
8323   "name": "CB_PERFCOUNTER2_LO"
8324  },
8325  {
8326   "chips": ["gfx11"],
8327   "map": {"at": 217132, "to": "mm"},
8328   "name": "CB_PERFCOUNTER2_HI"
8329  },
8330  {
8331   "chips": ["gfx11"],
8332   "map": {"at": 217136, "to": "mm"},
8333   "name": "CB_PERFCOUNTER3_LO"
8334  },
8335  {
8336   "chips": ["gfx11"],
8337   "map": {"at": 217140, "to": "mm"},
8338   "name": "CB_PERFCOUNTER3_HI"
8339  },
8340  {
8341   "chips": ["gfx11"],
8342   "map": {"at": 217344, "to": "mm"},
8343   "name": "DB_PERFCOUNTER0_LO"
8344  },
8345  {
8346   "chips": ["gfx11"],
8347   "map": {"at": 217348, "to": "mm"},
8348   "name": "DB_PERFCOUNTER0_HI"
8349  },
8350  {
8351   "chips": ["gfx11"],
8352   "map": {"at": 217352, "to": "mm"},
8353   "name": "DB_PERFCOUNTER1_LO"
8354  },
8355  {
8356   "chips": ["gfx11"],
8357   "map": {"at": 217356, "to": "mm"},
8358   "name": "DB_PERFCOUNTER1_HI"
8359  },
8360  {
8361   "chips": ["gfx11"],
8362   "map": {"at": 217360, "to": "mm"},
8363   "name": "DB_PERFCOUNTER2_LO"
8364  },
8365  {
8366   "chips": ["gfx11"],
8367   "map": {"at": 217364, "to": "mm"},
8368   "name": "DB_PERFCOUNTER2_HI"
8369  },
8370  {
8371   "chips": ["gfx11"],
8372   "map": {"at": 217368, "to": "mm"},
8373   "name": "DB_PERFCOUNTER3_LO"
8374  },
8375  {
8376   "chips": ["gfx11"],
8377   "map": {"at": 217372, "to": "mm"},
8378   "name": "DB_PERFCOUNTER3_HI"
8379  },
8380  {
8381   "chips": ["gfx11"],
8382   "map": {"at": 217600, "to": "mm"},
8383   "name": "RLC_PERFCOUNTER0_LO"
8384  },
8385  {
8386   "chips": ["gfx11"],
8387   "map": {"at": 217604, "to": "mm"},
8388   "name": "RLC_PERFCOUNTER0_HI"
8389  },
8390  {
8391   "chips": ["gfx11"],
8392   "map": {"at": 217608, "to": "mm"},
8393   "name": "RLC_PERFCOUNTER1_LO"
8394  },
8395  {
8396   "chips": ["gfx11"],
8397   "map": {"at": 217612, "to": "mm"},
8398   "name": "RLC_PERFCOUNTER1_HI"
8399  },
8400  {
8401   "chips": ["gfx11"],
8402   "map": {"at": 217856, "to": "mm"},
8403   "name": "RMI_PERFCOUNTER0_LO"
8404  },
8405  {
8406   "chips": ["gfx11"],
8407   "map": {"at": 217860, "to": "mm"},
8408   "name": "RMI_PERFCOUNTER0_HI"
8409  },
8410  {
8411   "chips": ["gfx11"],
8412   "map": {"at": 217864, "to": "mm"},
8413   "name": "RMI_PERFCOUNTER1_LO"
8414  },
8415  {
8416   "chips": ["gfx11"],
8417   "map": {"at": 217868, "to": "mm"},
8418   "name": "RMI_PERFCOUNTER1_HI"
8419  },
8420  {
8421   "chips": ["gfx11"],
8422   "map": {"at": 217872, "to": "mm"},
8423   "name": "RMI_PERFCOUNTER2_LO"
8424  },
8425  {
8426   "chips": ["gfx11"],
8427   "map": {"at": 217876, "to": "mm"},
8428   "name": "RMI_PERFCOUNTER2_HI"
8429  },
8430  {
8431   "chips": ["gfx11"],
8432   "map": {"at": 217880, "to": "mm"},
8433   "name": "RMI_PERFCOUNTER3_LO"
8434  },
8435  {
8436   "chips": ["gfx11"],
8437   "map": {"at": 217884, "to": "mm"},
8438   "name": "RMI_PERFCOUNTER3_HI"
8439  },
8440  {
8441   "chips": ["gfx11"],
8442   "map": {"at": 217984, "to": "mm"},
8443   "name": "GCVML2_PERFCOUNTER2_0_LO"
8444  },
8445  {
8446   "chips": ["gfx11"],
8447   "map": {"at": 217988, "to": "mm"},
8448   "name": "GCVML2_PERFCOUNTER2_1_LO"
8449  },
8450  {
8451   "chips": ["gfx11"],
8452   "map": {"at": 217992, "to": "mm"},
8453   "name": "GCVML2_PERFCOUNTER2_0_HI"
8454  },
8455  {
8456   "chips": ["gfx11"],
8457   "map": {"at": 217996, "to": "mm"},
8458   "name": "GCVML2_PERFCOUNTER2_1_HI"
8459  },
8460  {
8461   "chips": ["gfx11"],
8462   "map": {"at": 218000, "to": "mm"},
8463   "name": "GCMC_VM_L2_PERFCOUNTER_LO"
8464  },
8465  {
8466   "chips": ["gfx11"],
8467   "map": {"at": 218004, "to": "mm"},
8468   "name": "GCMC_VM_L2_PERFCOUNTER_HI",
8469   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_HI"
8470  },
8471  {
8472   "chips": ["gfx11"],
8473   "map": {"at": 218008, "to": "mm"},
8474   "name": "GCUTCL2_PERFCOUNTER_LO"
8475  },
8476  {
8477   "chips": ["gfx11"],
8478   "map": {"at": 218012, "to": "mm"},
8479   "name": "GCUTCL2_PERFCOUNTER_HI",
8480   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_HI"
8481  },
8482  {
8483   "chips": ["gfx11"],
8484   "map": {"at": 218240, "to": "mm"},
8485   "name": "GCR_PERFCOUNTER0_LO"
8486  },
8487  {
8488   "chips": ["gfx11"],
8489   "map": {"at": 218244, "to": "mm"},
8490   "name": "GCR_PERFCOUNTER0_HI"
8491  },
8492  {
8493   "chips": ["gfx11"],
8494   "map": {"at": 218248, "to": "mm"},
8495   "name": "GCR_PERFCOUNTER1_LO"
8496  },
8497  {
8498   "chips": ["gfx11"],
8499   "map": {"at": 218252, "to": "mm"},
8500   "name": "GCR_PERFCOUNTER1_HI"
8501  },
8502  {
8503   "chips": ["gfx11"],
8504   "map": {"at": 218624, "to": "mm"},
8505   "name": "PA_PH_PERFCOUNTER0_LO"
8506  },
8507  {
8508   "chips": ["gfx11"],
8509   "map": {"at": 218628, "to": "mm"},
8510   "name": "PA_PH_PERFCOUNTER0_HI"
8511  },
8512  {
8513   "chips": ["gfx11"],
8514   "map": {"at": 218632, "to": "mm"},
8515   "name": "PA_PH_PERFCOUNTER1_LO"
8516  },
8517  {
8518   "chips": ["gfx11"],
8519   "map": {"at": 218636, "to": "mm"},
8520   "name": "PA_PH_PERFCOUNTER1_HI"
8521  },
8522  {
8523   "chips": ["gfx11"],
8524   "map": {"at": 218640, "to": "mm"},
8525   "name": "PA_PH_PERFCOUNTER2_LO"
8526  },
8527  {
8528   "chips": ["gfx11"],
8529   "map": {"at": 218644, "to": "mm"},
8530   "name": "PA_PH_PERFCOUNTER2_HI"
8531  },
8532  {
8533   "chips": ["gfx11"],
8534   "map": {"at": 218648, "to": "mm"},
8535   "name": "PA_PH_PERFCOUNTER3_LO"
8536  },
8537  {
8538   "chips": ["gfx11"],
8539   "map": {"at": 218652, "to": "mm"},
8540   "name": "PA_PH_PERFCOUNTER3_HI"
8541  },
8542  {
8543   "chips": ["gfx11"],
8544   "map": {"at": 218656, "to": "mm"},
8545   "name": "PA_PH_PERFCOUNTER4_LO"
8546  },
8547  {
8548   "chips": ["gfx11"],
8549   "map": {"at": 218660, "to": "mm"},
8550   "name": "PA_PH_PERFCOUNTER4_HI"
8551  },
8552  {
8553   "chips": ["gfx11"],
8554   "map": {"at": 218664, "to": "mm"},
8555   "name": "PA_PH_PERFCOUNTER5_LO"
8556  },
8557  {
8558   "chips": ["gfx11"],
8559   "map": {"at": 218668, "to": "mm"},
8560   "name": "PA_PH_PERFCOUNTER5_HI"
8561  },
8562  {
8563   "chips": ["gfx11"],
8564   "map": {"at": 218672, "to": "mm"},
8565   "name": "PA_PH_PERFCOUNTER6_LO"
8566  },
8567  {
8568   "chips": ["gfx11"],
8569   "map": {"at": 218676, "to": "mm"},
8570   "name": "PA_PH_PERFCOUNTER6_HI"
8571  },
8572  {
8573   "chips": ["gfx11"],
8574   "map": {"at": 218680, "to": "mm"},
8575   "name": "PA_PH_PERFCOUNTER7_LO"
8576  },
8577  {
8578   "chips": ["gfx11"],
8579   "map": {"at": 218684, "to": "mm"},
8580   "name": "PA_PH_PERFCOUNTER7_HI"
8581  },
8582  {
8583   "chips": ["gfx11"],
8584   "map": {"at": 218752, "to": "mm"},
8585   "name": "UTCL1_PERFCOUNTER0_LO"
8586  },
8587  {
8588   "chips": ["gfx11"],
8589   "map": {"at": 218756, "to": "mm"},
8590   "name": "UTCL1_PERFCOUNTER0_HI"
8591  },
8592  {
8593   "chips": ["gfx11"],
8594   "map": {"at": 218760, "to": "mm"},
8595   "name": "UTCL1_PERFCOUNTER1_LO"
8596  },
8597  {
8598   "chips": ["gfx11"],
8599   "map": {"at": 218764, "to": "mm"},
8600   "name": "UTCL1_PERFCOUNTER1_HI"
8601  },
8602  {
8603   "chips": ["gfx11"],
8604   "map": {"at": 218768, "to": "mm"},
8605   "name": "UTCL1_PERFCOUNTER2_LO"
8606  },
8607  {
8608   "chips": ["gfx11"],
8609   "map": {"at": 218772, "to": "mm"},
8610   "name": "UTCL1_PERFCOUNTER2_HI"
8611  },
8612  {
8613   "chips": ["gfx11"],
8614   "map": {"at": 218776, "to": "mm"},
8615   "name": "UTCL1_PERFCOUNTER3_LO"
8616  },
8617  {
8618   "chips": ["gfx11"],
8619   "map": {"at": 218780, "to": "mm"},
8620   "name": "UTCL1_PERFCOUNTER3_HI"
8621  },
8622  {
8623   "chips": ["gfx11"],
8624   "map": {"at": 218880, "to": "mm"},
8625   "name": "GL1A_PERFCOUNTER0_LO"
8626  },
8627  {
8628   "chips": ["gfx11"],
8629   "map": {"at": 218884, "to": "mm"},
8630   "name": "GL1A_PERFCOUNTER0_HI"
8631  },
8632  {
8633   "chips": ["gfx11"],
8634   "map": {"at": 218888, "to": "mm"},
8635   "name": "GL1A_PERFCOUNTER1_LO"
8636  },
8637  {
8638   "chips": ["gfx11"],
8639   "map": {"at": 218892, "to": "mm"},
8640   "name": "GL1A_PERFCOUNTER1_HI"
8641  },
8642  {
8643   "chips": ["gfx11"],
8644   "map": {"at": 218896, "to": "mm"},
8645   "name": "GL1A_PERFCOUNTER2_LO"
8646  },
8647  {
8648   "chips": ["gfx11"],
8649   "map": {"at": 218900, "to": "mm"},
8650   "name": "GL1A_PERFCOUNTER2_HI"
8651  },
8652  {
8653   "chips": ["gfx11"],
8654   "map": {"at": 218904, "to": "mm"},
8655   "name": "GL1A_PERFCOUNTER3_LO"
8656  },
8657  {
8658   "chips": ["gfx11"],
8659   "map": {"at": 218908, "to": "mm"},
8660   "name": "GL1A_PERFCOUNTER3_HI"
8661  },
8662  {
8663   "chips": ["gfx11"],
8664   "map": {"at": 218944, "to": "mm"},
8665   "name": "GL1H_PERFCOUNTER0_LO"
8666  },
8667  {
8668   "chips": ["gfx11"],
8669   "map": {"at": 218948, "to": "mm"},
8670   "name": "GL1H_PERFCOUNTER0_HI"
8671  },
8672  {
8673   "chips": ["gfx11"],
8674   "map": {"at": 218952, "to": "mm"},
8675   "name": "GL1H_PERFCOUNTER1_LO"
8676  },
8677  {
8678   "chips": ["gfx11"],
8679   "map": {"at": 218956, "to": "mm"},
8680   "name": "GL1H_PERFCOUNTER1_HI"
8681  },
8682  {
8683   "chips": ["gfx11"],
8684   "map": {"at": 218960, "to": "mm"},
8685   "name": "GL1H_PERFCOUNTER2_LO"
8686  },
8687  {
8688   "chips": ["gfx11"],
8689   "map": {"at": 218964, "to": "mm"},
8690   "name": "GL1H_PERFCOUNTER2_HI"
8691  },
8692  {
8693   "chips": ["gfx11"],
8694   "map": {"at": 218968, "to": "mm"},
8695   "name": "GL1H_PERFCOUNTER3_LO"
8696  },
8697  {
8698   "chips": ["gfx11"],
8699   "map": {"at": 218972, "to": "mm"},
8700   "name": "GL1H_PERFCOUNTER3_HI"
8701  },
8702  {
8703   "chips": ["gfx11"],
8704   "map": {"at": 219136, "to": "mm"},
8705   "name": "CHA_PERFCOUNTER0_LO"
8706  },
8707  {
8708   "chips": ["gfx11"],
8709   "map": {"at": 219140, "to": "mm"},
8710   "name": "CHA_PERFCOUNTER0_HI"
8711  },
8712  {
8713   "chips": ["gfx11"],
8714   "map": {"at": 219144, "to": "mm"},
8715   "name": "CHA_PERFCOUNTER1_LO"
8716  },
8717  {
8718   "chips": ["gfx11"],
8719   "map": {"at": 219148, "to": "mm"},
8720   "name": "CHA_PERFCOUNTER1_HI"
8721  },
8722  {
8723   "chips": ["gfx11"],
8724   "map": {"at": 219152, "to": "mm"},
8725   "name": "CHA_PERFCOUNTER2_LO"
8726  },
8727  {
8728   "chips": ["gfx11"],
8729   "map": {"at": 219156, "to": "mm"},
8730   "name": "CHA_PERFCOUNTER2_HI"
8731  },
8732  {
8733   "chips": ["gfx11"],
8734   "map": {"at": 219160, "to": "mm"},
8735   "name": "CHA_PERFCOUNTER3_LO"
8736  },
8737  {
8738   "chips": ["gfx11"],
8739   "map": {"at": 219164, "to": "mm"},
8740   "name": "CHA_PERFCOUNTER3_HI"
8741  },
8742  {
8743   "chips": ["gfx11"],
8744   "map": {"at": 219392, "to": "mm"},
8745   "name": "GUS_PERFCOUNTER2_LO"
8746  },
8747  {
8748   "chips": ["gfx11"],
8749   "map": {"at": 219396, "to": "mm"},
8750   "name": "GUS_PERFCOUNTER2_HI"
8751  },
8752  {
8753   "chips": ["gfx11"],
8754   "map": {"at": 219400, "to": "mm"},
8755   "name": "GUS_PERFCOUNTER_LO"
8756  },
8757  {
8758   "chips": ["gfx11"],
8759   "map": {"at": 219404, "to": "mm"},
8760   "name": "GUS_PERFCOUNTER_HI",
8761   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_HI"
8762  },
8763  {
8764   "chips": ["gfx11"],
8765   "map": {"at": 219520, "to": "mm"},
8766   "name": "SDMA0_PERFCNT_PERFCOUNTER_LO"
8767  },
8768  {
8769   "chips": ["gfx11"],
8770   "map": {"at": 219524, "to": "mm"},
8771   "name": "SDMA0_PERFCNT_PERFCOUNTER_HI",
8772   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_HI"
8773  },
8774  {
8775   "chips": ["gfx11"],
8776   "map": {"at": 219528, "to": "mm"},
8777   "name": "SDMA0_PERFCOUNTER0_LO"
8778  },
8779  {
8780   "chips": ["gfx11"],
8781   "map": {"at": 219532, "to": "mm"},
8782   "name": "SDMA0_PERFCOUNTER0_HI"
8783  },
8784  {
8785   "chips": ["gfx11"],
8786   "map": {"at": 219536, "to": "mm"},
8787   "name": "SDMA0_PERFCOUNTER1_LO"
8788  },
8789  {
8790   "chips": ["gfx11"],
8791   "map": {"at": 219540, "to": "mm"},
8792   "name": "SDMA0_PERFCOUNTER1_HI"
8793  },
8794  {
8795   "chips": ["gfx11"],
8796   "map": {"at": 219568, "to": "mm"},
8797   "name": "SDMA1_PERFCNT_PERFCOUNTER_LO"
8798  },
8799  {
8800   "chips": ["gfx11"],
8801   "map": {"at": 219572, "to": "mm"},
8802   "name": "SDMA1_PERFCNT_PERFCOUNTER_HI",
8803   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_HI"
8804  },
8805  {
8806   "chips": ["gfx11"],
8807   "map": {"at": 219576, "to": "mm"},
8808   "name": "SDMA1_PERFCOUNTER0_LO"
8809  },
8810  {
8811   "chips": ["gfx11"],
8812   "map": {"at": 219580, "to": "mm"},
8813   "name": "SDMA1_PERFCOUNTER0_HI"
8814  },
8815  {
8816   "chips": ["gfx11"],
8817   "map": {"at": 219584, "to": "mm"},
8818   "name": "SDMA1_PERFCOUNTER1_LO"
8819  },
8820  {
8821   "chips": ["gfx11"],
8822   "map": {"at": 219588, "to": "mm"},
8823   "name": "SDMA1_PERFCOUNTER1_HI"
8824  },
8825  {
8826   "chips": ["gfx11"],
8827   "map": {"at": 221184, "to": "mm"},
8828   "name": "CPG_PERFCOUNTER1_SELECT",
8829   "type_ref": "CPG_PERFCOUNTER1_SELECT"
8830  },
8831  {
8832   "chips": ["gfx11"],
8833   "map": {"at": 221188, "to": "mm"},
8834   "name": "CPG_PERFCOUNTER0_SELECT1",
8835   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
8836  },
8837  {
8838   "chips": ["gfx11"],
8839   "map": {"at": 221192, "to": "mm"},
8840   "name": "CPG_PERFCOUNTER0_SELECT",
8841   "type_ref": "CPG_PERFCOUNTER0_SELECT"
8842  },
8843  {
8844   "chips": ["gfx11"],
8845   "map": {"at": 221196, "to": "mm"},
8846   "name": "CPC_PERFCOUNTER1_SELECT",
8847   "type_ref": "CPG_PERFCOUNTER1_SELECT"
8848  },
8849  {
8850   "chips": ["gfx11"],
8851   "map": {"at": 221200, "to": "mm"},
8852   "name": "CPC_PERFCOUNTER0_SELECT1",
8853   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
8854  },
8855  {
8856   "chips": ["gfx11"],
8857   "map": {"at": 221204, "to": "mm"},
8858   "name": "CPF_PERFCOUNTER1_SELECT",
8859   "type_ref": "CPG_PERFCOUNTER1_SELECT"
8860  },
8861  {
8862   "chips": ["gfx11"],
8863   "map": {"at": 221208, "to": "mm"},
8864   "name": "CPF_PERFCOUNTER0_SELECT1",
8865   "type_ref": "CPG_PERFCOUNTER0_SELECT1"
8866  },
8867  {
8868   "chips": ["gfx11"],
8869   "map": {"at": 221212, "to": "mm"},
8870   "name": "CPF_PERFCOUNTER0_SELECT",
8871   "type_ref": "CPG_PERFCOUNTER0_SELECT"
8872  },
8873  {
8874   "chips": ["gfx11"],
8875   "map": {"at": 221216, "to": "mm"},
8876   "name": "CP_PERFMON_CNTL",
8877   "type_ref": "CP_PERFMON_CNTL"
8878  },
8879  {
8880   "chips": ["gfx11"],
8881   "map": {"at": 221220, "to": "mm"},
8882   "name": "CPC_PERFCOUNTER0_SELECT",
8883   "type_ref": "CPG_PERFCOUNTER0_SELECT"
8884  },
8885  {
8886   "chips": ["gfx11"],
8887   "map": {"at": 221224, "to": "mm"},
8888   "name": "CPF_TC_PERF_COUNTER_WINDOW_SELECT",
8889   "type_ref": "CPF_TC_PERF_COUNTER_WINDOW_SELECT"
8890  },
8891  {
8892   "chips": ["gfx11"],
8893   "map": {"at": 221228, "to": "mm"},
8894   "name": "CPG_TC_PERF_COUNTER_WINDOW_SELECT",
8895   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
8896  },
8897  {
8898   "chips": ["gfx11"],
8899   "map": {"at": 221232, "to": "mm"},
8900   "name": "CPF_LATENCY_STATS_SELECT",
8901   "type_ref": "CPF_LATENCY_STATS_SELECT"
8902  },
8903  {
8904   "chips": ["gfx11"],
8905   "map": {"at": 221236, "to": "mm"},
8906   "name": "CPG_LATENCY_STATS_SELECT",
8907   "type_ref": "CPG_LATENCY_STATS_SELECT"
8908  },
8909  {
8910   "chips": ["gfx11"],
8911   "map": {"at": 221240, "to": "mm"},
8912   "name": "CPC_LATENCY_STATS_SELECT",
8913   "type_ref": "CPF_LATENCY_STATS_SELECT"
8914  },
8915  {
8916   "chips": ["gfx11"],
8917   "map": {"at": 221244, "to": "mm"},
8918   "name": "CPC_TC_PERF_COUNTER_WINDOW_SELECT",
8919   "type_ref": "CPG_TC_PERF_COUNTER_WINDOW_SELECT"
8920  },
8921  {
8922   "chips": ["gfx11"],
8923   "map": {"at": 221248, "to": "mm"},
8924   "name": "CP_DRAW_OBJECT"
8925  },
8926  {
8927   "chips": ["gfx11"],
8928   "map": {"at": 221252, "to": "mm"},
8929   "name": "CP_DRAW_OBJECT_COUNTER",
8930   "type_ref": "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE"
8931  },
8932  {
8933   "chips": ["gfx11"],
8934   "map": {"at": 221256, "to": "mm"},
8935   "name": "CP_DRAW_WINDOW_MASK_HI"
8936  },
8937  {
8938   "chips": ["gfx11"],
8939   "map": {"at": 221260, "to": "mm"},
8940   "name": "CP_DRAW_WINDOW_HI"
8941  },
8942  {
8943   "chips": ["gfx11"],
8944   "map": {"at": 221264, "to": "mm"},
8945   "name": "CP_DRAW_WINDOW_LO",
8946   "type_ref": "CP_DRAW_WINDOW_LO"
8947  },
8948  {
8949   "chips": ["gfx11"],
8950   "map": {"at": 221268, "to": "mm"},
8951   "name": "CP_DRAW_WINDOW_CNTL",
8952   "type_ref": "CP_DRAW_WINDOW_CNTL"
8953  },
8954  {
8955   "chips": ["gfx11"],
8956   "map": {"at": 221440, "to": "mm"},
8957   "name": "GRBM_PERFCOUNTER0_SELECT",
8958   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
8959  },
8960  {
8961   "chips": ["gfx11"],
8962   "map": {"at": 221444, "to": "mm"},
8963   "name": "GRBM_PERFCOUNTER1_SELECT",
8964   "type_ref": "GRBM_PERFCOUNTER0_SELECT"
8965  },
8966  {
8967   "chips": ["gfx11"],
8968   "map": {"at": 221448, "to": "mm"},
8969   "name": "GRBM_SE0_PERFCOUNTER_SELECT",
8970   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8971  },
8972  {
8973   "chips": ["gfx11"],
8974   "map": {"at": 221452, "to": "mm"},
8975   "name": "GRBM_SE1_PERFCOUNTER_SELECT",
8976   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8977  },
8978  {
8979   "chips": ["gfx11"],
8980   "map": {"at": 221456, "to": "mm"},
8981   "name": "GRBM_SE2_PERFCOUNTER_SELECT",
8982   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8983  },
8984  {
8985   "chips": ["gfx11"],
8986   "map": {"at": 221460, "to": "mm"},
8987   "name": "GRBM_SE3_PERFCOUNTER_SELECT",
8988   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8989  },
8990  {
8991   "chips": ["gfx11"],
8992   "map": {"at": 221464, "to": "mm"},
8993   "name": "GRBM_SE4_PERFCOUNTER_SELECT",
8994   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
8995  },
8996  {
8997   "chips": ["gfx11"],
8998   "map": {"at": 221468, "to": "mm"},
8999   "name": "GRBM_SE5_PERFCOUNTER_SELECT",
9000   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9001  },
9002  {
9003   "chips": ["gfx11"],
9004   "map": {"at": 221472, "to": "mm"},
9005   "name": "GRBM_SE6_PERFCOUNTER_SELECT",
9006   "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT"
9007  },
9008  {
9009   "chips": ["gfx11"],
9010   "map": {"at": 221492, "to": "mm"},
9011   "name": "GRBM_PERFCOUNTER0_SELECT_HI",
9012   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
9013  },
9014  {
9015   "chips": ["gfx11"],
9016   "map": {"at": 221496, "to": "mm"},
9017   "name": "GRBM_PERFCOUNTER1_SELECT_HI",
9018   "type_ref": "GRBM_PERFCOUNTER0_SELECT_HI"
9019  },
9020  {
9021   "chips": ["gfx11"],
9022   "map": {"at": 221840, "to": "mm"},
9023   "name": "GE1_PERFCOUNTER0_SELECT",
9024   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9025  },
9026  {
9027   "chips": ["gfx11"],
9028   "map": {"at": 221844, "to": "mm"},
9029   "name": "GE1_PERFCOUNTER0_SELECT1",
9030   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9031  },
9032  {
9033   "chips": ["gfx11"],
9034   "map": {"at": 221848, "to": "mm"},
9035   "name": "GE1_PERFCOUNTER1_SELECT",
9036   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9037  },
9038  {
9039   "chips": ["gfx11"],
9040   "map": {"at": 221852, "to": "mm"},
9041   "name": "GE1_PERFCOUNTER1_SELECT1",
9042   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9043  },
9044  {
9045   "chips": ["gfx11"],
9046   "map": {"at": 221856, "to": "mm"},
9047   "name": "GE1_PERFCOUNTER2_SELECT",
9048   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9049  },
9050  {
9051   "chips": ["gfx11"],
9052   "map": {"at": 221860, "to": "mm"},
9053   "name": "GE1_PERFCOUNTER2_SELECT1",
9054   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9055  },
9056  {
9057   "chips": ["gfx11"],
9058   "map": {"at": 221864, "to": "mm"},
9059   "name": "GE1_PERFCOUNTER3_SELECT",
9060   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9061  },
9062  {
9063   "chips": ["gfx11"],
9064   "map": {"at": 221868, "to": "mm"},
9065   "name": "GE1_PERFCOUNTER3_SELECT1",
9066   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9067  },
9068  {
9069   "chips": ["gfx11"],
9070   "map": {"at": 221872, "to": "mm"},
9071   "name": "GE2_DIST_PERFCOUNTER0_SELECT",
9072   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9073  },
9074  {
9075   "chips": ["gfx11"],
9076   "map": {"at": 221876, "to": "mm"},
9077   "name": "GE2_DIST_PERFCOUNTER0_SELECT1",
9078   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9079  },
9080  {
9081   "chips": ["gfx11"],
9082   "map": {"at": 221880, "to": "mm"},
9083   "name": "GE2_DIST_PERFCOUNTER1_SELECT",
9084   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9085  },
9086  {
9087   "chips": ["gfx11"],
9088   "map": {"at": 221884, "to": "mm"},
9089   "name": "GE2_DIST_PERFCOUNTER1_SELECT1",
9090   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9091  },
9092  {
9093   "chips": ["gfx11"],
9094   "map": {"at": 221888, "to": "mm"},
9095   "name": "GE2_DIST_PERFCOUNTER2_SELECT",
9096   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9097  },
9098  {
9099   "chips": ["gfx11"],
9100   "map": {"at": 221892, "to": "mm"},
9101   "name": "GE2_DIST_PERFCOUNTER2_SELECT1",
9102   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9103  },
9104  {
9105   "chips": ["gfx11"],
9106   "map": {"at": 221896, "to": "mm"},
9107   "name": "GE2_DIST_PERFCOUNTER3_SELECT",
9108   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9109  },
9110  {
9111   "chips": ["gfx11"],
9112   "map": {"at": 221900, "to": "mm"},
9113   "name": "GE2_DIST_PERFCOUNTER3_SELECT1",
9114   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9115  },
9116  {
9117   "chips": ["gfx11"],
9118   "map": {"at": 221904, "to": "mm"},
9119   "name": "GE2_SE_PERFCOUNTER0_SELECT",
9120   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9121  },
9122  {
9123   "chips": ["gfx11"],
9124   "map": {"at": 221908, "to": "mm"},
9125   "name": "GE2_SE_PERFCOUNTER0_SELECT1",
9126   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9127  },
9128  {
9129   "chips": ["gfx11"],
9130   "map": {"at": 221912, "to": "mm"},
9131   "name": "GE2_SE_PERFCOUNTER1_SELECT",
9132   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9133  },
9134  {
9135   "chips": ["gfx11"],
9136   "map": {"at": 221916, "to": "mm"},
9137   "name": "GE2_SE_PERFCOUNTER1_SELECT1",
9138   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9139  },
9140  {
9141   "chips": ["gfx11"],
9142   "map": {"at": 221920, "to": "mm"},
9143   "name": "GE2_SE_PERFCOUNTER2_SELECT",
9144   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9145  },
9146  {
9147   "chips": ["gfx11"],
9148   "map": {"at": 221924, "to": "mm"},
9149   "name": "GE2_SE_PERFCOUNTER2_SELECT1",
9150   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9151  },
9152  {
9153   "chips": ["gfx11"],
9154   "map": {"at": 221928, "to": "mm"},
9155   "name": "GE2_SE_PERFCOUNTER3_SELECT",
9156   "type_ref": "GE1_PERFCOUNTER0_SELECT"
9157  },
9158  {
9159   "chips": ["gfx11"],
9160   "map": {"at": 221932, "to": "mm"},
9161   "name": "GE2_SE_PERFCOUNTER3_SELECT1",
9162   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9163  },
9164  {
9165   "chips": ["gfx11"],
9166   "map": {"at": 222208, "to": "mm"},
9167   "name": "PA_SU_PERFCOUNTER0_SELECT",
9168   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9169  },
9170  {
9171   "chips": ["gfx11"],
9172   "map": {"at": 222212, "to": "mm"},
9173   "name": "PA_SU_PERFCOUNTER0_SELECT1",
9174   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9175  },
9176  {
9177   "chips": ["gfx11"],
9178   "map": {"at": 222216, "to": "mm"},
9179   "name": "PA_SU_PERFCOUNTER1_SELECT",
9180   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9181  },
9182  {
9183   "chips": ["gfx11"],
9184   "map": {"at": 222220, "to": "mm"},
9185   "name": "PA_SU_PERFCOUNTER1_SELECT1",
9186   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9187  },
9188  {
9189   "chips": ["gfx11"],
9190   "map": {"at": 222224, "to": "mm"},
9191   "name": "PA_SU_PERFCOUNTER2_SELECT",
9192   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9193  },
9194  {
9195   "chips": ["gfx11"],
9196   "map": {"at": 222228, "to": "mm"},
9197   "name": "PA_SU_PERFCOUNTER2_SELECT1",
9198   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9199  },
9200  {
9201   "chips": ["gfx11"],
9202   "map": {"at": 222232, "to": "mm"},
9203   "name": "PA_SU_PERFCOUNTER3_SELECT",
9204   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9205  },
9206  {
9207   "chips": ["gfx11"],
9208   "map": {"at": 222236, "to": "mm"},
9209   "name": "PA_SU_PERFCOUNTER3_SELECT1",
9210   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9211  },
9212  {
9213   "chips": ["gfx11"],
9214   "map": {"at": 222464, "to": "mm"},
9215   "name": "PA_SC_PERFCOUNTER0_SELECT",
9216   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9217  },
9218  {
9219   "chips": ["gfx11"],
9220   "map": {"at": 222468, "to": "mm"},
9221   "name": "PA_SC_PERFCOUNTER0_SELECT1",
9222   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9223  },
9224  {
9225   "chips": ["gfx11"],
9226   "map": {"at": 222472, "to": "mm"},
9227   "name": "PA_SC_PERFCOUNTER1_SELECT",
9228   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9229  },
9230  {
9231   "chips": ["gfx11"],
9232   "map": {"at": 222476, "to": "mm"},
9233   "name": "PA_SC_PERFCOUNTER2_SELECT",
9234   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9235  },
9236  {
9237   "chips": ["gfx11"],
9238   "map": {"at": 222480, "to": "mm"},
9239   "name": "PA_SC_PERFCOUNTER3_SELECT",
9240   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9241  },
9242  {
9243   "chips": ["gfx11"],
9244   "map": {"at": 222484, "to": "mm"},
9245   "name": "PA_SC_PERFCOUNTER4_SELECT",
9246   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9247  },
9248  {
9249   "chips": ["gfx11"],
9250   "map": {"at": 222488, "to": "mm"},
9251   "name": "PA_SC_PERFCOUNTER5_SELECT",
9252   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9253  },
9254  {
9255   "chips": ["gfx11"],
9256   "map": {"at": 222492, "to": "mm"},
9257   "name": "PA_SC_PERFCOUNTER6_SELECT",
9258   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9259  },
9260  {
9261   "chips": ["gfx11"],
9262   "map": {"at": 222496, "to": "mm"},
9263   "name": "PA_SC_PERFCOUNTER7_SELECT",
9264   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9265  },
9266  {
9267   "chips": ["gfx11"],
9268   "map": {"at": 222720, "to": "mm"},
9269   "name": "SPI_PERFCOUNTER0_SELECT",
9270   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9271  },
9272  {
9273   "chips": ["gfx11"],
9274   "map": {"at": 222724, "to": "mm"},
9275   "name": "SPI_PERFCOUNTER1_SELECT",
9276   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9277  },
9278  {
9279   "chips": ["gfx11"],
9280   "map": {"at": 222728, "to": "mm"},
9281   "name": "SPI_PERFCOUNTER2_SELECT",
9282   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9283  },
9284  {
9285   "chips": ["gfx11"],
9286   "map": {"at": 222732, "to": "mm"},
9287   "name": "SPI_PERFCOUNTER3_SELECT",
9288   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9289  },
9290  {
9291   "chips": ["gfx11"],
9292   "map": {"at": 222736, "to": "mm"},
9293   "name": "SPI_PERFCOUNTER0_SELECT1",
9294   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9295  },
9296  {
9297   "chips": ["gfx11"],
9298   "map": {"at": 222740, "to": "mm"},
9299   "name": "SPI_PERFCOUNTER1_SELECT1",
9300   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9301  },
9302  {
9303   "chips": ["gfx11"],
9304   "map": {"at": 222744, "to": "mm"},
9305   "name": "SPI_PERFCOUNTER2_SELECT1",
9306   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9307  },
9308  {
9309   "chips": ["gfx11"],
9310   "map": {"at": 222748, "to": "mm"},
9311   "name": "SPI_PERFCOUNTER3_SELECT1",
9312   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9313  },
9314  {
9315   "chips": ["gfx11"],
9316   "map": {"at": 222752, "to": "mm"},
9317   "name": "SPI_PERFCOUNTER4_SELECT",
9318   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9319  },
9320  {
9321   "chips": ["gfx11"],
9322   "map": {"at": 222756, "to": "mm"},
9323   "name": "SPI_PERFCOUNTER5_SELECT",
9324   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
9325  },
9326  {
9327   "chips": ["gfx11"],
9328   "map": {"at": 222760, "to": "mm"},
9329   "name": "SPI_PERFCOUNTER_BINS",
9330   "type_ref": "SPI_PERFCOUNTER_BINS"
9331  },
9332  {
9333   "chips": ["gfx11"],
9334   "map": {"at": 222768, "to": "mm"},
9335   "name": "PC_PERFCOUNTER0_SELECT",
9336   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9337  },
9338  {
9339   "chips": ["gfx11"],
9340   "map": {"at": 222772, "to": "mm"},
9341   "name": "PC_PERFCOUNTER1_SELECT",
9342   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9343  },
9344  {
9345   "chips": ["gfx11"],
9346   "map": {"at": 222776, "to": "mm"},
9347   "name": "PC_PERFCOUNTER2_SELECT",
9348   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9349  },
9350  {
9351   "chips": ["gfx11"],
9352   "map": {"at": 222780, "to": "mm"},
9353   "name": "PC_PERFCOUNTER3_SELECT",
9354   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9355  },
9356  {
9357   "chips": ["gfx11"],
9358   "map": {"at": 222784, "to": "mm"},
9359   "name": "PC_PERFCOUNTER0_SELECT1",
9360   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9361  },
9362  {
9363   "chips": ["gfx11"],
9364   "map": {"at": 222788, "to": "mm"},
9365   "name": "PC_PERFCOUNTER1_SELECT1",
9366   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9367  },
9368  {
9369   "chips": ["gfx11"],
9370   "map": {"at": 222792, "to": "mm"},
9371   "name": "PC_PERFCOUNTER2_SELECT1",
9372   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9373  },
9374  {
9375   "chips": ["gfx11"],
9376   "map": {"at": 222796, "to": "mm"},
9377   "name": "PC_PERFCOUNTER3_SELECT1",
9378   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9379  },
9380  {
9381   "chips": ["gfx11"],
9382   "map": {"at": 222976, "to": "mm"},
9383   "name": "SQ_PERFCOUNTER0_SELECT",
9384   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9385  },
9386  {
9387   "chips": ["gfx11"],
9388   "map": {"at": 222980, "to": "mm"},
9389   "name": "SQ_PERFCOUNTER1_SELECT",
9390   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9391  },
9392  {
9393   "chips": ["gfx11"],
9394   "map": {"at": 222984, "to": "mm"},
9395   "name": "SQ_PERFCOUNTER2_SELECT",
9396   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9397  },
9398  {
9399   "chips": ["gfx11"],
9400   "map": {"at": 222988, "to": "mm"},
9401   "name": "SQ_PERFCOUNTER3_SELECT",
9402   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9403  },
9404  {
9405   "chips": ["gfx11"],
9406   "map": {"at": 222992, "to": "mm"},
9407   "name": "SQ_PERFCOUNTER4_SELECT",
9408   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9409  },
9410  {
9411   "chips": ["gfx11"],
9412   "map": {"at": 222996, "to": "mm"},
9413   "name": "SQ_PERFCOUNTER5_SELECT",
9414   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9415  },
9416  {
9417   "chips": ["gfx11"],
9418   "map": {"at": 223000, "to": "mm"},
9419   "name": "SQ_PERFCOUNTER6_SELECT",
9420   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9421  },
9422  {
9423   "chips": ["gfx11"],
9424   "map": {"at": 223004, "to": "mm"},
9425   "name": "SQ_PERFCOUNTER7_SELECT",
9426   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9427  },
9428  {
9429   "chips": ["gfx11"],
9430   "map": {"at": 223008, "to": "mm"},
9431   "name": "SQ_PERFCOUNTER8_SELECT",
9432   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9433  },
9434  {
9435   "chips": ["gfx11"],
9436   "map": {"at": 223012, "to": "mm"},
9437   "name": "SQ_PERFCOUNTER9_SELECT",
9438   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9439  },
9440  {
9441   "chips": ["gfx11"],
9442   "map": {"at": 223016, "to": "mm"},
9443   "name": "SQ_PERFCOUNTER10_SELECT",
9444   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9445  },
9446  {
9447   "chips": ["gfx11"],
9448   "map": {"at": 223020, "to": "mm"},
9449   "name": "SQ_PERFCOUNTER11_SELECT",
9450   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9451  },
9452  {
9453   "chips": ["gfx11"],
9454   "map": {"at": 223024, "to": "mm"},
9455   "name": "SQ_PERFCOUNTER12_SELECT",
9456   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9457  },
9458  {
9459   "chips": ["gfx11"],
9460   "map": {"at": 223028, "to": "mm"},
9461   "name": "SQ_PERFCOUNTER13_SELECT",
9462   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9463  },
9464  {
9465   "chips": ["gfx11"],
9466   "map": {"at": 223032, "to": "mm"},
9467   "name": "SQ_PERFCOUNTER14_SELECT",
9468   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9469  },
9470  {
9471   "chips": ["gfx11"],
9472   "map": {"at": 223036, "to": "mm"},
9473   "name": "SQ_PERFCOUNTER15_SELECT",
9474   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9475  },
9476  {
9477   "chips": ["gfx11"],
9478   "map": {"at": 223040, "to": "mm"},
9479   "name": "SQG_PERFCOUNTER0_SELECT",
9480   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9481  },
9482  {
9483   "chips": ["gfx11"],
9484   "map": {"at": 223044, "to": "mm"},
9485   "name": "SQG_PERFCOUNTER1_SELECT",
9486   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9487  },
9488  {
9489   "chips": ["gfx11"],
9490   "map": {"at": 223048, "to": "mm"},
9491   "name": "SQG_PERFCOUNTER2_SELECT",
9492   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9493  },
9494  {
9495   "chips": ["gfx11"],
9496   "map": {"at": 223052, "to": "mm"},
9497   "name": "SQG_PERFCOUNTER3_SELECT",
9498   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9499  },
9500  {
9501   "chips": ["gfx11"],
9502   "map": {"at": 223056, "to": "mm"},
9503   "name": "SQG_PERFCOUNTER4_SELECT",
9504   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9505  },
9506  {
9507   "chips": ["gfx11"],
9508   "map": {"at": 223060, "to": "mm"},
9509   "name": "SQG_PERFCOUNTER5_SELECT",
9510   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9511  },
9512  {
9513   "chips": ["gfx11"],
9514   "map": {"at": 223064, "to": "mm"},
9515   "name": "SQG_PERFCOUNTER6_SELECT",
9516   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9517  },
9518  {
9519   "chips": ["gfx11"],
9520   "map": {"at": 223068, "to": "mm"},
9521   "name": "SQG_PERFCOUNTER7_SELECT",
9522   "type_ref": "SQ_PERFCOUNTER0_SELECT"
9523  },
9524  {
9525   "chips": ["gfx11"],
9526   "map": {"at": 223072, "to": "mm"},
9527   "name": "SQG_PERFCOUNTER_CTRL",
9528   "type_ref": "SQG_PERFCOUNTER_CTRL"
9529  },
9530  {
9531   "chips": ["gfx11"],
9532   "map": {"at": 223080, "to": "mm"},
9533   "name": "SQG_PERFCOUNTER_CTRL2",
9534   "type_ref": "SQG_PERFCOUNTER_CTRL2"
9535  },
9536  {
9537   "chips": ["gfx11"],
9538   "map": {"at": 223084, "to": "mm"},
9539   "name": "SQG_PERF_SAMPLE_FINISH",
9540   "type_ref": "SQG_PERF_SAMPLE_FINISH"
9541  },
9542  {
9543   "chips": ["gfx11"],
9544   "map": {"at": 223104, "to": "mm"},
9545   "name": "SQ_PERFCOUNTER_CTRL",
9546   "type_ref": "SQG_PERFCOUNTER_CTRL"
9547  },
9548  {
9549   "chips": ["gfx11"],
9550   "map": {"at": 223112, "to": "mm"},
9551   "name": "SQ_PERFCOUNTER_CTRL2",
9552   "type_ref": "SQG_PERFCOUNTER_CTRL2"
9553  },
9554  {
9555   "chips": ["gfx11"],
9556   "map": {"at": 223136, "to": "mm"},
9557   "name": "SQ_THREAD_TRACE_BUF0_BASE"
9558  },
9559  {
9560   "chips": ["gfx11"],
9561   "map": {"at": 223140, "to": "mm"},
9562   "name": "SQ_THREAD_TRACE_BUF0_SIZE",
9563   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
9564  },
9565  {
9566   "chips": ["gfx11"],
9567   "map": {"at": 223144, "to": "mm"},
9568   "name": "SQ_THREAD_TRACE_BUF1_BASE"
9569  },
9570  {
9571   "chips": ["gfx11"],
9572   "map": {"at": 223148, "to": "mm"},
9573   "name": "SQ_THREAD_TRACE_BUF1_SIZE",
9574   "type_ref": "SQ_THREAD_TRACE_BUF0_SIZE"
9575  },
9576  {
9577   "chips": ["gfx11"],
9578   "map": {"at": 223152, "to": "mm"},
9579   "name": "SQ_THREAD_TRACE_CTRL",
9580   "type_ref": "SQ_THREAD_TRACE_CTRL"
9581  },
9582  {
9583   "chips": ["gfx11"],
9584   "map": {"at": 223156, "to": "mm"},
9585   "name": "SQ_THREAD_TRACE_MASK",
9586   "type_ref": "SQ_THREAD_TRACE_MASK"
9587  },
9588  {
9589   "chips": ["gfx11"],
9590   "map": {"at": 223160, "to": "mm"},
9591   "name": "SQ_THREAD_TRACE_TOKEN_MASK",
9592   "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK"
9593  },
9594  {
9595   "chips": ["gfx11"],
9596   "map": {"at": 223164, "to": "mm"},
9597   "name": "SQ_THREAD_TRACE_WPTR",
9598   "type_ref": "SQ_THREAD_TRACE_WPTR"
9599  },
9600  {
9601   "chips": ["gfx11"],
9602   "map": {"at": 223184, "to": "mm"},
9603   "name": "SQ_THREAD_TRACE_STATUS",
9604   "type_ref": "SQ_THREAD_TRACE_STATUS"
9605  },
9606  {
9607   "chips": ["gfx11"],
9608   "map": {"at": 223188, "to": "mm"},
9609   "name": "SQ_THREAD_TRACE_STATUS2",
9610   "type_ref": "SQ_THREAD_TRACE_STATUS2"
9611  },
9612  {
9613   "chips": ["gfx11"],
9614   "map": {"at": 223192, "to": "mm"},
9615   "name": "SQ_THREAD_TRACE_GFX_DRAW_CNTR"
9616  },
9617  {
9618   "chips": ["gfx11"],
9619   "map": {"at": 223196, "to": "mm"},
9620   "name": "SQ_THREAD_TRACE_GFX_MARKER_CNTR"
9621  },
9622  {
9623   "chips": ["gfx11"],
9624   "map": {"at": 223200, "to": "mm"},
9625   "name": "SQ_THREAD_TRACE_HP3D_DRAW_CNTR"
9626  },
9627  {
9628   "chips": ["gfx11"],
9629   "map": {"at": 223204, "to": "mm"},
9630   "name": "SQ_THREAD_TRACE_HP3D_MARKER_CNTR"
9631  },
9632  {
9633   "chips": ["gfx11"],
9634   "map": {"at": 223208, "to": "mm"},
9635   "name": "SQ_THREAD_TRACE_DROPPED_CNTR"
9636  },
9637  {
9638   "chips": ["gfx11"],
9639   "map": {"at": 223232, "to": "mm"},
9640   "name": "GCEA_PERFCOUNTER2_SELECT",
9641   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9642  },
9643  {
9644   "chips": ["gfx11"],
9645   "map": {"at": 223236, "to": "mm"},
9646   "name": "GCEA_PERFCOUNTER2_SELECT1",
9647   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9648  },
9649  {
9650   "chips": ["gfx11"],
9651   "map": {"at": 223240, "to": "mm"},
9652   "name": "GCEA_PERFCOUNTER2_MODE",
9653   "type_ref": "GCVML2_PERFCOUNTER2_0_MODE"
9654  },
9655  {
9656   "chips": ["gfx11"],
9657   "map": {"at": 223244, "to": "mm"},
9658   "name": "GCEA_PERFCOUNTER0_CFG",
9659   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
9660  },
9661  {
9662   "chips": ["gfx11"],
9663   "map": {"at": 223248, "to": "mm"},
9664   "name": "GCEA_PERFCOUNTER1_CFG",
9665   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
9666  },
9667  {
9668   "chips": ["gfx11"],
9669   "map": {"at": 223252, "to": "mm"},
9670   "name": "GCEA_PERFCOUNTER_RSLT_CNTL",
9671   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL"
9672  },
9673  {
9674   "chips": ["gfx11"],
9675   "map": {"at": 223488, "to": "mm"},
9676   "name": "SX_PERFCOUNTER0_SELECT",
9677   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9678  },
9679  {
9680   "chips": ["gfx11"],
9681   "map": {"at": 223492, "to": "mm"},
9682   "name": "SX_PERFCOUNTER1_SELECT",
9683   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9684  },
9685  {
9686   "chips": ["gfx11"],
9687   "map": {"at": 223496, "to": "mm"},
9688   "name": "SX_PERFCOUNTER2_SELECT",
9689   "type_ref": "SX_PERFCOUNTER2_SELECT"
9690  },
9691  {
9692   "chips": ["gfx11"],
9693   "map": {"at": 223500, "to": "mm"},
9694   "name": "SX_PERFCOUNTER3_SELECT",
9695   "type_ref": "SX_PERFCOUNTER2_SELECT"
9696  },
9697  {
9698   "chips": ["gfx11"],
9699   "map": {"at": 223504, "to": "mm"},
9700   "name": "SX_PERFCOUNTER0_SELECT1",
9701   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9702  },
9703  {
9704   "chips": ["gfx11"],
9705   "map": {"at": 223508, "to": "mm"},
9706   "name": "SX_PERFCOUNTER1_SELECT1",
9707   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9708  },
9709  {
9710   "chips": ["gfx11"],
9711   "map": {"at": 223744, "to": "mm"},
9712   "name": "GDS_PERFCOUNTER0_SELECT",
9713   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9714  },
9715  {
9716   "chips": ["gfx11"],
9717   "map": {"at": 223748, "to": "mm"},
9718   "name": "GDS_PERFCOUNTER1_SELECT",
9719   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9720  },
9721  {
9722   "chips": ["gfx11"],
9723   "map": {"at": 223752, "to": "mm"},
9724   "name": "GDS_PERFCOUNTER2_SELECT",
9725   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9726  },
9727  {
9728   "chips": ["gfx11"],
9729   "map": {"at": 223756, "to": "mm"},
9730   "name": "GDS_PERFCOUNTER3_SELECT",
9731   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9732  },
9733  {
9734   "chips": ["gfx11"],
9735   "map": {"at": 223760, "to": "mm"},
9736   "name": "GDS_PERFCOUNTER0_SELECT1",
9737   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9738  },
9739  {
9740   "chips": ["gfx11"],
9741   "map": {"at": 223764, "to": "mm"},
9742   "name": "GDS_PERFCOUNTER1_SELECT1",
9743   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9744  },
9745  {
9746   "chips": ["gfx11"],
9747   "map": {"at": 223768, "to": "mm"},
9748   "name": "GDS_PERFCOUNTER2_SELECT1",
9749   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9750  },
9751  {
9752   "chips": ["gfx11"],
9753   "map": {"at": 223772, "to": "mm"},
9754   "name": "GDS_PERFCOUNTER3_SELECT1",
9755   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9756  },
9757  {
9758   "chips": ["gfx11"],
9759   "map": {"at": 224000, "to": "mm"},
9760   "name": "TA_PERFCOUNTER0_SELECT",
9761   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9762  },
9763  {
9764   "chips": ["gfx11"],
9765   "map": {"at": 224004, "to": "mm"},
9766   "name": "TA_PERFCOUNTER0_SELECT1",
9767   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9768  },
9769  {
9770   "chips": ["gfx11"],
9771   "map": {"at": 224008, "to": "mm"},
9772   "name": "TA_PERFCOUNTER1_SELECT",
9773   "type_ref": "SX_PERFCOUNTER2_SELECT"
9774  },
9775  {
9776   "chips": ["gfx11"],
9777   "map": {"at": 224256, "to": "mm"},
9778   "name": "TD_PERFCOUNTER0_SELECT",
9779   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9780  },
9781  {
9782   "chips": ["gfx11"],
9783   "map": {"at": 224260, "to": "mm"},
9784   "name": "TD_PERFCOUNTER0_SELECT1",
9785   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9786  },
9787  {
9788   "chips": ["gfx11"],
9789   "map": {"at": 224264, "to": "mm"},
9790   "name": "TD_PERFCOUNTER1_SELECT",
9791   "type_ref": "SX_PERFCOUNTER2_SELECT"
9792  },
9793  {
9794   "chips": ["gfx11"],
9795   "map": {"at": 224512, "to": "mm"},
9796   "name": "TCP_PERFCOUNTER0_SELECT",
9797   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9798  },
9799  {
9800   "chips": ["gfx11"],
9801   "map": {"at": 224516, "to": "mm"},
9802   "name": "TCP_PERFCOUNTER0_SELECT1",
9803   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9804  },
9805  {
9806   "chips": ["gfx11"],
9807   "map": {"at": 224520, "to": "mm"},
9808   "name": "TCP_PERFCOUNTER1_SELECT",
9809   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9810  },
9811  {
9812   "chips": ["gfx11"],
9813   "map": {"at": 224524, "to": "mm"},
9814   "name": "TCP_PERFCOUNTER1_SELECT1",
9815   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
9816  },
9817  {
9818   "chips": ["gfx11"],
9819   "map": {"at": 224528, "to": "mm"},
9820   "name": "TCP_PERFCOUNTER2_SELECT",
9821   "type_ref": "SX_PERFCOUNTER2_SELECT"
9822  },
9823  {
9824   "chips": ["gfx11"],
9825   "map": {"at": 224532, "to": "mm"},
9826   "name": "TCP_PERFCOUNTER3_SELECT",
9827   "type_ref": "SX_PERFCOUNTER2_SELECT"
9828  },
9829  {
9830   "chips": ["gfx11"],
9831   "map": {"at": 224768, "to": "mm"},
9832   "name": "GL2C_PERFCOUNTER0_SELECT",
9833   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9834  },
9835  {
9836   "chips": ["gfx11"],
9837   "map": {"at": 224772, "to": "mm"},
9838   "name": "GL2C_PERFCOUNTER0_SELECT1",
9839   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9840  },
9841  {
9842   "chips": ["gfx11"],
9843   "map": {"at": 224776, "to": "mm"},
9844   "name": "GL2C_PERFCOUNTER1_SELECT",
9845   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9846  },
9847  {
9848   "chips": ["gfx11"],
9849   "map": {"at": 224780, "to": "mm"},
9850   "name": "GL2C_PERFCOUNTER1_SELECT1",
9851   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9852  },
9853  {
9854   "chips": ["gfx11"],
9855   "map": {"at": 224784, "to": "mm"},
9856   "name": "GL2C_PERFCOUNTER2_SELECT",
9857   "type_ref": "SX_PERFCOUNTER2_SELECT"
9858  },
9859  {
9860   "chips": ["gfx11"],
9861   "map": {"at": 224788, "to": "mm"},
9862   "name": "GL2C_PERFCOUNTER3_SELECT",
9863   "type_ref": "SX_PERFCOUNTER2_SELECT"
9864  },
9865  {
9866   "chips": ["gfx11"],
9867   "map": {"at": 224832, "to": "mm"},
9868   "name": "GL2A_PERFCOUNTER0_SELECT",
9869   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9870  },
9871  {
9872   "chips": ["gfx11"],
9873   "map": {"at": 224836, "to": "mm"},
9874   "name": "GL2A_PERFCOUNTER0_SELECT1",
9875   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9876  },
9877  {
9878   "chips": ["gfx11"],
9879   "map": {"at": 224840, "to": "mm"},
9880   "name": "GL2A_PERFCOUNTER1_SELECT",
9881   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9882  },
9883  {
9884   "chips": ["gfx11"],
9885   "map": {"at": 224844, "to": "mm"},
9886   "name": "GL2A_PERFCOUNTER1_SELECT1",
9887   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9888  },
9889  {
9890   "chips": ["gfx11"],
9891   "map": {"at": 224848, "to": "mm"},
9892   "name": "GL2A_PERFCOUNTER2_SELECT",
9893   "type_ref": "SX_PERFCOUNTER2_SELECT"
9894  },
9895  {
9896   "chips": ["gfx11"],
9897   "map": {"at": 224852, "to": "mm"},
9898   "name": "GL2A_PERFCOUNTER3_SELECT",
9899   "type_ref": "SX_PERFCOUNTER2_SELECT"
9900  },
9901  {
9902   "chips": ["gfx11"],
9903   "map": {"at": 224896, "to": "mm"},
9904   "name": "GL1C_PERFCOUNTER0_SELECT",
9905   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9906  },
9907  {
9908   "chips": ["gfx11"],
9909   "map": {"at": 224900, "to": "mm"},
9910   "name": "GL1C_PERFCOUNTER0_SELECT1",
9911   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9912  },
9913  {
9914   "chips": ["gfx11"],
9915   "map": {"at": 224904, "to": "mm"},
9916   "name": "GL1C_PERFCOUNTER1_SELECT",
9917   "type_ref": "SX_PERFCOUNTER2_SELECT"
9918  },
9919  {
9920   "chips": ["gfx11"],
9921   "map": {"at": 224908, "to": "mm"},
9922   "name": "GL1C_PERFCOUNTER2_SELECT",
9923   "type_ref": "SX_PERFCOUNTER2_SELECT"
9924  },
9925  {
9926   "chips": ["gfx11"],
9927   "map": {"at": 224912, "to": "mm"},
9928   "name": "GL1C_PERFCOUNTER3_SELECT",
9929   "type_ref": "SX_PERFCOUNTER2_SELECT"
9930  },
9931  {
9932   "chips": ["gfx11"],
9933   "map": {"at": 225024, "to": "mm"},
9934   "name": "CHC_PERFCOUNTER0_SELECT",
9935   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9936  },
9937  {
9938   "chips": ["gfx11"],
9939   "map": {"at": 225028, "to": "mm"},
9940   "name": "CHC_PERFCOUNTER0_SELECT1",
9941   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9942  },
9943  {
9944   "chips": ["gfx11"],
9945   "map": {"at": 225032, "to": "mm"},
9946   "name": "CHC_PERFCOUNTER1_SELECT",
9947   "type_ref": "SX_PERFCOUNTER2_SELECT"
9948  },
9949  {
9950   "chips": ["gfx11"],
9951   "map": {"at": 225036, "to": "mm"},
9952   "name": "CHC_PERFCOUNTER2_SELECT",
9953   "type_ref": "SX_PERFCOUNTER2_SELECT"
9954  },
9955  {
9956   "chips": ["gfx11"],
9957   "map": {"at": 225040, "to": "mm"},
9958   "name": "CHC_PERFCOUNTER3_SELECT",
9959   "type_ref": "SX_PERFCOUNTER2_SELECT"
9960  },
9961  {
9962   "chips": ["gfx11"],
9963   "map": {"at": 225048, "to": "mm"},
9964   "name": "CHCG_PERFCOUNTER0_SELECT",
9965   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
9966  },
9967  {
9968   "chips": ["gfx11"],
9969   "map": {"at": 225052, "to": "mm"},
9970   "name": "CHCG_PERFCOUNTER0_SELECT1",
9971   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
9972  },
9973  {
9974   "chips": ["gfx11"],
9975   "map": {"at": 225056, "to": "mm"},
9976   "name": "CHCG_PERFCOUNTER1_SELECT",
9977   "type_ref": "SX_PERFCOUNTER2_SELECT"
9978  },
9979  {
9980   "chips": ["gfx11"],
9981   "map": {"at": 225060, "to": "mm"},
9982   "name": "CHCG_PERFCOUNTER2_SELECT",
9983   "type_ref": "SX_PERFCOUNTER2_SELECT"
9984  },
9985  {
9986   "chips": ["gfx11"],
9987   "map": {"at": 225064, "to": "mm"},
9988   "name": "CHCG_PERFCOUNTER3_SELECT",
9989   "type_ref": "SX_PERFCOUNTER2_SELECT"
9990  },
9991  {
9992   "chips": ["gfx11"],
9993   "map": {"at": 225280, "to": "mm"},
9994   "name": "CB_PERFCOUNTER_FILTER",
9995   "type_ref": "CB_PERFCOUNTER_FILTER"
9996  },
9997  {
9998   "chips": ["gfx11"],
9999   "map": {"at": 225284, "to": "mm"},
10000   "name": "CB_PERFCOUNTER0_SELECT",
10001   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10002  },
10003  {
10004   "chips": ["gfx11"],
10005   "map": {"at": 225288, "to": "mm"},
10006   "name": "CB_PERFCOUNTER0_SELECT1",
10007   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10008  },
10009  {
10010   "chips": ["gfx11"],
10011   "map": {"at": 225292, "to": "mm"},
10012   "name": "CB_PERFCOUNTER1_SELECT",
10013   "type_ref": "CB_PERFCOUNTER1_SELECT"
10014  },
10015  {
10016   "chips": ["gfx11"],
10017   "map": {"at": 225296, "to": "mm"},
10018   "name": "CB_PERFCOUNTER2_SELECT",
10019   "type_ref": "CB_PERFCOUNTER1_SELECT"
10020  },
10021  {
10022   "chips": ["gfx11"],
10023   "map": {"at": 225300, "to": "mm"},
10024   "name": "CB_PERFCOUNTER3_SELECT",
10025   "type_ref": "CB_PERFCOUNTER1_SELECT"
10026  },
10027  {
10028   "chips": ["gfx11"],
10029   "map": {"at": 225536, "to": "mm"},
10030   "name": "DB_PERFCOUNTER0_SELECT",
10031   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10032  },
10033  {
10034   "chips": ["gfx11"],
10035   "map": {"at": 225540, "to": "mm"},
10036   "name": "DB_PERFCOUNTER0_SELECT1",
10037   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10038  },
10039  {
10040   "chips": ["gfx11"],
10041   "map": {"at": 225544, "to": "mm"},
10042   "name": "DB_PERFCOUNTER1_SELECT",
10043   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10044  },
10045  {
10046   "chips": ["gfx11"],
10047   "map": {"at": 225548, "to": "mm"},
10048   "name": "DB_PERFCOUNTER1_SELECT1",
10049   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10050  },
10051  {
10052   "chips": ["gfx11"],
10053   "map": {"at": 225552, "to": "mm"},
10054   "name": "DB_PERFCOUNTER2_SELECT",
10055   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10056  },
10057  {
10058   "chips": ["gfx11"],
10059   "map": {"at": 225560, "to": "mm"},
10060   "name": "DB_PERFCOUNTER3_SELECT",
10061   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10062  },
10063  {
10064   "chips": ["gfx11"],
10065   "map": {"at": 225792, "to": "mm"},
10066   "name": "RLC_SPM_PERFMON_CNTL",
10067   "type_ref": "RLC_SPM_PERFMON_CNTL"
10068  },
10069  {
10070   "chips": ["gfx11"],
10071   "map": {"at": 225796, "to": "mm"},
10072   "name": "RLC_SPM_PERFMON_RING_BASE_LO"
10073  },
10074  {
10075   "chips": ["gfx11"],
10076   "map": {"at": 225800, "to": "mm"},
10077   "name": "RLC_SPM_PERFMON_RING_BASE_HI",
10078   "type_ref": "RLC_SPM_PERFMON_RING_BASE_HI"
10079  },
10080  {
10081   "chips": ["gfx11"],
10082   "map": {"at": 225804, "to": "mm"},
10083   "name": "RLC_SPM_PERFMON_RING_SIZE"
10084  },
10085  {
10086   "chips": ["gfx11"],
10087   "map": {"at": 225808, "to": "mm"},
10088   "name": "RLC_SPM_RING_WRPTR",
10089   "type_ref": "RLC_SPM_RING_WRPTR"
10090  },
10091  {
10092   "chips": ["gfx11"],
10093   "map": {"at": 225812, "to": "mm"},
10094   "name": "RLC_SPM_RING_RDPTR"
10095  },
10096  {
10097   "chips": ["gfx11"],
10098   "map": {"at": 225816, "to": "mm"},
10099   "name": "RLC_SPM_SEGMENT_THRESHOLD",
10100   "type_ref": "RLC_SPM_SEGMENT_THRESHOLD"
10101  },
10102  {
10103   "chips": ["gfx11"],
10104   "map": {"at": 225820, "to": "mm"},
10105   "name": "RLC_SPM_PERFMON_SEGMENT_SIZE",
10106   "type_ref": "RLC_SPM_PERFMON_SEGMENT_SIZE"
10107  },
10108  {
10109   "chips": ["gfx11"],
10110   "map": {"at": 225824, "to": "mm"},
10111   "name": "RLC_SPM_GLOBAL_MUXSEL_ADDR",
10112   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
10113  },
10114  {
10115   "chips": ["gfx11"],
10116   "map": {"at": 225828, "to": "mm"},
10117   "name": "RLC_SPM_GLOBAL_MUXSEL_DATA",
10118   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_DATA"
10119  },
10120  {
10121   "chips": ["gfx11"],
10122   "map": {"at": 225832, "to": "mm"},
10123   "name": "RLC_SPM_SE_MUXSEL_ADDR",
10124   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_ADDR"
10125  },
10126  {
10127   "chips": ["gfx11"],
10128   "map": {"at": 225836, "to": "mm"},
10129   "name": "RLC_SPM_SE_MUXSEL_DATA",
10130   "type_ref": "RLC_SPM_GLOBAL_MUXSEL_DATA"
10131  },
10132  {
10133   "chips": ["gfx11"],
10134   "map": {"at": 225864, "to": "mm"},
10135   "name": "RLC_SPM_ACCUM_DATARAM_ADDR",
10136   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
10137  },
10138  {
10139   "chips": ["gfx11"],
10140   "map": {"at": 225868, "to": "mm"},
10141   "name": "RLC_SPM_ACCUM_DATARAM_DATA"
10142  },
10143  {
10144   "chips": ["gfx11"],
10145   "map": {"at": 225872, "to": "mm"},
10146   "name": "RLC_SPM_ACCUM_SWA_DATARAM_ADDR",
10147   "type_ref": "RLC_SPM_ACCUM_DATARAM_ADDR"
10148  },
10149  {
10150   "chips": ["gfx11"],
10151   "map": {"at": 225876, "to": "mm"},
10152   "name": "RLC_SPM_ACCUM_SWA_DATARAM_DATA"
10153  },
10154  {
10155   "chips": ["gfx11"],
10156   "map": {"at": 225880, "to": "mm"},
10157   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR",
10158   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR"
10159  },
10160  {
10161   "chips": ["gfx11"],
10162   "map": {"at": 225884, "to": "mm"},
10163   "name": "RLC_SPM_ACCUM_CTRLRAM_DATA",
10164   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_DATA"
10165  },
10166  {
10167   "chips": ["gfx11"],
10168   "map": {"at": 225888, "to": "mm"},
10169   "name": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET",
10170   "type_ref": "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET"
10171  },
10172  {
10173   "chips": ["gfx11"],
10174   "map": {"at": 225892, "to": "mm"},
10175   "name": "RLC_SPM_ACCUM_STATUS",
10176   "type_ref": "RLC_SPM_ACCUM_STATUS"
10177  },
10178  {
10179   "chips": ["gfx11"],
10180   "map": {"at": 225896, "to": "mm"},
10181   "name": "RLC_SPM_ACCUM_CTRL",
10182   "type_ref": "RLC_SPM_ACCUM_CTRL"
10183  },
10184  {
10185   "chips": ["gfx11"],
10186   "map": {"at": 225900, "to": "mm"},
10187   "name": "RLC_SPM_ACCUM_MODE",
10188   "type_ref": "RLC_SPM_ACCUM_MODE"
10189  },
10190  {
10191   "chips": ["gfx11"],
10192   "map": {"at": 225904, "to": "mm"},
10193   "name": "RLC_SPM_ACCUM_THRESHOLD",
10194   "type_ref": "RLC_SPM_ACCUM_THRESHOLD"
10195  },
10196  {
10197   "chips": ["gfx11"],
10198   "map": {"at": 225908, "to": "mm"},
10199   "name": "RLC_SPM_ACCUM_SAMPLES_REQUESTED",
10200   "type_ref": "RLC_SPM_ACCUM_SAMPLES_REQUESTED"
10201  },
10202  {
10203   "chips": ["gfx11"],
10204   "map": {"at": 225912, "to": "mm"},
10205   "name": "RLC_SPM_ACCUM_DATARAM_WRCOUNT",
10206   "type_ref": "RLC_SPM_ACCUM_DATARAM_WRCOUNT"
10207  },
10208  {
10209   "chips": ["gfx11"],
10210   "map": {"at": 225916, "to": "mm"},
10211   "name": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS",
10212   "type_ref": "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS"
10213  },
10214  {
10215   "chips": ["gfx11"],
10216   "map": {"at": 225928, "to": "mm"},
10217   "name": "RLC_SPM_PAUSE",
10218   "type_ref": "RLC_SPM_PAUSE"
10219  },
10220  {
10221   "chips": ["gfx11"],
10222   "map": {"at": 225932, "to": "mm"},
10223   "name": "RLC_SPM_STATUS",
10224   "type_ref": "RLC_SPM_STATUS"
10225  },
10226  {
10227   "chips": ["gfx11"],
10228   "map": {"at": 225936, "to": "mm"},
10229   "name": "RLC_SPM_GFXCLOCK_LOWCOUNT"
10230  },
10231  {
10232   "chips": ["gfx11"],
10233   "map": {"at": 225940, "to": "mm"},
10234   "name": "RLC_SPM_GFXCLOCK_HIGHCOUNT"
10235  },
10236  {
10237   "chips": ["gfx11"],
10238   "map": {"at": 225972, "to": "mm"},
10239   "name": "RLC_SPM_MODE",
10240   "type_ref": "RLC_SPM_MODE"
10241  },
10242  {
10243   "chips": ["gfx11"],
10244   "map": {"at": 225976, "to": "mm"},
10245   "name": "RLC_SPM_RSPM_REQ_DATA_LO"
10246  },
10247  {
10248   "chips": ["gfx11"],
10249   "map": {"at": 225980, "to": "mm"},
10250   "name": "RLC_SPM_RSPM_REQ_DATA_HI",
10251   "type_ref": "RLC_SPM_RSPM_REQ_DATA_HI"
10252  },
10253  {
10254   "chips": ["gfx11"],
10255   "map": {"at": 225984, "to": "mm"},
10256   "name": "RLC_SPM_RSPM_REQ_OP",
10257   "type_ref": "RLC_SPM_RSPM_REQ_OP"
10258  },
10259  {
10260   "chips": ["gfx11"],
10261   "map": {"at": 225988, "to": "mm"},
10262   "name": "RLC_SPM_RSPM_RET_DATA"
10263  },
10264  {
10265   "chips": ["gfx11"],
10266   "map": {"at": 225992, "to": "mm"},
10267   "name": "RLC_SPM_RSPM_RET_OP",
10268   "type_ref": "RLC_SPM_RSPM_RET_OP"
10269  },
10270  {
10271   "chips": ["gfx11"],
10272   "map": {"at": 225996, "to": "mm"},
10273   "name": "RLC_SPM_SE_RSPM_REQ_DATA_LO"
10274  },
10275  {
10276   "chips": ["gfx11"],
10277   "map": {"at": 226000, "to": "mm"},
10278   "name": "RLC_SPM_SE_RSPM_REQ_DATA_HI",
10279   "type_ref": "RLC_SPM_RSPM_REQ_DATA_HI"
10280  },
10281  {
10282   "chips": ["gfx11"],
10283   "map": {"at": 226004, "to": "mm"},
10284   "name": "RLC_SPM_SE_RSPM_REQ_OP",
10285   "type_ref": "RLC_SPM_RSPM_REQ_OP"
10286  },
10287  {
10288   "chips": ["gfx11"],
10289   "map": {"at": 226008, "to": "mm"},
10290   "name": "RLC_SPM_SE_RSPM_RET_DATA"
10291  },
10292  {
10293   "chips": ["gfx11"],
10294   "map": {"at": 226012, "to": "mm"},
10295   "name": "RLC_SPM_SE_RSPM_RET_OP",
10296   "type_ref": "RLC_SPM_RSPM_RET_OP"
10297  },
10298  {
10299   "chips": ["gfx11"],
10300   "map": {"at": 226016, "to": "mm"},
10301   "name": "RLC_SPM_RSPM_CMD",
10302   "type_ref": "RLC_SPM_RSPM_CMD"
10303  },
10304  {
10305   "chips": ["gfx11"],
10306   "map": {"at": 226020, "to": "mm"},
10307   "name": "RLC_SPM_RSPM_CMD_ACK",
10308   "type_ref": "RLC_SPM_RSPM_CMD_ACK"
10309  },
10310  {
10311   "chips": ["gfx11"],
10312   "map": {"at": 226044, "to": "mm"},
10313   "name": "RLC_SPM_SPARE"
10314  },
10315  {
10316   "chips": ["gfx11"],
10317   "map": {"at": 226048, "to": "mm"},
10318   "name": "RLC_PERFMON_CNTL",
10319   "type_ref": "RLC_PERFMON_CNTL"
10320  },
10321  {
10322   "chips": ["gfx11"],
10323   "map": {"at": 226052, "to": "mm"},
10324   "name": "RLC_PERFCOUNTER0_SELECT",
10325   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10326  },
10327  {
10328   "chips": ["gfx11"],
10329   "map": {"at": 226056, "to": "mm"},
10330   "name": "RLC_PERFCOUNTER1_SELECT",
10331   "type_ref": "RLC_PERFCOUNTER0_SELECT"
10332  },
10333  {
10334   "chips": ["gfx11"],
10335   "map": {"at": 226060, "to": "mm"},
10336   "name": "RLC_GPU_IOV_PERF_CNT_CNTL",
10337   "type_ref": "RLC_GPU_IOV_PERF_CNT_CNTL"
10338  },
10339  {
10340   "chips": ["gfx11"],
10341   "map": {"at": 226064, "to": "mm"},
10342   "name": "RLC_GPU_IOV_PERF_CNT_WR_ADDR",
10343   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10344  },
10345  {
10346   "chips": ["gfx11"],
10347   "map": {"at": 226068, "to": "mm"},
10348   "name": "RLC_GPU_IOV_PERF_CNT_WR_DATA"
10349  },
10350  {
10351   "chips": ["gfx11"],
10352   "map": {"at": 226072, "to": "mm"},
10353   "name": "RLC_GPU_IOV_PERF_CNT_RD_ADDR",
10354   "type_ref": "RLC_GPU_IOV_PERF_CNT_WR_ADDR"
10355  },
10356  {
10357   "chips": ["gfx11"],
10358   "map": {"at": 226076, "to": "mm"},
10359   "name": "RLC_GPU_IOV_PERF_CNT_RD_DATA"
10360  },
10361  {
10362   "chips": ["gfx11"],
10363   "map": {"at": 226304, "to": "mm"},
10364   "name": "RMI_PERFCOUNTER0_SELECT",
10365   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10366  },
10367  {
10368   "chips": ["gfx11"],
10369   "map": {"at": 226308, "to": "mm"},
10370   "name": "RMI_PERFCOUNTER0_SELECT1",
10371   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10372  },
10373  {
10374   "chips": ["gfx11"],
10375   "map": {"at": 226312, "to": "mm"},
10376   "name": "RMI_PERFCOUNTER1_SELECT",
10377   "type_ref": "CB_PERFCOUNTER1_SELECT"
10378  },
10379  {
10380   "chips": ["gfx11"],
10381   "map": {"at": 226316, "to": "mm"},
10382   "name": "RMI_PERFCOUNTER2_SELECT",
10383   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10384  },
10385  {
10386   "chips": ["gfx11"],
10387   "map": {"at": 226320, "to": "mm"},
10388   "name": "RMI_PERFCOUNTER2_SELECT1",
10389   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10390  },
10391  {
10392   "chips": ["gfx11"],
10393   "map": {"at": 226324, "to": "mm"},
10394   "name": "RMI_PERFCOUNTER3_SELECT",
10395   "type_ref": "CB_PERFCOUNTER1_SELECT"
10396  },
10397  {
10398   "chips": ["gfx11"],
10399   "map": {"at": 226328, "to": "mm"},
10400   "name": "RMI_PERF_COUNTER_CNTL",
10401   "type_ref": "RMI_PERF_COUNTER_CNTL"
10402  },
10403  {
10404   "chips": ["gfx11"],
10405   "map": {"at": 226432, "to": "mm"},
10406   "name": "GCVML2_PERFCOUNTER2_0_SELECT",
10407   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10408  },
10409  {
10410   "chips": ["gfx11"],
10411   "map": {"at": 226436, "to": "mm"},
10412   "name": "GCVML2_PERFCOUNTER2_1_SELECT",
10413   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10414  },
10415  {
10416   "chips": ["gfx11"],
10417   "map": {"at": 226440, "to": "mm"},
10418   "name": "GCVML2_PERFCOUNTER2_0_SELECT1",
10419   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10420  },
10421  {
10422   "chips": ["gfx11"],
10423   "map": {"at": 226444, "to": "mm"},
10424   "name": "GCVML2_PERFCOUNTER2_1_SELECT1",
10425   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10426  },
10427  {
10428   "chips": ["gfx11"],
10429   "map": {"at": 226448, "to": "mm"},
10430   "name": "GCVML2_PERFCOUNTER2_0_MODE",
10431   "type_ref": "GCVML2_PERFCOUNTER2_0_MODE"
10432  },
10433  {
10434   "chips": ["gfx11"],
10435   "map": {"at": 226452, "to": "mm"},
10436   "name": "GCVML2_PERFCOUNTER2_1_MODE",
10437   "type_ref": "GCVML2_PERFCOUNTER2_0_MODE"
10438  },
10439  {
10440   "chips": ["gfx11"],
10441   "map": {"at": 226496, "to": "mm"},
10442   "name": "GCMC_VM_L2_PERFCOUNTER0_CFG",
10443   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10444  },
10445  {
10446   "chips": ["gfx11"],
10447   "map": {"at": 226500, "to": "mm"},
10448   "name": "GCMC_VM_L2_PERFCOUNTER1_CFG",
10449   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10450  },
10451  {
10452   "chips": ["gfx11"],
10453   "map": {"at": 226504, "to": "mm"},
10454   "name": "GCMC_VM_L2_PERFCOUNTER2_CFG",
10455   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10456  },
10457  {
10458   "chips": ["gfx11"],
10459   "map": {"at": 226508, "to": "mm"},
10460   "name": "GCMC_VM_L2_PERFCOUNTER3_CFG",
10461   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10462  },
10463  {
10464   "chips": ["gfx11"],
10465   "map": {"at": 226512, "to": "mm"},
10466   "name": "GCMC_VM_L2_PERFCOUNTER4_CFG",
10467   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10468  },
10469  {
10470   "chips": ["gfx11"],
10471   "map": {"at": 226516, "to": "mm"},
10472   "name": "GCMC_VM_L2_PERFCOUNTER5_CFG",
10473   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10474  },
10475  {
10476   "chips": ["gfx11"],
10477   "map": {"at": 226520, "to": "mm"},
10478   "name": "GCMC_VM_L2_PERFCOUNTER6_CFG",
10479   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10480  },
10481  {
10482   "chips": ["gfx11"],
10483   "map": {"at": 226524, "to": "mm"},
10484   "name": "GCMC_VM_L2_PERFCOUNTER7_CFG",
10485   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10486  },
10487  {
10488   "chips": ["gfx11"],
10489   "map": {"at": 226528, "to": "mm"},
10490   "name": "GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL",
10491   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL"
10492  },
10493  {
10494   "chips": ["gfx11"],
10495   "map": {"at": 226532, "to": "mm"},
10496   "name": "GCUTCL2_PERFCOUNTER0_CFG",
10497   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10498  },
10499  {
10500   "chips": ["gfx11"],
10501   "map": {"at": 226536, "to": "mm"},
10502   "name": "GCUTCL2_PERFCOUNTER1_CFG",
10503   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10504  },
10505  {
10506   "chips": ["gfx11"],
10507   "map": {"at": 226540, "to": "mm"},
10508   "name": "GCUTCL2_PERFCOUNTER2_CFG",
10509   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10510  },
10511  {
10512   "chips": ["gfx11"],
10513   "map": {"at": 226544, "to": "mm"},
10514   "name": "GCUTCL2_PERFCOUNTER3_CFG",
10515   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10516  },
10517  {
10518   "chips": ["gfx11"],
10519   "map": {"at": 226548, "to": "mm"},
10520   "name": "GCUTCL2_PERFCOUNTER_RSLT_CNTL",
10521   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL"
10522  },
10523  {
10524   "chips": ["gfx11"],
10525   "map": {"at": 226688, "to": "mm"},
10526   "name": "GCR_PERFCOUNTER0_SELECT",
10527   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10528  },
10529  {
10530   "chips": ["gfx11"],
10531   "map": {"at": 226692, "to": "mm"},
10532   "name": "GCR_PERFCOUNTER0_SELECT1",
10533   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10534  },
10535  {
10536   "chips": ["gfx11"],
10537   "map": {"at": 226696, "to": "mm"},
10538   "name": "GCR_PERFCOUNTER1_SELECT",
10539   "type_ref": "SX_PERFCOUNTER2_SELECT"
10540  },
10541  {
10542   "chips": ["gfx11"],
10543   "map": {"at": 226816, "to": "mm"},
10544   "name": "PA_PH_PERFCOUNTER0_SELECT",
10545   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10546  },
10547  {
10548   "chips": ["gfx11"],
10549   "map": {"at": 226820, "to": "mm"},
10550   "name": "PA_PH_PERFCOUNTER0_SELECT1",
10551   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10552  },
10553  {
10554   "chips": ["gfx11"],
10555   "map": {"at": 226824, "to": "mm"},
10556   "name": "PA_PH_PERFCOUNTER1_SELECT",
10557   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10558  },
10559  {
10560   "chips": ["gfx11"],
10561   "map": {"at": 226828, "to": "mm"},
10562   "name": "PA_PH_PERFCOUNTER2_SELECT",
10563   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10564  },
10565  {
10566   "chips": ["gfx11"],
10567   "map": {"at": 226832, "to": "mm"},
10568   "name": "PA_PH_PERFCOUNTER3_SELECT",
10569   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10570  },
10571  {
10572   "chips": ["gfx11"],
10573   "map": {"at": 226836, "to": "mm"},
10574   "name": "PA_PH_PERFCOUNTER4_SELECT",
10575   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10576  },
10577  {
10578   "chips": ["gfx11"],
10579   "map": {"at": 226840, "to": "mm"},
10580   "name": "PA_PH_PERFCOUNTER5_SELECT",
10581   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10582  },
10583  {
10584   "chips": ["gfx11"],
10585   "map": {"at": 226844, "to": "mm"},
10586   "name": "PA_PH_PERFCOUNTER6_SELECT",
10587   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10588  },
10589  {
10590   "chips": ["gfx11"],
10591   "map": {"at": 226848, "to": "mm"},
10592   "name": "PA_PH_PERFCOUNTER7_SELECT",
10593   "type_ref": "PA_SC_PERFCOUNTER1_SELECT"
10594  },
10595  {
10596   "chips": ["gfx11"],
10597   "map": {"at": 226880, "to": "mm"},
10598   "name": "PA_PH_PERFCOUNTER1_SELECT1",
10599   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10600  },
10601  {
10602   "chips": ["gfx11"],
10603   "map": {"at": 226884, "to": "mm"},
10604   "name": "PA_PH_PERFCOUNTER2_SELECT1",
10605   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10606  },
10607  {
10608   "chips": ["gfx11"],
10609   "map": {"at": 226888, "to": "mm"},
10610   "name": "PA_PH_PERFCOUNTER3_SELECT1",
10611   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10612  },
10613  {
10614   "chips": ["gfx11"],
10615   "map": {"at": 226944, "to": "mm"},
10616   "name": "UTCL1_PERFCOUNTER0_SELECT",
10617   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
10618  },
10619  {
10620   "chips": ["gfx11"],
10621   "map": {"at": 226948, "to": "mm"},
10622   "name": "UTCL1_PERFCOUNTER1_SELECT",
10623   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
10624  },
10625  {
10626   "chips": ["gfx11"],
10627   "map": {"at": 226952, "to": "mm"},
10628   "name": "UTCL1_PERFCOUNTER2_SELECT",
10629   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
10630  },
10631  {
10632   "chips": ["gfx11"],
10633   "map": {"at": 226956, "to": "mm"},
10634   "name": "UTCL1_PERFCOUNTER3_SELECT",
10635   "type_ref": "UTCL1_PERFCOUNTER0_SELECT"
10636  },
10637  {
10638   "chips": ["gfx11"],
10639   "map": {"at": 227072, "to": "mm"},
10640   "name": "GL1A_PERFCOUNTER0_SELECT",
10641   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10642  },
10643  {
10644   "chips": ["gfx11"],
10645   "map": {"at": 227076, "to": "mm"},
10646   "name": "GL1A_PERFCOUNTER0_SELECT1",
10647   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
10648  },
10649  {
10650   "chips": ["gfx11"],
10651   "map": {"at": 227080, "to": "mm"},
10652   "name": "GL1A_PERFCOUNTER1_SELECT",
10653   "type_ref": "SX_PERFCOUNTER2_SELECT"
10654  },
10655  {
10656   "chips": ["gfx11"],
10657   "map": {"at": 227084, "to": "mm"},
10658   "name": "GL1A_PERFCOUNTER2_SELECT",
10659   "type_ref": "SX_PERFCOUNTER2_SELECT"
10660  },
10661  {
10662   "chips": ["gfx11"],
10663   "map": {"at": 227088, "to": "mm"},
10664   "name": "GL1A_PERFCOUNTER3_SELECT",
10665   "type_ref": "SX_PERFCOUNTER2_SELECT"
10666  },
10667  {
10668   "chips": ["gfx11"],
10669   "map": {"at": 227136, "to": "mm"},
10670   "name": "GL1H_PERFCOUNTER0_SELECT",
10671   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10672  },
10673  {
10674   "chips": ["gfx11"],
10675   "map": {"at": 227140, "to": "mm"},
10676   "name": "GL1H_PERFCOUNTER0_SELECT1",
10677   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
10678  },
10679  {
10680   "chips": ["gfx11"],
10681   "map": {"at": 227144, "to": "mm"},
10682   "name": "GL1H_PERFCOUNTER1_SELECT",
10683   "type_ref": "SX_PERFCOUNTER2_SELECT"
10684  },
10685  {
10686   "chips": ["gfx11"],
10687   "map": {"at": 227148, "to": "mm"},
10688   "name": "GL1H_PERFCOUNTER2_SELECT",
10689   "type_ref": "SX_PERFCOUNTER2_SELECT"
10690  },
10691  {
10692   "chips": ["gfx11"],
10693   "map": {"at": 227152, "to": "mm"},
10694   "name": "GL1H_PERFCOUNTER3_SELECT",
10695   "type_ref": "SX_PERFCOUNTER2_SELECT"
10696  },
10697  {
10698   "chips": ["gfx11"],
10699   "map": {"at": 227200, "to": "mm"},
10700   "name": "CHA_PERFCOUNTER0_SELECT",
10701   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10702  },
10703  {
10704   "chips": ["gfx11"],
10705   "map": {"at": 227204, "to": "mm"},
10706   "name": "CHA_PERFCOUNTER0_SELECT1",
10707   "type_ref": "GL2C_PERFCOUNTER0_SELECT1"
10708  },
10709  {
10710   "chips": ["gfx11"],
10711   "map": {"at": 227208, "to": "mm"},
10712   "name": "CHA_PERFCOUNTER1_SELECT",
10713   "type_ref": "SX_PERFCOUNTER2_SELECT"
10714  },
10715  {
10716   "chips": ["gfx11"],
10717   "map": {"at": 227212, "to": "mm"},
10718   "name": "CHA_PERFCOUNTER2_SELECT",
10719   "type_ref": "SX_PERFCOUNTER2_SELECT"
10720  },
10721  {
10722   "chips": ["gfx11"],
10723   "map": {"at": 227216, "to": "mm"},
10724   "name": "CHA_PERFCOUNTER3_SELECT",
10725   "type_ref": "SX_PERFCOUNTER2_SELECT"
10726  },
10727  {
10728   "chips": ["gfx11"],
10729   "map": {"at": 227328, "to": "mm"},
10730   "name": "GUS_PERFCOUNTER2_SELECT",
10731   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10732  },
10733  {
10734   "chips": ["gfx11"],
10735   "map": {"at": 227332, "to": "mm"},
10736   "name": "GUS_PERFCOUNTER2_SELECT1",
10737   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10738  },
10739  {
10740   "chips": ["gfx11"],
10741   "map": {"at": 227336, "to": "mm"},
10742   "name": "GUS_PERFCOUNTER2_MODE",
10743   "type_ref": "GCVML2_PERFCOUNTER2_0_MODE"
10744  },
10745  {
10746   "chips": ["gfx11"],
10747   "map": {"at": 227340, "to": "mm"},
10748   "name": "GUS_PERFCOUNTER0_CFG",
10749   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10750  },
10751  {
10752   "chips": ["gfx11"],
10753   "map": {"at": 227344, "to": "mm"},
10754   "name": "GUS_PERFCOUNTER1_CFG",
10755   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10756  },
10757  {
10758   "chips": ["gfx11"],
10759   "map": {"at": 227348, "to": "mm"},
10760   "name": "GUS_PERFCOUNTER_RSLT_CNTL",
10761   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL"
10762  },
10763  {
10764   "chips": ["gfx11"],
10765   "map": {"at": 227456, "to": "mm"},
10766   "name": "SDMA0_PERFCNT_PERFCOUNTER0_CFG",
10767   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10768  },
10769  {
10770   "chips": ["gfx11"],
10771   "map": {"at": 227460, "to": "mm"},
10772   "name": "SDMA0_PERFCNT_PERFCOUNTER1_CFG",
10773   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10774  },
10775  {
10776   "chips": ["gfx11"],
10777   "map": {"at": 227464, "to": "mm"},
10778   "name": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL",
10779   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL"
10780  },
10781  {
10782   "chips": ["gfx11"],
10783   "map": {"at": 227468, "to": "mm"},
10784   "name": "SDMA0_PERFCNT_MISC_CNTL",
10785   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
10786  },
10787  {
10788   "chips": ["gfx11"],
10789   "map": {"at": 227472, "to": "mm"},
10790   "name": "SDMA0_PERFCOUNTER0_SELECT",
10791   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10792  },
10793  {
10794   "chips": ["gfx11"],
10795   "map": {"at": 227476, "to": "mm"},
10796   "name": "SDMA0_PERFCOUNTER0_SELECT1",
10797   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10798  },
10799  {
10800   "chips": ["gfx11"],
10801   "map": {"at": 227480, "to": "mm"},
10802   "name": "SDMA0_PERFCOUNTER1_SELECT",
10803   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10804  },
10805  {
10806   "chips": ["gfx11"],
10807   "map": {"at": 227484, "to": "mm"},
10808   "name": "SDMA0_PERFCOUNTER1_SELECT1",
10809   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10810  },
10811  {
10812   "chips": ["gfx11"],
10813   "map": {"at": 227504, "to": "mm"},
10814   "name": "SDMA1_PERFCNT_PERFCOUNTER0_CFG",
10815   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10816  },
10817  {
10818   "chips": ["gfx11"],
10819   "map": {"at": 227508, "to": "mm"},
10820   "name": "SDMA1_PERFCNT_PERFCOUNTER1_CFG",
10821   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER0_CFG"
10822  },
10823  {
10824   "chips": ["gfx11"],
10825   "map": {"at": 227512, "to": "mm"},
10826   "name": "SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL",
10827   "type_ref": "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL"
10828  },
10829  {
10830   "chips": ["gfx11"],
10831   "map": {"at": 227516, "to": "mm"},
10832   "name": "SDMA1_PERFCNT_MISC_CNTL",
10833   "type_ref": "SDMA0_PERFCNT_MISC_CNTL"
10834  },
10835  {
10836   "chips": ["gfx11"],
10837   "map": {"at": 227520, "to": "mm"},
10838   "name": "SDMA1_PERFCOUNTER0_SELECT",
10839   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10840  },
10841  {
10842   "chips": ["gfx11"],
10843   "map": {"at": 227524, "to": "mm"},
10844   "name": "SDMA1_PERFCOUNTER0_SELECT1",
10845   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10846  },
10847  {
10848   "chips": ["gfx11"],
10849   "map": {"at": 227528, "to": "mm"},
10850   "name": "SDMA1_PERFCOUNTER1_SELECT",
10851   "type_ref": "SDMA0_PERFCOUNTER0_SELECT"
10852  },
10853  {
10854   "chips": ["gfx11"],
10855   "map": {"at": 227532, "to": "mm"},
10856   "name": "SDMA1_PERFCOUNTER1_SELECT1",
10857   "type_ref": "SDMA0_PERFCOUNTER0_SELECT1"
10858  }
10859 ],
10860 "register_types": {
10861  "CB_BLEND0_CONTROL": {
10862   "fields": [
10863    {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"},
10864    {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"},
10865    {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"},
10866    {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"},
10867    {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"},
10868    {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"},
10869    {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"},
10870    {"bits": [30, 30], "name": "ENABLE"},
10871    {"bits": [31, 31], "name": "DISABLE_ROP3"}
10872   ]
10873  },
10874  "CB_COLOR0_ATTRIB": {
10875   "fields": [
10876    {"bits": [0, 1], "name": "NUM_FRAGMENTS"},
10877    {"bits": [2, 2], "name": "FORCE_DST_ALPHA_1"},
10878    {"bits": [3, 3], "name": "DISABLE_FMASK_NOALLOC_OPT"},
10879    {"bits": [4, 4], "name": "LIMIT_COLOR_FETCH_TO_256B_MAX"},
10880    {"bits": [5, 5], "name": "FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX"}
10881   ]
10882  },
10883  "CB_COLOR0_ATTRIB2": {
10884   "fields": [
10885    {"bits": [0, 13], "name": "MIP0_HEIGHT"},
10886    {"bits": [14, 27], "name": "MIP0_WIDTH"},
10887    {"bits": [28, 31], "name": "MAX_MIP"}
10888   ]
10889  },
10890  "CB_COLOR0_ATTRIB3": {
10891   "fields": [
10892    {"bits": [0, 12], "name": "MIP0_DEPTH"},
10893    {"bits": [13, 13], "name": "META_LINEAR"},
10894    {"bits": [14, 18], "name": "COLOR_SW_MODE"},
10895    {"bits": [24, 25], "name": "RESOURCE_TYPE"},
10896    {"bits": [30, 30], "name": "DCC_PIPE_ALIGNED"}
10897   ]
10898  },
10899  "CB_COLOR0_FDCC_CONTROL": {
10900   "fields": [
10901    {"bits": [0, 0], "name": "SAMPLE_MASK_TRACKER_DISABLE"},
10902    {"bits": [1, 1], "name": "SAMPLE_MASK_TRACKER_FEA_FORCE"},
10903    {"bits": [2, 3], "enum_ref": "CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE", "name": "MAX_UNCOMPRESSED_BLOCK_SIZE"},
10904    {"bits": [4, 4], "enum_ref": "CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE", "name": "MIN_COMPRESSED_BLOCK_SIZE"},
10905    {"bits": [5, 6], "name": "MAX_COMPRESSED_BLOCK_SIZE"},
10906    {"bits": [7, 8], "name": "COLOR_TRANSFORM"},
10907    {"bits": [9, 9], "name": "INDEPENDENT_64B_BLOCKS"},
10908    {"bits": [10, 10], "name": "INDEPENDENT_128B_BLOCKS"},
10909    {"bits": [18, 18], "name": "DISABLE_CONSTANT_ENCODE_REG"},
10910    {"bits": [19, 19], "name": "ENABLE_CONSTANT_ENCODE_REG_WRITE"},
10911    {"bits": [21, 21], "name": "SKIP_LOW_COMP_RATIO"},
10912    {"bits": [22, 22], "name": "FDCC_ENABLE"},
10913    {"bits": [23, 23], "name": "DCC_COMPRESS_DISABLE"},
10914    {"bits": [24, 24], "name": "FRAGMENT_COMPRESS_DISABLE"}
10915   ]
10916  },
10917  "CB_COLOR0_INFO": {
10918   "fields": [
10919    {"bits": [0, 4], "enum_ref": "ColorFormat", "name": "FORMAT"},
10920    {"bits": [7, 7], "name": "LINEAR_GENERAL"},
10921    {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"},
10922    {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"},
10923    {"bits": [15, 15], "name": "BLEND_CLAMP"},
10924    {"bits": [16, 16], "name": "BLEND_BYPASS"},
10925    {"bits": [17, 17], "name": "SIMPLE_FLOAT"},
10926    {"bits": [18, 18], "name": "ROUND_MODE"},
10927    {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"},
10928    {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}
10929   ]
10930  },
10931  "CB_COLOR0_VIEW": {
10932   "fields": [
10933    {"bits": [0, 12], "name": "SLICE_START"},
10934    {"bits": [13, 25], "name": "SLICE_MAX"},
10935    {"bits": [26, 29], "name": "MIP_LEVEL"}
10936   ]
10937  },
10938  "CB_COLOR_CONTROL": {
10939   "fields": [
10940    {"bits": [0, 0], "name": "DISABLE_DUAL_QUAD"},
10941    {"bits": [1, 1], "name": "ENABLE_1FRAG_PS_INVOKE"},
10942    {"bits": [3, 3], "name": "DEGAMMA_ENABLE"},
10943    {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"},
10944    {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"}
10945   ]
10946  },
10947  "CB_COVERAGE_OUT_CONTROL": {
10948   "fields": [
10949    {"bits": [0, 0], "name": "COVERAGE_OUT_ENABLE"},
10950    {"bits": [1, 3], "name": "COVERAGE_OUT_MRT"},
10951    {"bits": [4, 5], "name": "COVERAGE_OUT_CHANNEL"},
10952    {"bits": [8, 11], "name": "COVERAGE_OUT_SAMPLES"}
10953   ]
10954  },
10955  "CB_FDCC_CONTROL": {
10956   "fields": [
10957    {"bits": [0, 0], "name": "SAMPLE_MASK_TRACKER_DISABLE"},
10958    {"bits": [2, 6], "name": "SAMPLE_MASK_TRACKER_WATERMARK"},
10959    {"bits": [8, 8], "name": "DISABLE_CONSTANT_ENCODE_AC01"},
10960    {"bits": [9, 9], "name": "DISABLE_CONSTANT_ENCODE_SINGLE"},
10961    {"bits": [10, 10], "name": "DISABLE_CONSTANT_ENCODE_REG"},
10962    {"bits": [12, 12], "name": "DISABLE_ELIMFC_SKIP_OF_AC01"},
10963    {"bits": [13, 13], "name": "DISABLE_ELIMFC_SKIP_OF_SINGLE"},
10964    {"bits": [14, 14], "name": "ENABLE_ELIMFC_SKIP_OF_REG"}
10965   ]
10966  },
10967  "CB_PERFCOUNTER1_SELECT": {
10968   "fields": [
10969    {"bits": [0, 9], "name": "PERF_SEL"},
10970    {"bits": [28, 31], "name": "PERF_MODE"}
10971   ]
10972  },
10973  "CB_PERFCOUNTER_FILTER": {
10974   "fields": [
10975    {"bits": [0, 0], "name": "OP_FILTER_ENABLE"},
10976    {"bits": [1, 3], "enum_ref": "CBPerfOpFilterSel", "name": "OP_FILTER_SEL"},
10977    {"bits": [4, 4], "name": "FORMAT_FILTER_ENABLE"},
10978    {"bits": [5, 9], "name": "FORMAT_FILTER_SEL"},
10979    {"bits": [10, 10], "name": "CLEAR_FILTER_ENABLE"},
10980    {"bits": [11, 11], "enum_ref": "CBPerfClearFilterSel", "name": "CLEAR_FILTER_SEL"},
10981    {"bits": [12, 12], "name": "MRT_FILTER_ENABLE"},
10982    {"bits": [13, 15], "name": "MRT_FILTER_SEL"},
10983    {"bits": [17, 17], "name": "NUM_SAMPLES_FILTER_ENABLE"},
10984    {"bits": [18, 20], "name": "NUM_SAMPLES_FILTER_SEL"},
10985    {"bits": [21, 21], "name": "NUM_FRAGMENTS_FILTER_ENABLE"},
10986    {"bits": [22, 23], "name": "NUM_FRAGMENTS_FILTER_SEL"}
10987   ]
10988  },
10989  "CB_RMI_GL2_CACHE_CONTROL": {
10990   "fields": [
10991    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "DCC_WR_POLICY"},
10992    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "COLOR_WR_POLICY"},
10993    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "DCC_RD_POLICY"},
10994    {"bits": [22, 23], "enum_ref": "ReadPolicy", "name": "COLOR_RD_POLICY"},
10995    {"bits": [26, 26], "name": "DCC_L3_BYPASS"},
10996    {"bits": [27, 27], "name": "COLOR_L3_BYPASS"},
10997    {"bits": [31, 31], "name": "COLOR_BIG_PAGE"}
10998   ]
10999  },
11000  "CB_SHADER_MASK": {
11001   "fields": [
11002    {"bits": [0, 3], "name": "OUTPUT0_ENABLE"},
11003    {"bits": [4, 7], "name": "OUTPUT1_ENABLE"},
11004    {"bits": [8, 11], "name": "OUTPUT2_ENABLE"},
11005    {"bits": [12, 15], "name": "OUTPUT3_ENABLE"},
11006    {"bits": [16, 19], "name": "OUTPUT4_ENABLE"},
11007    {"bits": [20, 23], "name": "OUTPUT5_ENABLE"},
11008    {"bits": [24, 27], "name": "OUTPUT6_ENABLE"},
11009    {"bits": [28, 31], "name": "OUTPUT7_ENABLE"}
11010   ]
11011  },
11012  "CB_TARGET_MASK": {
11013   "fields": [
11014    {"bits": [0, 3], "name": "TARGET0_ENABLE"},
11015    {"bits": [4, 7], "name": "TARGET1_ENABLE"},
11016    {"bits": [8, 11], "name": "TARGET2_ENABLE"},
11017    {"bits": [12, 15], "name": "TARGET3_ENABLE"},
11018    {"bits": [16, 19], "name": "TARGET4_ENABLE"},
11019    {"bits": [20, 23], "name": "TARGET5_ENABLE"},
11020    {"bits": [24, 27], "name": "TARGET6_ENABLE"},
11021    {"bits": [28, 31], "name": "TARGET7_ENABLE"}
11022   ]
11023  },
11024  "CHA_CHC_CREDITS": {
11025   "fields": [
11026    {"bits": [0, 7], "name": "CHC_REQ_CREDITS"},
11027    {"bits": [8, 15], "name": "CHCG_REQ_CREDITS"}
11028   ]
11029  },
11030  "CHA_CLIENT_FREE_DELAY": {
11031   "fields": [
11032    {"bits": [0, 2], "name": "CLIENT_TYPE_0_FREE_DELAY"},
11033    {"bits": [3, 5], "name": "CLIENT_TYPE_1_FREE_DELAY"},
11034    {"bits": [6, 8], "name": "CLIENT_TYPE_2_FREE_DELAY"},
11035    {"bits": [9, 11], "name": "CLIENT_TYPE_3_FREE_DELAY"},
11036    {"bits": [12, 14], "name": "CLIENT_TYPE_4_FREE_DELAY"}
11037   ]
11038  },
11039  "CHCG_CTRL": {
11040   "fields": [
11041    {"bits": [0, 3], "name": "BUFFER_DEPTH_MAX"},
11042    {"bits": [4, 7], "name": "VC0_BUFFER_DEPTH_MAX"},
11043    {"bits": [8, 14], "name": "GL2_REQ_CREDITS"},
11044    {"bits": [15, 21], "name": "GL2_DATA_CREDITS"},
11045    {"bits": [22, 22], "name": "TO_L1_REPEATER_FGCG_DISABLE"},
11046    {"bits": [23, 23], "name": "TO_L2_REPEATER_FGCG_DISABLE"}
11047   ]
11048  },
11049  "CHCG_STATUS": {
11050   "fields": [
11051    {"bits": [0, 0], "name": "INPUT_BUFFER_VC0_FIFO_FULL"},
11052    {"bits": [1, 1], "name": "OUTPUT_FIFOS_BUSY"},
11053    {"bits": [2, 2], "name": "SRC_DATA_FIFO_VC0_FULL"},
11054    {"bits": [3, 3], "name": "GL2_REQ_VC0_STALL"},
11055    {"bits": [4, 4], "name": "GL2_DATA_VC0_STALL"},
11056    {"bits": [5, 5], "name": "GL2_REQ_VC1_STALL"},
11057    {"bits": [6, 6], "name": "GL2_DATA_VC1_STALL"},
11058    {"bits": [7, 7], "name": "INPUT_BUFFER_VC0_BUSY"},
11059    {"bits": [8, 8], "name": "SRC_DATA_FIFO_VC0_BUSY"},
11060    {"bits": [9, 9], "name": "GL2_RH_BUSY"},
11061    {"bits": [10, 19], "name": "NUM_REQ_PENDING_FROM_L2"},
11062    {"bits": [20, 20], "name": "VIRTUAL_FIFO_FULL_STALL"},
11063    {"bits": [21, 21], "name": "REQUEST_TRACKER_BUFFER_STALL"},
11064    {"bits": [22, 22], "name": "REQUEST_TRACKER_BUSY"},
11065    {"bits": [23, 23], "name": "BUFFER_FULL"},
11066    {"bits": [24, 24], "name": "INPUT_BUFFER_VC1_BUSY"},
11067    {"bits": [25, 25], "name": "SRC_DATA_FIFO_VC1_BUSY"},
11068    {"bits": [26, 26], "name": "INPUT_BUFFER_VC1_FIFO_FULL"},
11069    {"bits": [27, 27], "name": "SRC_DATA_FIFO_VC1_FULL"}
11070   ]
11071  },
11072  "CHC_CTRL": {
11073   "fields": [
11074    {"bits": [0, 3], "name": "BUFFER_DEPTH_MAX"},
11075    {"bits": [4, 10], "name": "GL2_REQ_CREDITS"},
11076    {"bits": [11, 17], "name": "GL2_DATA_CREDITS"},
11077    {"bits": [18, 18], "name": "TO_L1_REPEATER_FGCG_DISABLE"},
11078    {"bits": [19, 19], "name": "TO_L2_REPEATER_FGCG_DISABLE"},
11079    {"bits": [29, 29], "name": "DISABLE_PERF_WR_DATA_ALLOC_COUNT"}
11080   ]
11081  },
11082  "CHC_STATUS": {
11083   "fields": [
11084    {"bits": [0, 0], "name": "INPUT_BUFFER_VC0_FIFO_FULL"},
11085    {"bits": [1, 1], "name": "OUTPUT_FIFOS_BUSY"},
11086    {"bits": [2, 2], "name": "SRC_DATA_FIFO_VC0_FULL"},
11087    {"bits": [3, 3], "name": "GL2_REQ_VC0_STALL"},
11088    {"bits": [4, 4], "name": "GL2_DATA_VC0_STALL"},
11089    {"bits": [5, 5], "name": "GL2_REQ_VC1_STALL"},
11090    {"bits": [6, 6], "name": "GL2_DATA_VC1_STALL"},
11091    {"bits": [7, 7], "name": "INPUT_BUFFER_VC0_BUSY"},
11092    {"bits": [8, 8], "name": "SRC_DATA_FIFO_VC0_BUSY"},
11093    {"bits": [9, 9], "name": "GL2_RH_BUSY"},
11094    {"bits": [10, 19], "name": "NUM_REQ_PENDING_FROM_L2"},
11095    {"bits": [20, 20], "name": "VIRTUAL_FIFO_FULL_STALL"},
11096    {"bits": [21, 21], "name": "REQUEST_TRACKER_BUFFER_STALL"},
11097    {"bits": [22, 22], "name": "REQUEST_TRACKER_BUSY"},
11098    {"bits": [23, 23], "name": "BUFFER_FULL"}
11099   ]
11100  },
11101  "CHI_CHR_REP_FGCG_OVERRIDE": {
11102   "fields": [
11103    {"bits": [0, 0], "name": "CHA_CHIW_REP_FGCG_OVERRIDE"},
11104    {"bits": [1, 1], "name": "CHA_CHIR_REP_FGCG_OVERRIDE"},
11105    {"bits": [2, 2], "name": "CHA_CHR_SRC_REP_FGCG_OVERRIDE"},
11106    {"bits": [3, 3], "name": "CHA_CHR_RET_REP_FGCG_OVERRIDE"}
11107   ]
11108  },
11109  "CH_ARB_CTRL": {
11110   "fields": [
11111    {"bits": [0, 1], "name": "NUM_MEM_PIPES"},
11112    {"bits": [2, 2], "name": "UC_IO_WR_PATH"},
11113    {"bits": [3, 3], "name": "FGCG_DISABLE"},
11114    {"bits": [4, 4], "name": "PERF_CNTR_EN_OVERRIDE"},
11115    {"bits": [5, 12], "name": "CHICKEN_BITS"}
11116   ]
11117  },
11118  "CH_ARB_STATUS": {
11119   "fields": [
11120    {"bits": [0, 0], "name": "REQ_ARB_BUSY"},
11121    {"bits": [1, 1], "name": "RET_ARB_BUSY"}
11122   ]
11123  },
11124  "CH_DRAM_BURST_CTRL": {
11125   "fields": [
11126    {"bits": [0, 2], "name": "MAX_DRAM_BURST"},
11127    {"bits": [3, 3], "name": "BURST_DISABLE"},
11128    {"bits": [4, 4], "name": "GATHER_64B_MEMORY_BURST_DISABLE"},
11129    {"bits": [5, 5], "name": "GATHER_64B_IO_BURST_DISABLE"},
11130    {"bits": [6, 6], "name": "GATHER_32B_MEMORY_BURST_DISABLE"},
11131    {"bits": [7, 7], "name": "GATHER_32B_IO_BURST_DISABLE"},
11132    {"bits": [8, 8], "name": "WRITE_BURSTABLE_STALL_DISABLE"}
11133   ]
11134  },
11135  "CH_DRAM_BURST_MASK": {
11136   "fields": [
11137    {"bits": [0, 7], "name": "DRAM_BURST_ADDR_MASK"}
11138   ]
11139  },
11140  "CH_VC5_ENABLE": {
11141   "fields": [
11142    {"bits": [1, 1], "name": "UTCL2_VC5_ENABLE"}
11143   ]
11144  },
11145  "COHER_DEST_BASE_HI_0": {
11146   "fields": [
11147    {"bits": [0, 7], "name": "DEST_BASE_HI_256B"}
11148   ]
11149  },
11150  "COMPUTE_DDID_INDEX": {
11151   "fields": [
11152    {"bits": [0, 10], "name": "INDEX"}
11153   ]
11154  },
11155  "COMPUTE_DISPATCH_INITIATOR": {
11156   "fields": [
11157    {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"},
11158    {"bits": [1, 1], "name": "PARTIAL_TG_EN"},
11159    {"bits": [2, 2], "name": "FORCE_START_AT_000"},
11160    {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"},
11161    {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"},
11162    {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"},
11163    {"bits": [6, 6], "name": "ORDER_MODE"},
11164    {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"},
11165    {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"},
11166    {"bits": [12, 12], "name": "RESERVED"},
11167    {"bits": [13, 13], "name": "TUNNEL_ENABLE"},
11168    {"bits": [14, 14], "name": "RESTORE"},
11169    {"bits": [15, 15], "name": "CS_W32_EN"},
11170    {"bits": [16, 16], "name": "AMP_SHADER_EN"},
11171    {"bits": [17, 17], "name": "DISABLE_DISP_PREMPT_EN"}
11172   ]
11173  },
11174  "COMPUTE_DISPATCH_INTERLEAVE": {
11175   "fields": [
11176    {"bits": [0, 9], "name": "INTERLEAVE"}
11177   ]
11178  },
11179  "COMPUTE_DISPATCH_TUNNEL": {
11180   "fields": [
11181    {"bits": [0, 9], "name": "OFF_DELAY"},
11182    {"bits": [10, 10], "name": "IMMEDIATE"}
11183   ]
11184  },
11185  "COMPUTE_MISC_RESERVED": {
11186   "fields": [
11187    {"bits": [0, 2], "name": "SEND_SEID"},
11188    {"bits": [3, 3], "name": "RESERVED3"},
11189    {"bits": [4, 4], "name": "RESERVED4"},
11190    {"bits": [5, 16], "name": "WAVE_ID_BASE"}
11191   ]
11192  },
11193  "COMPUTE_NUM_THREAD_X": {
11194   "fields": [
11195    {"bits": [0, 15], "name": "NUM_THREAD_FULL"},
11196    {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"}
11197   ]
11198  },
11199  "COMPUTE_PERFCOUNT_ENABLE": {
11200   "fields": [
11201    {"bits": [0, 0], "name": "PERFCOUNT_ENABLE"}
11202   ]
11203  },
11204  "COMPUTE_PGM_HI": {
11205   "fields": [
11206    {"bits": [0, 7], "name": "DATA"}
11207   ]
11208  },
11209  "COMPUTE_PGM_RSRC1": {
11210   "fields": [
11211    {"bits": [0, 5], "name": "VGPRS"},
11212    {"bits": [6, 9], "name": "SGPRS"},
11213    {"bits": [10, 11], "name": "PRIORITY"},
11214    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
11215    {"bits": [20, 20], "name": "PRIV"},
11216    {"bits": [21, 21], "name": "DX10_CLAMP"},
11217    {"bits": [23, 23], "name": "IEEE_MODE"},
11218    {"bits": [24, 24], "name": "BULKY"},
11219    {"bits": [26, 26], "name": "FP16_OVFL"},
11220    {"bits": [29, 29], "name": "WGP_MODE"},
11221    {"bits": [30, 30], "name": "MEM_ORDERED"},
11222    {"bits": [31, 31], "name": "FWD_PROGRESS"}
11223   ]
11224  },
11225  "COMPUTE_PGM_RSRC2": {
11226   "fields": [
11227    {"bits": [0, 0], "name": "SCRATCH_EN"},
11228    {"bits": [1, 5], "name": "USER_SGPR"},
11229    {"bits": [6, 6], "name": "TRAP_PRESENT"},
11230    {"bits": [7, 7], "name": "TGID_X_EN"},
11231    {"bits": [8, 8], "name": "TGID_Y_EN"},
11232    {"bits": [9, 9], "name": "TGID_Z_EN"},
11233    {"bits": [10, 10], "name": "TG_SIZE_EN"},
11234    {"bits": [11, 12], "name": "TIDIG_COMP_CNT"},
11235    {"bits": [13, 14], "name": "EXCP_EN_MSB"},
11236    {"bits": [15, 23], "name": "LDS_SIZE"},
11237    {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}
11238   ]
11239  },
11240  "COMPUTE_PGM_RSRC3": {
11241   "fields": [
11242    {"bits": [0, 3], "name": "SHARED_VGPR_CNT"},
11243    {"bits": [4, 9], "name": "INST_PREF_SIZE"},
11244    {"bits": [10, 10], "name": "TRAP_ON_START"},
11245    {"bits": [11, 11], "name": "TRAP_ON_END"},
11246    {"bits": [31, 31], "name": "IMAGE_OP"}
11247   ]
11248  },
11249  "COMPUTE_PIPELINESTAT_ENABLE": {
11250   "fields": [
11251    {"bits": [0, 0], "name": "PIPELINESTAT_ENABLE"}
11252   ]
11253  },
11254  "COMPUTE_RELAUNCH": {
11255   "fields": [
11256    {"bits": [0, 29], "name": "PAYLOAD"},
11257    {"bits": [30, 30], "name": "IS_EVENT"},
11258    {"bits": [31, 31], "name": "IS_STATE"}
11259   ]
11260  },
11261  "COMPUTE_REQ_CTRL": {
11262   "fields": [
11263    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
11264    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
11265    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
11266    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
11267    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
11268    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
11269    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
11270    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"},
11271    {"bits": [20, 26], "name": "DEDICATED_PREALLOCATION_BUFFER_LIMIT"}
11272   ]
11273  },
11274  "COMPUTE_RESOURCE_LIMITS": {
11275   "fields": [
11276    {"bits": [0, 9], "name": "WAVES_PER_SH"},
11277    {"bits": [12, 15], "name": "TG_PER_CU"},
11278    {"bits": [16, 21], "name": "LOCK_THRESHOLD"},
11279    {"bits": [22, 22], "name": "SIMD_DEST_CNTL"},
11280    {"bits": [23, 23], "name": "FORCE_SIMD_DIST"},
11281    {"bits": [24, 26], "name": "CU_GROUP_COUNT"}
11282   ]
11283  },
11284  "COMPUTE_STATIC_THREAD_MGMT_SE4": {
11285   "fields": [
11286    {"bits": [0, 15], "name": "SA0_CU_EN"},
11287    {"bits": [16, 31], "name": "SA1_CU_EN"}
11288   ]
11289  },
11290  "COMPUTE_THREAD_TRACE_ENABLE": {
11291   "fields": [
11292    {"bits": [0, 0], "name": "THREAD_TRACE_ENABLE"}
11293   ]
11294  },
11295  "COMPUTE_TMPRING_SIZE": {
11296   "fields": [
11297    {"bits": [0, 11], "name": "WAVES"},
11298    {"bits": [12, 26], "name": "WAVESIZE"}
11299   ]
11300  },
11301  "COMPUTE_VMID": {
11302   "fields": [
11303    {"bits": [0, 3], "name": "DATA"}
11304   ]
11305  },
11306  "COMPUTE_WAVE_RESTORE_ADDR_HI": {
11307   "fields": [
11308    {"bits": [0, 15], "name": "ADDR"}
11309   ]
11310  },
11311  "CPF_LATENCY_STATS_SELECT": {
11312   "fields": [
11313    {"bits": [0, 3], "name": "INDEX"},
11314    {"bits": [30, 30], "name": "CLEAR"},
11315    {"bits": [31, 31], "name": "ENABLE"}
11316   ]
11317  },
11318  "CPF_TC_PERF_COUNTER_WINDOW_SELECT": {
11319   "fields": [
11320    {"bits": [0, 2], "name": "INDEX"},
11321    {"bits": [30, 30], "name": "ALWAYS"},
11322    {"bits": [31, 31], "name": "ENABLE"}
11323   ]
11324  },
11325  "CPG_LATENCY_STATS_SELECT": {
11326   "fields": [
11327    {"bits": [0, 4], "name": "INDEX"},
11328    {"bits": [30, 30], "name": "CLEAR"},
11329    {"bits": [31, 31], "name": "ENABLE"}
11330   ]
11331  },
11332  "CPG_PERFCOUNTER0_SELECT": {
11333   "fields": [
11334    {"bits": [0, 9], "name": "PERF_SEL"},
11335    {"bits": [10, 19], "name": "PERF_SEL1"},
11336    {"bits": [20, 23], "name": "SPM_MODE"},
11337    {"bits": [24, 27], "name": "CNTR_MODE1"},
11338    {"bits": [28, 31], "name": "CNTR_MODE0"}
11339   ]
11340  },
11341  "CPG_PERFCOUNTER0_SELECT1": {
11342   "fields": [
11343    {"bits": [0, 9], "name": "PERF_SEL2"},
11344    {"bits": [10, 19], "name": "PERF_SEL3"},
11345    {"bits": [24, 27], "name": "CNTR_MODE3"},
11346    {"bits": [28, 31], "name": "CNTR_MODE2"}
11347   ]
11348  },
11349  "CPG_PERFCOUNTER1_SELECT": {
11350   "fields": [
11351    {"bits": [0, 9], "name": "PERF_SEL"},
11352    {"bits": [20, 23], "name": "SPM_MODE"},
11353    {"bits": [28, 31], "name": "CNTR_MODE"}
11354   ]
11355  },
11356  "CPG_TC_PERF_COUNTER_WINDOW_SELECT": {
11357   "fields": [
11358    {"bits": [0, 4], "name": "INDEX"},
11359    {"bits": [30, 30], "name": "ALWAYS"},
11360    {"bits": [31, 31], "name": "ENABLE"}
11361   ]
11362  },
11363  "CP_APPEND_ADDR_HI": {
11364   "fields": [
11365    {"bits": [0, 15], "name": "MEM_ADDR_HI"},
11366    {"bits": [16, 17], "name": "CS_PS_SEL"},
11367    {"bits": [18, 18], "name": "FENCE_SIZE"},
11368    {"bits": [19, 19], "name": "PWS_ENABLE"},
11369    {"bits": [25, 26], "name": "CACHE_POLICY"},
11370    {"bits": [29, 31], "name": "COMMAND"}
11371   ]
11372  },
11373  "CP_APPEND_ADDR_LO": {
11374   "fields": [
11375    {"bits": [2, 31], "name": "MEM_ADDR_LO"}
11376   ]
11377  },
11378  "CP_CPC_BUSY_STAT": {
11379   "fields": [
11380    {"bits": [0, 0], "name": "MEC1_LOAD_BUSY"},
11381    {"bits": [1, 1], "name": "MEC1_SEMAPHORE_BUSY"},
11382    {"bits": [2, 2], "name": "MEC1_MUTEX_BUSY"},
11383    {"bits": [3, 3], "name": "MEC1_MESSAGE_BUSY"},
11384    {"bits": [4, 4], "name": "MEC1_EOP_QUEUE_BUSY"},
11385    {"bits": [5, 5], "name": "MEC1_IQ_QUEUE_BUSY"},
11386    {"bits": [6, 6], "name": "MEC1_IB_QUEUE_BUSY"},
11387    {"bits": [7, 7], "name": "MEC1_TC_BUSY"},
11388    {"bits": [8, 8], "name": "MEC1_DMA_BUSY"},
11389    {"bits": [9, 9], "name": "MEC1_PARTIAL_FLUSH_BUSY"},
11390    {"bits": [10, 10], "name": "MEC1_PIPE0_BUSY"},
11391    {"bits": [11, 11], "name": "MEC1_PIPE1_BUSY"},
11392    {"bits": [12, 12], "name": "MEC1_PIPE2_BUSY"},
11393    {"bits": [13, 13], "name": "MEC1_PIPE3_BUSY"},
11394    {"bits": [16, 16], "name": "MEC2_LOAD_BUSY"},
11395    {"bits": [17, 17], "name": "MEC2_SEMAPHORE_BUSY"},
11396    {"bits": [18, 18], "name": "MEC2_MUTEX_BUSY"},
11397    {"bits": [19, 19], "name": "MEC2_MESSAGE_BUSY"},
11398    {"bits": [20, 20], "name": "MEC2_EOP_QUEUE_BUSY"},
11399    {"bits": [21, 21], "name": "MEC2_IQ_QUEUE_BUSY"},
11400    {"bits": [22, 22], "name": "MEC2_IB_QUEUE_BUSY"},
11401    {"bits": [23, 23], "name": "MEC2_TC_BUSY"},
11402    {"bits": [24, 24], "name": "MEC2_DMA_BUSY"},
11403    {"bits": [25, 25], "name": "MEC2_PARTIAL_FLUSH_BUSY"},
11404    {"bits": [26, 26], "name": "MEC2_PIPE0_BUSY"},
11405    {"bits": [27, 27], "name": "MEC2_PIPE1_BUSY"},
11406    {"bits": [28, 28], "name": "MEC2_PIPE2_BUSY"},
11407    {"bits": [29, 29], "name": "MEC2_PIPE3_BUSY"}
11408   ]
11409  },
11410  "CP_CPC_BUSY_STAT2": {
11411   "fields": [
11412    {"bits": [0, 0], "name": "MES_LOAD_BUSY"},
11413    {"bits": [2, 2], "name": "MES_MUTEX_BUSY"},
11414    {"bits": [3, 3], "name": "MES_MESSAGE_BUSY"},
11415    {"bits": [7, 7], "name": "MES_TC_BUSY"},
11416    {"bits": [8, 8], "name": "MES_DMA_BUSY"},
11417    {"bits": [10, 10], "name": "MES_PIPE0_BUSY"},
11418    {"bits": [11, 11], "name": "MES_PIPE1_BUSY"},
11419    {"bits": [12, 12], "name": "MES_PIPE2_BUSY"},
11420    {"bits": [13, 13], "name": "MES_PIPE3_BUSY"}
11421   ]
11422  },
11423  "CP_CPC_DEBUG_CNTL": {
11424   "fields": [
11425    {"bits": [0, 6], "name": "DEBUG_INDX"}
11426   ]
11427  },
11428  "CP_CPC_GRBM_FREE_COUNT": {
11429   "fields": [
11430    {"bits": [0, 5], "name": "FREE_COUNT"}
11431   ]
11432  },
11433  "CP_CPC_HALT_HYST_COUNT": {
11434   "fields": [
11435    {"bits": [0, 3], "name": "COUNT"}
11436   ]
11437  },
11438  "CP_CPC_PRIV_VIOLATION_ADDR": {
11439   "fields": [
11440    {"bits": [0, 17], "name": "PRIV_VIOLATION_ADDR"}
11441   ]
11442  },
11443  "CP_CPC_SCRATCH_INDEX": {
11444   "fields": [
11445    {"bits": [0, 8], "name": "SCRATCH_INDEX"},
11446    {"bits": [31, 31], "name": "SCRATCH_INDEX_64BIT_MODE"}
11447   ]
11448  },
11449  "CP_CPC_STALLED_STAT1": {
11450   "fields": [
11451    {"bits": [3, 3], "name": "RCIU_TX_FREE_STALL"},
11452    {"bits": [4, 4], "name": "RCIU_PRIV_VIOLATION"},
11453    {"bits": [6, 6], "name": "TCIU_TX_FREE_STALL"},
11454    {"bits": [7, 7], "name": "TCIU_WAITING_ON_TAGS"},
11455    {"bits": [8, 8], "name": "MEC1_DECODING_PACKET"},
11456    {"bits": [9, 9], "name": "MEC1_WAIT_ON_RCIU"},
11457    {"bits": [10, 10], "name": "MEC1_WAIT_ON_RCIU_READ"},
11458    {"bits": [13, 13], "name": "MEC1_WAIT_ON_ROQ_DATA"},
11459    {"bits": [16, 16], "name": "MEC2_DECODING_PACKET"},
11460    {"bits": [17, 17], "name": "MEC2_WAIT_ON_RCIU"},
11461    {"bits": [18, 18], "name": "MEC2_WAIT_ON_RCIU_READ"},
11462    {"bits": [21, 21], "name": "MEC2_WAIT_ON_ROQ_DATA"},
11463    {"bits": [22, 22], "name": "UTCL2IU_WAITING_ON_FREE"},
11464    {"bits": [23, 23], "name": "UTCL2IU_WAITING_ON_TAGS"},
11465    {"bits": [24, 24], "name": "UTCL1_WAITING_ON_TRANS"},
11466    {"bits": [25, 25], "name": "GCRIU_WAITING_ON_FREE"}
11467   ]
11468  },
11469  "CP_CPC_STATUS": {
11470   "fields": [
11471    {"bits": [0, 0], "name": "MEC1_BUSY"},
11472    {"bits": [1, 1], "name": "MEC2_BUSY"},
11473    {"bits": [2, 2], "name": "DC0_BUSY"},
11474    {"bits": [3, 3], "name": "DC1_BUSY"},
11475    {"bits": [4, 4], "name": "RCIU1_BUSY"},
11476    {"bits": [5, 5], "name": "RCIU2_BUSY"},
11477    {"bits": [6, 6], "name": "ROQ1_BUSY"},
11478    {"bits": [7, 7], "name": "ROQ2_BUSY"},
11479    {"bits": [10, 10], "name": "TCIU_BUSY"},
11480    {"bits": [11, 11], "name": "SCRATCH_RAM_BUSY"},
11481    {"bits": [12, 12], "name": "QU_BUSY"},
11482    {"bits": [13, 13], "name": "UTCL2IU_BUSY"},
11483    {"bits": [14, 14], "name": "SAVE_RESTORE_BUSY"},
11484    {"bits": [15, 15], "name": "GCRIU_BUSY"},
11485    {"bits": [16, 16], "name": "MES_BUSY"},
11486    {"bits": [17, 17], "name": "MES_SCRATCH_RAM_BUSY"},
11487    {"bits": [18, 18], "name": "RCIU3_BUSY"},
11488    {"bits": [19, 19], "name": "MES_INSTRUCTION_CACHE_BUSY"},
11489    {"bits": [20, 20], "name": "MES_DATA_CACHE_BUSY"},
11490    {"bits": [21, 21], "name": "MEC_DATA_CACHE_BUSY"},
11491    {"bits": [29, 29], "name": "CPG_CPC_BUSY"},
11492    {"bits": [30, 30], "name": "CPF_CPC_BUSY"},
11493    {"bits": [31, 31], "name": "CPC_BUSY"}
11494   ]
11495  },
11496  "CP_CPF_BUSY_STAT": {
11497   "fields": [
11498    {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"},
11499    {"bits": [1, 1], "name": "CSF_RING_BUSY"},
11500    {"bits": [2, 2], "name": "CSF_INDIRECT1_BUSY"},
11501    {"bits": [3, 3], "name": "CSF_INDIRECT2_BUSY"},
11502    {"bits": [4, 4], "name": "CSF_STATE_BUSY"},
11503    {"bits": [5, 5], "name": "CSF_CE_INDR1_BUSY"},
11504    {"bits": [6, 6], "name": "CSF_CE_INDR2_BUSY"},
11505    {"bits": [7, 7], "name": "CSF_ARBITER_BUSY"},
11506    {"bits": [8, 8], "name": "CSF_INPUT_BUSY"},
11507    {"bits": [9, 9], "name": "CSF_DATA_BUSY"},
11508    {"bits": [10, 10], "name": "CSF_CE_DATA_BUSY"},
11509    {"bits": [11, 11], "name": "HPD_PROCESSING_EOP_BUSY"},
11510    {"bits": [12, 12], "name": "HQD_DISPATCH_BUSY"},
11511    {"bits": [13, 13], "name": "HQD_IQ_TIMER_BUSY"},
11512    {"bits": [14, 14], "name": "HQD_DMA_OFFLOAD_BUSY"},
11513    {"bits": [15, 15], "name": "HQD_WAIT_SEMAPHORE_BUSY"},
11514    {"bits": [16, 16], "name": "HQD_SIGNAL_SEMAPHORE_BUSY"},
11515    {"bits": [17, 17], "name": "HQD_MESSAGE_BUSY"},
11516    {"bits": [18, 18], "name": "HQD_PQ_FETCHER_BUSY"},
11517    {"bits": [19, 19], "name": "HQD_IB_FETCHER_BUSY"},
11518    {"bits": [20, 20], "name": "HQD_IQ_FETCHER_BUSY"},
11519    {"bits": [21, 21], "name": "HQD_EOP_FETCHER_BUSY"},
11520    {"bits": [22, 22], "name": "HQD_CONSUMED_RPTR_BUSY"},
11521    {"bits": [23, 23], "name": "HQD_FETCHER_ARB_BUSY"},
11522    {"bits": [24, 24], "name": "HQD_ROQ_ALIGN_BUSY"},
11523    {"bits": [25, 25], "name": "HQD_ROQ_EOP_BUSY"},
11524    {"bits": [26, 26], "name": "HQD_ROQ_IQ_BUSY"},
11525    {"bits": [27, 27], "name": "HQD_ROQ_PQ_BUSY"},
11526    {"bits": [28, 28], "name": "HQD_ROQ_IB_BUSY"},
11527    {"bits": [29, 29], "name": "HQD_WPTR_POLL_BUSY"},
11528    {"bits": [30, 30], "name": "HQD_PQ_BUSY"},
11529    {"bits": [31, 31], "name": "HQD_IB_BUSY"}
11530   ]
11531  },
11532  "CP_CPF_BUSY_STAT2": {
11533   "fields": [
11534    {"bits": [0, 0], "name": "CP_SDMA_CPG_BUSY"},
11535    {"bits": [1, 1], "name": "CP_SDMA_CPC_BUSY"},
11536    {"bits": [12, 12], "name": "MES_HQD_DISPATCH_BUSY"},
11537    {"bits": [14, 14], "name": "MES_HQD_DMA_OFFLOAD_BUSY"},
11538    {"bits": [17, 17], "name": "MES_HQD_MESSAGE_BUSY"},
11539    {"bits": [18, 18], "name": "MES_HQD_PQ_FETCHER_BUSY"},
11540    {"bits": [22, 22], "name": "MES_HQD_CONSUMED_RPTR_BUSY"},
11541    {"bits": [23, 23], "name": "MES_HQD_FETCHER_ARB_BUSY"},
11542    {"bits": [24, 24], "name": "MES_HQD_ROQ_ALIGN_BUSY"},
11543    {"bits": [27, 27], "name": "MES_HQD_ROQ_PQ_BUSY"},
11544    {"bits": [30, 30], "name": "MES_HQD_PQ_BUSY"}
11545   ]
11546  },
11547  "CP_CPF_GRBM_FREE_COUNT": {
11548   "fields": [
11549    {"bits": [0, 2], "name": "FREE_COUNT"}
11550   ]
11551  },
11552  "CP_CPF_STALLED_STAT1": {
11553   "fields": [
11554    {"bits": [0, 0], "name": "RING_FETCHING_DATA"},
11555    {"bits": [1, 1], "name": "INDR1_FETCHING_DATA"},
11556    {"bits": [2, 2], "name": "INDR2_FETCHING_DATA"},
11557    {"bits": [3, 3], "name": "STATE_FETCHING_DATA"},
11558    {"bits": [5, 5], "name": "TCIU_WAITING_ON_FREE"},
11559    {"bits": [6, 6], "name": "TCIU_WAITING_ON_TAGS"},
11560    {"bits": [7, 7], "name": "UTCL2IU_WAITING_ON_FREE"},
11561    {"bits": [8, 8], "name": "UTCL2IU_WAITING_ON_TAGS"},
11562    {"bits": [9, 9], "name": "GFX_UTCL1_WAITING_ON_TRANS"},
11563    {"bits": [10, 10], "name": "CMP_UTCL1_WAITING_ON_TRANS"},
11564    {"bits": [11, 11], "name": "RCIU_WAITING_ON_FREE"},
11565    {"bits": [12, 12], "name": "DATA_FETCHING_DATA"},
11566    {"bits": [13, 13], "name": "GCRIU_WAIT_ON_FREE"}
11567   ]
11568  },
11569  "CP_CPF_STATUS": {
11570   "fields": [
11571    {"bits": [0, 0], "name": "POST_WPTR_GFX_BUSY"},
11572    {"bits": [1, 1], "name": "CSF_BUSY"},
11573    {"bits": [4, 4], "name": "ROQ_ALIGN_BUSY"},
11574    {"bits": [5, 5], "name": "ROQ_RING_BUSY"},
11575    {"bits": [6, 6], "name": "ROQ_INDIRECT1_BUSY"},
11576    {"bits": [7, 7], "name": "ROQ_INDIRECT2_BUSY"},
11577    {"bits": [8, 8], "name": "ROQ_STATE_BUSY"},
11578    {"bits": [9, 9], "name": "ROQ_CE_RING_BUSY"},
11579    {"bits": [10, 10], "name": "ROQ_CE_INDIRECT1_BUSY"},
11580    {"bits": [11, 11], "name": "ROQ_CE_INDIRECT2_BUSY"},
11581    {"bits": [12, 12], "name": "SEMAPHORE_BUSY"},
11582    {"bits": [13, 13], "name": "INTERRUPT_BUSY"},
11583    {"bits": [14, 14], "name": "TCIU_BUSY"},
11584    {"bits": [15, 15], "name": "HQD_BUSY"},
11585    {"bits": [16, 16], "name": "PRT_BUSY"},
11586    {"bits": [17, 17], "name": "UTCL2IU_BUSY"},
11587    {"bits": [18, 18], "name": "RCIU_BUSY"},
11588    {"bits": [19, 19], "name": "RCIU_GFX_BUSY"},
11589    {"bits": [20, 20], "name": "RCIU_CMP_BUSY"},
11590    {"bits": [21, 21], "name": "ROQ_DATA_BUSY"},
11591    {"bits": [22, 22], "name": "ROQ_CE_DATA_BUSY"},
11592    {"bits": [23, 23], "name": "GCRIU_BUSY"},
11593    {"bits": [24, 24], "name": "MES_HQD_BUSY"},
11594    {"bits": [26, 26], "name": "CPF_GFX_BUSY"},
11595    {"bits": [27, 27], "name": "CPF_CMP_BUSY"},
11596    {"bits": [28, 29], "name": "GRBM_CPF_STAT_BUSY"},
11597    {"bits": [30, 30], "name": "CPC_CPF_BUSY"},
11598    {"bits": [31, 31], "name": "CPF_BUSY"}
11599   ]
11600  },
11601  "CP_DB_BASE_HI": {
11602   "fields": [
11603    {"bits": [0, 15], "name": "DB_BASE_HI"}
11604   ]
11605  },
11606  "CP_DB_BASE_LO": {
11607   "fields": [
11608    {"bits": [2, 31], "name": "DB_BASE_LO"}
11609   ]
11610  },
11611  "CP_DB_BUFSZ": {
11612   "fields": [
11613    {"bits": [0, 19], "name": "DB_BUFSZ"}
11614   ]
11615  },
11616  "CP_DB_CMD_BUFSZ": {
11617   "fields": [
11618    {"bits": [0, 19], "name": "DB_CMD_REQSZ"}
11619   ]
11620  },
11621  "CP_DMA_CNTL": {
11622   "fields": [
11623    {"bits": [0, 0], "name": "UTCL1_FAULT_CONTROL"},
11624    {"bits": [1, 1], "name": "WATCH_CONTROL"},
11625    {"bits": [4, 5], "name": "MIN_AVAILSZ"},
11626    {"bits": [16, 24], "name": "BUFFER_DEPTH"},
11627    {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"},
11628    {"bits": [29, 29], "name": "PIO_FIFO_FULL"},
11629    {"bits": [30, 31], "name": "PIO_COUNT"}
11630   ]
11631  },
11632  "CP_DMA_ME_CMD_ADDR_HI": {
11633   "fields": [
11634    {"bits": [0, 15], "name": "ADDR_HI"},
11635    {"bits": [16, 31], "name": "RSVD"}
11636   ]
11637  },
11638  "CP_DMA_ME_CMD_ADDR_LO": {
11639   "fields": [
11640    {"bits": [0, 1], "name": "RSVD"},
11641    {"bits": [2, 31], "name": "ADDR_LO"}
11642   ]
11643  },
11644  "CP_DMA_ME_COMMAND": {
11645   "fields": [
11646    {"bits": [0, 25], "name": "BYTE_COUNT"},
11647    {"bits": [26, 26], "name": "SAS"},
11648    {"bits": [27, 27], "name": "DAS"},
11649    {"bits": [28, 28], "name": "SAIC"},
11650    {"bits": [29, 29], "name": "DAIC"},
11651    {"bits": [30, 30], "name": "RAW_WAIT"},
11652    {"bits": [31, 31], "name": "DIS_WC"}
11653   ]
11654  },
11655  "CP_DMA_ME_DST_ADDR_HI": {
11656   "fields": [
11657    {"bits": [0, 15], "name": "DST_ADDR_HI"}
11658   ]
11659  },
11660  "CP_DMA_ME_SRC_ADDR_HI": {
11661   "fields": [
11662    {"bits": [0, 15], "name": "SRC_ADDR_HI"}
11663   ]
11664  },
11665  "CP_DMA_PFP_CONTROL": {
11666   "fields": [
11667    {"bits": [0, 3], "name": "VMID"},
11668    {"bits": [4, 4], "name": "TMZ"},
11669    {"bits": [10, 10], "name": "MEMLOG_CLEAR"},
11670    {"bits": [13, 14], "name": "SRC_CACHE_POLICY"},
11671    {"bits": [15, 15], "name": "SRC_VOLATLE"},
11672    {"bits": [20, 21], "name": "DST_SELECT"},
11673    {"bits": [25, 26], "name": "DST_CACHE_POLICY"},
11674    {"bits": [27, 27], "name": "DST_VOLATLE"},
11675    {"bits": [29, 30], "name": "SRC_SELECT"}
11676   ]
11677  },
11678  "CP_DMA_READ_TAGS": {
11679   "fields": [
11680    {"bits": [0, 25], "name": "DMA_READ_TAG"},
11681    {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"}
11682   ]
11683  },
11684  "CP_DRAW_WINDOW_CNTL": {
11685   "fields": [
11686    {"bits": [0, 0], "name": "DISABLE_DRAW_WINDOW_LO_MAX"},
11687    {"bits": [1, 1], "name": "DISABLE_DRAW_WINDOW_LO_MIN"},
11688    {"bits": [2, 2], "name": "DISABLE_DRAW_WINDOW_HI"},
11689    {"bits": [8, 8], "name": "MODE"}
11690   ]
11691  },
11692  "CP_DRAW_WINDOW_LO": {
11693   "fields": [
11694    {"bits": [0, 15], "name": "MIN"},
11695    {"bits": [16, 31], "name": "MAX"}
11696   ]
11697  },
11698  "CP_EOP_DONE_ADDR_HI": {
11699   "fields": [
11700    {"bits": [0, 15], "name": "ADDR_HI"}
11701   ]
11702  },
11703  "CP_EOP_DONE_ADDR_LO": {
11704   "fields": [
11705    {"bits": [2, 31], "name": "ADDR_LO"}
11706   ]
11707  },
11708  "CP_EOP_DONE_DATA_CNTL": {
11709   "fields": [
11710    {"bits": [16, 17], "name": "DST_SEL"},
11711    {"bits": [19, 19], "name": "SEMAPHORE_SIGNAL_TYPE"},
11712    {"bits": [20, 21], "name": "ACTION_PIPE_ID"},
11713    {"bits": [22, 23], "name": "ACTION_ID"},
11714    {"bits": [24, 26], "name": "INT_SEL"},
11715    {"bits": [29, 31], "name": "DATA_SEL"}
11716   ]
11717  },
11718  "CP_EOP_DONE_EVENT_CNTL": {
11719   "fields": [
11720    {"bits": [12, 24], "name": "GCR_CNTL"},
11721    {"bits": [25, 26], "name": "CACHE_POLICY"},
11722    {"bits": [27, 27], "name": "EOP_VOLATILE"},
11723    {"bits": [28, 28], "name": "EXECUTE"},
11724    {"bits": [30, 30], "name": "GLK_INV"},
11725    {"bits": [31, 31], "name": "PWS_ENABLE"}
11726   ]
11727  },
11728  "CP_IB2_BASE_HI": {
11729   "fields": [
11730    {"bits": [0, 15], "name": "IB2_BASE_HI"}
11731   ]
11732  },
11733  "CP_IB2_BASE_LO": {
11734   "fields": [
11735    {"bits": [2, 31], "name": "IB2_BASE_LO"}
11736   ]
11737  },
11738  "CP_IB2_BUFSZ": {
11739   "fields": [
11740    {"bits": [0, 19], "name": "IB2_BUFSZ"}
11741   ]
11742  },
11743  "CP_IB2_CMD_BUFSZ": {
11744   "fields": [
11745    {"bits": [0, 19], "name": "IB2_CMD_REQSZ"}
11746   ]
11747  },
11748  "CP_IB2_OFFSET": {
11749   "fields": [
11750    {"bits": [0, 19], "name": "IB2_OFFSET"}
11751   ]
11752  },
11753  "CP_IB2_PREAMBLE_BEGIN": {
11754   "fields": [
11755    {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"}
11756   ]
11757  },
11758  "CP_IB2_PREAMBLE_END": {
11759   "fields": [
11760    {"bits": [0, 19], "name": "IB2_PREAMBLE_END"}
11761   ]
11762  },
11763  "CP_INDEX_TYPE": {
11764   "fields": [
11765    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}
11766   ]
11767  },
11768  "CP_ME_COHER_BASE_HI": {
11769   "fields": [
11770    {"bits": [0, 7], "name": "COHER_BASE_HI_256B"}
11771   ]
11772  },
11773  "CP_ME_COHER_CNTL": {
11774   "fields": [
11775    {"bits": [0, 0], "name": "DEST_BASE_0_ENA"},
11776    {"bits": [1, 1], "name": "DEST_BASE_1_ENA"},
11777    {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"},
11778    {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"},
11779    {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"},
11780    {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"},
11781    {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"},
11782    {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"},
11783    {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"},
11784    {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"},
11785    {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"},
11786    {"bits": [19, 19], "name": "DEST_BASE_2_ENA"},
11787    {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}
11788   ]
11789  },
11790  "CP_ME_COHER_SIZE_HI": {
11791   "fields": [
11792    {"bits": [0, 7], "name": "COHER_SIZE_HI_256B"}
11793   ]
11794  },
11795  "CP_ME_COHER_STATUS": {
11796   "fields": [
11797    {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"},
11798    {"bits": [31, 31], "name": "STATUS"}
11799   ]
11800  },
11801  "CP_ME_MC_RADDR_HI": {
11802   "fields": [
11803    {"bits": [0, 15], "name": "ME_MC_RADDR_HI"},
11804    {"bits": [16, 19], "name": "SIZE"},
11805    {"bits": [22, 23], "name": "CACHE_POLICY"},
11806    {"bits": [24, 27], "name": "VMID"},
11807    {"bits": [31, 31], "name": "PRIVILEGE"}
11808   ]
11809  },
11810  "CP_ME_MC_RADDR_LO": {
11811   "fields": [
11812    {"bits": [2, 31], "name": "ME_MC_RADDR_LO"}
11813   ]
11814  },
11815  "CP_ME_MC_WADDR_HI": {
11816   "fields": [
11817    {"bits": [0, 15], "name": "ME_MC_WADDR_HI"},
11818    {"bits": [17, 17], "name": "WRITE_CONFIRM"},
11819    {"bits": [18, 18], "name": "WRITE64"},
11820    {"bits": [22, 23], "name": "CACHE_POLICY"},
11821    {"bits": [24, 27], "name": "VMID"},
11822    {"bits": [28, 29], "name": "RINGID"},
11823    {"bits": [31, 31], "name": "PRIVILEGE"}
11824   ]
11825  },
11826  "CP_ME_MC_WADDR_LO": {
11827   "fields": [
11828    {"bits": [2, 31], "name": "ME_MC_WADDR_LO"}
11829   ]
11830  },
11831  "CP_PERFMON_CNTL": {
11832   "fields": [
11833    {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
11834    {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"},
11835    {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"},
11836    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
11837   ]
11838  },
11839  "CP_PERFMON_CNTX_CNTL": {
11840   "fields": [
11841    {"bits": [31, 31], "name": "PERFMON_ENABLE"}
11842   ]
11843  },
11844  "CP_PFP_COMPLETION_STATUS": {
11845   "fields": [
11846    {"bits": [0, 1], "name": "STATUS"}
11847   ]
11848  },
11849  "CP_PFP_IB_CONTROL": {
11850   "fields": [
11851    {"bits": [0, 7], "name": "IB_EN"}
11852   ]
11853  },
11854  "CP_PFP_LOAD_CONTROL": {
11855   "fields": [
11856    {"bits": [0, 0], "name": "CONFIG_REG_EN"},
11857    {"bits": [1, 1], "name": "CNTX_REG_EN"},
11858    {"bits": [15, 15], "name": "UCONFIG_REG_EN"},
11859    {"bits": [16, 16], "name": "SH_GFX_REG_EN"},
11860    {"bits": [24, 24], "name": "SH_CS_REG_EN"},
11861    {"bits": [31, 31], "name": "LOAD_ORDINAL"}
11862   ]
11863  },
11864  "CP_PIPEID": {
11865   "fields": [
11866    {"bits": [0, 1], "name": "PIPE_ID"}
11867   ]
11868  },
11869  "CP_PIPE_STATS_ADDR_HI": {
11870   "fields": [
11871    {"bits": [0, 15], "name": "PIPE_STATS_ADDR_HI"}
11872   ]
11873  },
11874  "CP_PIPE_STATS_ADDR_LO": {
11875   "fields": [
11876    {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"}
11877   ]
11878  },
11879  "CP_PIPE_STATS_CONTROL": {
11880   "fields": [
11881    {"bits": [25, 26], "name": "CACHE_POLICY"}
11882   ]
11883  },
11884  "CP_PRED_NOT_VISIBLE": {
11885   "fields": [
11886    {"bits": [0, 0], "name": "NOT_VISIBLE"}
11887   ]
11888  },
11889  "CP_RB_OFFSET": {
11890   "fields": [
11891    {"bits": [0, 19], "name": "RB_OFFSET"}
11892   ]
11893  },
11894  "CP_SAMPLE_STATUS": {
11895   "fields": [
11896    {"bits": [0, 0], "name": "Z_PASS_ACITVE"},
11897    {"bits": [1, 1], "name": "STREAMOUT_ACTIVE"},
11898    {"bits": [2, 2], "name": "PIPELINE_ACTIVE"},
11899    {"bits": [3, 3], "name": "STIPPLE_ACTIVE"},
11900    {"bits": [4, 4], "name": "VGT_BUFFERS_ACTIVE"},
11901    {"bits": [5, 5], "name": "SCREEN_EXT_ACTIVE"},
11902    {"bits": [6, 6], "name": "DRAW_INDIRECT_ACTIVE"},
11903    {"bits": [7, 7], "name": "DISP_INDIRECT_ACTIVE"}
11904   ]
11905  },
11906  "CP_SIG_SEM_ADDR_HI": {
11907   "fields": [
11908    {"bits": [0, 15], "name": "SEM_ADDR_HI"},
11909    {"bits": [16, 16], "name": "SEM_USE_MAILBOX"},
11910    {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"},
11911    {"bits": [24, 25], "name": "SEM_CLIENT_CODE"},
11912    {"bits": [29, 31], "name": "SEM_SELECT"}
11913   ]
11914  },
11915  "CP_SIG_SEM_ADDR_LO": {
11916   "fields": [
11917    {"bits": [0, 0], "name": "SEM_PRIV"},
11918    {"bits": [3, 31], "name": "SEM_ADDR_LO"}
11919   ]
11920  },
11921  "CP_ST_BASE_HI": {
11922   "fields": [
11923    {"bits": [0, 15], "name": "ST_BASE_HI"}
11924   ]
11925  },
11926  "CP_ST_BASE_LO": {
11927   "fields": [
11928    {"bits": [2, 31], "name": "ST_BASE_LO"}
11929   ]
11930  },
11931  "CP_ST_BUFSZ": {
11932   "fields": [
11933    {"bits": [0, 19], "name": "ST_BUFSZ"}
11934   ]
11935  },
11936  "CP_ST_CMD_BUFSZ": {
11937   "fields": [
11938    {"bits": [0, 19], "name": "ST_CMD_REQSZ"}
11939   ]
11940  },
11941  "CP_VMID": {
11942   "fields": [
11943    {"bits": [0, 3], "name": "VMID"}
11944   ]
11945  },
11946  "DB_ALPHA_TO_MASK": {
11947   "fields": [
11948    {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"},
11949    {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"},
11950    {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"},
11951    {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"},
11952    {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"},
11953    {"bits": [16, 16], "name": "OFFSET_ROUND"}
11954   ]
11955  },
11956  "DB_COUNT_CONTROL": {
11957   "fields": [
11958    {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"},
11959    {"bits": [2, 2], "name": "DISABLE_CONSERVATIVE_ZPASS_COUNTS"},
11960    {"bits": [3, 3], "name": "ENHANCED_CONSERVATIVE_ZPASS_COUNTS"},
11961    {"bits": [4, 6], "name": "SAMPLE_RATE"},
11962    {"bits": [8, 11], "name": "ZPASS_ENABLE"},
11963    {"bits": [12, 15], "name": "ZFAIL_ENABLE"},
11964    {"bits": [16, 19], "name": "SFAIL_ENABLE"},
11965    {"bits": [20, 23], "name": "DBFAIL_ENABLE"},
11966    {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"},
11967    {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"}
11968   ]
11969  },
11970  "DB_DEPTH_CONTROL": {
11971   "fields": [
11972    {"bits": [0, 0], "name": "STENCIL_ENABLE"},
11973    {"bits": [1, 1], "name": "Z_ENABLE"},
11974    {"bits": [2, 2], "name": "Z_WRITE_ENABLE"},
11975    {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"},
11976    {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"},
11977    {"bits": [7, 7], "name": "BACKFACE_ENABLE"},
11978    {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"},
11979    {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"},
11980    {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"},
11981    {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"}
11982   ]
11983  },
11984  "DB_DEPTH_SIZE_XY": {
11985   "fields": [
11986    {"bits": [0, 13], "name": "X_MAX"},
11987    {"bits": [16, 29], "name": "Y_MAX"}
11988   ]
11989  },
11990  "DB_DEPTH_VIEW": {
11991   "fields": [
11992    {"bits": [0, 10], "name": "SLICE_START"},
11993    {"bits": [11, 12], "name": "SLICE_START_HI"},
11994    {"bits": [13, 23], "name": "SLICE_MAX"},
11995    {"bits": [24, 24], "name": "Z_READ_ONLY"},
11996    {"bits": [25, 25], "name": "STENCIL_READ_ONLY"},
11997    {"bits": [26, 29], "name": "MIPID"},
11998    {"bits": [30, 31], "name": "SLICE_MAX_HI"}
11999   ]
12000  },
12001  "DB_EQAA": {
12002   "fields": [
12003    {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"},
12004    {"bits": [4, 6], "name": "PS_ITER_SAMPLES"},
12005    {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"},
12006    {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"},
12007    {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"},
12008    {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"},
12009    {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"},
12010    {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"},
12011    {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"},
12012    {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"},
12013    {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"},
12014    {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"}
12015   ]
12016  },
12017  "DB_HTILE_SURFACE": {
12018   "fields": [
12019    {"bits": [0, 0], "name": "RESERVED_FIELD_1"},
12020    {"bits": [1, 1], "name": "FULL_CACHE"},
12021    {"bits": [2, 2], "name": "RESERVED_FIELD_2"},
12022    {"bits": [3, 3], "name": "RESERVED_FIELD_3"},
12023    {"bits": [4, 9], "name": "RESERVED_FIELD_4"},
12024    {"bits": [10, 15], "name": "RESERVED_FIELD_5"},
12025    {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"},
12026    {"bits": [17, 17], "name": "RESERVED_FIELD_6"},
12027    {"bits": [18, 18], "name": "PIPE_ALIGNED"}
12028   ]
12029  },
12030  "DB_OCCLUSION_COUNT0_HI": {
12031   "fields": [
12032    {"bits": [0, 30], "name": "COUNT_HI"}
12033   ]
12034  },
12035  "DB_PRELOAD_CONTROL": {
12036   "fields": [
12037    {"bits": [0, 7], "name": "START_X"},
12038    {"bits": [8, 15], "name": "START_Y"},
12039    {"bits": [16, 23], "name": "MAX_X"},
12040    {"bits": [24, 31], "name": "MAX_Y"}
12041   ]
12042  },
12043  "DB_RENDER_CONTROL": {
12044   "fields": [
12045    {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"},
12046    {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"},
12047    {"bits": [2, 2], "name": "DEPTH_COPY"},
12048    {"bits": [3, 3], "name": "STENCIL_COPY"},
12049    {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"},
12050    {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"},
12051    {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"},
12052    {"bits": [7, 7], "name": "COPY_CENTROID"},
12053    {"bits": [8, 11], "name": "COPY_SAMPLE"},
12054    {"bits": [12, 12], "name": "DECOMPRESS_ENABLE"},
12055    {"bits": [14, 14], "name": "PS_INVOKE_DISABLE"},
12056    {"bits": [16, 17], "enum_ref": "OreoMode", "name": "OREO_MODE"},
12057    {"bits": [18, 18], "name": "FORCE_OREO_MODE"},
12058    {"bits": [19, 19], "name": "FORCE_EXPORT_ORDER"},
12059    {"bits": [20, 23], "name": "MAX_ALLOWED_TILES_IN_WAVE"}
12060   ]
12061  },
12062  "DB_RENDER_OVERRIDE": {
12063   "fields": [
12064    {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"},
12065    {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"},
12066    {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"},
12067    {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"},
12068    {"bits": [7, 7], "name": "FAST_Z_DISABLE"},
12069    {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"},
12070    {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"},
12071    {"bits": [10, 10], "name": "FORCE_COLOR_KILL"},
12072    {"bits": [11, 11], "name": "FORCE_Z_READ"},
12073    {"bits": [12, 12], "name": "FORCE_STENCIL_READ"},
12074    {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"},
12075    {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"},
12076    {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"},
12077    {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"},
12078    {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"},
12079    {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"},
12080    {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"},
12081    {"bits": [27, 27], "name": "FORCE_Z_DIRTY"},
12082    {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"},
12083    {"bits": [29, 29], "name": "FORCE_Z_VALID"},
12084    {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"},
12085    {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"}
12086   ]
12087  },
12088  "DB_RENDER_OVERRIDE2": {
12089   "fields": [
12090    {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"},
12091    {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"},
12092    {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"},
12093    {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"},
12094    {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"},
12095    {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"},
12096    {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"},
12097    {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"},
12098    {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"},
12099    {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"},
12100    {"bits": [15, 17], "name": "HIS_SFUNC_FF"},
12101    {"bits": [18, 20], "name": "HIS_SFUNC_BF"},
12102    {"bits": [21, 21], "name": "PRESERVE_ZRANGE"},
12103    {"bits": [22, 22], "name": "PRESERVE_SRESULTS"},
12104    {"bits": [23, 23], "name": "DISABLE_FAST_PASS"},
12105    {"bits": [25, 25], "name": "ALLOW_PARTIAL_RES_HIER_KILL"},
12106    {"bits": [27, 28], "name": "CENTROID_COMPUTATION_MODE"},
12107    {"bits": [29, 29], "name": "DISABLE_NOZ"}
12108   ]
12109  },
12110  "DB_RESERVED_REG_1": {
12111   "fields": [
12112    {"bits": [0, 10], "name": "FIELD_1"},
12113    {"bits": [11, 21], "name": "FIELD_2"}
12114   ]
12115  },
12116  "DB_RESERVED_REG_2": {
12117   "fields": [
12118    {"bits": [0, 3], "name": "FIELD_1"},
12119    {"bits": [4, 7], "name": "FIELD_2"},
12120    {"bits": [8, 12], "name": "FIELD_3"},
12121    {"bits": [13, 14], "name": "FIELD_4"},
12122    {"bits": [15, 16], "name": "FIELD_5"},
12123    {"bits": [17, 18], "name": "FIELD_6"},
12124    {"bits": [19, 20], "name": "FIELD_7"},
12125    {"bits": [28, 31], "name": "FIELD_8"}
12126   ]
12127  },
12128  "DB_RESERVED_REG_3": {
12129   "fields": [
12130    {"bits": [0, 21], "name": "FIELD_1"}
12131   ]
12132  },
12133  "DB_RMI_L2_CACHE_CONTROL": {
12134   "fields": [
12135    {"bits": [0, 1], "enum_ref": "WritePolicy", "name": "Z_WR_POLICY"},
12136    {"bits": [2, 3], "enum_ref": "WritePolicy", "name": "S_WR_POLICY"},
12137    {"bits": [4, 5], "enum_ref": "WritePolicy", "name": "HTILE_WR_POLICY"},
12138    {"bits": [6, 7], "enum_ref": "WritePolicy", "name": "ZPCPSD_WR_POLICY"},
12139    {"bits": [16, 17], "enum_ref": "ReadPolicy", "name": "Z_RD_POLICY"},
12140    {"bits": [18, 19], "enum_ref": "ReadPolicy", "name": "S_RD_POLICY"},
12141    {"bits": [20, 21], "enum_ref": "ReadPolicy", "name": "HTILE_RD_POLICY"},
12142    {"bits": [24, 24], "name": "Z_BIG_PAGE"},
12143    {"bits": [25, 25], "name": "S_BIG_PAGE"},
12144    {"bits": [26, 26], "name": "Z_NOALLOC"},
12145    {"bits": [27, 27], "name": "S_NOALLOC"},
12146    {"bits": [28, 28], "name": "HTILE_NOALLOC"},
12147    {"bits": [29, 29], "name": "ZPCPSD_NOALLOC"}
12148   ]
12149  },
12150  "DB_SHADER_CONTROL": {
12151   "fields": [
12152    {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"},
12153    {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"},
12154    {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"},
12155    {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"},
12156    {"bits": [6, 6], "name": "KILL_ENABLE"},
12157    {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"},
12158    {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"},
12159    {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"},
12160    {"bits": [10, 10], "name": "EXEC_ON_NOOP"},
12161    {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"},
12162    {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"},
12163    {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"},
12164    {"bits": [15, 15], "name": "DUAL_QUAD_DISABLE"},
12165    {"bits": [16, 16], "name": "PRIMITIVE_ORDERED_PIXEL_SHADER"},
12166    {"bits": [23, 23], "name": "PRE_SHADER_DEPTH_COVERAGE_ENABLE"},
12167    {"bits": [24, 24], "name": "OREO_BLEND_ENABLE"},
12168    {"bits": [25, 25], "name": "OVERRIDE_INTRINSIC_RATE_ENABLE"},
12169    {"bits": [26, 28], "name": "OVERRIDE_INTRINSIC_RATE"}
12170   ]
12171  },
12172  "DB_SRESULTS_COMPARE_STATE0": {
12173   "fields": [
12174    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"},
12175    {"bits": [4, 11], "name": "COMPAREVALUE0"},
12176    {"bits": [12, 19], "name": "COMPAREMASK0"},
12177    {"bits": [24, 24], "name": "ENABLE0"}
12178   ]
12179  },
12180  "DB_SRESULTS_COMPARE_STATE1": {
12181   "fields": [
12182    {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"},
12183    {"bits": [4, 11], "name": "COMPAREVALUE1"},
12184    {"bits": [12, 19], "name": "COMPAREMASK1"},
12185    {"bits": [24, 24], "name": "ENABLE1"}
12186   ]
12187  },
12188  "DB_STENCILREFMASK": {
12189   "fields": [
12190    {"bits": [0, 7], "name": "STENCILTESTVAL"},
12191    {"bits": [8, 15], "name": "STENCILMASK"},
12192    {"bits": [16, 23], "name": "STENCILWRITEMASK"},
12193    {"bits": [24, 31], "name": "STENCILOPVAL"}
12194   ]
12195  },
12196  "DB_STENCILREFMASK_BF": {
12197   "fields": [
12198    {"bits": [0, 7], "name": "STENCILTESTVAL_BF"},
12199    {"bits": [8, 15], "name": "STENCILMASK_BF"},
12200    {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"},
12201    {"bits": [24, 31], "name": "STENCILOPVAL_BF"}
12202   ]
12203  },
12204  "DB_STENCIL_CLEAR": {
12205   "fields": [
12206    {"bits": [0, 7], "name": "CLEAR"}
12207   ]
12208  },
12209  "DB_STENCIL_CONTROL": {
12210   "fields": [
12211    {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"},
12212    {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"},
12213    {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"},
12214    {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"},
12215    {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"},
12216    {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"}
12217   ]
12218  },
12219  "DB_STENCIL_INFO": {
12220   "fields": [
12221    {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"},
12222    {"bits": [4, 8], "name": "SW_MODE"},
12223    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12224    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12225    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12226    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12227    {"bits": [20, 20], "name": "ITERATE_256"},
12228    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12229    {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"}
12230   ]
12231  },
12232  "DB_Z_INFO": {
12233   "fields": [
12234    {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"},
12235    {"bits": [2, 3], "name": "NUM_SAMPLES"},
12236    {"bits": [4, 8], "name": "SW_MODE"},
12237    {"bits": [9, 10], "enum_ref": "DbPRTFaultBehavior", "name": "FAULT_BEHAVIOR"},
12238    {"bits": [11, 11], "name": "ITERATE_FLUSH"},
12239    {"bits": [12, 12], "name": "PARTIALLY_RESIDENT"},
12240    {"bits": [13, 15], "name": "RESERVED_FIELD_1"},
12241    {"bits": [16, 19], "name": "MAXMIP"},
12242    {"bits": [20, 20], "name": "ITERATE_256"},
12243    {"bits": [23, 26], "name": "DECOMPRESS_ON_N_ZPLANES"},
12244    {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"},
12245    {"bits": [28, 28], "name": "READ_SIZE"},
12246    {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"},
12247    {"bits": [31, 31], "name": "ZRANGE_PRECISION"}
12248   ]
12249  },
12250  "DB_Z_READ_BASE_HI": {
12251   "fields": [
12252    {"bits": [0, 7], "name": "BASE_HI"}
12253   ]
12254  },
12255  "GB_ADDR_CONFIG": {
12256   "fields": [
12257    {"bits": [0, 2], "name": "NUM_PIPES"},
12258    {"bits": [3, 5], "name": "PIPE_INTERLEAVE_SIZE"},
12259    {"bits": [6, 7], "name": "MAX_COMPRESSED_FRAGS"},
12260    {"bits": [8, 10], "name": "NUM_PKRS"},
12261    {"bits": [19, 20], "name": "NUM_SHADER_ENGINES"},
12262    {"bits": [26, 27], "name": "NUM_RB_PER_SE"}
12263   ]
12264  },
12265  "GCVML2_PERFCOUNTER2_0_MODE": {
12266   "fields": [
12267    {"bits": [0, 1], "name": "COMPARE_MODE0"},
12268    {"bits": [2, 3], "name": "COMPARE_MODE1"},
12269    {"bits": [4, 5], "name": "COMPARE_MODE2"},
12270    {"bits": [6, 7], "name": "COMPARE_MODE3"},
12271    {"bits": [8, 11], "name": "COMPARE_VALUE0"},
12272    {"bits": [12, 15], "name": "COMPARE_VALUE1"},
12273    {"bits": [16, 19], "name": "COMPARE_VALUE2"},
12274    {"bits": [20, 23], "name": "COMPARE_VALUE3"}
12275   ]
12276  },
12277  "GDS_ATOM_BASE": {
12278   "fields": [
12279    {"bits": [0, 11], "name": "BASE"},
12280    {"bits": [12, 31], "name": "UNUSED"}
12281   ]
12282  },
12283  "GDS_ATOM_CNTL": {
12284   "fields": [
12285    {"bits": [0, 5], "name": "AINC"},
12286    {"bits": [6, 7], "name": "UNUSED1"},
12287    {"bits": [8, 9], "name": "DMODE"},
12288    {"bits": [10, 31], "name": "UNUSED2"}
12289   ]
12290  },
12291  "GDS_ATOM_COMPLETE": {
12292   "fields": [
12293    {"bits": [0, 0], "name": "COMPLETE"},
12294    {"bits": [1, 31], "name": "UNUSED"}
12295   ]
12296  },
12297  "GDS_ATOM_OFFSET0": {
12298   "fields": [
12299    {"bits": [0, 7], "name": "OFFSET0"},
12300    {"bits": [8, 31], "name": "UNUSED"}
12301   ]
12302  },
12303  "GDS_ATOM_OFFSET1": {
12304   "fields": [
12305    {"bits": [0, 7], "name": "OFFSET1"},
12306    {"bits": [8, 31], "name": "UNUSED"}
12307   ]
12308  },
12309  "GDS_ATOM_OP": {
12310   "fields": [
12311    {"bits": [0, 7], "name": "OP"},
12312    {"bits": [8, 31], "name": "UNUSED"}
12313   ]
12314  },
12315  "GDS_ATOM_SIZE": {
12316   "fields": [
12317    {"bits": [0, 12], "name": "SIZE"},
12318    {"bits": [13, 31], "name": "UNUSED"}
12319   ]
12320  },
12321  "GDS_GWS_RESOURCE": {
12322   "fields": [
12323    {"bits": [0, 0], "name": "FLAG"},
12324    {"bits": [1, 12], "name": "COUNTER"},
12325    {"bits": [13, 13], "name": "TYPE"},
12326    {"bits": [14, 14], "name": "DED"},
12327    {"bits": [15, 15], "name": "RELEASE_ALL"},
12328    {"bits": [16, 28], "name": "HEAD_QUEUE"},
12329    {"bits": [29, 29], "name": "HEAD_VALID"},
12330    {"bits": [30, 30], "name": "HEAD_FLAG"},
12331    {"bits": [31, 31], "name": "HALTED"}
12332   ]
12333  },
12334  "GDS_GWS_RESOURCE_CNT": {
12335   "fields": [
12336    {"bits": [0, 15], "name": "RESOURCE_CNT"},
12337    {"bits": [16, 31], "name": "UNUSED"}
12338   ]
12339  },
12340  "GDS_GWS_RESOURCE_CNTL": {
12341   "fields": [
12342    {"bits": [0, 5], "name": "INDEX"},
12343    {"bits": [6, 31], "name": "UNUSED"}
12344   ]
12345  },
12346  "GDS_OA_ADDRESS": {
12347   "fields": [
12348    {"bits": [0, 15], "name": "DS_ADDRESS"},
12349    {"bits": [16, 19], "name": "CRAWLER_TYPE"},
12350    {"bits": [20, 23], "name": "CRAWLER"},
12351    {"bits": [24, 29], "name": "UNUSED"},
12352    {"bits": [30, 30], "name": "NO_ALLOC"},
12353    {"bits": [31, 31], "name": "ENABLE"}
12354   ]
12355  },
12356  "GDS_OA_CNTL": {
12357   "fields": [
12358    {"bits": [0, 3], "name": "INDEX"},
12359    {"bits": [4, 31], "name": "UNUSED"}
12360   ]
12361  },
12362  "GDS_OA_INCDEC": {
12363   "fields": [
12364    {"bits": [0, 30], "name": "VALUE"},
12365    {"bits": [31, 31], "name": "INCDEC"}
12366   ]
12367  },
12368  "GE1_PERFCOUNTER0_SELECT": {
12369   "fields": [
12370    {"bits": [0, 9], "name": "PERF_SEL0"},
12371    {"bits": [10, 19], "name": "PERF_SEL1"},
12372    {"bits": [20, 23], "name": "CNTR_MODE"},
12373    {"bits": [24, 27], "name": "PERF_MODE1"},
12374    {"bits": [28, 31], "name": "PERF_MODE0"}
12375   ]
12376  },
12377  "GE_CNTL": {
12378   "fields": [
12379    {"bits": [0, 8], "name": "PRIMS_PER_SUBGRP"},
12380    {"bits": [9, 17], "name": "VERTS_PER_SUBGRP"},
12381    {"bits": [18, 18], "name": "BREAK_SUBGRP_AT_EOI"},
12382    {"bits": [19, 19], "name": "PACKET_TO_ONE_PA"},
12383    {"bits": [20, 20], "name": "BREAK_PRIMGRP_AT_EOI"},
12384    {"bits": [21, 29], "name": "PRIM_GRP_SIZE"},
12385    {"bits": [30, 30], "name": "GCR_DISABLE"},
12386    {"bits": [31, 31], "name": "DIS_PG_SIZE_ADJUST_FOR_STRIP"}
12387   ]
12388  },
12389  "GE_GS_FAST_LAUNCH_WG_DIM": {
12390   "fields": [
12391    {"bits": [0, 15], "name": "GS_FL_DIM_X"},
12392    {"bits": [16, 31], "name": "GS_FL_DIM_Y"}
12393   ]
12394  },
12395  "GE_GS_FAST_LAUNCH_WG_DIM_1": {
12396   "fields": [
12397    {"bits": [0, 15], "name": "GS_FL_DIM_Z"}
12398   ]
12399  },
12400  "GE_MAX_OUTPUT_PER_SUBGROUP": {
12401   "fields": [
12402    {"bits": [0, 9], "name": "MAX_VERTS_PER_SUBGROUP"}
12403   ]
12404  },
12405  "GE_MULTI_PRIM_IB_RESET_EN": {
12406   "fields": [
12407    {"bits": [0, 0], "name": "RESET_EN"},
12408    {"bits": [1, 1], "name": "MATCH_ALL_BITS"},
12409    {"bits": [2, 2], "name": "DISABLE_FOR_AUTO_INDEX"}
12410   ]
12411  },
12412  "GE_NGG_SUBGRP_CNTL": {
12413   "fields": [
12414    {"bits": [0, 8], "name": "PRIM_AMP_FACTOR"},
12415    {"bits": [9, 17], "name": "THDS_PER_SUBGRP"}
12416   ]
12417  },
12418  "GE_PC_ALLOC": {
12419   "fields": [
12420    {"bits": [0, 0], "name": "OVERSUB_EN"},
12421    {"bits": [1, 10], "name": "NUM_PC_LINES"}
12422   ]
12423  },
12424  "GE_STEREO_CNTL": {
12425   "fields": [
12426    {"bits": [0, 2], "name": "RT_SLICE"},
12427    {"bits": [3, 6], "name": "VIEWPORT"},
12428    {"bits": [8, 8], "name": "EN_STEREO"}
12429   ]
12430  },
12431  "GE_USER_VGPR_EN": {
12432   "fields": [
12433    {"bits": [0, 0], "name": "EN_USER_VGPR1"},
12434    {"bits": [1, 1], "name": "EN_USER_VGPR2"},
12435    {"bits": [2, 2], "name": "EN_USER_VGPR3"}
12436   ]
12437  },
12438  "GFX_COPY_STATE": {
12439   "fields": [
12440    {"bits": [0, 2], "name": "SRC_STATE_ID"}
12441   ]
12442  },
12443  "GL1C_STATUS": {
12444   "fields": [
12445    {"bits": [0, 0], "name": "INPUT_BUFFER_VC0_FIFO_FULL"},
12446    {"bits": [1, 1], "name": "OUTPUT_FIFOS_BUSY"},
12447    {"bits": [2, 2], "name": "SRC_DATA_FIFO_VC0_FULL"},
12448    {"bits": [3, 3], "name": "GL2_REQ_VC0_STALL"},
12449    {"bits": [4, 4], "name": "GL2_DATA_VC0_STALL"},
12450    {"bits": [5, 5], "name": "GL2_REQ_VC1_STALL"},
12451    {"bits": [6, 6], "name": "GL2_DATA_VC1_STALL"},
12452    {"bits": [7, 7], "name": "INPUT_BUFFER_VC0_BUSY"},
12453    {"bits": [8, 8], "name": "SRC_DATA_FIFO_VC0_BUSY"},
12454    {"bits": [9, 9], "name": "GL2_RH_BUSY"},
12455    {"bits": [10, 19], "name": "NUM_REQ_PENDING_FROM_L2"},
12456    {"bits": [20, 20], "name": "LATENCY_FIFO_FULL_STALL"},
12457    {"bits": [21, 21], "name": "TAG_STALL"},
12458    {"bits": [22, 22], "name": "TAG_BUSY"},
12459    {"bits": [23, 23], "name": "TAG_ACK_STALL"},
12460    {"bits": [24, 24], "name": "TAG_GCR_INV_STALL"},
12461    {"bits": [25, 25], "name": "TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL"},
12462    {"bits": [26, 26], "name": "TAG_EVICT"},
12463    {"bits": [27, 30], "name": "TAG_REQUEST_STATE_OPERATION"},
12464    {"bits": [31, 31], "name": "TRACKER_LAST_SET_MATCHES_CURRENT_SET"}
12465   ]
12466  },
12467  "GL1C_UTCL0_CNTL2": {
12468   "fields": [
12469    {"bits": [0, 7], "name": "SPARE"},
12470    {"bits": [8, 8], "name": "COMP_SYNC_DISABLE"},
12471    {"bits": [9, 9], "name": "MTYPE_OVRD_DIS"},
12472    {"bits": [10, 10], "name": "ANY_LINE_VALID"},
12473    {"bits": [14, 14], "name": "FORCE_SNOOP"},
12474    {"bits": [17, 17], "name": "DISABLE_BURST"},
12475    {"bits": [26, 26], "name": "FORCE_FRAG_2M_TO_64K"},
12476    {"bits": [30, 30], "name": "FGCG_DISABLE"},
12477    {"bits": [31, 31], "name": "BIG_PAGE_DISABLE"}
12478   ]
12479  },
12480  "GL1C_UTCL0_RETRY": {
12481   "fields": [
12482    {"bits": [0, 7], "name": "INCR"},
12483    {"bits": [8, 11], "name": "COUNT"}
12484   ]
12485  },
12486  "GL1C_UTCL0_STATUS": {
12487   "fields": [
12488    {"bits": [0, 0], "name": "FAULT_DETECTED"},
12489    {"bits": [1, 1], "name": "RETRY_DETECTED"},
12490    {"bits": [2, 2], "name": "PRT_DETECTED"}
12491   ]
12492  },
12493  "GL2C_PERFCOUNTER0_SELECT1": {
12494   "fields": [
12495    {"bits": [0, 9], "name": "PERF_SEL2"},
12496    {"bits": [10, 19], "name": "PERF_SEL3"},
12497    {"bits": [24, 27], "name": "PERF_MODE2"},
12498    {"bits": [28, 31], "name": "PERF_MODE3"}
12499   ]
12500  },
12501  "GRBM_GFX_INDEX": {
12502   "fields": [
12503    {"bits": [0, 7], "name": "INSTANCE_INDEX"},
12504    {"bits": [8, 15], "name": "SA_INDEX"},
12505    {"bits": [16, 23], "name": "SE_INDEX"},
12506    {"bits": [29, 29], "name": "SA_BROADCAST_WRITES"},
12507    {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"},
12508    {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"}
12509   ]
12510  },
12511  "GRBM_PERFCOUNTER0_SELECT": {
12512   "fields": [
12513    {"bits": [0, 5], "name": "PERF_SEL"},
12514    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
12515    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
12516    {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"},
12517    {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"},
12518    {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"},
12519    {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"},
12520    {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"},
12521    {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"},
12522    {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"},
12523    {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"},
12524    {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"},
12525    {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"},
12526    {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"},
12527    {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"},
12528    {"bits": [27, 27], "name": "TCP_BUSY_USER_DEFINED_MASK"},
12529    {"bits": [28, 28], "name": "GE_BUSY_USER_DEFINED_MASK"},
12530    {"bits": [29, 29], "name": "UTCL2_BUSY_USER_DEFINED_MASK"},
12531    {"bits": [30, 30], "name": "EA_BUSY_USER_DEFINED_MASK"},
12532    {"bits": [31, 31], "name": "RMI_BUSY_USER_DEFINED_MASK"}
12533   ]
12534  },
12535  "GRBM_PERFCOUNTER0_SELECT_HI": {
12536   "fields": [
12537    {"bits": [1, 1], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
12538    {"bits": [2, 2], "name": "GL2CC_BUSY_USER_DEFINED_MASK"},
12539    {"bits": [3, 3], "name": "SDMA_BUSY_USER_DEFINED_MASK"},
12540    {"bits": [4, 4], "name": "CH_BUSY_USER_DEFINED_MASK"},
12541    {"bits": [5, 5], "name": "PH_BUSY_USER_DEFINED_MASK"},
12542    {"bits": [6, 6], "name": "PMM_BUSY_USER_DEFINED_MASK"},
12543    {"bits": [7, 7], "name": "GUS_BUSY_USER_DEFINED_MASK"},
12544    {"bits": [8, 8], "name": "GL1CC_BUSY_USER_DEFINED_MASK"},
12545    {"bits": [9, 9], "name": "GL1H_BUSY_USER_DEFINED_MASK"}
12546   ]
12547  },
12548  "GRBM_SE0_PERFCOUNTER_SELECT": {
12549   "fields": [
12550    {"bits": [0, 5], "name": "PERF_SEL"},
12551    {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"},
12552    {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"},
12553    {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"},
12554    {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"},
12555    {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"},
12556    {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"},
12557    {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"},
12558    {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"},
12559    {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"},
12560    {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"},
12561    {"bits": [22, 22], "name": "RMI_BUSY_USER_DEFINED_MASK"},
12562    {"bits": [23, 23], "name": "UTCL1_BUSY_USER_DEFINED_MASK"},
12563    {"bits": [24, 24], "name": "TCP_BUSY_USER_DEFINED_MASK"},
12564    {"bits": [25, 25], "name": "GL1CC_BUSY_USER_DEFINED_MASK"},
12565    {"bits": [26, 26], "name": "GL1H_BUSY_USER_DEFINED_MASK"},
12566    {"bits": [27, 27], "name": "PC_BUSY_USER_DEFINED_MASK"},
12567    {"bits": [28, 28], "name": "SEDC_BUSY_USER_DEFINED_MASK"}
12568   ]
12569  },
12570  "GRBM_STATUS": {
12571   "fields": [
12572    {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"},
12573    {"bits": [6, 6], "name": "SDMA_RQ_PENDING"},
12574    {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"},
12575    {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"},
12576    {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"},
12577    {"bits": [12, 12], "name": "DB_CLEAN"},
12578    {"bits": [13, 13], "name": "CB_CLEAN"},
12579    {"bits": [14, 14], "name": "TA_BUSY"},
12580    {"bits": [15, 15], "name": "GDS_BUSY"},
12581    {"bits": [16, 16], "name": "GE_BUSY_NO_DMA"},
12582    {"bits": [20, 20], "name": "SX_BUSY"},
12583    {"bits": [21, 21], "name": "GE_BUSY"},
12584    {"bits": [22, 22], "name": "SPI_BUSY"},
12585    {"bits": [23, 23], "name": "BCI_BUSY"},
12586    {"bits": [24, 24], "name": "SC_BUSY"},
12587    {"bits": [25, 25], "name": "PA_BUSY"},
12588    {"bits": [26, 26], "name": "DB_BUSY"},
12589    {"bits": [27, 27], "name": "ANY_ACTIVE"},
12590    {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"},
12591    {"bits": [29, 29], "name": "CP_BUSY"},
12592    {"bits": [30, 30], "name": "CB_BUSY"},
12593    {"bits": [31, 31], "name": "GUI_ACTIVE"}
12594   ]
12595  },
12596  "GRBM_STATUS2": {
12597   "fields": [
12598    {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"},
12599    {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"},
12600    {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"},
12601    {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"},
12602    {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"},
12603    {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"},
12604    {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"},
12605    {"bits": [14, 14], "name": "RLC_RQ_PENDING"},
12606    {"bits": [15, 15], "name": "UTCL2_BUSY"},
12607    {"bits": [16, 16], "name": "EA_BUSY"},
12608    {"bits": [17, 17], "name": "RMI_BUSY"},
12609    {"bits": [18, 18], "name": "UTCL2_RQ_PENDING"},
12610    {"bits": [19, 19], "name": "SDMA_SCH_RQ_PENDING"},
12611    {"bits": [20, 20], "name": "EA_LINK_BUSY"},
12612    {"bits": [21, 21], "name": "SDMA_BUSY"},
12613    {"bits": [22, 22], "name": "SDMA0_RQ_PENDING"},
12614    {"bits": [23, 23], "name": "SDMA1_RQ_PENDING"},
12615    {"bits": [26, 26], "name": "RLC_BUSY"},
12616    {"bits": [27, 27], "name": "TCP_BUSY"},
12617    {"bits": [28, 28], "name": "CPF_BUSY"},
12618    {"bits": [29, 29], "name": "CPC_BUSY"},
12619    {"bits": [30, 30], "name": "CPG_BUSY"}
12620   ]
12621  },
12622  "GRBM_STATUS3": {
12623   "fields": [
12624    {"bits": [5, 5], "name": "GRBM_RLC_INTR_CREDIT_PENDING"},
12625    {"bits": [7, 7], "name": "GRBM_CPF_INTR_CREDIT_PENDING"},
12626    {"bits": [8, 8], "name": "MESPIPE0_RQ_PENDING"},
12627    {"bits": [9, 9], "name": "MESPIPE1_RQ_PENDING"},
12628    {"bits": [13, 13], "name": "PH_BUSY"},
12629    {"bits": [14, 14], "name": "CH_BUSY"},
12630    {"bits": [15, 15], "name": "GL2CC_BUSY"},
12631    {"bits": [16, 16], "name": "GL1CC_BUSY"},
12632    {"bits": [25, 25], "name": "SEDC_BUSY"},
12633    {"bits": [26, 26], "name": "PC_BUSY"},
12634    {"bits": [27, 27], "name": "GL1H_BUSY"},
12635    {"bits": [28, 28], "name": "GUS_LINK_BUSY"},
12636    {"bits": [29, 29], "name": "GUS_BUSY"},
12637    {"bits": [30, 30], "name": "UTCL1_BUSY"},
12638    {"bits": [31, 31], "name": "PMM_BUSY"}
12639   ]
12640  },
12641  "GRBM_STATUS_SE0": {
12642   "fields": [
12643    {"bits": [1, 1], "name": "DB_CLEAN"},
12644    {"bits": [2, 2], "name": "CB_CLEAN"},
12645    {"bits": [3, 3], "name": "UTCL1_BUSY"},
12646    {"bits": [4, 4], "name": "TCP_BUSY"},
12647    {"bits": [5, 5], "name": "GL1CC_BUSY"},
12648    {"bits": [6, 6], "name": "GL1H_BUSY"},
12649    {"bits": [7, 7], "name": "PC_BUSY"},
12650    {"bits": [8, 8], "name": "SEDC_BUSY"},
12651    {"bits": [21, 21], "name": "RMI_BUSY"},
12652    {"bits": [22, 22], "name": "BCI_BUSY"},
12653    {"bits": [24, 24], "name": "PA_BUSY"},
12654    {"bits": [25, 25], "name": "TA_BUSY"},
12655    {"bits": [26, 26], "name": "SX_BUSY"},
12656    {"bits": [27, 27], "name": "SPI_BUSY"},
12657    {"bits": [29, 29], "name": "SC_BUSY"},
12658    {"bits": [30, 30], "name": "DB_BUSY"},
12659    {"bits": [31, 31], "name": "CB_BUSY"}
12660   ]
12661  },
12662  "GUS_DRAM_GROUP_BURST": {
12663   "fields": [
12664    {"bits": [0, 7], "name": "DRAM_LIMIT_LO"},
12665    {"bits": [8, 15], "name": "DRAM_LIMIT_HI"}
12666   ]
12667  },
12668  "GUS_DRAM_PRI_QUANT1_PRI2": {
12669   "fields": [
12670    {"bits": [0, 7], "name": "GROUP4_THRESHOLD"},
12671    {"bits": [8, 15], "name": "GROUP5_THRESHOLD"}
12672   ]
12673  },
12674  "GUS_ERR_STATUS": {
12675   "fields": [
12676    {"bits": [0, 3], "name": "SDP_RDRSP_STATUS"},
12677    {"bits": [4, 7], "name": "SDP_WRRSP_STATUS"},
12678    {"bits": [8, 9], "name": "SDP_RDRSP_DATASTATUS"},
12679    {"bits": [10, 10], "name": "SDP_RDRSP_DATAPARITY_ERROR"},
12680    {"bits": [11, 11], "name": "CLEAR_ERROR_STATUS"},
12681    {"bits": [12, 12], "name": "BUSY_ON_ERROR"},
12682    {"bits": [13, 13], "name": "FUE_FLAG"}
12683   ]
12684  },
12685  "GUS_IO_RD_COMBINE_FLUSH": {
12686   "fields": [
12687    {"bits": [0, 3], "name": "GROUP0_TIMER"},
12688    {"bits": [4, 7], "name": "GROUP1_TIMER"},
12689    {"bits": [8, 11], "name": "GROUP2_TIMER"},
12690    {"bits": [12, 15], "name": "GROUP3_TIMER"},
12691    {"bits": [16, 19], "name": "GROUP4_TIMER"},
12692    {"bits": [20, 23], "name": "GROUP5_TIMER"},
12693    {"bits": [24, 25], "name": "COMB_MODE"}
12694   ]
12695  },
12696  "GUS_IO_RD_PRI_AGE_COEFF": {
12697   "fields": [
12698    {"bits": [0, 2], "name": "GROUP0_AGE_COEFFICIENT"},
12699    {"bits": [3, 5], "name": "GROUP1_AGE_COEFFICIENT"},
12700    {"bits": [6, 8], "name": "GROUP2_AGE_COEFFICIENT"},
12701    {"bits": [9, 11], "name": "GROUP3_AGE_COEFFICIENT"},
12702    {"bits": [12, 14], "name": "GROUP4_AGE_COEFFICIENT"},
12703    {"bits": [15, 17], "name": "GROUP5_AGE_COEFFICIENT"}
12704   ]
12705  },
12706  "GUS_IO_RD_PRI_AGE_RATE": {
12707   "fields": [
12708    {"bits": [0, 2], "name": "GROUP0_AGING_RATE"},
12709    {"bits": [3, 5], "name": "GROUP1_AGING_RATE"},
12710    {"bits": [6, 8], "name": "GROUP2_AGING_RATE"},
12711    {"bits": [9, 11], "name": "GROUP3_AGING_RATE"},
12712    {"bits": [12, 14], "name": "GROUP4_AGING_RATE"},
12713    {"bits": [15, 17], "name": "GROUP5_AGING_RATE"}
12714   ]
12715  },
12716  "GUS_LATENCY_SAMPLING": {
12717   "fields": [
12718    {"bits": [0, 0], "name": "SAMPLER0_DRAM"},
12719    {"bits": [1, 1], "name": "SAMPLER1_DRAM"},
12720    {"bits": [2, 2], "name": "SAMPLER0_IO"},
12721    {"bits": [3, 3], "name": "SAMPLER1_IO"},
12722    {"bits": [4, 4], "name": "SAMPLER0_READ"},
12723    {"bits": [5, 5], "name": "SAMPLER1_READ"},
12724    {"bits": [6, 6], "name": "SAMPLER0_WRITE"},
12725    {"bits": [7, 7], "name": "SAMPLER1_WRITE"},
12726    {"bits": [8, 8], "name": "SAMPLER0_ATOMIC_RET"},
12727    {"bits": [9, 9], "name": "SAMPLER1_ATOMIC_RET"},
12728    {"bits": [10, 10], "name": "SAMPLER0_ATOMIC_NORET"},
12729    {"bits": [11, 11], "name": "SAMPLER1_ATOMIC_NORET"},
12730    {"bits": [12, 19], "name": "SAMPLER0_VC"},
12731    {"bits": [20, 27], "name": "SAMPLER1_VC"}
12732   ]
12733  },
12734  "GUS_MISC": {
12735   "fields": [
12736    {"bits": [0, 0], "name": "RELATIVE_PRI_IN_DRAM_ARB"},
12737    {"bits": [1, 1], "name": "RELATIVE_PRI_IN_IO_RD_ARB"},
12738    {"bits": [2, 2], "name": "RELATIVE_PRI_IN_IO_WR_ARB"},
12739    {"bits": [3, 3], "name": "EARLY_SDP_ORIGDATA"},
12740    {"bits": [4, 5], "name": "LINKMGR_DYNAMIC_MODE"},
12741    {"bits": [6, 7], "name": "LINKMGR_HALT_THRESHOLD"},
12742    {"bits": [8, 9], "name": "LINKMGR_RECONNECT_DELAY"},
12743    {"bits": [10, 14], "name": "LINKMGR_IDLE_THRESHOLD"},
12744    {"bits": [15, 15], "name": "SEND0_IOWR_ONLY"}
12745   ]
12746  },
12747  "GUS_MISC2": {
12748   "fields": [
12749    {"bits": [0, 0], "name": "IO_RDWR_PRIORITY_ENABLE"},
12750    {"bits": [1, 1], "name": "CH_L1_RO_MASK"},
12751    {"bits": [2, 2], "name": "SA0_L1_RO_MASK"},
12752    {"bits": [3, 3], "name": "SA1_L1_RO_MASK"},
12753    {"bits": [4, 4], "name": "SA2_L1_RO_MASK"},
12754    {"bits": [5, 5], "name": "SA3_L1_RO_MASK"},
12755    {"bits": [6, 6], "name": "CH_L1_PERF_MASK"},
12756    {"bits": [7, 7], "name": "SA0_L1_PERF_MASK"},
12757    {"bits": [8, 8], "name": "SA1_L1_PERF_MASK"},
12758    {"bits": [9, 9], "name": "SA2_L1_PERF_MASK"},
12759    {"bits": [10, 10], "name": "SA3_L1_PERF_MASK"},
12760    {"bits": [11, 11], "name": "FP_ATOMICS_ENABLE"},
12761    {"bits": [12, 12], "name": "L1_RET_CLKEN"},
12762    {"bits": [13, 13], "name": "FGCLKEN_HIGH"},
12763    {"bits": [14, 14], "name": "BLOCK_REQUESTS"},
12764    {"bits": [15, 15], "name": "REQUESTS_BLOCKED"},
12765    {"bits": [16, 16], "name": "RIO_ICG_L1_ROUTER_BUSY_MASK"},
12766    {"bits": [17, 17], "name": "WIO_ICG_L1_ROUTER_BUSY_MASK"},
12767    {"bits": [18, 18], "name": "DRAM_ICG_L1_ROUTER_BUSY_MASK"}
12768   ]
12769  },
12770  "GUS_MISC3": {
12771   "fields": [
12772    {"bits": [0, 0], "name": "FP_ATOMICS_LOG"},
12773    {"bits": [1, 1], "name": "CLEAR_LOG"}
12774   ]
12775  },
12776  "GUS_SDP_ENABLE": {
12777   "fields": [
12778    {"bits": [0, 0], "name": "ENABLE"}
12779   ]
12780  },
12781  "GUS_SDP_REQ_CNTL": {
12782   "fields": [
12783    {"bits": [0, 0], "name": "REQ_PASS_PW_OVERRIDE_READ"},
12784    {"bits": [1, 1], "name": "REQ_PASS_PW_OVERRIDE_WRITE"},
12785    {"bits": [2, 2], "name": "REQ_PASS_PW_OVERRIDE_ATOMIC"},
12786    {"bits": [3, 3], "name": "REQ_CHAIN_OVERRIDE_DRAM"},
12787    {"bits": [4, 4], "name": "INNER_DOMAIN_MODE"}
12788   ]
12789  },
12790  "GUS_SDP_TAG_RESERVE1": {
12791   "fields": [
12792    {"bits": [0, 7], "name": "VC4"},
12793    {"bits": [8, 15], "name": "VC5"},
12794    {"bits": [16, 23], "name": "VC6"},
12795    {"bits": [24, 31], "name": "VC7"}
12796   ]
12797  },
12798  "GUS_SDP_VCC_RESERVE0": {
12799   "fields": [
12800    {"bits": [0, 5], "name": "VC0_CREDITS"},
12801    {"bits": [6, 11], "name": "VC1_CREDITS"},
12802    {"bits": [12, 17], "name": "VC2_CREDITS"},
12803    {"bits": [18, 23], "name": "VC3_CREDITS"},
12804    {"bits": [24, 29], "name": "VC4_CREDITS"}
12805   ]
12806  },
12807  "GUS_SDP_VCC_RESERVE1": {
12808   "fields": [
12809    {"bits": [0, 5], "name": "VC5_CREDITS"},
12810    {"bits": [6, 11], "name": "VC6_CREDITS"},
12811    {"bits": [12, 17], "name": "VC7_CREDITS"},
12812    {"bits": [31, 31], "name": "DISTRIBUTE_POOL"}
12813   ]
12814  },
12815  "GUS_WRRSP_FIFO_CNTL": {
12816   "fields": [
12817    {"bits": [0, 5], "name": "THRESHOLD"}
12818   ]
12819  },
12820  "PA_CL_CLIP_CNTL": {
12821   "fields": [
12822    {"bits": [0, 0], "name": "UCP_ENA_0"},
12823    {"bits": [1, 1], "name": "UCP_ENA_1"},
12824    {"bits": [2, 2], "name": "UCP_ENA_2"},
12825    {"bits": [3, 3], "name": "UCP_ENA_3"},
12826    {"bits": [4, 4], "name": "UCP_ENA_4"},
12827    {"bits": [5, 5], "name": "UCP_ENA_5"},
12828    {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"},
12829    {"bits": [14, 15], "name": "PS_UCP_MODE"},
12830    {"bits": [16, 16], "name": "CLIP_DISABLE"},
12831    {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"},
12832    {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"},
12833    {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"},
12834    {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"},
12835    {"bits": [21, 21], "name": "VTX_KILL_OR"},
12836    {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"},
12837    {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"},
12838    {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"},
12839    {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"},
12840    {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"},
12841    {"bits": [28, 28], "name": "ZCLIP_PROG_NEAR_ENA"}
12842   ]
12843  },
12844  "PA_CL_NANINF_CNTL": {
12845   "fields": [
12846    {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"},
12847    {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"},
12848    {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"},
12849    {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"},
12850    {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"},
12851    {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"},
12852    {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"},
12853    {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"},
12854    {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"},
12855    {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"},
12856    {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"},
12857    {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"},
12858    {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"},
12859    {"bits": [13, 13], "name": "VS_W_INF_RETAIN"},
12860    {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"},
12861    {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"}
12862   ]
12863  },
12864  "PA_CL_NGG_CNTL": {
12865   "fields": [
12866    {"bits": [0, 0], "name": "VERTEX_REUSE_OFF"},
12867    {"bits": [1, 1], "name": "INDEX_BUF_EDGE_FLAG_ENA"},
12868    {"bits": [2, 9], "name": "VERTEX_REUSE_DEPTH"}
12869   ]
12870  },
12871  "PA_CL_VRS_CNTL": {
12872   "fields": [
12873    {"bits": [0, 2], "enum_ref": "VRSCombinerModeSC", "name": "VERTEX_RATE_COMBINER_MODE"},
12874    {"bits": [3, 5], "enum_ref": "VRSCombinerModeSC", "name": "PRIMITIVE_RATE_COMBINER_MODE"},
12875    {"bits": [6, 8], "enum_ref": "VRSCombinerModeSC", "name": "HTILE_RATE_COMBINER_MODE"},
12876    {"bits": [9, 11], "enum_ref": "VRSCombinerModeSC", "name": "SAMPLE_ITER_COMBINER_MODE"},
12877    {"bits": [13, 13], "name": "EXPOSE_VRS_PIXELS_MASK"},
12878    {"bits": [14, 14], "name": "CMASK_RATE_HINT_FORCE_ZERO"}
12879   ]
12880  },
12881  "PA_CL_VS_OUT_CNTL": {
12882   "fields": [
12883    {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"},
12884    {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"},
12885    {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"},
12886    {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"},
12887    {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"},
12888    {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"},
12889    {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"},
12890    {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"},
12891    {"bits": [8, 8], "name": "CULL_DIST_ENA_0"},
12892    {"bits": [9, 9], "name": "CULL_DIST_ENA_1"},
12893    {"bits": [10, 10], "name": "CULL_DIST_ENA_2"},
12894    {"bits": [11, 11], "name": "CULL_DIST_ENA_3"},
12895    {"bits": [12, 12], "name": "CULL_DIST_ENA_4"},
12896    {"bits": [13, 13], "name": "CULL_DIST_ENA_5"},
12897    {"bits": [14, 14], "name": "CULL_DIST_ENA_6"},
12898    {"bits": [15, 15], "name": "CULL_DIST_ENA_7"},
12899    {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"},
12900    {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"},
12901    {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"},
12902    {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"},
12903    {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"},
12904    {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"},
12905    {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"},
12906    {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"},
12907    {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"},
12908    {"bits": [27, 27], "name": "USE_VTX_LINE_WIDTH"},
12909    {"bits": [28, 28], "name": "USE_VTX_VRS_RATE"},
12910    {"bits": [29, 29], "name": "BYPASS_VTX_RATE_COMBINER"},
12911    {"bits": [30, 30], "name": "BYPASS_PRIM_RATE_COMBINER"}
12912   ]
12913  },
12914  "PA_CL_VTE_CNTL": {
12915   "fields": [
12916    {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"},
12917    {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"},
12918    {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"},
12919    {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"},
12920    {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"},
12921    {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"},
12922    {"bits": [8, 8], "name": "VTX_XY_FMT"},
12923    {"bits": [9, 9], "name": "VTX_Z_FMT"},
12924    {"bits": [10, 10], "name": "VTX_W0_FMT"},
12925    {"bits": [11, 11], "name": "PERFCOUNTER_REF"}
12926   ]
12927  },
12928  "PA_RATE_CNTL": {
12929   "fields": [
12930    {"bits": [0, 3], "name": "VERTEX_RATE"},
12931    {"bits": [4, 7], "name": "PRIM_RATE"}
12932   ]
12933  },
12934  "PA_SC_AA_CONFIG": {
12935   "fields": [
12936    {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"},
12937    {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"},
12938    {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"},
12939    {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"},
12940    {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"},
12941    {"bits": [26, 27], "enum_ref": "CovToShaderSel", "name": "COVERAGE_TO_SHADER_SELECT"},
12942    {"bits": [28, 28], "name": "SAMPLE_COVERAGE_ENCODING"},
12943    {"bits": [29, 29], "name": "COVERED_CENTROID_IS_CENTER"}
12944   ]
12945  },
12946  "PA_SC_AA_MASK_X0Y0_X1Y0": {
12947   "fields": [
12948    {"bits": [0, 15], "name": "AA_MASK_X0Y0"},
12949    {"bits": [16, 31], "name": "AA_MASK_X1Y0"}
12950   ]
12951  },
12952  "PA_SC_AA_MASK_X0Y1_X1Y1": {
12953   "fields": [
12954    {"bits": [0, 15], "name": "AA_MASK_X0Y1"},
12955    {"bits": [16, 31], "name": "AA_MASK_X1Y1"}
12956   ]
12957  },
12958  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": {
12959   "fields": [
12960    {"bits": [0, 3], "name": "S0_X"},
12961    {"bits": [4, 7], "name": "S0_Y"},
12962    {"bits": [8, 11], "name": "S1_X"},
12963    {"bits": [12, 15], "name": "S1_Y"},
12964    {"bits": [16, 19], "name": "S2_X"},
12965    {"bits": [20, 23], "name": "S2_Y"},
12966    {"bits": [24, 27], "name": "S3_X"},
12967    {"bits": [28, 31], "name": "S3_Y"}
12968   ]
12969  },
12970  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": {
12971   "fields": [
12972    {"bits": [0, 3], "name": "S4_X"},
12973    {"bits": [4, 7], "name": "S4_Y"},
12974    {"bits": [8, 11], "name": "S5_X"},
12975    {"bits": [12, 15], "name": "S5_Y"},
12976    {"bits": [16, 19], "name": "S6_X"},
12977    {"bits": [20, 23], "name": "S6_Y"},
12978    {"bits": [24, 27], "name": "S7_X"},
12979    {"bits": [28, 31], "name": "S7_Y"}
12980   ]
12981  },
12982  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": {
12983   "fields": [
12984    {"bits": [0, 3], "name": "S8_X"},
12985    {"bits": [4, 7], "name": "S8_Y"},
12986    {"bits": [8, 11], "name": "S9_X"},
12987    {"bits": [12, 15], "name": "S9_Y"},
12988    {"bits": [16, 19], "name": "S10_X"},
12989    {"bits": [20, 23], "name": "S10_Y"},
12990    {"bits": [24, 27], "name": "S11_X"},
12991    {"bits": [28, 31], "name": "S11_Y"}
12992   ]
12993  },
12994  "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": {
12995   "fields": [
12996    {"bits": [0, 3], "name": "S12_X"},
12997    {"bits": [4, 7], "name": "S12_Y"},
12998    {"bits": [8, 11], "name": "S13_X"},
12999    {"bits": [12, 15], "name": "S13_Y"},
13000    {"bits": [16, 19], "name": "S14_X"},
13001    {"bits": [20, 23], "name": "S14_Y"},
13002    {"bits": [24, 27], "name": "S15_X"},
13003    {"bits": [28, 31], "name": "S15_Y"}
13004   ]
13005  },
13006  "PA_SC_BINNER_CNTL_0": {
13007   "fields": [
13008    {"bits": [0, 1], "enum_ref": "BinningMode", "name": "BINNING_MODE"},
13009    {"bits": [2, 2], "name": "BIN_SIZE_X"},
13010    {"bits": [3, 3], "name": "BIN_SIZE_Y"},
13011    {"bits": [4, 6], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_X_EXTEND"},
13012    {"bits": [7, 9], "enum_ref": "BinSizeExtend", "name": "BIN_SIZE_Y_EXTEND"},
13013    {"bits": [10, 12], "name": "CONTEXT_STATES_PER_BIN"},
13014    {"bits": [13, 17], "name": "PERSISTENT_STATES_PER_BIN"},
13015    {"bits": [18, 18], "name": "DISABLE_START_OF_PRIM"},
13016    {"bits": [19, 26], "name": "FPOVS_PER_BATCH"},
13017    {"bits": [27, 27], "name": "OPTIMAL_BIN_SELECTION"},
13018    {"bits": [28, 28], "name": "FLUSH_ON_BINNING_TRANSITION"},
13019    {"bits": [29, 30], "enum_ref": "BinMapMode", "name": "BIN_MAPPING_MODE"}
13020   ]
13021  },
13022  "PA_SC_BINNER_CNTL_1": {
13023   "fields": [
13024    {"bits": [0, 15], "name": "MAX_ALLOC_COUNT"},
13025    {"bits": [16, 31], "name": "MAX_PRIM_PER_BATCH"}
13026   ]
13027  },
13028  "PA_SC_BINNER_CNTL_2": {
13029   "fields": [
13030    {"bits": [0, 0], "name": "BIN_SIZE_X_MULT_BY_1P5X"},
13031    {"bits": [1, 1], "name": "BIN_SIZE_Y_MULT_BY_1P5X"},
13032    {"bits": [2, 2], "name": "ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION"},
13033    {"bits": [3, 3], "name": "DUAL_LIGHT_SHAFT_IN_DRAW"},
13034    {"bits": [4, 6], "name": "LIGHT_SHAFT_DRAW_CALL_LIMIT"},
13035    {"bits": [7, 10], "name": "CONTEXT_DONE_EVENTS_PER_BIN"},
13036    {"bits": [11, 11], "name": "ZPP_ENABLED"},
13037    {"bits": [12, 12], "name": "ZPP_OPTIMIZATION_ENABLED"},
13038    {"bits": [13, 20], "name": "ZPP_AREA_THRESHOLD"},
13039    {"bits": [21, 21], "name": "DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION"}
13040   ]
13041  },
13042  "PA_SC_CENTROID_PRIORITY_0": {
13043   "fields": [
13044    {"bits": [0, 3], "name": "DISTANCE_0"},
13045    {"bits": [4, 7], "name": "DISTANCE_1"},
13046    {"bits": [8, 11], "name": "DISTANCE_2"},
13047    {"bits": [12, 15], "name": "DISTANCE_3"},
13048    {"bits": [16, 19], "name": "DISTANCE_4"},
13049    {"bits": [20, 23], "name": "DISTANCE_5"},
13050    {"bits": [24, 27], "name": "DISTANCE_6"},
13051    {"bits": [28, 31], "name": "DISTANCE_7"}
13052   ]
13053  },
13054  "PA_SC_CENTROID_PRIORITY_1": {
13055   "fields": [
13056    {"bits": [0, 3], "name": "DISTANCE_8"},
13057    {"bits": [4, 7], "name": "DISTANCE_9"},
13058    {"bits": [8, 11], "name": "DISTANCE_10"},
13059    {"bits": [12, 15], "name": "DISTANCE_11"},
13060    {"bits": [16, 19], "name": "DISTANCE_12"},
13061    {"bits": [20, 23], "name": "DISTANCE_13"},
13062    {"bits": [24, 27], "name": "DISTANCE_14"},
13063    {"bits": [28, 31], "name": "DISTANCE_15"}
13064   ]
13065  },
13066  "PA_SC_CLIPRECT_0_TL": {
13067   "fields": [
13068    {"bits": [0, 14], "name": "TL_X"},
13069    {"bits": [16, 30], "name": "TL_Y"}
13070   ]
13071  },
13072  "PA_SC_CLIPRECT_RULE": {
13073   "fields": [
13074    {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"}
13075   ]
13076  },
13077  "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL": {
13078   "fields": [
13079    {"bits": [0, 0], "name": "OVER_RAST_ENABLE"},
13080    {"bits": [1, 4], "name": "OVER_RAST_SAMPLE_SELECT"},
13081    {"bits": [5, 5], "name": "UNDER_RAST_ENABLE"},
13082    {"bits": [6, 9], "name": "UNDER_RAST_SAMPLE_SELECT"},
13083    {"bits": [10, 10], "name": "PBB_UNCERTAINTY_REGION_ENABLE"},
13084    {"bits": [11, 11], "name": "ZMM_TRI_EXTENT"},
13085    {"bits": [12, 12], "name": "ZMM_TRI_OFFSET"},
13086    {"bits": [13, 13], "name": "OVERRIDE_OVER_RAST_INNER_TO_NORMAL"},
13087    {"bits": [14, 14], "name": "OVERRIDE_UNDER_RAST_INNER_TO_NORMAL"},
13088    {"bits": [15, 15], "name": "DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE"},
13089    {"bits": [16, 17], "enum_ref": "ScUncertaintyRegionMode", "name": "UNCERTAINTY_REGION_MODE"},
13090    {"bits": [18, 18], "name": "OUTER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13091    {"bits": [19, 19], "name": "INNER_UNCERTAINTY_EDGERULE_OVERRIDE"},
13092    {"bits": [20, 20], "name": "NULL_SQUAD_AA_MASK_ENABLE"},
13093    {"bits": [21, 21], "name": "COVERAGE_AA_MASK_ENABLE"},
13094    {"bits": [22, 22], "name": "PREZ_AA_MASK_ENABLE"},
13095    {"bits": [23, 23], "name": "POSTZ_AA_MASK_ENABLE"},
13096    {"bits": [24, 24], "name": "CENTROID_SAMPLE_OVERRIDE"},
13097    {"bits": [25, 26], "name": "UNCERTAINTY_REGION_MULT"},
13098    {"bits": [27, 28], "name": "UNCERTAINTY_REGION_PBB_MULT"}
13099   ]
13100  },
13101  "PA_SC_EDGERULE": {
13102   "fields": [
13103    {"bits": [0, 3], "name": "ER_TRI"},
13104    {"bits": [4, 7], "name": "ER_POINT"},
13105    {"bits": [8, 11], "name": "ER_RECT"},
13106    {"bits": [12, 17], "name": "ER_LINE_LR"},
13107    {"bits": [18, 23], "name": "ER_LINE_RL"},
13108    {"bits": [24, 27], "name": "ER_LINE_TB"},
13109    {"bits": [28, 31], "name": "ER_LINE_BT"}
13110   ]
13111  },
13112  "PA_SC_LINE_CNTL": {
13113   "fields": [
13114    {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"},
13115    {"bits": [10, 10], "name": "LAST_PIXEL"},
13116    {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"},
13117    {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"},
13118    {"bits": [13, 13], "name": "EXTRA_DX_DY_PRECISION"}
13119   ]
13120  },
13121  "PA_SC_LINE_STIPPLE": {
13122   "fields": [
13123    {"bits": [0, 15], "name": "LINE_PATTERN"},
13124    {"bits": [16, 23], "name": "REPEAT_COUNT"},
13125    {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"},
13126    {"bits": [29, 30], "name": "AUTO_RESET_CNTL"}
13127   ]
13128  },
13129  "PA_SC_LINE_STIPPLE_STATE": {
13130   "fields": [
13131    {"bits": [0, 3], "name": "CURRENT_PTR"},
13132    {"bits": [8, 15], "name": "CURRENT_COUNT"}
13133   ]
13134  },
13135  "PA_SC_MODE_CNTL_0": {
13136   "fields": [
13137    {"bits": [0, 0], "name": "MSAA_ENABLE"},
13138    {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"},
13139    {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"},
13140    {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"},
13141    {"bits": [5, 5], "name": "ALTERNATE_RBS_PER_TILE"},
13142    {"bits": [6, 6], "name": "COARSE_TILE_STARTS_ON_EVEN_RB"}
13143   ]
13144  },
13145  "PA_SC_MODE_CNTL_1": {
13146   "fields": [
13147    {"bits": [0, 0], "name": "WALK_SIZE"},
13148    {"bits": [1, 1], "name": "WALK_ALIGNMENT"},
13149    {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"},
13150    {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"},
13151    {"bits": [4, 6], "name": "WALK_FENCE_SIZE"},
13152    {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"},
13153    {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"},
13154    {"bits": [9, 9], "name": "TILE_COVER_DISABLE"},
13155    {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"},
13156    {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"},
13157    {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"},
13158    {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"},
13159    {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"},
13160    {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"},
13161    {"bits": [16, 16], "name": "PS_ITER_SAMPLE"},
13162    {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"},
13163    {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"},
13164    {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"},
13165    {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"},
13166    {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"},
13167    {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"},
13168    {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"},
13169    {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"},
13170    {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"}
13171   ]
13172  },
13173  "PA_SC_NGG_MODE_CNTL": {
13174   "fields": [
13175    {"bits": [0, 10], "name": "MAX_DEALLOCS_IN_WAVE"},
13176    {"bits": [12, 12], "name": "DISABLE_FPOG_AND_DEALLOC_CONFLICT"},
13177    {"bits": [13, 13], "name": "DISABLE_MAX_DEALLOC"},
13178    {"bits": [14, 14], "name": "DISABLE_MAX_ATTRIBUTES"},
13179    {"bits": [16, 23], "name": "MAX_FPOVS_IN_WAVE"},
13180    {"bits": [24, 31], "name": "MAX_ATTRIBUTES_IN_WAVE"}
13181   ]
13182  },
13183  "PA_SC_P3D_TRAP_SCREEN_H": {
13184   "fields": [
13185    {"bits": [0, 13], "name": "X_COORD"}
13186   ]
13187  },
13188  "PA_SC_P3D_TRAP_SCREEN_HV_EN": {
13189   "fields": [
13190    {"bits": [0, 0], "name": "ENABLE_HV_PRE_SHADER"},
13191    {"bits": [1, 1], "name": "FORCE_PRE_SHADER_ALL_PIXELS"}
13192   ]
13193  },
13194  "PA_SC_P3D_TRAP_SCREEN_OCCURRENCE": {
13195   "fields": [
13196    {"bits": [0, 15], "name": "COUNT"}
13197   ]
13198  },
13199  "PA_SC_P3D_TRAP_SCREEN_V": {
13200   "fields": [
13201    {"bits": [0, 13], "name": "Y_COORD"}
13202   ]
13203  },
13204  "PA_SC_PERFCOUNTER1_SELECT": {
13205   "fields": [
13206    {"bits": [0, 9], "name": "PERF_SEL"}
13207   ]
13208  },
13209  "PA_SC_RASTER_CONFIG": {
13210   "fields": [
13211    {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"},
13212    {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"},
13213    {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"},
13214    {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"},
13215    {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"},
13216    {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"},
13217    {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"},
13218    {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"},
13219    {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"},
13220    {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"},
13221    {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"},
13222    {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"},
13223    {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"},
13224    {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"},
13225    {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"}
13226   ]
13227  },
13228  "PA_SC_RASTER_CONFIG_1": {
13229   "fields": [
13230    {"bits": [0, 1], "enum_ref": "SePairMap", "name": "SE_PAIR_MAP"},
13231    {"bits": [2, 3], "enum_ref": "SePairXsel", "name": "SE_PAIR_XSEL"},
13232    {"bits": [4, 5], "enum_ref": "SePairYsel", "name": "SE_PAIR_YSEL"}
13233   ]
13234  },
13235  "PA_SC_SCREEN_EXTENT_CONTROL": {
13236   "fields": [
13237    {"bits": [0, 1], "name": "SLICE_EVEN_ENABLE"},
13238    {"bits": [2, 3], "name": "SLICE_ODD_ENABLE"}
13239   ]
13240  },
13241  "PA_SC_SCREEN_EXTENT_MIN_0": {
13242   "fields": [
13243    {"bits": [0, 15], "name": "X"},
13244    {"bits": [16, 31], "name": "Y"}
13245   ]
13246  },
13247  "PA_SC_SCREEN_SCISSOR_BR": {
13248   "fields": [
13249    {"bits": [0, 15], "name": "BR_X"},
13250    {"bits": [16, 31], "name": "BR_Y"}
13251   ]
13252  },
13253  "PA_SC_SCREEN_SCISSOR_TL": {
13254   "fields": [
13255    {"bits": [0, 15], "name": "TL_X"},
13256    {"bits": [16, 31], "name": "TL_Y"}
13257   ]
13258  },
13259  "PA_SC_SHADER_CONTROL": {
13260   "fields": [
13261    {"bits": [0, 1], "name": "REALIGN_DQUADS_AFTER_N_WAVES"},
13262    {"bits": [2, 2], "name": "LOAD_COLLISION_WAVEID"},
13263    {"bits": [3, 3], "name": "LOAD_INTRAWAVE_COLLISION"},
13264    {"bits": [5, 6], "name": "WAVE_BREAK_REGION_SIZE"},
13265    {"bits": [7, 7], "name": "DISABLE_OREO_CONFLICT_QUAD"}
13266   ]
13267  },
13268  "PA_SC_TILE_STEERING_OVERRIDE": {
13269   "fields": [
13270    {"bits": [0, 0], "name": "ENABLE"},
13271    {"bits": [12, 13], "name": "NUM_SC"},
13272    {"bits": [16, 17], "name": "NUM_RB_PER_SC"},
13273    {"bits": [20, 21], "name": "NUM_PACKER_PER_SC"}
13274   ]
13275  },
13276  "PA_SC_VRS_OVERRIDE_CNTL": {
13277   "fields": [
13278    {"bits": [0, 2], "enum_ref": "VRSCombinerModeSC", "name": "VRS_OVERRIDE_RATE_COMBINER_MODE"},
13279    {"bits": [4, 7], "enum_ref": "VRSrate", "name": "VRS_RATE"},
13280    {"bits": [12, 12], "name": "VRS_SURFACE_ENABLE"},
13281    {"bits": [13, 13], "name": "RATE_HINT_WRITE_BACK_ENABLE"},
13282    {"bits": [14, 14], "name": "VRS_FEEDBACK_RATE_OVERRIDE"}
13283   ]
13284  },
13285  "PA_SC_VRS_RATE_BASE_EXT": {
13286   "fields": [
13287    {"bits": [0, 7], "name": "BASE_256B"},
13288    {"bits": [28, 31], "name": "TB_SYNC_SIM_ID"}
13289   ]
13290  },
13291  "PA_SC_VRS_RATE_CACHE_CNTL": {
13292   "fields": [
13293    {"bits": [0, 0], "name": "BIG_PAGE_RD"},
13294    {"bits": [1, 1], "name": "BIG_PAGE_WR"},
13295    {"bits": [2, 3], "name": "L1_RD_POLICY"},
13296    {"bits": [4, 5], "name": "L2_RD_POLICY"},
13297    {"bits": [6, 7], "name": "L2_WR_POLICY"},
13298    {"bits": [8, 8], "name": "LLC_RD_NOALLOC"},
13299    {"bits": [9, 9], "name": "LLC_WR_NOALLOC"},
13300    {"bits": [10, 10], "name": "NOFILL_RD"},
13301    {"bits": [11, 11], "name": "NOFILL_WR"},
13302    {"bits": [12, 12], "name": "PERF_CNTR_EN_RD"},
13303    {"bits": [13, 13], "name": "PERF_CNTR_EN_WR"}
13304   ]
13305  },
13306  "PA_SC_VRS_RATE_FEEDBACK_BASE_EXT": {
13307   "fields": [
13308    {"bits": [0, 7], "name": "BASE_256B"}
13309   ]
13310  },
13311  "PA_SC_VRS_RATE_FEEDBACK_SIZE_XY": {
13312   "fields": [
13313    {"bits": [0, 10], "name": "X_MAX"},
13314    {"bits": [16, 26], "name": "Y_MAX"}
13315   ]
13316  },
13317  "PA_SC_WINDOW_OFFSET": {
13318   "fields": [
13319    {"bits": [0, 15], "name": "WINDOW_X_OFFSET"},
13320    {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"}
13321   ]
13322  },
13323  "PA_SC_WINDOW_SCISSOR_BR": {
13324   "fields": [
13325    {"bits": [0, 14], "name": "BR_X"},
13326    {"bits": [16, 30], "name": "BR_Y"}
13327   ]
13328  },
13329  "PA_SC_WINDOW_SCISSOR_TL": {
13330   "fields": [
13331    {"bits": [0, 14], "name": "TL_X"},
13332    {"bits": [16, 30], "name": "TL_Y"},
13333    {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"}
13334   ]
13335  },
13336  "PA_STEREO_CNTL": {
13337   "fields": [
13338    {"bits": [1, 4], "name": "STEREO_MODE"},
13339    {"bits": [5, 7], "name": "RT_SLICE_MODE"},
13340    {"bits": [8, 11], "name": "RT_SLICE_OFFSET"},
13341    {"bits": [16, 18], "name": "VP_ID_MODE"},
13342    {"bits": [19, 22], "name": "VP_ID_OFFSET"}
13343   ]
13344  },
13345  "PA_SU_HARDWARE_SCREEN_OFFSET": {
13346   "fields": [
13347    {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"},
13348    {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"}
13349   ]
13350  },
13351  "PA_SU_LINE_CNTL": {
13352   "fields": [
13353    {"bits": [0, 15], "name": "WIDTH"}
13354   ]
13355  },
13356  "PA_SU_LINE_STIPPLE_CNTL": {
13357   "fields": [
13358    {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"},
13359    {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"},
13360    {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}
13361   ]
13362  },
13363  "PA_SU_LINE_STIPPLE_VALUE": {
13364   "fields": [
13365    {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"}
13366   ]
13367  },
13368  "PA_SU_OVER_RASTERIZATION_CNTL": {
13369   "fields": [
13370    {"bits": [0, 0], "name": "DISCARD_0_AREA_TRIANGLES"},
13371    {"bits": [1, 1], "name": "DISCARD_0_AREA_LINES"},
13372    {"bits": [2, 2], "name": "DISCARD_0_AREA_POINTS"},
13373    {"bits": [3, 3], "name": "DISCARD_0_AREA_RECTANGLES"},
13374    {"bits": [4, 4], "name": "USE_PROVOKING_ZW"}
13375   ]
13376  },
13377  "PA_SU_POINT_MINMAX": {
13378   "fields": [
13379    {"bits": [0, 15], "name": "MIN_SIZE"},
13380    {"bits": [16, 31], "name": "MAX_SIZE"}
13381   ]
13382  },
13383  "PA_SU_POINT_SIZE": {
13384   "fields": [
13385    {"bits": [0, 15], "name": "HEIGHT"},
13386    {"bits": [16, 31], "name": "WIDTH"}
13387   ]
13388  },
13389  "PA_SU_POLY_OFFSET_DB_FMT_CNTL": {
13390   "fields": [
13391    {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"},
13392    {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"}
13393   ]
13394  },
13395  "PA_SU_PRIM_FILTER_CNTL": {
13396   "fields": [
13397    {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"},
13398    {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"},
13399    {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"},
13400    {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"},
13401    {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"},
13402    {"bits": [5, 5], "name": "LINE_EXPAND_ENA"},
13403    {"bits": [6, 6], "name": "POINT_EXPAND_ENA"},
13404    {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"},
13405    {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"},
13406    {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"},
13407    {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"}
13408   ]
13409  },
13410  "PA_SU_SC_MODE_CNTL": {
13411   "fields": [
13412    {"bits": [0, 0], "name": "CULL_FRONT"},
13413    {"bits": [1, 1], "name": "CULL_BACK"},
13414    {"bits": [2, 2], "name": "FACE"},
13415    {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"},
13416    {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"},
13417    {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"},
13418    {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"},
13419    {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"},
13420    {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"},
13421    {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"},
13422    {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"},
13423    {"bits": [20, 20], "name": "PERSP_CORR_DIS"},
13424    {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"},
13425    {"bits": [22, 22], "name": "RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF"},
13426    {"bits": [23, 23], "name": "NEW_QUAD_DECOMPOSITION"},
13427    {"bits": [24, 24], "name": "KEEP_TOGETHER_ENABLE"}
13428   ]
13429  },
13430  "PA_SU_SMALL_PRIM_FILTER_CNTL": {
13431   "fields": [
13432    {"bits": [0, 0], "name": "SMALL_PRIM_FILTER_ENABLE"},
13433    {"bits": [1, 1], "name": "TRIANGLE_FILTER_DISABLE"},
13434    {"bits": [2, 2], "name": "LINE_FILTER_DISABLE"},
13435    {"bits": [3, 3], "name": "POINT_FILTER_DISABLE"},
13436    {"bits": [4, 4], "name": "RECTANGLE_FILTER_DISABLE"}
13437   ]
13438  },
13439  "PA_SU_VTX_CNTL": {
13440   "fields": [
13441    {"bits": [0, 0], "name": "PIX_CENTER"},
13442    {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"},
13443    {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"}
13444   ]
13445  },
13446  "RLC_GPM_PERF_COUNT_0": {
13447   "fields": [
13448    {"bits": [0, 3], "name": "FEATURE_SEL"},
13449    {"bits": [4, 7], "name": "SE_INDEX"},
13450    {"bits": [8, 11], "name": "SA_INDEX"},
13451    {"bits": [12, 15], "name": "WGP_INDEX"},
13452    {"bits": [16, 17], "name": "EVENT_SEL"},
13453    {"bits": [18, 19], "name": "UNUSED"},
13454    {"bits": [20, 20], "name": "ENABLE"},
13455    {"bits": [21, 31], "name": "RESERVED"}
13456   ]
13457  },
13458  "RLC_GPU_IOV_PERF_CNT_CNTL": {
13459   "fields": [
13460    {"bits": [0, 0], "name": "ENABLE"},
13461    {"bits": [1, 1], "name": "MODE_SELECT"},
13462    {"bits": [2, 2], "name": "RESET"},
13463    {"bits": [3, 31], "name": "RESERVED"}
13464   ]
13465  },
13466  "RLC_GPU_IOV_PERF_CNT_WR_ADDR": {
13467   "fields": [
13468    {"bits": [0, 3], "name": "VFID"},
13469    {"bits": [4, 5], "name": "CNT_ID"},
13470    {"bits": [6, 31], "name": "RESERVED"}
13471   ]
13472  },
13473  "RLC_PERFCOUNTER0_SELECT": {
13474   "fields": [
13475    {"bits": [0, 7], "name": "PERFCOUNTER_SELECT"}
13476   ]
13477  },
13478  "RLC_PERFMON_CNTL": {
13479   "fields": [
13480    {"bits": [0, 2], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"},
13481    {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"}
13482   ]
13483  },
13484  "RLC_SPM_ACCUM_CTRL": {
13485   "fields": [
13486    {"bits": [0, 0], "name": "StrobeResetPerfMonitors"},
13487    {"bits": [1, 1], "name": "StrobeStartAccumulation"},
13488    {"bits": [2, 2], "name": "StrobeRearmAccum"},
13489    {"bits": [3, 3], "name": "StrobeResetSpmBlock"},
13490    {"bits": [4, 7], "name": "StrobeStartSpm"},
13491    {"bits": [8, 8], "name": "StrobeRearmSwaAccum"},
13492    {"bits": [9, 9], "name": "StrobeStartSwa"},
13493    {"bits": [10, 10], "name": "StrobePerfmonSampleWires"},
13494    {"bits": [11, 31], "name": "RESERVED"}
13495   ]
13496  },
13497  "RLC_SPM_ACCUM_CTRLRAM_ADDR": {
13498   "fields": [
13499    {"bits": [0, 10], "name": "addr"},
13500    {"bits": [11, 31], "name": "RESERVED"}
13501   ]
13502  },
13503  "RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET": {
13504   "fields": [
13505    {"bits": [0, 7], "name": "global_offset"},
13506    {"bits": [8, 15], "name": "spmwithaccum_se_offset"},
13507    {"bits": [16, 23], "name": "spmwithaccum_global_offset"},
13508    {"bits": [24, 31], "name": "RESERVED"}
13509   ]
13510  },
13511  "RLC_SPM_ACCUM_CTRLRAM_DATA": {
13512   "fields": [
13513    {"bits": [0, 7], "name": "data"},
13514    {"bits": [8, 31], "name": "RESERVED"}
13515   ]
13516  },
13517  "RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS": {
13518   "fields": [
13519    {"bits": [0, 7], "name": "spp_addr_region"},
13520    {"bits": [8, 15], "name": "swa_addr_region"},
13521    {"bits": [16, 31], "name": "RESERVED"}
13522   ]
13523  },
13524  "RLC_SPM_ACCUM_DATARAM_ADDR": {
13525   "fields": [
13526    {"bits": [0, 6], "name": "addr"},
13527    {"bits": [7, 31], "name": "RESERVED"}
13528   ]
13529  },
13530  "RLC_SPM_ACCUM_DATARAM_WRCOUNT": {
13531   "fields": [
13532    {"bits": [0, 18], "name": "DataRamWrCount"},
13533    {"bits": [19, 31], "name": "RESERVED"}
13534   ]
13535  },
13536  "RLC_SPM_ACCUM_MODE": {
13537   "fields": [
13538    {"bits": [0, 0], "name": "EnableAccum"},
13539    {"bits": [1, 1], "name": "EnableSpmWithAccumMode"},
13540    {"bits": [2, 2], "name": "EnableSPPMode"},
13541    {"bits": [3, 3], "name": "AutoResetPerfmonDisable"},
13542    {"bits": [5, 5], "name": "AutoAccumEn"},
13543    {"bits": [6, 6], "name": "SwaAutoAccumEn"},
13544    {"bits": [7, 7], "name": "AutoSpmEn"},
13545    {"bits": [8, 8], "name": "SwaAutoSpmEn"},
13546    {"bits": [9, 9], "name": "Globals_LoadOverride"},
13547    {"bits": [10, 10], "name": "Globals_SwaLoadOverride"},
13548    {"bits": [11, 11], "name": "SE0_LoadOverride"},
13549    {"bits": [12, 12], "name": "SE0_SwaLoadOverride"},
13550    {"bits": [13, 13], "name": "SE1_LoadOverride"},
13551    {"bits": [14, 14], "name": "SE1_SwaLoadOverride"},
13552    {"bits": [15, 15], "name": "SE2_LoadOverride"},
13553    {"bits": [16, 16], "name": "SE2_SwaLoadOverride"},
13554    {"bits": [17, 17], "name": "SE3_LoadOverride"},
13555    {"bits": [18, 18], "name": "SE3_SwaLoadOverride"},
13556    {"bits": [19, 19], "name": "SE4_LoadOverride"},
13557    {"bits": [20, 20], "name": "SE4_SwaLoadOverride"},
13558    {"bits": [21, 21], "name": "SE5_LoadOverride"},
13559    {"bits": [22, 22], "name": "SE5_SwaLoadOverride"}
13560   ]
13561  },
13562  "RLC_SPM_ACCUM_SAMPLES_REQUESTED": {
13563   "fields": [
13564    {"bits": [0, 7], "name": "SamplesRequested"}
13565   ]
13566  },
13567  "RLC_SPM_ACCUM_STATUS": {
13568   "fields": [
13569    {"bits": [0, 7], "name": "NumbSamplesCompleted"},
13570    {"bits": [8, 8], "name": "AccumDone"},
13571    {"bits": [9, 9], "name": "SpmDone"},
13572    {"bits": [10, 10], "name": "AccumOverflow"},
13573    {"bits": [11, 11], "name": "AccumArmed"},
13574    {"bits": [12, 12], "name": "SequenceInProgress"},
13575    {"bits": [13, 13], "name": "FinalSequenceInProgress"},
13576    {"bits": [14, 14], "name": "AllFifosEmpty"},
13577    {"bits": [15, 15], "name": "FSMIsIdle"},
13578    {"bits": [16, 16], "name": "SwaAccumDone"},
13579    {"bits": [17, 17], "name": "SwaSpmDone"},
13580    {"bits": [18, 18], "name": "SwaAccumOverflow"},
13581    {"bits": [19, 19], "name": "SwaAccumArmed"},
13582    {"bits": [20, 20], "name": "AllSegsDone"},
13583    {"bits": [21, 21], "name": "RearmSwaPending"},
13584    {"bits": [22, 22], "name": "RearmSppPending"},
13585    {"bits": [23, 23], "name": "MultiSampleAborted"},
13586    {"bits": [24, 31], "name": "RESERVED"}
13587   ]
13588  },
13589  "RLC_SPM_ACCUM_THRESHOLD": {
13590   "fields": [
13591    {"bits": [0, 15], "name": "Threshold"}
13592   ]
13593  },
13594  "RLC_SPM_GLOBAL_MUXSEL_ADDR": {
13595   "fields": [
13596    {"bits": [0, 11], "name": "ADDR"}
13597   ]
13598  },
13599  "RLC_SPM_GLOBAL_MUXSEL_DATA": {
13600   "fields": [
13601    {"bits": [0, 15], "name": "SEL0"},
13602    {"bits": [16, 31], "name": "SEL1"}
13603   ]
13604  },
13605  "RLC_SPM_MODE": {
13606   "fields": [
13607    {"bits": [0, 0], "name": "MODE"}
13608   ]
13609  },
13610  "RLC_SPM_PAUSE": {
13611   "fields": [
13612    {"bits": [0, 0], "name": "PAUSE"},
13613    {"bits": [1, 1], "name": "PAUSED"}
13614   ]
13615  },
13616  "RLC_SPM_PERFMON_CNTL": {
13617   "fields": [
13618    {"bits": [0, 11], "name": "RESERVED1"},
13619    {"bits": [12, 13], "name": "PERFMON_RING_MODE"},
13620    {"bits": [14, 14], "name": "DISABLE_GFXCLOCK_COUNT"},
13621    {"bits": [15, 15], "name": "RESERVED"},
13622    {"bits": [16, 31], "name": "PERFMON_SAMPLE_INTERVAL"}
13623   ]
13624  },
13625  "RLC_SPM_PERFMON_RING_BASE_HI": {
13626   "fields": [
13627    {"bits": [0, 15], "name": "RING_BASE_HI"},
13628    {"bits": [16, 31], "name": "RESERVED"}
13629   ]
13630  },
13631  "RLC_SPM_PERFMON_SEGMENT_SIZE": {
13632   "fields": [
13633    {"bits": [0, 15], "name": "TOTAL_NUM_SEGMENT"},
13634    {"bits": [16, 23], "name": "GLOBAL_NUM_SEGMENT"},
13635    {"bits": [24, 31], "name": "SE_NUM_SEGMENT"}
13636   ]
13637  },
13638  "RLC_SPM_RING_WRPTR": {
13639   "fields": [
13640    {"bits": [0, 4], "name": "RESERVED"},
13641    {"bits": [5, 31], "name": "PERFMON_RING_WRPTR"}
13642   ]
13643  },
13644  "RLC_SPM_RSPM_CMD": {
13645   "fields": [
13646    {"bits": [0, 3], "name": "CMD"}
13647   ]
13648  },
13649  "RLC_SPM_RSPM_CMD_ACK": {
13650   "fields": [
13651    {"bits": [0, 0], "name": "SE0_ACK"},
13652    {"bits": [1, 1], "name": "SE1_ACK"},
13653    {"bits": [2, 2], "name": "SE2_ACK"},
13654    {"bits": [3, 3], "name": "SE3_ACK"},
13655    {"bits": [4, 4], "name": "SE4_ACK"},
13656    {"bits": [5, 5], "name": "SE5_ACK"},
13657    {"bits": [6, 6], "name": "SE6_ACK"},
13658    {"bits": [7, 7], "name": "SE7_ACK"},
13659    {"bits": [8, 8], "name": "SPM_ACK"}
13660   ]
13661  },
13662  "RLC_SPM_RSPM_REQ_DATA_HI": {
13663   "fields": [
13664    {"bits": [0, 11], "name": "DATA"}
13665   ]
13666  },
13667  "RLC_SPM_RSPM_REQ_OP": {
13668   "fields": [
13669    {"bits": [0, 3], "name": "OP"}
13670   ]
13671  },
13672  "RLC_SPM_RSPM_RET_OP": {
13673   "fields": [
13674    {"bits": [0, 3], "name": "OP"},
13675    {"bits": [8, 8], "name": "VALID"}
13676   ]
13677  },
13678  "RLC_SPM_SEGMENT_THRESHOLD": {
13679   "fields": [
13680    {"bits": [0, 7], "name": "NUM_SEGMENT_THRESHOLD"},
13681    {"bits": [8, 31], "name": "RESERVED"}
13682   ]
13683  },
13684  "RLC_SPM_STATUS": {
13685   "fields": [
13686    {"bits": [0, 0], "name": "CTL_BUSY"},
13687    {"bits": [1, 1], "name": "RSPM_REG_BUSY"},
13688    {"bits": [2, 2], "name": "SPM_RSPM_BUSY"},
13689    {"bits": [3, 3], "name": "SPM_RSPM_IO_BUSY"},
13690    {"bits": [4, 11], "name": "SE_RSPM_IO_BUSY"},
13691    {"bits": [15, 15], "name": "ACCUM_BUSY"},
13692    {"bits": [16, 19], "name": "FSM_MASTER_STATE"},
13693    {"bits": [20, 23], "name": "FSM_MEMORY_STATE"},
13694    {"bits": [24, 25], "name": "CTL_REQ_STATE"},
13695    {"bits": [26, 26], "name": "CTL_RET_STATE"}
13696   ]
13697  },
13698  "RMI_PERF_COUNTER_CNTL": {
13699   "fields": [
13700    {"bits": [0, 1], "name": "TRANS_BASED_PERF_EN_SEL"},
13701    {"bits": [2, 3], "name": "EVENT_BASED_PERF_EN_SEL"},
13702    {"bits": [4, 5], "name": "TC_PERF_EN_SEL"},
13703    {"bits": [6, 7], "name": "PERF_EVENT_WINDOW_MASK0"},
13704    {"bits": [8, 9], "name": "PERF_EVENT_WINDOW_MASK1"},
13705    {"bits": [10, 13], "name": "PERF_COUNTER_CID"},
13706    {"bits": [14, 18], "name": "PERF_COUNTER_VMID"},
13707    {"bits": [19, 24], "name": "PERF_COUNTER_BURST_LENGTH_THRESHOLD"},
13708    {"bits": [25, 25], "name": "PERF_SOFT_RESET"},
13709    {"bits": [26, 26], "name": "PERF_CNTR_SPM_SEL"}
13710   ]
13711  },
13712  "SCRATCH_REG_ATOMIC": {
13713   "fields": [
13714    {"bits": [0, 23], "name": "IMMED"},
13715    {"bits": [24, 26], "name": "ID"},
13716    {"bits": [27, 27], "name": "reserved27"},
13717    {"bits": [28, 30], "name": "OP"},
13718    {"bits": [31, 31], "name": "reserved31"}
13719   ]
13720  },
13721  "SDMA0_PERFCNT_MISC_CNTL": {
13722   "fields": [
13723    {"bits": [0, 15], "name": "CMD_OP"}
13724   ]
13725  },
13726  "SDMA0_PERFCNT_PERFCOUNTER0_CFG": {
13727   "fields": [
13728    {"bits": [0, 7], "name": "PERF_SEL"},
13729    {"bits": [8, 15], "name": "PERF_SEL_END"},
13730    {"bits": [24, 27], "name": "PERF_MODE"},
13731    {"bits": [28, 28], "name": "ENABLE"},
13732    {"bits": [29, 29], "name": "CLEAR"}
13733   ]
13734  },
13735  "SDMA0_PERFCNT_PERFCOUNTER_HI": {
13736   "fields": [
13737    {"bits": [0, 15], "name": "COUNTER_HI"},
13738    {"bits": [16, 31], "name": "COMPARE_VALUE"}
13739   ]
13740  },
13741  "SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL": {
13742   "fields": [
13743    {"bits": [0, 3], "name": "PERF_COUNTER_SELECT"},
13744    {"bits": [8, 15], "name": "START_TRIGGER"},
13745    {"bits": [16, 23], "name": "STOP_TRIGGER"},
13746    {"bits": [24, 24], "name": "ENABLE_ANY"},
13747    {"bits": [25, 25], "name": "CLEAR_ALL"},
13748    {"bits": [26, 26], "name": "STOP_ALL_ON_SATURATE"}
13749   ]
13750  },
13751  "SDMA0_PERFCOUNTER0_SELECT": {
13752   "fields": [
13753    {"bits": [0, 9], "name": "PERF_SEL"},
13754    {"bits": [10, 19], "name": "PERF_SEL1"},
13755    {"bits": [20, 23], "name": "CNTR_MODE"},
13756    {"bits": [24, 27], "name": "PERF_MODE1"},
13757    {"bits": [28, 31], "name": "PERF_MODE"}
13758   ]
13759  },
13760  "SDMA0_PERFCOUNTER0_SELECT1": {
13761   "fields": [
13762    {"bits": [0, 9], "name": "PERF_SEL2"},
13763    {"bits": [10, 19], "name": "PERF_SEL3"},
13764    {"bits": [24, 27], "name": "PERF_MODE3"},
13765    {"bits": [28, 31], "name": "PERF_MODE2"}
13766   ]
13767  },
13768  "SPI_ATTRIBUTE_RING_SIZE": {
13769   "fields": [
13770    {"bits": [0, 7], "name": "MEM_SIZE"},
13771    {"bits": [16, 16], "name": "BIG_PAGE"},
13772    {"bits": [17, 18], "name": "L1_POLICY"},
13773    {"bits": [19, 20], "name": "L2_POLICY"},
13774    {"bits": [21, 21], "name": "LLC_NOALLOC"},
13775    {"bits": [22, 22], "name": "GL1_PERF_COUNTER_DISABLE"}
13776   ]
13777  },
13778  "SPI_BARYC_CNTL": {
13779   "fields": [
13780    {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"},
13781    {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"},
13782    {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"},
13783    {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"},
13784    {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"},
13785    {"bits": [20, 20], "name": "POS_FLOAT_ULC"},
13786    {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"}
13787   ]
13788  },
13789  "SPI_CONFIG_CNTL": {
13790   "fields": [
13791    {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"},
13792    {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"},
13793    {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"},
13794    {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"},
13795    {"bits": [28, 28], "name": "ALLOC_ARB_LRU_ENA"},
13796    {"bits": [29, 29], "name": "EXP_ARB_LRU_ENA"},
13797    {"bits": [30, 31], "name": "PS_PKR_PRIORITY_CNTL"}
13798   ]
13799  },
13800  "SPI_CONFIG_CNTL_1": {
13801   "fields": [
13802    {"bits": [0, 3], "name": "VTX_DONE_DELAY"},
13803    {"bits": [4, 4], "name": "INTERP_ONE_PRIM_PER_ROW"},
13804    {"bits": [5, 6], "name": "PC_LIMIT_ENABLE"},
13805    {"bits": [7, 7], "name": "PC_LIMIT_STRICT"},
13806    {"bits": [8, 8], "name": "PS_GROUP_TIMEOUT_MODE"},
13807    {"bits": [9, 9], "name": "OREO_EXPALLOC_STALL"},
13808    {"bits": [10, 13], "name": "LBPW_CU_CHK_CNT"},
13809    {"bits": [14, 14], "name": "CSC_PWR_SAVE_DISABLE"},
13810    {"bits": [15, 15], "name": "CSG_PWR_SAVE_DISABLE"},
13811    {"bits": [16, 20], "name": "MAX_VTX_SYNC_CNT"},
13812    {"bits": [21, 21], "name": "EN_USER_ACCUM"},
13813    {"bits": [22, 22], "name": "SA_SCREEN_MAP"},
13814    {"bits": [23, 31], "name": "PS_GROUP_TIMEOUT"}
13815   ]
13816  },
13817  "SPI_CONFIG_CNTL_2": {
13818   "fields": [
13819    {"bits": [0, 3], "name": "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD"},
13820    {"bits": [4, 7], "name": "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD"},
13821    {"bits": [8, 8], "name": "PWS_CSG_WAIT_DISABLE"},
13822    {"bits": [9, 9], "name": "PWS_HS_WAIT_DISABLE"},
13823    {"bits": [10, 10], "name": "PWS_GS_WAIT_DISABLE"},
13824    {"bits": [11, 11], "name": "PWS_PS_WAIT_DISABLE"},
13825    {"bits": [12, 16], "name": "CSC_HALT_ACK_DELAY"}
13826   ]
13827  },
13828  "SPI_GS_THROTTLE_CNTL1": {
13829   "fields": [
13830    {"bits": [0, 3], "name": "PH_POLL_INTERVAL"},
13831    {"bits": [4, 7], "name": "PH_THROTTLE_BASE"},
13832    {"bits": [8, 11], "name": "PH_THROTTLE_STEP_SIZE"},
13833    {"bits": [12, 15], "name": "SPI_VGPR_THRESHOLD"},
13834    {"bits": [16, 19], "name": "SPI_LDS_THRESHOLD"},
13835    {"bits": [20, 23], "name": "SPI_POLL_INTERVAL"},
13836    {"bits": [24, 27], "name": "SPI_THROTTLE_BASE"},
13837    {"bits": [28, 31], "name": "SPI_THROTTLE_STEP_SIZE"}
13838   ]
13839  },
13840  "SPI_GS_THROTTLE_CNTL2": {
13841   "fields": [
13842    {"bits": [0, 1], "name": "SPI_THROTTLE_MODE"},
13843    {"bits": [2, 5], "name": "GRP_LIFETIME_THRESHOLD"},
13844    {"bits": [6, 7], "name": "GRP_LIFETIME_THRESHOLD_FACTOR"},
13845    {"bits": [8, 10], "name": "GRP_LIFETIME_PENALTY1"},
13846    {"bits": [11, 13], "name": "GRP_LIFETIME_PENALTY2"},
13847    {"bits": [14, 15], "name": "PS_STALL_THRESHOLD"},
13848    {"bits": [16, 16], "name": "PH_MODE"},
13849    {"bits": [17, 31], "name": "RESERVED"}
13850   ]
13851  },
13852  "SPI_INTERP_CONTROL_0": {
13853   "fields": [
13854    {"bits": [0, 0], "name": "FLAT_SHADE_ENA"},
13855    {"bits": [1, 1], "name": "PNT_SPRITE_ENA"},
13856    {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"},
13857    {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"},
13858    {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"},
13859    {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"},
13860    {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"}
13861   ]
13862  },
13863  "SPI_PERFCOUNTER_BINS": {
13864   "fields": [
13865    {"bits": [0, 3], "name": "BIN0_MIN"},
13866    {"bits": [4, 7], "name": "BIN0_MAX"},
13867    {"bits": [8, 11], "name": "BIN1_MIN"},
13868    {"bits": [12, 15], "name": "BIN1_MAX"},
13869    {"bits": [16, 19], "name": "BIN2_MIN"},
13870    {"bits": [20, 23], "name": "BIN2_MAX"},
13871    {"bits": [24, 27], "name": "BIN3_MIN"},
13872    {"bits": [28, 31], "name": "BIN3_MAX"}
13873   ]
13874  },
13875  "SPI_PS_INPUT_CNTL_0": {
13876   "fields": [
13877    {"bits": [0, 5], "name": "OFFSET"},
13878    {"bits": [8, 9], "name": "DEFAULT_VAL"},
13879    {"bits": [10, 10], "name": "FLAT_SHADE"},
13880    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
13881    {"bits": [12, 12], "name": "PRIM_ATTR"},
13882    {"bits": [17, 17], "name": "PT_SPRITE_TEX"},
13883    {"bits": [18, 18], "name": "DUP"},
13884    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
13885    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
13886    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
13887    {"bits": [23, 23], "name": "PT_SPRITE_TEX_ATTR1"},
13888    {"bits": [24, 24], "name": "ATTR0_VALID"},
13889    {"bits": [25, 25], "name": "ATTR1_VALID"}
13890   ]
13891  },
13892  "SPI_PS_INPUT_CNTL_20": {
13893   "fields": [
13894    {"bits": [0, 5], "name": "OFFSET"},
13895    {"bits": [8, 9], "name": "DEFAULT_VAL"},
13896    {"bits": [10, 10], "name": "FLAT_SHADE"},
13897    {"bits": [11, 11], "name": "ROTATE_PC_PTR"},
13898    {"bits": [12, 12], "name": "PRIM_ATTR"},
13899    {"bits": [18, 18], "name": "DUP"},
13900    {"bits": [19, 19], "name": "FP16_INTERP_MODE"},
13901    {"bits": [20, 20], "name": "USE_DEFAULT_ATTR1"},
13902    {"bits": [21, 22], "name": "DEFAULT_VAL_ATTR1"},
13903    {"bits": [24, 24], "name": "ATTR0_VALID"},
13904    {"bits": [25, 25], "name": "ATTR1_VALID"}
13905   ]
13906  },
13907  "SPI_PS_INPUT_ENA": {
13908   "fields": [
13909    {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"},
13910    {"bits": [1, 1], "name": "PERSP_CENTER_ENA"},
13911    {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"},
13912    {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"},
13913    {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"},
13914    {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"},
13915    {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"},
13916    {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"},
13917    {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"},
13918    {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"},
13919    {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"},
13920    {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"},
13921    {"bits": [12, 12], "name": "FRONT_FACE_ENA"},
13922    {"bits": [13, 13], "name": "ANCILLARY_ENA"},
13923    {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"},
13924    {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"}
13925   ]
13926  },
13927  "SPI_PS_IN_CONTROL": {
13928   "fields": [
13929    {"bits": [0, 5], "name": "NUM_INTERP"},
13930    {"bits": [6, 6], "name": "PARAM_GEN"},
13931    {"bits": [7, 7], "name": "OFFCHIP_PARAM_EN"},
13932    {"bits": [8, 8], "name": "LATE_PC_DEALLOC"},
13933    {"bits": [9, 13], "name": "NUM_PRIM_INTERP"},
13934    {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"},
13935    {"bits": [15, 15], "name": "PS_W32_EN"}
13936   ]
13937  },
13938  "SPI_SHADER_COL_FORMAT": {
13939   "fields": [
13940    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"},
13941    {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"},
13942    {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"},
13943    {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"},
13944    {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"},
13945    {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"},
13946    {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"},
13947    {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"}
13948   ]
13949  },
13950  "SPI_SHADER_GS_MESHLET_DIM": {
13951   "fields": [
13952    {"bits": [0, 7], "name": "MESHLET_NUM_THREAD_X"},
13953    {"bits": [8, 15], "name": "MESHLET_NUM_THREAD_Y"},
13954    {"bits": [16, 23], "name": "MESHLET_NUM_THREAD_Z"},
13955    {"bits": [24, 31], "name": "MESHLET_THREADGROUP_SIZE"}
13956   ]
13957  },
13958  "SPI_SHADER_GS_MESHLET_EXP_ALLOC": {
13959   "fields": [
13960    {"bits": [0, 8], "name": "MAX_EXP_VERTS"},
13961    {"bits": [9, 17], "name": "MAX_EXP_PRIMS"}
13962   ]
13963  },
13964  "SPI_SHADER_IDX_FORMAT": {
13965   "fields": [
13966    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "IDX0_EXPORT_FORMAT"}
13967   ]
13968  },
13969  "SPI_SHADER_PGM_HI_PS": {
13970   "fields": [
13971    {"bits": [0, 7], "name": "MEM_BASE"}
13972   ]
13973  },
13974  "SPI_SHADER_PGM_RSRC1_GS": {
13975   "fields": [
13976    {"bits": [0, 5], "name": "VGPRS"},
13977    {"bits": [6, 9], "name": "SGPRS"},
13978    {"bits": [10, 11], "name": "PRIORITY"},
13979    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
13980    {"bits": [20, 20], "name": "PRIV"},
13981    {"bits": [21, 21], "name": "DX10_CLAMP"},
13982    {"bits": [23, 23], "name": "IEEE_MODE"},
13983    {"bits": [24, 24], "name": "CU_GROUP_ENABLE"},
13984    {"bits": [25, 25], "name": "MEM_ORDERED"},
13985    {"bits": [26, 26], "name": "FWD_PROGRESS"},
13986    {"bits": [27, 27], "name": "WGP_MODE"},
13987    {"bits": [29, 30], "name": "GS_VGPR_COMP_CNT"},
13988    {"bits": [31, 31], "name": "FP16_OVFL"}
13989   ]
13990  },
13991  "SPI_SHADER_PGM_RSRC1_HS": {
13992   "fields": [
13993    {"bits": [0, 5], "name": "VGPRS"},
13994    {"bits": [6, 9], "name": "SGPRS"},
13995    {"bits": [10, 11], "name": "PRIORITY"},
13996    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
13997    {"bits": [20, 20], "name": "PRIV"},
13998    {"bits": [21, 21], "name": "DX10_CLAMP"},
13999    {"bits": [23, 23], "name": "IEEE_MODE"},
14000    {"bits": [24, 24], "name": "MEM_ORDERED"},
14001    {"bits": [25, 25], "name": "FWD_PROGRESS"},
14002    {"bits": [26, 26], "name": "WGP_MODE"},
14003    {"bits": [28, 29], "name": "LS_VGPR_COMP_CNT"},
14004    {"bits": [30, 30], "name": "FP16_OVFL"}
14005   ]
14006  },
14007  "SPI_SHADER_PGM_RSRC1_PS": {
14008   "fields": [
14009    {"bits": [0, 5], "name": "VGPRS"},
14010    {"bits": [6, 9], "name": "SGPRS"},
14011    {"bits": [10, 11], "name": "PRIORITY"},
14012    {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"},
14013    {"bits": [20, 20], "name": "PRIV"},
14014    {"bits": [21, 21], "name": "DX10_CLAMP"},
14015    {"bits": [23, 23], "name": "IEEE_MODE"},
14016    {"bits": [24, 24], "name": "CU_GROUP_DISABLE"},
14017    {"bits": [25, 25], "name": "MEM_ORDERED"},
14018    {"bits": [26, 26], "name": "FWD_PROGRESS"},
14019    {"bits": [27, 27], "name": "LOAD_PROVOKING_VTX"},
14020    {"bits": [29, 29], "name": "FP16_OVFL"}
14021   ]
14022  },
14023  "SPI_SHADER_PGM_RSRC2_GS": {
14024   "fields": [
14025    {"bits": [0, 0], "name": "SCRATCH_EN"},
14026    {"bits": [1, 5], "name": "USER_SGPR"},
14027    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14028    {"bits": [7, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14029    {"bits": [16, 17], "name": "ES_VGPR_COMP_CNT"},
14030    {"bits": [18, 18], "name": "OC_LDS_EN"},
14031    {"bits": [19, 26], "name": "LDS_SIZE"},
14032    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14033    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14034   ]
14035  },
14036  "SPI_SHADER_PGM_RSRC2_HS": {
14037   "fields": [
14038    {"bits": [0, 0], "name": "SCRATCH_EN"},
14039    {"bits": [1, 5], "name": "USER_SGPR"},
14040    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14041    {"bits": [7, 7], "name": "OC_LDS_EN"},
14042    {"bits": [8, 8], "name": "TG_SIZE_EN"},
14043    {"bits": [9, 17], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14044    {"bits": [18, 26], "name": "LDS_SIZE"},
14045    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14046    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14047   ]
14048  },
14049  "SPI_SHADER_PGM_RSRC2_PS": {
14050   "fields": [
14051    {"bits": [0, 0], "name": "SCRATCH_EN"},
14052    {"bits": [1, 5], "name": "USER_SGPR"},
14053    {"bits": [6, 6], "name": "TRAP_PRESENT"},
14054    {"bits": [7, 7], "name": "WAVE_CNT_EN"},
14055    {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"},
14056    {"bits": [16, 24], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14057    {"bits": [25, 25], "name": "LOAD_COLLISION_WAVEID"},
14058    {"bits": [26, 26], "name": "LOAD_INTRAWAVE_COLLISION"},
14059    {"bits": [27, 27], "name": "USER_SGPR_MSB"},
14060    {"bits": [28, 31], "name": "SHARED_VGPR_CNT"}
14061   ]
14062  },
14063  "SPI_SHADER_PGM_RSRC3_GS": {
14064   "fields": [
14065    {"bits": [0, 15], "name": "CU_EN"},
14066    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14067    {"bits": [22, 25], "name": "LOCK_LOW_THRESHOLD"},
14068    {"bits": [26, 31], "name": "GROUP_FIFO_DEPTH"}
14069   ]
14070  },
14071  "SPI_SHADER_PGM_RSRC3_HS": {
14072   "fields": [
14073    {"bits": [0, 5], "name": "WAVE_LIMIT"},
14074    {"bits": [6, 9], "name": "LOCK_LOW_THRESHOLD"},
14075    {"bits": [10, 15], "name": "GROUP_FIFO_DEPTH"},
14076    {"bits": [16, 31], "name": "CU_EN"}
14077   ]
14078  },
14079  "SPI_SHADER_PGM_RSRC3_PS": {
14080   "fields": [
14081    {"bits": [0, 15], "name": "CU_EN"},
14082    {"bits": [16, 21], "name": "WAVE_LIMIT"},
14083    {"bits": [22, 23], "name": "LDS_GROUP_SIZE"}
14084   ]
14085  },
14086  "SPI_SHADER_PGM_RSRC4_GS": {
14087   "fields": [
14088    {"bits": [0, 0], "name": "CU_EN"},
14089    {"bits": [1, 13], "name": "RESERVED"},
14090    {"bits": [14, 14], "name": "PH_THROTTLE_EN"},
14091    {"bits": [15, 15], "name": "SPI_THROTTLE_EN"},
14092    {"bits": [16, 22], "name": "SPI_SHADER_LATE_ALLOC_GS"},
14093    {"bits": [23, 28], "name": "INST_PREF_SIZE"},
14094    {"bits": [29, 29], "name": "TRAP_ON_START"},
14095    {"bits": [30, 30], "name": "TRAP_ON_END"},
14096    {"bits": [31, 31], "name": "IMAGE_OP"}
14097   ]
14098  },
14099  "SPI_SHADER_PGM_RSRC4_PS": {
14100   "fields": [
14101    {"bits": [0, 15], "name": "CU_EN"},
14102    {"bits": [16, 21], "name": "INST_PREF_SIZE"},
14103    {"bits": [29, 29], "name": "TRAP_ON_START"},
14104    {"bits": [30, 30], "name": "TRAP_ON_END"},
14105    {"bits": [31, 31], "name": "IMAGE_OP"}
14106   ]
14107  },
14108  "SPI_SHADER_POS_FORMAT": {
14109   "fields": [
14110    {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"},
14111    {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"},
14112    {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"},
14113    {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"},
14114    {"bits": [16, 19], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS4_EXPORT_FORMAT"}
14115   ]
14116  },
14117  "SPI_SHADER_REQ_CTRL_PS": {
14118   "fields": [
14119    {"bits": [0, 0], "name": "SOFT_GROUPING_EN"},
14120    {"bits": [1, 4], "name": "NUMBER_OF_REQUESTS_PER_CU"},
14121    {"bits": [5, 8], "name": "SOFT_GROUPING_ALLOCATION_TIMEOUT"},
14122    {"bits": [9, 9], "name": "HARD_LOCK_HYSTERESIS"},
14123    {"bits": [10, 14], "name": "HARD_LOCK_LOW_THRESHOLD"},
14124    {"bits": [15, 15], "name": "PRODUCER_REQUEST_LOCKOUT"},
14125    {"bits": [16, 16], "name": "GLOBAL_SCANNING_EN"},
14126    {"bits": [17, 19], "name": "ALLOCATION_RATE_THROTTLING_THRESHOLD"}
14127   ]
14128  },
14129  "SPI_SHADER_USER_ACCUM_PS_0": {
14130   "fields": [
14131    {"bits": [0, 6], "name": "CONTRIBUTION"}
14132   ]
14133  },
14134  "SPI_SHADER_Z_FORMAT": {
14135   "fields": [
14136    {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"}
14137   ]
14138  },
14139  "SPI_VS_OUT_CONFIG": {
14140   "fields": [
14141    {"bits": [1, 5], "name": "VS_EXPORT_COUNT"},
14142    {"bits": [7, 7], "name": "NO_PC_EXPORT"},
14143    {"bits": [8, 12], "name": "PRIM_EXPORT_COUNT"}
14144   ]
14145  },
14146  "SPI_WAVE_LIMIT_CNTL": {
14147   "fields": [
14148    {"bits": [0, 1], "name": "PS_WAVE_GRAN"},
14149    {"bits": [4, 5], "name": "GS_WAVE_GRAN"},
14150    {"bits": [6, 7], "name": "HS_WAVE_GRAN"}
14151   ]
14152  },
14153  "SQC_CACHES": {
14154   "fields": [
14155    {"bits": [0, 0], "name": "TARGET_INST"},
14156    {"bits": [1, 1], "name": "TARGET_DATA"},
14157    {"bits": [2, 2], "name": "INVALIDATE"},
14158    {"bits": [16, 16], "name": "COMPLETE"}
14159   ]
14160  },
14161  "SQG_PERFCOUNTER_CTRL": {
14162   "fields": [
14163    {"bits": [0, 0], "name": "PS_EN"},
14164    {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14165    {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14166    {"bits": [6, 6], "name": "CS_EN"},
14167    {"bits": [14, 14], "name": "DISABLE_ME0PIPE0_PERF"},
14168    {"bits": [15, 15], "name": "DISABLE_ME0PIPE1_PERF"},
14169    {"bits": [16, 16], "name": "DISABLE_ME1PIPE0_PERF"},
14170    {"bits": [17, 17], "name": "DISABLE_ME1PIPE1_PERF"},
14171    {"bits": [18, 18], "name": "DISABLE_ME1PIPE2_PERF"},
14172    {"bits": [19, 19], "name": "DISABLE_ME1PIPE3_PERF"}
14173   ]
14174  },
14175  "SQG_PERFCOUNTER_CTRL2": {
14176   "fields": [
14177    {"bits": [0, 0], "name": "FORCE_EN"},
14178    {"bits": [1, 16], "name": "VMID_EN"}
14179   ]
14180  },
14181  "SQG_PERF_SAMPLE_FINISH": {
14182   "fields": [
14183    {"bits": [0, 6], "name": "STATUS"}
14184   ]
14185  },
14186  "SQ_PERFCOUNTER0_SELECT": {
14187   "fields": [
14188    {"bits": [0, 8], "name": "PERF_SEL"},
14189    {"bits": [20, 23], "name": "SPM_MODE"},
14190    {"bits": [28, 31], "name": "PERF_MODE"}
14191   ]
14192  },
14193  "SQ_THREAD_TRACE_BUF0_SIZE": {
14194   "fields": [
14195    {"bits": [0, 3], "name": "BASE_HI"},
14196    {"bits": [8, 29], "name": "SIZE"}
14197   ]
14198  },
14199  "SQ_THREAD_TRACE_CTRL": {
14200   "fields": [
14201    {"bits": [0, 1], "name": "MODE"},
14202    {"bits": [2, 2], "name": "ALL_VMID"},
14203    {"bits": [3, 3], "name": "GL1_PERF_EN"},
14204    {"bits": [4, 4], "name": "INTERRUPT_EN"},
14205    {"bits": [5, 5], "name": "DOUBLE_BUFFER"},
14206    {"bits": [6, 8], "name": "HIWATER"},
14207    {"bits": [9, 10], "name": "REG_AT_HWM"},
14208    {"bits": [11, 11], "name": "SPI_STALL_EN"},
14209    {"bits": [12, 12], "name": "SQ_STALL_EN"},
14210    {"bits": [13, 13], "name": "UTIL_TIMER"},
14211    {"bits": [14, 15], "name": "WAVESTART_MODE"},
14212    {"bits": [16, 17], "name": "RT_FREQ"},
14213    {"bits": [18, 18], "name": "SYNC_COUNT_MARKERS"},
14214    {"bits": [19, 19], "name": "SYNC_COUNT_DRAWS"},
14215    {"bits": [20, 22], "name": "LOWATER_OFFSET"},
14216    {"bits": [28, 28], "name": "AUTO_FLUSH_PADDING_DIS"},
14217    {"bits": [29, 29], "name": "AUTO_FLUSH_MODE"},
14218    {"bits": [31, 31], "name": "DRAW_EVENT_EN"}
14219   ]
14220  },
14221  "SQ_THREAD_TRACE_MASK": {
14222   "fields": [
14223    {"bits": [0, 1], "name": "SIMD_SEL"},
14224    {"bits": [4, 7], "name": "WGP_SEL"},
14225    {"bits": [9, 9], "name": "SA_SEL"},
14226    {"bits": [10, 16], "name": "WTYPE_INCLUDE"},
14227    {"bits": [17, 17], "name": "EXCLUDE_NONDETAIL_SHADERDATA"}
14228   ]
14229  },
14230  "SQ_THREAD_TRACE_STATUS": {
14231   "fields": [
14232    {"bits": [0, 11], "name": "FINISH_PENDING"},
14233    {"bits": [12, 23], "name": "FINISH_DONE"},
14234    {"bits": [24, 24], "name": "WRITE_ERROR"},
14235    {"bits": [25, 25], "name": "BUSY"},
14236    {"bits": [28, 31], "name": "OWNER_VMID"}
14237   ]
14238  },
14239  "SQ_THREAD_TRACE_STATUS2": {
14240   "fields": [
14241    {"bits": [0, 0], "name": "BUF0_FULL"},
14242    {"bits": [1, 1], "name": "BUF1_FULL"},
14243    {"bits": [4, 4], "name": "PACKET_LOST_BUF_NO_LOCKDOWN"},
14244    {"bits": [8, 12], "name": "BUF_ISSUE_STATUS"},
14245    {"bits": [13, 13], "name": "BUF_ISSUE"},
14246    {"bits": [14, 14], "name": "WRITE_BUF_FULL"}
14247   ]
14248  },
14249  "SQ_THREAD_TRACE_TOKEN_MASK": {
14250   "fields": [
14251    {"bits": [0, 10], "enum_ref": "ThreadTraceTokenExclude", "name": "TOKEN_EXCLUDE"},
14252    {"bits": [11, 11], "name": "TTRACE_EXEC"},
14253    {"bits": [12, 12], "name": "BOP_EVENTS_TOKEN_INCLUDE"},
14254    {"bits": [16, 23], "enum_ref": "ThreadTraceRegInclude", "name": "REG_INCLUDE"},
14255    {"bits": [24, 25], "name": "INST_EXCLUDE"},
14256    {"bits": [26, 28], "name": "REG_EXCLUDE"},
14257    {"bits": [31, 31], "name": "REG_DETAIL_ALL"}
14258   ]
14259  },
14260  "SQ_THREAD_TRACE_WPTR": {
14261   "fields": [
14262    {"bits": [0, 28], "name": "OFFSET"},
14263    {"bits": [31, 31], "name": "BUFFER_ID"}
14264   ]
14265  },
14266  "SQ_WAVE_ACTIVE": {
14267   "fields": [
14268    {"bits": [0, 19], "name": "WAVE_SLOT"}
14269   ]
14270  },
14271  "SQ_WAVE_GPR_ALLOC": {
14272   "fields": [
14273    {"bits": [0, 8], "name": "VGPR_BASE"},
14274    {"bits": [12, 19], "name": "VGPR_SIZE"}
14275   ]
14276  },
14277  "SQ_WAVE_HW_ID1": {
14278   "fields": [
14279    {"bits": [0, 4], "name": "WAVE_ID"},
14280    {"bits": [8, 9], "name": "SIMD_ID"},
14281    {"bits": [10, 13], "name": "WGP_ID"},
14282    {"bits": [16, 16], "name": "SA_ID"},
14283    {"bits": [18, 20], "name": "SE_ID"},
14284    {"bits": [29, 31], "name": "DP_RATE"}
14285   ]
14286  },
14287  "SQ_WAVE_HW_ID2": {
14288   "fields": [
14289    {"bits": [0, 3], "name": "QUEUE_ID"},
14290    {"bits": [4, 5], "name": "PIPE_ID"},
14291    {"bits": [8, 9], "name": "ME_ID"},
14292    {"bits": [12, 14], "name": "STATE_ID"},
14293    {"bits": [16, 20], "name": "WG_ID"},
14294    {"bits": [24, 27], "name": "VM_ID"}
14295   ]
14296  },
14297  "SQ_WAVE_IB_DBG1": {
14298   "fields": [
14299    {"bits": [24, 24], "name": "WAVE_IDLE"},
14300    {"bits": [25, 31], "name": "MISC_CNT"}
14301   ]
14302  },
14303  "SQ_WAVE_IB_STS": {
14304   "fields": [
14305    {"bits": [0, 2], "name": "EXP_CNT"},
14306    {"bits": [4, 9], "name": "LGKM_CNT"},
14307    {"bits": [10, 15], "name": "VM_CNT"},
14308    {"bits": [26, 31], "name": "VS_CNT"}
14309   ]
14310  },
14311  "SQ_WAVE_IB_STS2": {
14312   "fields": [
14313    {"bits": [0, 1], "name": "INST_PREFETCH"},
14314    {"bits": [8, 9], "name": "MEM_ORDER"},
14315    {"bits": [10, 10], "name": "FWD_PROGRESS"},
14316    {"bits": [11, 11], "name": "WAVE64"}
14317   ]
14318  },
14319  "SQ_WAVE_LDS_ALLOC": {
14320   "fields": [
14321    {"bits": [0, 8], "name": "LDS_BASE"},
14322    {"bits": [12, 20], "name": "LDS_SIZE"},
14323    {"bits": [24, 27], "name": "VGPR_SHARED_SIZE"}
14324   ]
14325  },
14326  "SQ_WAVE_MODE": {
14327   "fields": [
14328    {"bits": [0, 3], "name": "FP_ROUND"},
14329    {"bits": [4, 7], "name": "FP_DENORM"},
14330    {"bits": [8, 8], "name": "DX10_CLAMP"},
14331    {"bits": [9, 9], "name": "IEEE"},
14332    {"bits": [10, 10], "name": "LOD_CLAMPED"},
14333    {"bits": [11, 11], "name": "TRAP_AFTER_INST_EN"},
14334    {"bits": [12, 20], "enum_ref": "EXCP_EN", "name": "EXCP_EN"},
14335    {"bits": [21, 21], "name": "WAVE_END"},
14336    {"bits": [23, 23], "name": "FP16_OVFL"},
14337    {"bits": [27, 27], "name": "DISABLE_PERF"}
14338   ]
14339  },
14340  "SQ_WAVE_PC_HI": {
14341   "fields": [
14342    {"bits": [0, 15], "name": "PC_HI"}
14343   ]
14344  },
14345  "SQ_WAVE_POPS_PACKER": {
14346   "fields": [
14347    {"bits": [0, 0], "name": "POPS_EN"},
14348    {"bits": [1, 2], "name": "POPS_PACKER_ID"}
14349   ]
14350  },
14351  "SQ_WAVE_SCHED_MODE": {
14352   "fields": [
14353    {"bits": [0, 1], "name": "DEP_MODE"}
14354   ]
14355  },
14356  "SQ_WAVE_SHADER_CYCLES": {
14357   "fields": [
14358    {"bits": [0, 19], "name": "CYCLES"}
14359   ]
14360  },
14361  "SQ_WAVE_STATUS": {
14362   "fields": [
14363    {"bits": [0, 0], "name": "SCC"},
14364    {"bits": [1, 2], "name": "SPI_PRIO"},
14365    {"bits": [3, 4], "name": "USER_PRIO"},
14366    {"bits": [5, 5], "name": "PRIV"},
14367    {"bits": [6, 6], "name": "TRAP_EN"},
14368    {"bits": [7, 7], "name": "TTRACE_EN"},
14369    {"bits": [8, 8], "name": "EXPORT_RDY"},
14370    {"bits": [9, 9], "name": "EXECZ"},
14371    {"bits": [10, 10], "name": "VCCZ"},
14372    {"bits": [11, 11], "name": "IN_TG"},
14373    {"bits": [12, 12], "name": "IN_BARRIER"},
14374    {"bits": [13, 13], "name": "HALT"},
14375    {"bits": [14, 14], "name": "TRAP"},
14376    {"bits": [15, 15], "name": "TTRACE_SIMD_EN"},
14377    {"bits": [16, 16], "name": "VALID"},
14378    {"bits": [17, 17], "name": "ECC_ERR"},
14379    {"bits": [18, 18], "name": "SKIP_EXPORT"},
14380    {"bits": [19, 19], "name": "PERF_EN"},
14381    {"bits": [22, 22], "name": "OREO_CONFLICT"},
14382    {"bits": [23, 23], "name": "FATAL_HALT"},
14383    {"bits": [24, 24], "name": "NO_VGPRS"},
14384    {"bits": [25, 25], "name": "LDS_PARAM_READY"},
14385    {"bits": [26, 26], "name": "MUST_GS_ALLOC"},
14386    {"bits": [27, 27], "name": "MUST_EXPORT"},
14387    {"bits": [28, 28], "name": "IDLE"},
14388    {"bits": [29, 29], "name": "SCRATCH_EN"}
14389   ]
14390  },
14391  "SQ_WAVE_TRAPSTS": {
14392   "fields": [
14393    {"bits": [0, 8], "enum_ref": "EXCP_EN", "name": "EXCP"},
14394    {"bits": [10, 10], "name": "SAVECTX"},
14395    {"bits": [11, 11], "name": "ILLEGAL_INST"},
14396    {"bits": [12, 14], "name": "EXCP_HI"},
14397    {"bits": [15, 15], "name": "BUFFER_OOB"},
14398    {"bits": [16, 16], "name": "HOST_TRAP"},
14399    {"bits": [17, 17], "name": "WAVESTART"},
14400    {"bits": [18, 18], "name": "WAVE_END"},
14401    {"bits": [19, 19], "name": "PERF_SNAPSHOT"},
14402    {"bits": [20, 20], "name": "TRAP_AFTER_INST"},
14403    {"bits": [28, 28], "name": "UTC_ERROR"}
14404   ]
14405  },
14406  "SX_BLEND_OPT_CONTROL": {
14407   "fields": [
14408    {"bits": [0, 0], "name": "MRT0_COLOR_OPT_DISABLE"},
14409    {"bits": [1, 1], "name": "MRT0_ALPHA_OPT_DISABLE"},
14410    {"bits": [4, 4], "name": "MRT1_COLOR_OPT_DISABLE"},
14411    {"bits": [5, 5], "name": "MRT1_ALPHA_OPT_DISABLE"},
14412    {"bits": [8, 8], "name": "MRT2_COLOR_OPT_DISABLE"},
14413    {"bits": [9, 9], "name": "MRT2_ALPHA_OPT_DISABLE"},
14414    {"bits": [12, 12], "name": "MRT3_COLOR_OPT_DISABLE"},
14415    {"bits": [13, 13], "name": "MRT3_ALPHA_OPT_DISABLE"},
14416    {"bits": [16, 16], "name": "MRT4_COLOR_OPT_DISABLE"},
14417    {"bits": [17, 17], "name": "MRT4_ALPHA_OPT_DISABLE"},
14418    {"bits": [20, 20], "name": "MRT5_COLOR_OPT_DISABLE"},
14419    {"bits": [21, 21], "name": "MRT5_ALPHA_OPT_DISABLE"},
14420    {"bits": [24, 24], "name": "MRT6_COLOR_OPT_DISABLE"},
14421    {"bits": [25, 25], "name": "MRT6_ALPHA_OPT_DISABLE"},
14422    {"bits": [28, 28], "name": "MRT7_COLOR_OPT_DISABLE"},
14423    {"bits": [29, 29], "name": "MRT7_ALPHA_OPT_DISABLE"},
14424    {"bits": [31, 31], "name": "PIXEN_ZERO_OPT_DISABLE"}
14425   ]
14426  },
14427  "SX_BLEND_OPT_EPSILON": {
14428   "fields": [
14429    {"bits": [0, 3], "enum_ref": "SX_BLEND_OPT_EPSILON__MRT0_EPSILON", "name": "MRT0_EPSILON"},
14430    {"bits": [4, 7], "name": "MRT1_EPSILON"},
14431    {"bits": [8, 11], "name": "MRT2_EPSILON"},
14432    {"bits": [12, 15], "name": "MRT3_EPSILON"},
14433    {"bits": [16, 19], "name": "MRT4_EPSILON"},
14434    {"bits": [20, 23], "name": "MRT5_EPSILON"},
14435    {"bits": [24, 27], "name": "MRT6_EPSILON"},
14436    {"bits": [28, 31], "name": "MRT7_EPSILON"}
14437   ]
14438  },
14439  "SX_MRT0_BLEND_OPT": {
14440   "fields": [
14441    {"bits": [0, 2], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_SRC_OPT"},
14442    {"bits": [4, 6], "enum_ref": "SX_BLEND_OPT", "name": "COLOR_DST_OPT"},
14443    {"bits": [8, 10], "enum_ref": "SX_OPT_COMB_FCN", "name": "COLOR_COMB_FCN"},
14444    {"bits": [16, 18], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_SRC_OPT"},
14445    {"bits": [20, 22], "enum_ref": "SX_BLEND_OPT", "name": "ALPHA_DST_OPT"},
14446    {"bits": [24, 26], "enum_ref": "SX_OPT_COMB_FCN", "name": "ALPHA_COMB_FCN"}
14447   ]
14448  },
14449  "SX_PERFCOUNTER2_SELECT": {
14450   "fields": [
14451    {"bits": [0, 9], "name": "PERF_SEL"},
14452    {"bits": [20, 23], "name": "CNTR_MODE"},
14453    {"bits": [28, 31], "name": "PERF_MODE"}
14454   ]
14455  },
14456  "SX_PS_DOWNCONVERT": {
14457   "fields": [
14458    {"bits": [0, 3], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT0"},
14459    {"bits": [4, 7], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT1"},
14460    {"bits": [8, 11], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT2"},
14461    {"bits": [12, 15], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT3"},
14462    {"bits": [16, 19], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT4"},
14463    {"bits": [20, 23], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT5"},
14464    {"bits": [24, 27], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT6"},
14465    {"bits": [28, 31], "enum_ref": "SX_DOWNCONVERT_FORMAT", "name": "MRT7"}
14466   ]
14467  },
14468  "SX_PS_DOWNCONVERT_CONTROL": {
14469   "fields": [
14470    {"bits": [0, 0], "name": "MRT0_FMT_MAPPING_DISABLE"},
14471    {"bits": [1, 1], "name": "MRT1_FMT_MAPPING_DISABLE"},
14472    {"bits": [2, 2], "name": "MRT2_FMT_MAPPING_DISABLE"},
14473    {"bits": [3, 3], "name": "MRT3_FMT_MAPPING_DISABLE"},
14474    {"bits": [4, 4], "name": "MRT4_FMT_MAPPING_DISABLE"},
14475    {"bits": [5, 5], "name": "MRT5_FMT_MAPPING_DISABLE"},
14476    {"bits": [6, 6], "name": "MRT6_FMT_MAPPING_DISABLE"},
14477    {"bits": [7, 7], "name": "MRT7_FMT_MAPPING_DISABLE"}
14478   ]
14479  },
14480  "TA_BC_BASE_ADDR_HI": {
14481   "fields": [
14482    {"bits": [0, 7], "name": "ADDRESS"}
14483   ]
14484  },
14485  "TCP_PERFCOUNTER_FILTER": {
14486   "fields": [
14487    {"bits": [0, 0], "name": "BUFFER"},
14488    {"bits": [1, 1], "name": "FLAT"},
14489    {"bits": [2, 4], "name": "DIM"},
14490    {"bits": [5, 11], "name": "DATA_FORMAT"},
14491    {"bits": [13, 16], "name": "NUM_FORMAT"},
14492    {"bits": [17, 21], "name": "SW_MODE"},
14493    {"bits": [22, 23], "name": "NUM_SAMPLES"},
14494    {"bits": [24, 26], "name": "OPCODE_TYPE"},
14495    {"bits": [27, 27], "name": "SLC"},
14496    {"bits": [28, 28], "name": "DLC"},
14497    {"bits": [29, 29], "name": "GLC"},
14498    {"bits": [30, 30], "name": "COMPRESSION_ENABLE"}
14499   ]
14500  },
14501  "TCP_PERFCOUNTER_FILTER2": {
14502   "fields": [
14503    {"bits": [0, 2], "name": "REQ_MODE"}
14504   ]
14505  },
14506  "TCP_PERFCOUNTER_FILTER_EN": {
14507   "fields": [
14508    {"bits": [0, 0], "name": "BUFFER"},
14509    {"bits": [1, 1], "name": "FLAT"},
14510    {"bits": [2, 2], "name": "DIM"},
14511    {"bits": [3, 3], "name": "DATA_FORMAT"},
14512    {"bits": [4, 4], "name": "NUM_FORMAT"},
14513    {"bits": [5, 5], "name": "SW_MODE"},
14514    {"bits": [6, 6], "name": "NUM_SAMPLES"},
14515    {"bits": [7, 7], "name": "OPCODE_TYPE"},
14516    {"bits": [8, 8], "name": "SLC"},
14517    {"bits": [9, 9], "name": "DLC"},
14518    {"bits": [10, 10], "name": "GLC"},
14519    {"bits": [11, 11], "name": "COMPRESSION_ENABLE"},
14520    {"bits": [12, 12], "name": "REQ_MODE"}
14521   ]
14522  },
14523  "UTCL1_PERFCOUNTER0_SELECT": {
14524   "fields": [
14525    {"bits": [0, 9], "name": "PERF_SEL"},
14526    {"bits": [28, 31], "name": "COUNTER_MODE"}
14527   ]
14528  },
14529  "VGT_DMA_BASE_HI": {
14530   "fields": [
14531    {"bits": [0, 15], "name": "BASE_ADDR"}
14532   ]
14533  },
14534  "VGT_DMA_INDEX_TYPE": {
14535   "fields": [
14536    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
14537    {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"},
14538    {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"},
14539    {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
14540    {"bits": [8, 8], "name": "ATC"},
14541    {"bits": [9, 9], "name": "NOT_EOP"},
14542    {"bits": [10, 10], "name": "REQ_PATH"},
14543    {"bits": [11, 13], "name": "MTYPE"},
14544    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
14545   ]
14546  },
14547  "VGT_DRAW_INITIATOR": {
14548   "fields": [
14549    {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"},
14550    {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"},
14551    {"bits": [4, 4], "name": "SPRITE_EN_R6XX"},
14552    {"bits": [5, 5], "name": "NOT_EOP"},
14553    {"bits": [6, 6], "name": "USE_OPAQUE"},
14554    {"bits": [29, 31], "name": "REG_RT_INDEX"}
14555   ]
14556  },
14557  "VGT_DRAW_PAYLOAD_CNTL": {
14558   "fields": [
14559    {"bits": [1, 1], "name": "EN_REG_RT_INDEX"},
14560    {"bits": [3, 3], "name": "EN_PRIM_PAYLOAD"},
14561    {"bits": [4, 4], "name": "EN_DRAW_VP"}
14562   ]
14563  },
14564  "VGT_ESGS_RING_ITEMSIZE": {
14565   "fields": [
14566    {"bits": [0, 14], "name": "ITEMSIZE"}
14567   ]
14568  },
14569  "VGT_EVENT_ADDRESS_REG": {
14570   "fields": [
14571    {"bits": [0, 27], "name": "ADDRESS_LOW"}
14572   ]
14573  },
14574  "VGT_EVENT_INITIATOR": {
14575   "fields": [
14576    {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"},
14577    {"bits": [10, 26], "name": "ADDRESS_HI"},
14578    {"bits": [27, 27], "name": "EXTENDED_EVENT"}
14579   ]
14580  },
14581  "VGT_GS_INSTANCE_CNT": {
14582   "fields": [
14583    {"bits": [0, 0], "name": "ENABLE"},
14584    {"bits": [2, 8], "name": "CNT"},
14585    {"bits": [31, 31], "name": "EN_MAX_VERT_OUT_PER_GS_INSTANCE"}
14586   ]
14587  },
14588  "VGT_GS_MAX_VERT_OUT": {
14589   "fields": [
14590    {"bits": [0, 10], "name": "MAX_VERT_OUT"}
14591   ]
14592  },
14593  "VGT_GS_OUT_PRIM_TYPE": {
14594   "fields": [
14595    {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}
14596   ]
14597  },
14598  "VGT_HS_OFFCHIP_PARAM": {
14599   "fields": [
14600    {"bits": [0, 9], "name": "OFFCHIP_BUFFERING"},
14601    {"bits": [10, 11], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"}
14602   ]
14603  },
14604  "VGT_INDEX_TYPE": {
14605   "fields": [
14606    {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"},
14607    {"bits": [14, 14], "name": "DISABLE_INSTANCE_PACKING"}
14608   ]
14609  },
14610  "VGT_LS_HS_CONFIG": {
14611   "fields": [
14612    {"bits": [0, 7], "name": "NUM_PATCHES"},
14613    {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"},
14614    {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"}
14615   ]
14616  },
14617  "VGT_PRIMITIVEID_EN": {
14618   "fields": [
14619    {"bits": [0, 0], "name": "PRIMITIVEID_EN"},
14620    {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"},
14621    {"bits": [2, 2], "name": "NGG_DISABLE_PROVOK_REUSE"}
14622   ]
14623  },
14624  "VGT_PRIMITIVE_TYPE": {
14625   "fields": [
14626    {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}
14627   ]
14628  },
14629  "VGT_REUSE_OFF": {
14630   "fields": [
14631    {"bits": [0, 0], "name": "REUSE_OFF"}
14632   ]
14633  },
14634  "VGT_SHADER_STAGES_EN": {
14635   "fields": [
14636    {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"},
14637    {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"},
14638    {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"},
14639    {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"},
14640    {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"},
14641    {"bits": [8, 8], "name": "DYNAMIC_HS"},
14642    {"bits": [12, 12], "name": "VS_WAVE_ID_EN"},
14643    {"bits": [13, 13], "name": "PRIMGEN_EN"},
14644    {"bits": [14, 14], "name": "ORDERED_ID_MODE"},
14645    {"bits": [15, 18], "name": "MAX_PRIMGRP_IN_WAVE"},
14646    {"bits": [19, 20], "name": "GS_FAST_LAUNCH"},
14647    {"bits": [21, 21], "name": "HS_W32_EN"},
14648    {"bits": [22, 22], "name": "GS_W32_EN"},
14649    {"bits": [23, 23], "name": "VS_W32_EN"},
14650    {"bits": [24, 24], "name": "NGG_WAVE_ID_EN"},
14651    {"bits": [25, 25], "name": "PRIMGEN_PASSTHRU_EN"},
14652    {"bits": [26, 26], "name": "PRIMGEN_PASSTHRU_NO_MSG"}
14653   ]
14654  },
14655  "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": {
14656   "fields": [
14657    {"bits": [0, 8], "name": "VERTEX_STRIDE"}
14658   ]
14659  },
14660  "VGT_TESS_DISTRIBUTION": {
14661   "fields": [
14662    {"bits": [0, 7], "name": "ACCUM_ISOLINE"},
14663    {"bits": [8, 15], "name": "ACCUM_TRI"},
14664    {"bits": [16, 23], "name": "ACCUM_QUAD"},
14665    {"bits": [24, 28], "name": "DONUT_SPLIT"},
14666    {"bits": [29, 31], "name": "TRAP_SPLIT"}
14667   ]
14668  },
14669  "VGT_TF_PARAM": {
14670   "fields": [
14671    {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"},
14672    {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"},
14673    {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"},
14674    {"bits": [9, 9], "name": "NOT_USED"},
14675    {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"},
14676    {"bits": [14, 14], "name": "DISABLE_DONUTS"},
14677    {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"},
14678    {"bits": [17, 18], "enum_ref": "VGT_DIST_MODE", "name": "DISTRIBUTION_MODE"},
14679    {"bits": [19, 19], "enum_ref": "VGT_DETECT_ONE", "name": "DETECT_ONE"},
14680    {"bits": [20, 20], "enum_ref": "VGT_DETECT_ZERO", "name": "DETECT_ZERO"},
14681    {"bits": [23, 25], "name": "MTYPE"}
14682   ]
14683  },
14684  "VGT_TF_RING_SIZE": {
14685   "fields": [
14686    {"bits": [0, 16], "name": "SIZE"}
14687   ]
14688  }
14689 }
14690}
14691