1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 /*
37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38 * Used in the LinkSys USB200M and various other adapters.
39 *
40 * Manuals available from:
41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43 * controller) to find the definitions for the RX control register.
44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
45 *
46 * Written by Bill Paul <wpaul@windriver.com>
47 * Senior Engineer
48 * Wind River Systems
49 */
50
51 /*
52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53 * It uses an external PHY (reference designs use a RealTek chip),
54 * and has a 64-bit multicast hash filter. There is some information
55 * missing from the manual which one needs to know in order to make
56 * the chip function:
57 *
58 * - You must set bit 7 in the RX control register, otherwise the
59 * chip won't receive any packets.
60 * - You must initialize all 3 IPG registers, or you won't be able
61 * to send any packets.
62 *
63 * Note that this device appears to only support loading the station
64 * address via autload from the EEPROM (i.e. there's no way to manually
65 * set it).
66 *
67 * (Adam Weinberger wanted me to name this driver if_gir.c.)
68 */
69
70 /*
71 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
73 *
74 * Manual here:
75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
77 */
78
79 #include <lwip/netif.h>
80 #include <lwip/dhcp.h>
81 #include <lwip/netifapi.h>
82 #include <lwip/inet.h>
83
84 #include "implementation/global_implementation.h"
85 #include "usb_ethernet.h"
86 #include "if_axereg.h"
87 #include "mii.h"
88
89 /*
90 * AXE_178_MAX_FRAME_BURST
91 * max frame burst size for Ax88178 and Ax88772
92 * 0 2048 bytes
93 * 1 4096 bytes
94 * 2 8192 bytes
95 * 3 16384 bytes
96 * use the largest your system can handle without USB stalling.
97 *
98 * NB: 88772 parts appear to generate lots of input errors with
99 * a 2K rx buffer and 8K is only slightly faster than 4K on an
100 * EHCI port on a T42 so change at your own risk.
101 */
102
103 #define AXE_178_MAX_FRAME_BURST 1
104 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
105
106 #undef USB_DEBUG_VAR
107 #define USB_DEBUG_VAR axe_debug
108 #ifdef LOSCFG_USB_DEBUG
109 static int axe_debug = 0;
110 void
usb_axe_debug_func(int level)111 usb_axe_debug_func(int level)
112 {
113 axe_debug = level;
114 PRINTK("The level of usb axe debug is %d\n", level);
115 }
116 DEBUG_MODULE(axe, usb_axe_debug_func);
117 #endif
118
119 #define IFF_DRV_OACTIVE IFF_MASTER
120 #define IFF_SIMPLEX IFF_SLAVE
121
122 /*
123 * Various supported device vendors/products.
124 */
125 static const STRUCT_USB_HOST_ID axe_devs[] = {
126 { USB_VPI(0x0B95, 0x772B, AXE_FLAG_772B) },
127 { USB_VPI(0x0B95, 0x772A, AXE_FLAG_772A) },
128 };
129
130 static device_probe_t axe_probe;
131 static device_attach_t axe_attach;
132 static device_detach_t axe_detach;
133
134 static usb_callback_t axe_bulk_read_callback;
135 static usb_callback_t axe_bulk_write_callback;
136
137 static int axe_miibus_writereg(struct axe_softc *sc, int reg, int val);
138 static uint16_t axe_miibus_readreg(struct axe_softc *sc, int reg);
139
140 static uether_fn_t axe_attach_post;
141 static uether_fn_t axe_init;
142 static uether_fn_t axe_stop;
143 static uether_fn_t axe_start;
144 static uether_fn_t axe_setmulti;
145 static uether_fn_t axe_setpromisc;
146 static uether_fn_t axe_tick;
147
148 static void axe_cmd(struct axe_softc *, int, int, int, void *);
149 static void axe_ax88178_init(struct axe_softc *);
150 static void axe_ax88772_init(struct axe_softc *);
151 static void axe_ax88772_phywake(struct axe_softc *);
152 static void axe_ax88772b_init(struct axe_softc *);
153 static int axe_get_phyno(struct axe_softc *, int);
154 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
155 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
156 unsigned int offset, unsigned int, struct axe_csum_hdr *);
157 static void axe_csum_cfg(struct usb_ether *);
158
159 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
160 { /* [AXE_BULK_DT_WR] = */
161 .type = UE_BULK,
162 .endpoint = UE_ADDR_ANY,
163 .direction = UE_DIR_OUT,
164 .frames = USB_AXE_MAX_FRAMES,
165 .bufsize = USB_AXE_MAX_FRAMES * MCLBYTES,
166 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
167 .callback = axe_bulk_write_callback,
168 .timeout = 10000, /* 10 seconds */
169 },
170 { /* [AXE_BULK_DT_RD] = */
171 .type = UE_BULK,
172 .endpoint = UE_ADDR_ANY,
173 .direction = UE_DIR_IN,
174 .bufsize = 16 * MCLBYTES, /* bytes */
175 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
176 .callback = axe_bulk_read_callback,
177 .timeout = 0, /* no timeout */
178 },
179 };
180
181 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
182 { 0x8000, 0x8001, 2048 },
183 { 0x8100, 0x8147, 4096 },
184 { 0x8200, 0x81EB, 6144 },
185 { 0x8300, 0x83D7, 8192 },
186 { 0x84C0, 0x861E, 16384 },
187 { 0x8500, 0x8666, 20480 },
188 { 0x8600, 0x87AE, 24576 },
189 { 0x8700, 0x851E, 32768 }
190 };
191
192 static device_method_t axe_methods[] = {
193 /* Device interface */
194 DEVMETHOD(device_probe, axe_probe),
195 DEVMETHOD(device_attach, axe_attach),
196 DEVMETHOD(device_detach, axe_detach),
197 DEVMETHOD_END
198 };
199
200 static driver_t axe_driver = {
201 .name = "USB_AXE",
202 .methods = axe_methods,
203 .size = sizeof(struct axe_softc),
204 };
205
206 static devclass_t axe_devclass;
207 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, 0, 0);
208
209 static const struct usb_ether_methods axe_ue_methods = {
210 .ue_attach_post = axe_attach_post,
211 .ue_start = axe_start,
212 .ue_init = axe_init,
213 .ue_stop = axe_stop,
214 .ue_setmulti = axe_setmulti,
215 .ue_setpromisc = axe_setpromisc,
216 .ue_tick = axe_tick,
217 };
218
219 static void
axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)220 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
221 {
222 struct usb_device_request req;
223 usb_error_t err;
224
225 AXE_LOCK_ASSERT(sc, MA_OWNED);
226
227 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
228 UT_WRITE_VENDOR_DEVICE :
229 UT_READ_VENDOR_DEVICE);
230 req.bRequest = AXE_CMD_CMD(cmd);
231 USETW(req.wValue, val);
232 USETW(req.wIndex, index);
233 USETW(req.wLength, AXE_CMD_LEN(cmd));
234
235 err = uether_do_request(&sc->sc_ue, &req, buf, 10000);
236 if (err != USB_ERR_NORMAL_COMPLETION) {
237 dprintf("Fatal Error in function [%s]! err:%d\n", __FUNCTION__, err);
238 }
239 }
240
241 static uint16_t
axe_miibus_readreg(struct axe_softc *sc, int reg)242 axe_miibus_readreg(struct axe_softc *sc, int reg)
243 {
244 uint16_t val;
245
246 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
247 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, 0x10, &val);
248 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
249
250 val = le16toh(val);
251 if (AXE_IS_772(sc) && reg == MII_BMSR) {
252 /*
253 * BMSR of AX88772 indicates that it supports extended
254 * capability but the extended status register is
255 * revered for embedded ethernet PHY. So clear the
256 * extended capability bit of BMSR.
257 */
258 val &= ~BMSR_EXTCAP;
259 }
260 return (val);
261 }
262
263 static int
axe_miibus_writereg(struct axe_softc *sc, int reg, int val)264 axe_miibus_writereg(struct axe_softc *sc, int reg, int val)
265 {
266 val = htole32(val);
267
268 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
269 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, 0x10, &val);
270 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
271 return (0);
272 }
273
274 static int
axe_setmedium(struct axe_softc *sc)275 axe_setmedium(struct axe_softc *sc)
276 {
277 uint16_t val = AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
278 uint16_t bmcr;
279 int b100 = 0;
280 int bfull = 0;
281
282 bmcr = axe_miibus_readreg(sc, 0);
283
284 if (bmcr & 0x2000) { /* 100Mbps */
285 val |= AXE_178_MEDIA_100TX;
286 b100 = 1;
287 }
288
289 if (bmcr & 0x100) { /* full-duplex */
290 val |= AXE_MEDIA_FULL_DUPLEX | AXE_178_MEDIA_TXFLOW_CONTROL_EN | AXE_178_MEDIA_RXFLOW_CONTROL_EN;
291 bfull = 1;
292 }
293
294 if (b100)
295 PRINTK("- 100Mbps/");
296 else
297 PRINTK("- 10Mbps/");
298
299 if (bfull)
300 PRINTK("Full\n");
301 else
302 PRINTK("Half\n");
303
304 axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
305 return (0);
306 }
307
308 static void
axe_setmulti(struct usb_ether *ue)309 axe_setmulti(struct usb_ether *ue)
310 {
311 }
312
313 static int
axe_get_phyno(struct axe_softc *sc, int sel)314 axe_get_phyno(struct axe_softc *sc, int sel)
315 {
316 int phyno;
317
318 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
319 case PHY_TYPE_100_HOME:
320 case PHY_TYPE_GIG:
321 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
322 break;
323 case PHY_TYPE_SPECIAL:
324 /* FALLTHROUGH */
325 case PHY_TYPE_RSVD:
326 /* FALLTHROUGH */
327 case PHY_TYPE_NON_SUP:
328 /* FALLTHROUGH */
329 default:
330 phyno = -1;
331 break;
332 }
333
334 return (phyno);
335 }
336
337 static void
axe_uether_pause(struct usb_ether * usbe, unsigned int t_ick)338 axe_uether_pause(struct usb_ether * usbe, unsigned int t_ick)
339 {
340 (void) uether_pause(usbe, t_ick);
341 }
342
343 #define AXE_GPIO_WRITE(x, y) do { \
344 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
345 axe_uether_pause(ue, (y)); \
346 } while (0)
347
348 static void
axe_ax88178_init(struct axe_softc *sc)349 axe_ax88178_init(struct axe_softc *sc)
350 {
351 struct usb_ether *ue;
352 int gpio0, ledmode, phymode;
353 uint16_t eeprom, val;
354
355 ue = &sc->sc_ue;
356 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
357 /* XXX magic */
358 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
359 eeprom = le16toh(eeprom);
360 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
361
362 /* if EEPROM is invalid we have to use to GPIO0 */
363 if (eeprom == 0xffff) {
364 phymode = AXE_PHY_MODE_MARVELL;
365 gpio0 = 1;
366 ledmode = 0;
367 } else {
368 phymode = eeprom & 0x7f;
369 gpio0 = (eeprom & 0x80) ? 0 : 1;
370 ledmode = eeprom >> 8;
371 }
372
373 /* Program GPIOs depending on PHY hardware. */
374 switch (phymode) {
375 case AXE_PHY_MODE_MARVELL:
376 if (gpio0 == 1) {
377 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
378 hz / 32);
379 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
380 hz / 32);
381 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
382 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
383 hz / 32);
384 } else {
385 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
386 AXE_GPIO1_EN, hz / 3);
387 if (ledmode == 1) {
388 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
389 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
390 hz / 3);
391 } else {
392 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
393 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
394 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
395 AXE_GPIO2_EN, hz / 4);
396 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
397 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
398 }
399 }
400 break;
401 case AXE_PHY_MODE_CICADA:
402 case AXE_PHY_MODE_CICADA_V2:
403 case AXE_PHY_MODE_CICADA_V2_ASIX:
404 if (gpio0 == 1)
405 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
406 AXE_GPIO0_EN, hz / 32);
407 else
408 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
409 AXE_GPIO1_EN, hz / 32);
410 break;
411 case AXE_PHY_MODE_AGERE:
412 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
413 AXE_GPIO1_EN, hz / 32);
414 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
415 AXE_GPIO2_EN, hz / 32);
416 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
417 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
418 AXE_GPIO2_EN, hz / 32);
419 break;
420 case AXE_PHY_MODE_REALTEK_8211CL:
421 case AXE_PHY_MODE_REALTEK_8211BN:
422 case AXE_PHY_MODE_REALTEK_8251CL:
423 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
424 AXE_GPIO1 | AXE_GPIO1_EN;
425 AXE_GPIO_WRITE(val, hz / 32);
426 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
427 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
428 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
429 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
430 (void) axe_miibus_writereg(sc, 0x1F, 0x0005);
431 (void) axe_miibus_writereg(sc, 0x0C, 0x0000);
432 val = axe_miibus_readreg(sc, 0x0001);
433 (void) axe_miibus_writereg(sc, 0x01, val | 0x0080);
434 (void) axe_miibus_writereg(sc, 0x1F, 0x0000);
435 }
436 break;
437 default:
438 /* Unknown PHY model or no need to program GPIOs. */
439 break;
440 }
441
442 /* soft reset */
443 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
444 axe_uether_pause(ue, hz / 4);
445
446 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
447 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
448 axe_uether_pause(ue, hz / 4);
449 /* Enable MII/GMII/RGMII interface to work with external PHY. */
450 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
451 axe_uether_pause(ue, hz / 4);
452
453 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
454 }
455
456 static void
axe_ax88772_init(struct axe_softc *sc)457 axe_ax88772_init(struct axe_softc *sc)
458 {
459 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
460 axe_uether_pause(&sc->sc_ue, hz / 16);
461
462 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
463 /* ask for the embedded PHY */
464 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
465 axe_uether_pause(&sc->sc_ue, hz / 64);
466
467 /* power down and reset state, pin reset state */
468 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
469 AXE_SW_RESET_CLEAR, NULL);
470 axe_uether_pause(&sc->sc_ue, hz / 16);
471
472 /* power down/reset state, pin operating state */
473 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
474 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
475 axe_uether_pause(&sc->sc_ue, hz / 4);
476
477 /* power up, reset */
478 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
479
480 /* power up, operating */
481 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
482 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
483 } else {
484 /* ask for external PHY */
485 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
486 axe_uether_pause(&sc->sc_ue, hz / 64);
487
488 /* power down internal PHY */
489 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
490 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
491 }
492
493 axe_uether_pause(&sc->sc_ue, hz / 4);
494 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
495 }
496
497 static void
axe_ax88772_phywake(struct axe_softc *sc)498 axe_ax88772_phywake(struct axe_softc *sc)
499 {
500 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
501 /* Manually select internal(embedded) PHY - MAC mode. */
502 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
503 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
504 NULL);
505 axe_uether_pause(&sc->sc_ue, hz / 32);
506 } else {
507 /*
508 * Manually select external PHY - MAC mode.
509 * Reverse MII/RMII is for AX88772A PHY mode.
510 */
511 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
512 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
513 axe_uether_pause(&sc->sc_ue, hz / 32);
514 }
515 /* Take PHY out of power down. */
516 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
517 AXE_SW_RESET_IPRL, NULL);
518 axe_uether_pause(&sc->sc_ue, hz / 4);
519 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
520 axe_uether_pause(&sc->sc_ue, hz);
521 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
522 axe_uether_pause(&sc->sc_ue, hz / 32);
523 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
524 axe_uether_pause(&sc->sc_ue, hz / 32);
525 }
526
527 static void
axe_ax88772b_init(struct axe_softc *sc)528 axe_ax88772b_init(struct axe_softc *sc)
529 {
530 struct usb_ether *ue = &sc->sc_ue;
531 uint16_t eeprom;
532 uint8_t *eaddr;
533 uint8_t *tmp;
534 uint8_t i;
535 struct los_eth_driver *ifp = ue->ue_drv_sc;
536
537 /* Reload EEPROM. */
538 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 2);
539 /*
540 * Save PHY power saving configuration(high byte) and
541 * clear EEPROM checksum value(low byte).
542 */
543 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
544 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
545
546 /*
547 * Auto-loaded default station address from internal ROM is
548 * 00:00:00:00:00:00 such that an explicit access to EEPROM
549 * is required to get real station address.
550 */
551 eaddr = ue->ue_eaddr;
552 ifp->ac_if.hwaddr_len = NETIF_MAX_HWADDR_LEN;
553 tmp = (uint8_t *) ifp->ac_if.hwaddr;
554 for (i = 0; i < NETIF_MAX_HWADDR_LEN / 2; i++) {
555 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, &eeprom);
556 eeprom = le16toh(eeprom);
557 *eaddr++ = (uint8_t)(eeprom & 0xFF);
558 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
559 *tmp++ = (uint8_t)(eeprom & 0xFF);
560 *tmp++ = (uint8_t)((eeprom >> 8) & 0xFF);
561 }
562 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, ue->ue_eaddr);
563
564 axe_attach_post(ue);
565
566 /* Wakeup PHY. */
567 axe_ax88772_phywake(sc);
568 /* Stop MAC. */
569 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
570
571 ifp = ue->ue_drv_sc;
572 ifp->ac_if.flags |= NETIF_FLAG_UP | NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET;
573 ifp->ac_if.flags &= ~NETIF_FLAG_LINK_UP;
574 sc->sc_flags &= ~AXE_FLAG_LINK;
575
576 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
577 }
578
579 #undef AXE_GPIO_WRITE
580
581 static void
axe_reset(struct axe_softc *sc)582 axe_reset(struct axe_softc *sc)
583 {
584 struct usb_config_descriptor *cd;
585 usb_error_t err;
586
587 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
588 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
589 cd->bConfigurationValue);
590 if (err)
591 DPRINTF("reset failed (ignored)\n");
592
593 /* Wait a little while for the chip to get its brains in order. */
594 axe_uether_pause(&sc->sc_ue, hz / 100);
595 /* Reinitialize controller to achieve full reset. */
596 if (sc->sc_flags & AXE_FLAG_178)
597 axe_ax88178_init(sc);
598 else if (sc->sc_flags & AXE_FLAG_772)
599 axe_ax88772_init(sc);
600 else if (sc->sc_flags & AXE_FLAG_772A)
601 axe_ax88772b_init(sc);
602 else if (sc->sc_flags & AXE_FLAG_772B)
603 axe_ax88772b_init(sc);
604
605 axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0,
606 AXE_MEDIA_FULL_DUPLEX | AXE_178_MEDIA_TXFLOW_CONTROL_EN | AXE_178_MEDIA_RXFLOW_CONTROL_EN
607 | AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC, NULL);
608 }
609
610 static void
axe_attach_post(struct usb_ether *ue)611 axe_attach_post(struct usb_ether *ue)
612 {
613 struct axe_softc *sc = uether_getsc(ue);
614 /*
615 * Load PHY indexes first. Needed by axe_xxx_init().
616 */
617 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
618 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
619 if (sc->sc_phyno == -1)
620 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
621 if (sc->sc_phyno == -1) {
622 device_printf(sc->sc_ue.ue_dev,
623 "no valid PHY address found, assuming PHY address 0\n");
624 sc->sc_phyno = 0;
625 }
626 /*
627 * Fetch IPG values.
628 */
629 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
630 /* Set IPG values. */
631 sc->sc_ipgs[0] = 0x15;
632 sc->sc_ipgs[1] = 0x16;
633 sc->sc_ipgs[2] = 0x1A;
634 } else
635 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
636 }
637 /*
638 * Probe for a AX88172 chip.
639 */
640 static int
axe_probe(device_t dev)641 axe_probe(device_t dev)
642 {
643 struct usb_attach_arg *uaa = device_get_ivars(dev);
644
645 if (uaa->usb_mode != USB_MODE_HOST)
646 return (ENXIO);
647 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
648 return (ENXIO);
649 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
650 return (ENXIO);
651 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
652 }
653
654 static void
axe_miibus_statchg(struct axe_softc *sc, uint16_t link_status)655 axe_miibus_statchg(struct axe_softc *sc, uint16_t link_status)
656 {
657 struct usb_ether *ue = &sc->sc_ue;
658 struct los_eth_driver *ifp = ue->ue_drv_sc;
659 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context;
660
661 if (drv_sc->state & IFF_DRV_RUNNING) {
662 if (link_status) {
663 if (sc->sc_flags & AXE_FLAG_772A) {
664 PRINTK("\nAX88772A Link Up ");
665 }
666 else if (sc->sc_flags & AXE_FLAG_772B) {
667 PRINTK("\nAX88772B Link Up ");
668 }
669
670 (void) axe_setmedium(sc);
671 axe_start(ue);
672
673 ifp->ac_if.flags |= NETIF_FLAG_LINK_UP;
674 (void)netifapi_netif_set_up(&ifp->ac_if);
675 } else {
676 if (sc->sc_flags & AXE_FLAG_772A)
677 PRINTK("\nAX88772A Link Down\n");
678 else if (sc->sc_flags & AXE_FLAG_772B)
679 PRINTK("\nAX88772B Link Down\n");
680
681 ifp->ac_if.flags &= ~NETIF_FLAG_LINK_UP;
682 }
683 }
684 }
685
686 /*
687 * Attach the interface. Allocate softc structures, do ifmedia
688 * setup and ethernet/BPF attach.
689 */
690 static int
axe_attach(device_t dev)691 axe_attach(device_t dev)
692 {
693 struct usb_attach_arg *uaa = device_get_ivars(dev);
694 struct axe_softc *sc = device_get_softc(dev);
695 struct usb_ether *ue = &sc->sc_ue;
696 uint8_t iface_index;
697 int error;
698 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
699 sc->sc_link_status = AXE_LINK_MASK;
700
701 device_set_usb_desc(dev);
702
703 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_RECURSE);
704
705 iface_index = AXE_IFACE_IDX;
706 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
707 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
708 if (error) {
709 device_printf(dev, "allocating USB transfers failed\n");
710 goto detach;
711 }
712
713 ue->ue_sc = sc;
714 ue->ue_dev = dev;
715 ue->ue_udev = uaa->device;
716 ue->ue_mtx = &sc->sc_mtx;
717 ue->ue_methods = &axe_ue_methods;
718 error = uether_ifattach(ue);
719 if (error) {
720 device_printf(dev, "could not attach interface\n");
721 goto detach;
722 }
723 return (0); /* success */
724
725 detach:
726 (void) axe_detach(dev);
727 return (ENXIO); /* failure */
728 }
729
730 static int
axe_detach(device_t dev)731 axe_detach(device_t dev)
732 {
733 struct axe_softc *sc = device_get_softc(dev);
734 struct usb_ether *ue = &sc->sc_ue;
735
736 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
737 uether_ifdetach(ue);
738 mtx_destroy(&sc->sc_mtx);
739
740 return (0);
741 }
742
743 #if (AXE_BULK_BUF_SIZE >= 0x10000)
744 #error "Please update axe_bulk_read_callback()!"
745 #endif
746
747 static void
axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)748 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
749 {
750 struct axe_softc *sc = usbd_xfer_softc(xfer);
751 struct usb_ether *ue = &sc->sc_ue;
752 struct usb_page_cache *pc;
753 int actlen;
754
755 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
756 switch (USB_GET_STATE(xfer)) {
757 case USB_ST_TRANSFERRED:
758 pc = usbd_xfer_get_frame(xfer, 0);
759 (void) axe_rx_frame(ue, pc, actlen);
760 /* FALLTHROUGH */
761 case USB_ST_SETUP:
762 tr_setup:
763 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
764 usbd_transfer_submit(xfer);
765 uether_rxflush(ue);
766 return;
767
768 default: /* Error */
769 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
770
771 if (error != USB_ERR_CANCELLED) {
772 /* try to clear stall first */
773 usbd_xfer_set_stall(xfer);
774 goto tr_setup;
775 }
776 return;
777 }
778 }
779
780 static int
axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)781 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
782 {
783 struct axe_softc *sc = ue->ue_sc;
784 struct axe_sframe_hdr hdr;
785 struct axe_csum_hdr csum_hdr;
786 int error, len, pos;
787
788 pos = 0;
789 len = 0;
790 error = 0;
791
792 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
793 while (pos < actlen) {
794 if ((int)(pos + sizeof(hdr)) > actlen) {
795 /* too little data */
796 error = EINVAL;
797 break;
798 }
799
800 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
801 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
802 /* we lost sync */
803 error = EINVAL;
804 break;
805 }
806 pos += sizeof(hdr);
807 len = le16toh(hdr.len);
808 if (pos + len > actlen) {
809 /* invalid length */
810 error = EINVAL;
811 break;
812 }
813 (void) axe_rxeof(ue, pc, pos, len, NULL);
814 pos += len + (len % 2);
815 }
816 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
817 while (pos < actlen) {
818 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
819 /* too little data */
820 error = EINVAL;
821 break;
822 }
823 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
824
825 csum_hdr.len = le16toh(csum_hdr.len);
826 csum_hdr.ilen = le16toh(csum_hdr.ilen);
827 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
828 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
829 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
830 sc->sc_lenmask) {
831 /* we lost sync */
832 error = EINVAL;
833 break;
834 }
835 /*
836 * Get total transferred frame length including
837 * checksum header. The length should be multiple
838 * of 4.
839 */
840 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
841 len = (len + 3) & ~3;
842 if (pos + len > actlen) {
843 /* invalid length */
844 error = EINVAL;
845 break;
846 }
847 (void) axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
848 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
849 pos += len;
850 }
851 } else {
852 (void)axe_rxeof(ue, pc, 0, actlen, NULL);
853 }
854 return (error);
855 }
856
857 static int
axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, unsigned int len, struct axe_csum_hdr *csum_hdr)858 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
859 unsigned int len, struct axe_csum_hdr *csum_hdr)
860 {
861 struct los_eth_driver *ifp = ue->ue_drv_sc;
862
863 struct pbuf *m = pbuf_alloc(PBUF_RAW, len+ETH_PAD_SIZE, PBUF_RAM);
864 struct pbuf *p;
865
866 if (len < ETHER_HDR_LEN) {
867 (void)pbuf_free(m);
868 return (EINVAL);
869 }
870
871 #if ETH_PAD_SIZE
872 /* drop the padding word */
873 if (pbuf_header(m, -ETH_PAD_SIZE)) {
874 PRINTK("[AXE_ERROR]axe_rxeof : pbuf_header drop failed\n");
875 (void)pbuf_free(m);
876 return (EINVAL);
877 }
878 #endif
879
880 for (p = m; p != NULL; p = p->next)
881 usbd_copy_out(pc, offset, p->payload, p->len);
882
883 #if ETH_PAD_SIZE
884 /* reclaim the padding word */
885 if (pbuf_header(m, ETH_PAD_SIZE)) {
886 PRINTK("[AXE_ERROR]axe_rxeof : pbuf_header drop failed\n");
887 (void)pbuf_free(m);
888 return (EINVAL);
889 }
890 #endif
891
892 driverif_input(&ifp->ac_if, m);
893 return (0);
894 }
895
896 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
897 #error "Please update axe_bulk_write_callback()!"
898 #endif
899
900 static void
axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)901 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
902 {
903 struct axe_softc *sc = usbd_xfer_softc(xfer);
904 struct axe_sframe_hdr hdr;
905 struct usb_ether *ue = &(sc->sc_ue);
906 struct los_eth_driver *ifp = ue->ue_drv_sc;
907 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context;
908 struct usb_page_cache *pc;
909 uint16_t txlen;
910 int nframes, pos;
911 struct pbuf *p;
912 uint8_t ustat;
913
914 ustat = USB_GET_STATE(xfer);
915 tr_setup:
916 switch (ustat) {
917 case USB_ST_TRANSFERRED:
918 DPRINTFN(11, "transfer complete\n");
919 drv_sc->state &= ~IFF_DRV_OACTIVE;
920 /* FALLTHROUGH */
921
922 case USB_ST_SETUP:
923 if (drv_sc->state & IFF_DRV_OACTIVE)
924 return;
925
926 UE_LOCK(ue);
927 IF_DEQUEUE(&(ue->ue_txq), p);
928 UE_UNLOCK(ue);
929
930 nframes = 0;
931 while (p) {
932 txlen = p->len;
933 if (txlen <= 0)
934 break;
935
936 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, nframes);
937 pos = 0;
938 pc = usbd_xfer_get_frame(xfer, nframes);
939 if (AXE_IS_178_FAMILY(sc)) {
940 hdr.len = htole16(txlen);
941 hdr.ilen = ~hdr.len;
942 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
943 pos += sizeof(hdr);
944 usbd_copy_in(pc, pos, p->payload, txlen);
945 pos += txlen;
946 } else {
947 usbd_copy_in(pc, pos, p->payload, txlen);
948 pos += txlen;
949 }
950
951 /* Set frame length. */
952 usbd_xfer_set_frame_len(xfer, nframes, pos);
953
954 uether_freebuf(p);
955 nframes++;
956 if (nframes >= USB_AXE_MAX_FRAMES)
957 break;
958
959 UE_LOCK(ue);
960 IF_DEQUEUE(&(ue->ue_txq), p);
961 UE_UNLOCK(ue);
962 }
963 if (nframes != 0) {
964 usbd_xfer_set_frames(xfer, nframes);
965 usbd_transfer_submit(xfer);
966 drv_sc->state |= IFF_DRV_OACTIVE;
967 }
968 break;
969
970 default: /* Error */
971 DPRINTFN(11, "transfer error, %s\n",
972 usbd_errstr(error));
973 drv_sc->state &= ~IFF_DRV_OACTIVE;
974 if (error != USB_ERR_CANCELLED) {
975 /* try to clear stall first */
976 usbd_xfer_set_stall(xfer);
977 ustat = USB_ST_SETUP;
978 goto tr_setup;
979 }
980 break;
981 }
982 }
983
984 static void
axe_start(struct usb_ether *ue)985 axe_start(struct usb_ether *ue)
986 {
987 struct axe_softc *sc = ue->ue_sc;
988
989 /*
990 * start the USB transfers, if not already started:
991 */
992 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
993 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
994 }
995
996 static void
axe_csum_cfg(struct usb_ether *ue)997 axe_csum_cfg(struct usb_ether *ue)
998 {
999 (void)ue;
1000 }
1001
1002 static void
axe_init(struct usb_ether *ue)1003 axe_init(struct usb_ether *ue)
1004 {
1005 struct axe_softc *sc = uether_getsc(ue);
1006 struct los_eth_driver *ifp = ue->ue_drv_sc;
1007 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context;
1008 uint16_t rxmode;
1009
1010 drv_sc->state = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1011
1012 AXE_LOCK_ASSERT(sc, MA_OWNED);
1013 if ((drv_sc->state & IFF_DRV_RUNNING) != 0)
1014 return;
1015
1016 /* Cancel pending I/O */
1017 axe_stop(ue);
1018 axe_reset(sc);
1019
1020 /* Set MAC address and transmitter IPG values. */
1021 if (AXE_IS_178_FAMILY(sc)) {
1022 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
1023 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1024 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1025 } else {
1026 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
1027 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1028 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1029 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1030 }
1031 if (AXE_IS_178_FAMILY(sc)) {
1032 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1033 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1034 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1035 }
1036 /* Configure TX/RX checksum offloading. */
1037 axe_csum_cfg(ue);
1038 if (sc->sc_flags & AXE_FLAG_772B) {
1039 /* AX88772B uses different maximum frame burst configuration. */
1040 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1041 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1042 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1043 }
1044
1045 /* Enable receiver, set RX mode. */
1046 rxmode = (AXE_RXCMD_ALLMULTI | AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1047 if (AXE_IS_178_FAMILY(sc)) {
1048 if (sc->sc_flags & AXE_FLAG_772B) {
1049 /*
1050 * Select RX header format type 1. Aligning IP
1051 * header on 4 byte boundary is not needed when
1052 * checksum offloading feature is not used
1053 * because we always copy the received frame in
1054 * RX handler. When RX checksum offloading is
1055 * active, aligning IP header is required to
1056 * reflect actual frame length including RX
1057 * header size.
1058 */
1059 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1060 } else {
1061 /*
1062 * Default Rx buffer size is too small to get
1063 * maximum performance.
1064 */
1065 if (sc->sc_flags & AXE_FLAG_772A)
1066 rxmode |= AXE_178_RXCMD_MFB_16384;
1067 }
1068 } else {
1069 rxmode |= AXE_172_RXCMD_UNICAST;
1070 }
1071
1072 /* If we want promiscuous mode, set the allframes bit. */
1073 if (drv_sc->state & IFF_PROMISC)
1074 rxmode |= AXE_RXCMD_PROMISC;
1075
1076 if (drv_sc->state & IFF_BROADCAST)
1077 rxmode |= AXE_RXCMD_BROADCAST;
1078
1079 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1080
1081 /* Load the multicast filter. */
1082 axe_setmulti(ue);
1083
1084 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1085 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_RD]);
1086
1087 drv_sc->state |= IFF_DRV_RUNNING;
1088 ifp->ac_if.link_layer_type = ETHERNET_DRIVER_IF;
1089 }
1090
1091 static void
axe_setpromisc(struct usb_ether *ue)1092 axe_setpromisc(struct usb_ether *ue)
1093 {
1094 struct axe_softc *sc = uether_getsc(ue);
1095 struct los_eth_driver *ifp = ue->ue_drv_sc;
1096 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context;
1097 uint16_t rxmode;
1098
1099 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1100
1101 rxmode = le16toh(rxmode);
1102
1103 if (drv_sc->state & IFF_PROMISC) {
1104 rxmode |= AXE_RXCMD_PROMISC;
1105 } else {
1106 rxmode &= ~AXE_RXCMD_PROMISC;
1107 }
1108
1109 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1110 axe_setmulti(ue);
1111 }
1112
1113 static void
axe_tick(struct usb_ether *ue)1114 axe_tick(struct usb_ether *ue)
1115 {
1116 struct axe_softc *sc = uether_getsc(ue);
1117 uint16_t link_status;
1118
1119 AXE_LOCK_ASSERT(sc, MA_OWNED);
1120
1121 link_status = axe_miibus_readreg(sc, MII_BMSR) & AXE_LINK_MASK;
1122 if (sc->sc_link_status != link_status) {
1123 axe_miibus_statchg(sc, link_status);
1124 sc->sc_link_status = link_status;
1125 }
1126 }
1127
1128 static void
axe_stop(struct usb_ether *ue)1129 axe_stop(struct usb_ether *ue)
1130 {
1131 struct axe_softc *sc = uether_getsc(ue);
1132 struct los_eth_driver *ifp = ue->ue_drv_sc;
1133 struct eth_drv_sc *drv_sc = (struct eth_drv_sc *)ifp->driver_context;
1134
1135 AXE_LOCK_ASSERT(sc, MA_OWNED);
1136 drv_sc->state &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1137 sc->sc_flags &= ~AXE_FLAG_LINK;
1138 /*
1139 * stop all the transfers, if not already stopped:
1140 */
1141 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1142 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1143 }
1144
1145 #undef USB_DEBUG_VAR
1146