1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31 #include <stdarg.h>
32 #include "securec.h"
33 #include "los_context.h"
34 #include "los_arch_interrupt.h"
35 #include "los_hook.h"
36 #include "los_task.h"
37 #include "los_sched.h"
38 #include "los_memory.h"
39 #include "los_membox.h"
40 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
41 #include "los_cpup.h"
42 #endif
43
44 /* ****************************************************************************
45 Function : HwiNumGet
46 Description : Get an interrupt number
47 Input : None
48 Output : None
49 Return : Interrupt Indexes number
50 **************************************************************************** */
HwiNumGetnull51 STATIC UINT32 HwiNumGet(VOID)
52 {
53 return __get_IPSR();
54 }
55
HwiUnmask(HWI_HANDLE_T hwiNum)56 STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
57 {
58 NVIC_EnableIRQ((IRQn_Type)hwiNum);
59 return LOS_OK;
60 }
61
HwiMask(HWI_HANDLE_T hwiNum)62 STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
63 {
64 NVIC_DisableIRQ((IRQn_Type)hwiNum);
65 return LOS_OK;
66 }
67
HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)68 STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority)
69 {
70 NVIC_SetPriority((IRQn_Type)hwiNum, priority);
71 return LOS_OK;
72 }
73
HwiPending(HWI_HANDLE_T hwiNum)74 STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum)
75 {
76 NVIC_SetPendingIRQ((IRQn_Type)hwiNum);
77 return LOS_OK;
78 }
79
HwiClear(HWI_HANDLE_T hwiNum)80 STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum)
81 {
82 NVIC_ClearPendingIRQ((IRQn_Type)hwiNum);
83 return LOS_OK;
84 }
85
HwiCreate(HWI_HANDLE_T hwiNum, HWI_PRIOR_T hwiPrio)86 STATIC UINT32 HwiCreate(HWI_HANDLE_T hwiNum, HWI_PRIOR_T hwiPrio)
87 {
88 HwiSetPriority(hwiNum, hwiPrio);
89 HwiUnmask(hwiNum);
90 return LOS_OK;
91 }
92
93 STATIC HwiControllerOps g_archHwiOps = {
94 .enableIrq = HwiUnmask,
95 .disableIrq = HwiMask,
96 .setIrqPriority = HwiSetPriority,
97 .getCurIrqNum = HwiNumGet,
98 .triggerIrq = HwiPending,
99 .clearIrq = HwiClear,
100 .createIrq = HwiCreate,
101 };
102
ArchIntOpsGetnull103 HwiControllerOps *ArchIntOpsGet(VOID)
104 {
105 return &g_archHwiOps;
106 }
107
108 /* ****************************************************************************
109 Function : HalInterrupt
110 Description : Hardware interrupt entry function
111 Input : None
112 Output : None
113 Return : None
114 **************************************************************************** */
HalInterruptnull115 LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
116 {
117 UINT32 hwiIndex;
118 UINT32 intSave;
119
120 #if (LOSCFG_KERNEL_RUNSTOP == 1)
121 SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
122 #endif
123
124 intSave = LOS_IntLock();
125 g_intCount++;
126 LOS_IntRestore(intSave);
127
128 hwiIndex = HwiNumGet();
129
130 OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
131 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
132 OsCpupIrqStart(hwiIndex);
133 #endif
134
135 HalPreInterruptHandler(hwiIndex);
136
137 #if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
138 if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
139 g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
140 }
141 #else
142 if (g_hwiHandlerForm[hwiIndex] != 0) {
143 g_hwiHandlerForm[hwiIndex]();
144 }
145 #endif
146
147 #if (LOSCFG_DEBUG_TOOLS == 1)
148 ++g_hwiFormCnt[hwiIndex];
149 #endif
150
151 HalAftInterruptHandler(hwiIndex);
152
153 #if (LOSCFG_CPUP_INCLUDE_IRQ == 1)
154 OsCpupIrqEnd(hwiIndex);
155 #endif
156
157 OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
158
159 intSave = LOS_IntLock();
160 g_intCount--;
161 LOS_IntRestore(intSave);
162 }
163
164 #define FAULT_STATUS_REG_BIT 32
165 #define USGFAULT (1 << 18)
166 #define BUSFAULT (1 << 17)
167 #define MEMFAULT (1 << 16)
168 #define DIV0FAULT (1 << 4)
169 #define UNALIGNFAULT (1 << 3)
170 #define HARDFAULT_IRQN (-13)
171
172 ExcInfo g_excInfo = {0};
173
174 UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
175 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
176 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
177 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
178 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
179 };
180
181 #if (LOSCFG_KERNEL_PRINTF != 0)
OsExcNvicDumpnull182 STATIC VOID OsExcNvicDump(VOID)
183 {
184 #define OS_NR_NVIC_EXC_DUMP_TYPES 7
185 UINT32 *base = NULL;
186 UINT32 len, i, j;
187 UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
188 OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
189 OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
190 };
191 UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
192 OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
193 OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
194 OS_NVIC_INT_CTRL_SIZE
195 };
196 CHAR strRgEnable[] = "enable";
197 CHAR strRgPending[] = "pending";
198 CHAR strRgActive[] = "active";
199 CHAR strRgPriority[] = "priority";
200 CHAR strRgException[] = "exception";
201 CHAR strRgShcsr[] = "shcsr";
202 CHAR strRgIntCtrl[] = "control";
203 CHAR *strRgs[] = {
204 strRgEnable, strRgPending, strRgActive, strRgPriority,
205 strRgException, strRgShcsr, strRgIntCtrl
206 };
207
208 PRINTK("\r\nOS exception NVIC dump:\n");
209 for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
210 base = (UINT32 *)rgNvicBases[i];
211 len = rgNvicLens[i];
212 PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
213 len = (len >> 2); /* 2: Gets the next register offset */
214 for (j = 0; j < len; j++) {
215 PRINTK("0x%x ", *(base + j));
216 if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
217 PRINTK("\n");
218 }
219 }
220 PRINTK("\n");
221 }
222 }
223
OsExcTypeInfo(const ExcInfo *excInfo)224 STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
225 {
226 CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
227
228 PRINTK("Type = %d\n", excInfo->type);
229 PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
230 PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
231 PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
232 }
233
OsExcCurTaskInfo(const ExcInfo *excInfo)234 STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
235 {
236 PRINTK("Current task info:\n");
237 if (excInfo->phase == OS_EXC_IN_TASK) {
238 LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
239 PRINTK("Task name = %s\n", taskCB->taskName);
240 PRINTK("Task ID = %d\n", taskCB->taskID);
241 PRINTK("Task SP = %p\n", taskCB->stackPointer);
242 PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
243 PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
244 } else if (excInfo->phase == OS_EXC_IN_HWI) {
245 PRINTK("Exception occur in interrupt phase!\n");
246 } else {
247 PRINTK("Exception occur in system init phase!\n");
248 }
249 }
250
OsExcRegInfo(const ExcInfo *excInfo)251 STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
252 {
253 PRINTK("Exception reg dump:\n");
254 PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
255 PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
256 PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
257 PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
258 PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
259 PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
260 PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
261 PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
262 PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
263 PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
264 PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
265 PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
266 PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
267 PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
268 PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
269 PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
270 PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
271 PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
272 }
273
274 #if (LOSCFG_KERNEL_BACKTRACE == 1)
OsExcBackTraceInfo(const ExcInfo *excInfo)275 STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
276 {
277 UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
278 UINT32 index;
279
280 OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
281
282 PRINTK("----- backtrace start -----\n");
283 for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
284 if (LR[index] == 0) {
285 break;
286 }
287 PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
288 }
289 PRINTK("----- backtrace end -----\n");
290 }
291 #endif
292
OsExcMemPoolCheckInfonull293 STATIC VOID OsExcMemPoolCheckInfo(VOID)
294 {
295 PRINTK("\r\nmemory pools check:\n");
296 #if (LOSCFG_PLATFORM_EXC == 1)
297 MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
298 UINT32 errCnt;
299 UINT32 i;
300
301 (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
302
303 errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
304 if (errCnt < OS_SYS_MEM_NUM) {
305 errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
306 }
307
308 if (errCnt == 0) {
309 PRINTK("all memory pool check passed!\n");
310 return;
311 }
312
313 for (i = 0; i < errCnt; i++) {
314 PRINTK("pool num = %d\n", i);
315 PRINTK("pool type = %d\n", memExcInfo[i].type);
316 PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
317 PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
318 PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
319 PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
320 PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
321 PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
322 PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
323 }
324 #endif
325 UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
326 if (ret == LOS_OK) {
327 PRINTK("system heap memcheck over, all passed!\n");
328 }
329
330 PRINTK("memory pool check end!\n");
331 }
332 #endif
333
OsExcInfoDisplay(const ExcInfo *excInfo)334 STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
335 {
336 #if (LOSCFG_KERNEL_PRINTF != 0)
337 PRINTK("*************Exception Information**************\n");
338 OsExcTypeInfo(excInfo);
339 OsExcCurTaskInfo(excInfo);
340 OsExcRegInfo(excInfo);
341 #if (LOSCFG_KERNEL_BACKTRACE == 1)
342 OsExcBackTraceInfo(excInfo);
343 #endif
344 OsGetAllTskInfo();
345 OsExcNvicDump();
346 OsExcMemPoolCheckInfo();
347 #endif
348 }
349
HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)350 LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
351 {
352 UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
353 g_intCount++;
354 g_excInfo.nestCnt++;
355
356 g_excInfo.type = excType & OS_NULL_SHORT;
357
358 if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
359 g_excInfo.faultAddr = faultAddr;
360 } else {
361 g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
362 }
363 if (g_losTask.runTask != NULL) {
364 if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
365 g_excInfo.phase = OS_EXC_IN_HWI;
366 g_excInfo.thrdPid = pid;
367 } else {
368 g_excInfo.phase = OS_EXC_IN_TASK;
369 g_excInfo.thrdPid = g_losTask.runTask->taskID;
370 }
371 } else {
372 g_excInfo.phase = OS_EXC_IN_INIT;
373 g_excInfo.thrdPid = OS_NULL_INT;
374 }
375 if (excType & OS_EXC_FLAG_NO_FLOAT) {
376 g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
377 } else {
378 g_excInfo.context = excBufAddr;
379 }
380
381 OsDoExcHook(EXC_INTERRUPT);
382 OsExcInfoDisplay(&g_excInfo);
383 ArchSysExit();
384 }
385
SysTick_Handlernull386 WEAK VOID SysTick_Handler(VOID)
387 {
388 return;
389 }
390
391 /* ****************************************************************************
392 Function : HalHwiInit
393 Description : initialization of the hardware interrupt
394 Input : None
395 Output : None
396 Return : None
397 **************************************************************************** */
HalHwiInitnull398 LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
399 {
400 #if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
401 UINT32 index;
402 HWI_PROC_FUNC *hwiForm = (HWI_PROC_FUNC *)ArchGetHwiFrom();
403 hwiForm[0] = 0; /* [0] Top of Stack */
404 hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */
405 for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
406 hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
407 }
408 /* Exception handler register */
409 hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI;
410 hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault;
411 hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault;
412 hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault;
413 hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault;
414 hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcSvcCall;
415 hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV;
416 hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)SysTick_Handler;
417
418 /* Interrupt vector table location */
419 SCB->VTOR = (UINT32)(UINTPTR)hwiForm;
420 #endif
421 #if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
422 NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
423 #endif
424
425 /* Enable USGFAULT, BUSFAULT, MEMFAULT */
426 *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
427
428 /* Enable DIV 0 and unaligned exception */
429 #ifdef LOSCFG_ARCH_UNALIGNED_EXC
430 *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
431 #else
432 *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
433 #endif
434
435 return;
436 }
437