1 /* 2 * This header was generated from the Linux kernel headers by update_headers.py, 3 * to provide necessary information from kernel to userspace, such as constants, 4 * structures, and macros, and thus, contains no copyrightable information. 5 */ 6 #ifndef VIRTGPU_DRM_H 7 #define VIRTGPU_DRM_H 8 #include "drm.h" 9 #if defined(__cplusplus) 10 extern "C" { 11 #endif 12 #define DRM_VIRTGPU_MAP 0x01 13 #define DRM_VIRTGPU_EXECBUFFER 0x02 14 #define DRM_VIRTGPU_GETPARAM 0x03 15 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 16 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 17 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 18 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 19 #define DRM_VIRTGPU_WAIT 0x08 20 #define DRM_VIRTGPU_GET_CAPS 0x09 21 struct drm_virtgpu_map { 22 __u64 offset; 23 __u32 handle; 24 __u32 pad; 25 }; 26 struct drm_virtgpu_execbuffer { 27 __u32 flags; 28 __u32 size; 29 __u64 command; 30 __u64 bo_handles; 31 __u32 num_bo_handles; 32 __u32 pad; 33 }; 34 #define VIRTGPU_PARAM_3D_FEATURES 1 35 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 36 struct drm_virtgpu_getparam { 37 __u64 param; 38 __u64 value; 39 }; 40 struct drm_virtgpu_resource_create { 41 __u32 target; 42 __u32 format; 43 __u32 bind; 44 __u32 width; 45 __u32 height; 46 __u32 depth; 47 __u32 array_size; 48 __u32 last_level; 49 __u32 nr_samples; 50 __u32 flags; 51 __u32 bo_handle; 52 __u32 res_handle; 53 __u32 size; 54 __u32 stride; 55 }; 56 struct drm_virtgpu_resource_info { 57 __u32 bo_handle; 58 __u32 res_handle; 59 __u32 size; 60 __u32 stride; 61 }; 62 struct drm_virtgpu_3d_box { 63 __u32 x; 64 __u32 y; 65 __u32 z; 66 __u32 w; 67 __u32 h; 68 __u32 d; 69 }; 70 struct drm_virtgpu_3d_transfer_to_host { 71 __u32 bo_handle; 72 struct drm_virtgpu_3d_box box; 73 __u32 level; 74 __u32 offset; 75 }; 76 struct drm_virtgpu_3d_transfer_from_host { 77 __u32 bo_handle; 78 struct drm_virtgpu_3d_box box; 79 __u32 level; 80 __u32 offset; 81 }; 82 #define VIRTGPU_WAIT_NOWAIT 1 83 struct drm_virtgpu_3d_wait { 84 __u32 handle; 85 __u32 flags; 86 }; 87 struct drm_virtgpu_get_caps { 88 __u32 cap_set_id; 89 __u32 cap_set_ver; 90 __u64 addr; 91 __u32 size; 92 __u32 pad; 93 }; 94 #define DRM_IOCTL_VIRTGPU_MAP \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 96 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ 98 struct drm_virtgpu_execbuffer) 99 #define DRM_IOCTL_VIRTGPU_GETPARAM \ 100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ 101 struct drm_virtgpu_getparam) 102 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ 103 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ 104 struct drm_virtgpu_resource_create) 105 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ 106 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ 107 struct drm_virtgpu_resource_info) 108 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ 109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ 110 struct drm_virtgpu_3d_transfer_from_host) 111 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ 112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ 113 struct drm_virtgpu_3d_transfer_to_host) 114 #define DRM_IOCTL_VIRTGPU_WAIT \ 115 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ 116 struct drm_virtgpu_3d_wait) 117 #define DRM_IOCTL_VIRTGPU_GET_CAPS \ 118 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ 119 struct drm_virtgpu_get_caps) 120 #if defined(__cplusplus) 121 } 122 #endif 123 #endif 124