1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9
10 #include "mt7996.h"
11 #include "mac.h"
12 #include "../trace.h"
13
14 static const struct __base mt7996_reg_base[] = {
15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
25 };
26
27 static const struct __map mt7996_reg_map[] = {
28 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
29 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
30 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
31 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
32 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
33 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
34 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
35 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
36 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
37 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
38 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
39 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
40 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
41 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
42 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
43 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
44 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
45 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
46 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
47 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
48 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
49 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
50 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
51 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
52 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
53 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
54 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
55 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
56 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
57 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
58 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
59 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
60 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
61 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
62 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
63 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
64 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
65 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
66 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
67 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
68 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
69 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
70 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
71 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
72 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
73 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
74 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
75 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
76 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
77 { 0x0, 0x0, 0x0 }, /* imply end of search */
78 };
79
mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)80 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr)
81 {
82 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
83 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
84
85 dev->reg_l1_backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
86 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1,
87 MT_HIF_REMAP_L1_MASK,
88 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
89 /* use read to push write */
90 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1);
91
92 return MT_HIF_REMAP_BASE_L1 + offset;
93 }
94
mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr)95 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr)
96 {
97 u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
98 u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
99
100 dev->reg_l2_backup = dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
101 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
102 MT_HIF_REMAP_L2_MASK,
103 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
104 /* use read to push write */
105 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
106
107 return MT_HIF_REMAP_BASE_L2 + offset;
108 }
109
mt7996_reg_remap_restore(struct mt7996_dev *dev)110 static void mt7996_reg_remap_restore(struct mt7996_dev *dev)
111 {
112 /* remap to ori status */
113 if (unlikely(dev->reg_l1_backup)) {
114 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L1, dev->reg_l1_backup);
115 dev->reg_l1_backup = 0;
116 }
117
118 if (dev->reg_l2_backup) {
119 dev->bus_ops->wr(&dev->mt76, MT_HIF_REMAP_L2, dev->reg_l2_backup);
120 dev->reg_l2_backup = 0;
121 }
122 }
123
__mt7996_reg_addr(struct mt7996_dev *dev, u32 addr)124 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr)
125 {
126 int i;
127
128 mt7996_reg_remap_restore(dev);
129
130 if (addr < 0x100000)
131 return addr;
132
133 for (i = 0; i < dev->reg.map_size; i++) {
134 u32 ofs;
135
136 if (addr < dev->reg.map[i].phys)
137 continue;
138
139 ofs = addr - dev->reg.map[i].phys;
140 if (ofs > dev->reg.map[i].size)
141 continue;
142
143 return dev->reg.map[i].mapped + ofs;
144 }
145
146 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
147 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
148 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
149 return mt7996_reg_map_l1(dev, addr);
150
151 if (dev_is_pci(dev->mt76.dev) &&
152 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
153 addr >= MT_CBTOP2_PHY_START))
154 return mt7996_reg_map_l1(dev, addr);
155
156 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
157 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
158 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
159 return mt7996_reg_map_l1(dev, addr);
160 }
161
162 return mt7996_reg_map_l2(dev, addr);
163 }
164
mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, size_t len)165 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
166 size_t len)
167 {
168 u32 addr = __mt7996_reg_addr(dev, offset);
169
170 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len);
171 }
172
mt7996_rr(struct mt76_dev *mdev, u32 offset)173 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset)
174 {
175 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
176
177 return dev->bus_ops->rr(mdev, __mt7996_reg_addr(dev, offset));
178 }
179
mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val)180 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val)
181 {
182 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
183
184 dev->bus_ops->wr(mdev, __mt7996_reg_addr(dev, offset), val);
185 }
186
mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)187 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
188 {
189 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
190
191 return dev->bus_ops->rmw(mdev, __mt7996_reg_addr(dev, offset), mask, val);
192 }
193
mt7996_mmio_init(struct mt76_dev *mdev, void __iomem *mem_base, u32 device_id)194 static int mt7996_mmio_init(struct mt76_dev *mdev,
195 void __iomem *mem_base,
196 u32 device_id)
197 {
198 struct mt76_bus_ops *bus_ops;
199 struct mt7996_dev *dev;
200
201 dev = container_of(mdev, struct mt7996_dev, mt76);
202 mt76_mmio_init(&dev->mt76, mem_base);
203
204 switch (device_id) {
205 case 0x7990:
206 dev->reg.base = mt7996_reg_base;
207 dev->reg.map = mt7996_reg_map;
208 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map);
209 break;
210 default:
211 return -EINVAL;
212 }
213
214 dev->bus_ops = dev->mt76.bus;
215 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
216 GFP_KERNEL);
217 if (!bus_ops)
218 return -ENOMEM;
219
220 bus_ops->rr = mt7996_rr;
221 bus_ops->wr = mt7996_wr;
222 bus_ops->rmw = mt7996_rmw;
223 dev->mt76.bus = bus_ops;
224
225 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff);
226
227 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
228
229 return 0;
230 }
231
mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, u32 clear, u32 set)232 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
233 u32 clear, u32 set)
234 {
235 struct mt76_dev *mdev = &dev->mt76;
236 unsigned long flags;
237
238 spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
239
240 mdev->mmio.irqmask &= ~clear;
241 mdev->mmio.irqmask |= set;
242
243 if (write_reg) {
244 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
245 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
246 }
247
248 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
249 }
250
mt7996_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)251 static void mt7996_rx_poll_complete(struct mt76_dev *mdev,
252 enum mt76_rxq_id q)
253 {
254 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76);
255
256 mt7996_irq_enable(dev, MT_INT_RX(q));
257 }
258
259 /* TODO: support 2/4/6/8 MSI-X vectors */
mt7996_irq_tasklet(struct tasklet_struct *t)260 static void mt7996_irq_tasklet(struct tasklet_struct *t)
261 {
262 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet);
263 u32 i, intr, mask, intr1;
264
265 mt76_wr(dev, MT_INT_MASK_CSR, 0);
266 if (dev->hif2)
267 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
268
269 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
270 intr &= dev->mt76.mmio.irqmask;
271 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
272
273 if (dev->hif2) {
274 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
275 intr1 &= dev->mt76.mmio.irqmask;
276 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
277
278 intr |= intr1;
279 }
280
281 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
282
283 mask = intr & MT_INT_RX_DONE_ALL;
284 if (intr & MT_INT_TX_DONE_MCU)
285 mask |= MT_INT_TX_DONE_MCU;
286 mt7996_irq_disable(dev, mask);
287
288 if (intr & MT_INT_TX_DONE_MCU)
289 napi_schedule(&dev->mt76.tx_napi);
290
291 for (i = 0; i < __MT_RXQ_MAX; i++) {
292 if ((intr & MT_INT_RX(i)))
293 napi_schedule(&dev->mt76.napi[i]);
294 }
295
296 if (intr & MT_INT_MCU_CMD) {
297 u32 val = mt76_rr(dev, MT_MCU_CMD);
298
299 mt76_wr(dev, MT_MCU_CMD, val);
300 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) {
301 dev->recovery.state = val;
302 mt7996_reset(dev);
303 }
304 }
305 }
306
mt7996_irq_handler(int irq, void *dev_instance)307 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance)
308 {
309 struct mt7996_dev *dev = dev_instance;
310
311 mt76_wr(dev, MT_INT_MASK_CSR, 0);
312 if (dev->hif2)
313 mt76_wr(dev, MT_INT1_MASK_CSR, 0);
314
315 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
316 return IRQ_NONE;
317
318 tasklet_schedule(&dev->mt76.irq_tasklet);
319
320 return IRQ_HANDLED;
321 }
322
mt7996_mmio_probe(struct device *pdev, void __iomem *mem_base, u32 device_id)323 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
324 void __iomem *mem_base, u32 device_id)
325 {
326 static const struct mt76_driver_ops drv_ops = {
327 /* txwi_size = txd size + txp size */
328 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
329 .drv_flags = MT_DRV_TXWI_NO_FREE |
330 MT_DRV_AMSDU_OFFLOAD |
331 MT_DRV_HW_MGMT_TXQ,
332 .survey_flags = SURVEY_INFO_TIME_TX |
333 SURVEY_INFO_TIME_RX |
334 SURVEY_INFO_TIME_BSS_RX,
335 .token_size = MT7996_TOKEN_SIZE,
336 .tx_prepare_skb = mt7996_tx_prepare_skb,
337 .tx_complete_skb = mt76_connac_tx_complete_skb,
338 .rx_skb = mt7996_queue_rx_skb,
339 .rx_check = mt7996_rx_check,
340 .rx_poll_complete = mt7996_rx_poll_complete,
341 .sta_add = mt7996_mac_sta_add,
342 .sta_remove = mt7996_mac_sta_remove,
343 .update_survey = mt7996_update_channel,
344 };
345 struct mt7996_dev *dev;
346 struct mt76_dev *mdev;
347 int ret;
348
349 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops);
350 if (!mdev)
351 return ERR_PTR(-ENOMEM);
352
353 dev = container_of(mdev, struct mt7996_dev, mt76);
354
355 ret = mt7996_mmio_init(mdev, mem_base, device_id);
356 if (ret)
357 goto error;
358
359 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet);
360
361 mt76_wr(dev, MT_INT_MASK_CSR, 0);
362
363 return dev;
364
365 error:
366 mt76_free_device(&dev->mt76);
367
368 return ERR_PTR(ret);
369 }
370
mt7996_init(void)371 static int __init mt7996_init(void)
372 {
373 int ret;
374
375 ret = pci_register_driver(&mt7996_hif_driver);
376 if (ret)
377 return ret;
378
379 ret = pci_register_driver(&mt7996_pci_driver);
380 if (ret)
381 pci_unregister_driver(&mt7996_hif_driver);
382
383 return ret;
384 }
385
mt7996_exit(void)386 static void __exit mt7996_exit(void)
387 {
388 pci_unregister_driver(&mt7996_pci_driver);
389 pci_unregister_driver(&mt7996_hif_driver);
390 }
391
392 module_init(mt7996_init);
393 module_exit(mt7996_exit);
394 MODULE_LICENSE("Dual BSD/GPL");
395