1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /*****************************************************************************/ 3 4 /* 5 * head.S -- common startup code for ColdFire CPUs. 6 * 7 * (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>. 8 */ 9 10 /*****************************************************************************/ 11 12 #include <linux/linkage.h> 13 #include <linux/init.h> 14 #include <asm/asm-offsets.h> 15 #include <asm/coldfire.h> 16 #include <asm/mcfsim.h> 17 #include <asm/mcfmmu.h> 18 #include <asm/thread_info.h> 19 20 /*****************************************************************************/ 21 22 /* 23 * If we don't have a fixed memory size, then lets build in code 24 * to auto detect the DRAM size. Obviously this is the preferred 25 * method, and should work for most boards. It won't work for those 26 * that do not have their RAM starting at address 0, and it only 27 * works on SDRAM (not boards fitted with SRAM). 28 */ 29 #if CONFIG_RAMSIZE != 0 30 .macro GET_MEM_SIZE 31 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ 32 .endm 33 34 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 35 defined(CONFIG_M5249) || defined(CONFIG_M525x) || \ 36 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 37 defined(CONFIG_M5307) || defined(CONFIG_M5407) 38 /* 39 * Not all these devices have exactly the same DRAM controller, 40 * but the DCMR register is virtually identical - give or take 41 * a couple of bits. The only exception is the 5272 devices, their 42 * DRAM controller is quite different. 43 */ 44 .macro GET_MEM_SIZE 45 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */ 46 btst #0,%d0 /* check if region enabled */ 47 beq 1f 48 andl #0xfffc0000,%d0 49 beq 1f 50 addl #0x00040000,%d0 /* convert mask to size */ 51 1: 52 movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */ 53 btst #0,%d1 /* check if region enabled */ 54 beq 2f 55 andl #0xfffc0000,%d1 56 beq 2f 57 addl #0x00040000,%d1 58 addl %d1,%d0 /* total mem size in d0 */ 59 2: 60 .endm 61 62 #elif defined(CONFIG_M5272) 63 .macro GET_MEM_SIZE 64 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ 65 andil #0xfffff000,%d0 /* mask out chip select options */ 66 negl %d0 /* negate bits */ 67 .endm 68 69 #elif defined(CONFIG_M520x) 70 .macro GET_MEM_SIZE 71 clrl %d0 72 movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */ 73 andl #0x1f, %d2 /* Get only the chip select size */ 74 beq 3f /* Check if it is enabled */ 75 addql #1, %d2 /* Form exponent */ 76 moveql #1, %d0 77 lsll %d2, %d0 /* 2 ^ exponent */ 78 3: 79 movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */ 80 andl #0x1f, %d2 /* Get only the chip select size */ 81 beq 4f /* Check if it is enabled */ 82 addql #1, %d2 /* Form exponent */ 83 moveql #1, %d1 84 lsll %d2, %d1 /* 2 ^ exponent */ 85 addl %d1, %d0 /* Total size of SDRAM in d0 */ 86 4: 87 .endm 88 89 #else 90 #error "ERROR: I don't know how to probe your boards memory size?" 91 #endif 92 93 /*****************************************************************************/ 94 95 /* 96 * Boards and platforms can do specific early hardware setup if 97 * they need to. Most don't need this, define away if not required. 98 */ 99 #ifndef PLATFORM_SETUP 100 #define PLATFORM_SETUP 101 #endif 102 103 /*****************************************************************************/ 104 105 .global _start 106 .global _rambase 107 .global _ramvec 108 .global _ramstart 109 .global _ramend 110 #if defined(CONFIG_UBOOT) 111 .global _init_sp 112 #endif 113 114 /*****************************************************************************/ 115 116 .data 117 118 /* 119 * During startup we store away the RAM setup. These are not in the 120 * bss, since their values are determined and written before the bss 121 * has been cleared. 122 */ 123 _rambase: 124 .long 0 125 _ramvec: 126 .long 0 127 _ramstart: 128 .long 0 129 _ramend: 130 .long 0 131 #if defined(CONFIG_UBOOT) 132 _init_sp: 133 .long 0 134 #endif 135 136 /*****************************************************************************/ 137 138 __HEAD 139 140 #ifdef CONFIG_MMU 141 _start0: 142 jmp _start 143 .global kernel_pg_dir 144 .equ kernel_pg_dir,_start0 145 .equ .,_start0+0x1000 146 #endif 147 148 /* 149 * This is the codes first entry point. This is where it all 150 * begins... 151 */ 152 153 _start: 154 nop /* filler */ 155 movew #0x2700, %sr /* no interrupts */ 156 movel #CACHE_INIT,%d0 /* disable cache */ 157 movec %d0,%CACR 158 nop 159 #if defined(CONFIG_UBOOT) 160 movel %sp,_init_sp /* save initial stack pointer */ 161 #endif 162 #ifdef CONFIG_MBAR 163 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */ 164 movec %d0,%MBAR /* set it */ 165 #endif 166 167 /* 168 * Do any platform or board specific setup now. Most boards 169 * don't need anything. Those exceptions are define this in 170 * their board specific includes. 171 */ 172 PLATFORM_SETUP 173 174 /* 175 * Create basic memory configuration. Set VBR accordingly, 176 * and size memory. 177 */ 178 movel #CONFIG_VECTORBASE,%a7 179 movec %a7,%VBR /* set vectors addr */ 180 movel %a7,_ramvec 181 182 movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */ 183 movel %a7,_rambase 184 185 GET_MEM_SIZE /* macro code determines size */ 186 addl %a7,%d0 187 movel %d0,_ramend /* set end ram addr */ 188 189 /* 190 * Now that we know what the memory is, lets enable cache 191 * and get things moving. This is Coldfire CPU specific. Not 192 * all version cores have identical cache register setup. But 193 * it is very similar. Define the exact settings in the headers 194 * then the code here is the same for all. 195 */ 196 movel #ACR0_MODE,%d0 /* set RAM region for caching */ 197 movec %d0,%ACR0 198 movel #ACR1_MODE,%d0 /* anything else to cache? */ 199 movec %d0,%ACR1 200 #ifdef ACR2_MODE 201 movel #ACR2_MODE,%d0 202 movec %d0,%ACR2 203 movel #ACR3_MODE,%d0 204 movec %d0,%ACR3 205 #endif 206 movel #CACHE_MODE,%d0 /* enable cache */ 207 movec %d0,%CACR 208 nop 209 210 #ifdef CONFIG_MMU 211 /* 212 * Identity mapping for the kernel region. 213 */ 214 movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */ 215 movec %d0,%MMUBAR 216 movel #MMUOR_CA,%d0 /* clear TLB entries */ 217 movel %d0,MMUOR 218 movel #0,%d0 /* set ASID to 0 */ 219 movec %d0,%asid 220 221 movel #MMUCR_EN,%d0 /* Enable the identity map */ 222 movel %d0,MMUCR 223 nop /* sync i-pipeline */ 224 225 movel #_vstart,%a0 /* jump to "virtual" space */ 226 jmp %a0@ 227 _vstart: 228 #endif /* CONFIG_MMU */ 229 230 #ifdef CONFIG_ROMFS_FS 231 /* 232 * Move ROM filesystem above bss :-) 233 */ 234 lea __bss_start,%a0 /* get start of bss */ 235 lea __bss_stop,%a1 /* set up destination */ 236 movel %a0,%a2 /* copy of bss start */ 237 238 movel 8(%a0),%d0 /* get size of ROMFS */ 239 addql #8,%d0 /* allow for rounding */ 240 andl #0xfffffffc, %d0 /* whole words */ 241 242 addl %d0,%a0 /* copy from end */ 243 addl %d0,%a1 /* copy from end */ 244 movel %a1,_ramstart /* set start of ram */ 245 246 _copy_romfs: 247 movel -(%a0),%d0 /* copy dword */ 248 movel %d0,-(%a1) 249 cmpl %a0,%a2 /* check if at end */ 250 bne _copy_romfs 251 252 #else /* CONFIG_ROMFS_FS */ 253 lea __bss_stop,%a1 254 movel %a1,_ramstart 255 #endif /* CONFIG_ROMFS_FS */ 256 257 258 /* 259 * Zero out the bss region. 260 */ 261 lea __bss_start,%a0 /* get start of bss */ 262 lea __bss_stop,%a1 /* get end of bss */ 263 clrl %d0 /* set value */ 264 _clear_bss: 265 movel %d0,(%a0)+ /* clear each word */ 266 cmpl %a0,%a1 /* check if at end */ 267 bne _clear_bss 268 269 /* 270 * Load the current task pointer and stack. 271 */ 272 lea init_thread_union,%a0 273 lea THREAD_SIZE(%a0),%sp 274 275 #ifdef CONFIG_MMU 276 .global m68k_cputype 277 .global m68k_mmutype 278 .global m68k_fputype 279 .global m68k_machtype 280 movel #CPU_COLDFIRE,%d0 281 movel %d0,m68k_cputype /* Mark us as a ColdFire */ 282 movel #MMU_COLDFIRE,%d0 283 movel %d0,m68k_mmutype 284 movel #FPUTYPE,%d0 285 movel %d0,m68k_fputype /* Mark FPU type */ 286 movel #MACHINE,%d0 287 movel %d0,m68k_machtype /* Mark machine type */ 288 lea init_task,%a2 /* Set "current" init task */ 289 #endif 290 291 /* 292 * Assembler start up done, start code proper. 293 */ 294 jsr start_kernel /* start Linux kernel */ 295 296 _exit: 297 jmp _exit /* should never get here */ 298 299 /*****************************************************************************/ 300