1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #define VF_UART0_BASE_ADDR 0x40027000 7 #define VF_UART1_BASE_ADDR 0x40028000 8 #define VF_UART2_BASE_ADDR 0x40029000 9 #define VF_UART3_BASE_ADDR 0x4002a000 10 #define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR 11 #define VF_UART_BASE(n) VF_UART_BASE_ADDR(n) 12 #define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT) 13 14 #define VF_UART_VIRTUAL_BASE 0xfe000000 15 16 .macro addruart, rp, rv, tmp 17 ldr \rp, =VF_UART_PHYSICAL_BASE @ physical 18 and \rv, \rp, #0xffffff @ offset within 16MB section 19 add \rv, \rv, #VF_UART_VIRTUAL_BASE 20 .endm 21 22 .macro senduart, rd, rx 23 strb \rd, [\rx, #0x7] @ Data Register 24 .endm 25 26 .macro busyuart, rd, rx 27 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1 28 tst \rd, #1 << 6 @ TC 29 beq 1001b @ wait until transmit done 30 .endm 31 32 .macro waituartcts,rd,rx 33 .endm 34 35 .macro waituarttxrdy,rd,rx 36 .endm 37