1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 *
5 * lpass-sc7180.c -- ALSA SoC platform-machine driver for QTi LPASS
6 */
7
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include <sound/pcm.h>
17 #include <sound/soc.h>
18
19 #include "lpass-lpaif-reg.h"
20 #include "lpass.h"
21
22 static struct snd_soc_dai_driver sc7180_lpass_cpu_dai_driver[] = {
23 {
24 .id = MI2S_PRIMARY,
25 .name = "Primary MI2S",
26 .playback = {
27 .stream_name = "Primary Playback",
28 .formats = SNDRV_PCM_FMTBIT_S16,
29 .rates = SNDRV_PCM_RATE_48000,
30 .rate_min = 48000,
31 .rate_max = 48000,
32 .channels_min = 2,
33 .channels_max = 2,
34 },
35 .capture = {
36 .stream_name = "Primary Capture",
37 .formats = SNDRV_PCM_FMTBIT_S16,
38 .rates = SNDRV_PCM_RATE_48000,
39 .rate_min = 48000,
40 .rate_max = 48000,
41 .channels_min = 2,
42 .channels_max = 2,
43 },
44 .probe = &asoc_qcom_lpass_cpu_dai_probe,
45 .ops = &asoc_qcom_lpass_cpu_dai_ops,
46 }, {
47 .id = MI2S_SECONDARY,
48 .name = "Secondary MI2S",
49 .playback = {
50 .stream_name = "Secondary Playback",
51 .formats = SNDRV_PCM_FMTBIT_S16,
52 .rates = SNDRV_PCM_RATE_48000,
53 .rate_min = 48000,
54 .rate_max = 48000,
55 .channels_min = 2,
56 .channels_max = 2,
57 },
58 .probe = &asoc_qcom_lpass_cpu_dai_probe,
59 .ops = &asoc_qcom_lpass_cpu_dai_ops,
60 }, {
61 .id = LPASS_DP_RX,
62 .name = "Hdmi",
63 .playback = {
64 .stream_name = "Hdmi Playback",
65 .formats = SNDRV_PCM_FMTBIT_S24,
66 .rates = SNDRV_PCM_RATE_48000,
67 .rate_min = 48000,
68 .rate_max = 48000,
69 .channels_min = 2,
70 .channels_max = 2,
71 },
72 .ops = &asoc_qcom_lpass_hdmi_dai_ops,
73 },
74 };
75
sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata, int direction, unsigned int dai_id)76 static int sc7180_lpass_alloc_dma_channel(struct lpass_data *drvdata,
77 int direction, unsigned int dai_id)
78 {
79 struct lpass_variant *v = drvdata->variant;
80 int chan = 0;
81
82 if (dai_id == LPASS_DP_RX) {
83 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
84 chan = find_first_zero_bit(&drvdata->hdmi_dma_ch_bit_map,
85 v->hdmi_rdma_channels);
86
87 if (chan >= v->hdmi_rdma_channels)
88 return -EBUSY;
89 }
90 set_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
91 } else {
92 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
93 chan = find_first_zero_bit(&drvdata->dma_ch_bit_map,
94 v->rdma_channels);
95
96 if (chan >= v->rdma_channels)
97 return -EBUSY;
98 } else {
99 chan = find_next_zero_bit(&drvdata->dma_ch_bit_map,
100 v->wrdma_channel_start +
101 v->wrdma_channels,
102 v->wrdma_channel_start);
103
104 if (chan >= v->wrdma_channel_start + v->wrdma_channels)
105 return -EBUSY;
106 }
107
108 set_bit(chan, &drvdata->dma_ch_bit_map);
109 }
110 return chan;
111 }
112
sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)113 static int sc7180_lpass_free_dma_channel(struct lpass_data *drvdata, int chan, unsigned int dai_id)
114 {
115 if (dai_id == LPASS_DP_RX)
116 clear_bit(chan, &drvdata->hdmi_dma_ch_bit_map);
117 else
118 clear_bit(chan, &drvdata->dma_ch_bit_map);
119
120 return 0;
121 }
122
sc7180_lpass_init(struct platform_device *pdev)123 static int sc7180_lpass_init(struct platform_device *pdev)
124 {
125 struct lpass_data *drvdata = platform_get_drvdata(pdev);
126 struct lpass_variant *variant = drvdata->variant;
127 struct device *dev = &pdev->dev;
128 int ret, i;
129
130 drvdata->clks = devm_kcalloc(dev, variant->num_clks,
131 sizeof(*drvdata->clks), GFP_KERNEL);
132 if (!drvdata->clks)
133 return -ENOMEM;
134
135 drvdata->num_clks = variant->num_clks;
136
137 for (i = 0; i < drvdata->num_clks; i++)
138 drvdata->clks[i].id = variant->clk_name[i];
139
140 ret = devm_clk_bulk_get(dev, drvdata->num_clks, drvdata->clks);
141 if (ret) {
142 dev_err(dev, "Failed to get clocks %d\n", ret);
143 return ret;
144 }
145
146 ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks);
147 if (ret) {
148 dev_err(dev, "sc7180 clk_enable failed\n");
149 return ret;
150 }
151
152 return 0;
153 }
154
sc7180_lpass_exit(struct platform_device *pdev)155 static int sc7180_lpass_exit(struct platform_device *pdev)
156 {
157 struct lpass_data *drvdata = platform_get_drvdata(pdev);
158
159 clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks);
160
161 return 0;
162 }
163
164 static struct lpass_variant sc7180_data = {
165 .i2sctrl_reg_base = 0x1000,
166 .i2sctrl_reg_stride = 0x1000,
167 .i2s_ports = 3,
168 .irq_reg_base = 0x9000,
169 .irq_reg_stride = 0x1000,
170 .irq_ports = 3,
171 .rdma_reg_base = 0xC000,
172 .rdma_reg_stride = 0x1000,
173 .rdma_channels = 5,
174 .hdmi_rdma_reg_base = 0x64000,
175 .hdmi_rdma_reg_stride = 0x1000,
176 .hdmi_rdma_channels = 4,
177 .dmactl_audif_start = 1,
178 .wrdma_reg_base = 0x18000,
179 .wrdma_reg_stride = 0x1000,
180 .wrdma_channel_start = 5,
181 .wrdma_channels = 4,
182
183 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
184 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
185 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
186 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
187 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
188 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
189 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
190 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
191 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
192
193 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
194 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
195 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
196 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
197 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
198 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
199
200 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
201 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
202 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
203 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
204 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
205 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
206
207 .hdmi_tx_ctl_addr = 0x1000,
208 .hdmi_legacy_addr = 0x1008,
209 .hdmi_vbit_addr = 0x610c0,
210 .hdmi_ch_lsb_addr = 0x61048,
211 .hdmi_ch_msb_addr = 0x6104c,
212 .ch_stride = 0x8,
213 .hdmi_parity_addr = 0x61034,
214 .hdmi_dmactl_addr = 0x61038,
215 .hdmi_dma_stride = 0x4,
216 .hdmi_DP_addr = 0x610c8,
217 .hdmi_sstream_addr = 0x6101c,
218 .hdmi_irq_reg_base = 0x63000,
219 .hdmi_irq_ports = 1,
220
221 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
222 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
223 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
224 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
225 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
226 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
227 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
228 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
229
230 .sstream_en = REG_FIELD(0x6101c, 0, 0),
231 .dma_sel = REG_FIELD(0x6101c, 1, 2),
232 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
233 .layout = REG_FIELD(0x6101c, 4, 4),
234 .layout_sp = REG_FIELD(0x6101c, 5, 8),
235 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
236 .dp_audio = REG_FIELD(0x6101c, 11, 11),
237 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
238 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
239
240 .mute = REG_FIELD(0x610c8, 0, 0),
241 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
242 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
243 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
244 .frequency = REG_FIELD(0x610c8, 16, 21),
245 .mst_index = REG_FIELD(0x610c8, 28, 29),
246 .dptx_index = REG_FIELD(0x610c8, 30, 31),
247
248 .soft_reset = REG_FIELD(0x1000, 31, 31),
249 .force_reset = REG_FIELD(0x1000, 30, 30),
250
251 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
252 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
253 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
254 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
255
256 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
257 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
258
259 .legacy_en = REG_FIELD(0x1008, 0, 0),
260 .calc_en = REG_FIELD(0x61034, 0, 0),
261 .lsb_bits = REG_FIELD(0x61048, 0, 31),
262 .msb_bits = REG_FIELD(0x6104c, 0, 31),
263
264
265 .clk_name = (const char*[]) {
266 "pcnoc-sway-clk",
267 "audio-core",
268 "pcnoc-mport-clk",
269 },
270 .num_clks = 3,
271 .dai_driver = sc7180_lpass_cpu_dai_driver,
272 .num_dai = ARRAY_SIZE(sc7180_lpass_cpu_dai_driver),
273 .dai_osr_clk_names = (const char *[]) {
274 "mclk0",
275 "null",
276 },
277 .dai_bit_clk_names = (const char *[]) {
278 "mi2s-bit-clk0",
279 "mi2s-bit-clk1",
280 },
281 .init = sc7180_lpass_init,
282 .exit = sc7180_lpass_exit,
283 .alloc_dma_channel = sc7180_lpass_alloc_dma_channel,
284 .free_dma_channel = sc7180_lpass_free_dma_channel,
285 };
286
287 static const struct of_device_id sc7180_lpass_cpu_device_id[] = {
288 {.compatible = "qcom,sc7180-lpass-cpu", .data = &sc7180_data},
289 {}
290 };
291 MODULE_DEVICE_TABLE(of, sc7180_lpass_cpu_device_id);
292
293 static struct platform_driver sc7180_lpass_cpu_platform_driver = {
294 .driver = {
295 .name = "sc7180-lpass-cpu",
296 .of_match_table = of_match_ptr(sc7180_lpass_cpu_device_id),
297 },
298 .probe = asoc_qcom_lpass_cpu_platform_probe,
299 .remove = asoc_qcom_lpass_cpu_platform_remove,
300 };
301
302 module_platform_driver(sc7180_lpass_cpu_platform_driver);
303
304 MODULE_DESCRIPTION("SC7180 LPASS CPU DRIVER");
305 MODULE_LICENSE("GPL v2");
306