1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 * Copyright (C) 2006, 2007 Maciej W. Rozycki
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15 #include <linux/bitrev.h>
16 #include <linux/compiler.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/errno.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/selection.h>
28 #include <linux/string.h>
29 #include <linux/tc.h>
30
31 #include <asm/io.h>
32
33 #include <video/tgafb.h>
34
35 #ifdef CONFIG_TC
36 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
37 #else
38 #define TGA_BUS_TC(dev) 0
39 #endif
40
41 /*
42 * Local functions.
43 */
44
45 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
46 static int tgafb_set_par(struct fb_info *);
47 static void tgafb_set_pll(struct tga_par *, int);
48 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
49 unsigned, struct fb_info *);
50 static int tgafb_blank(int, struct fb_info *);
51 static void tgafb_init_fix(struct fb_info *);
52
53 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
54 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
55 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
56 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
57
58 static int tgafb_register(struct device *dev);
59 static void tgafb_unregister(struct device *dev);
60
61 static const char *mode_option;
62 static const char *mode_option_pci = "640x480@60";
63 static const char *mode_option_tc = "1280x1024@72";
64
65
66 static struct pci_driver tgafb_pci_driver;
67 static struct tc_driver tgafb_tc_driver;
68
69 /*
70 * Frame buffer operations
71 */
72
73 static const struct fb_ops tgafb_ops = {
74 .owner = THIS_MODULE,
75 .fb_check_var = tgafb_check_var,
76 .fb_set_par = tgafb_set_par,
77 .fb_setcolreg = tgafb_setcolreg,
78 .fb_blank = tgafb_blank,
79 .fb_pan_display = tgafb_pan_display,
80 .fb_fillrect = tgafb_fillrect,
81 .fb_copyarea = tgafb_copyarea,
82 .fb_imageblit = tgafb_imageblit,
83 };
84
85
86 #ifdef CONFIG_PCI
87 /*
88 * PCI registration operations
89 */
90 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
91 static void tgafb_pci_unregister(struct pci_dev *);
92
93 static struct pci_device_id const tgafb_pci_table[] = {
94 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
95 { }
96 };
97 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
98
99 static struct pci_driver tgafb_pci_driver = {
100 .name = "tgafb",
101 .id_table = tgafb_pci_table,
102 .probe = tgafb_pci_register,
103 .remove = tgafb_pci_unregister,
104 };
105
tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)106 static int tgafb_pci_register(struct pci_dev *pdev,
107 const struct pci_device_id *ent)
108 {
109 return tgafb_register(&pdev->dev);
110 }
111
tgafb_pci_unregister(struct pci_dev *pdev)112 static void tgafb_pci_unregister(struct pci_dev *pdev)
113 {
114 tgafb_unregister(&pdev->dev);
115 }
116 #endif /* CONFIG_PCI */
117
118 #ifdef CONFIG_TC
119 /*
120 * TC registration operations
121 */
122 static int tgafb_tc_register(struct device *);
123 static int tgafb_tc_unregister(struct device *);
124
125 static struct tc_device_id const tgafb_tc_table[] = {
126 { "DEC ", "PMAGD-AA" },
127 { "DEC ", "PMAGD " },
128 { }
129 };
130 MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
131
132 static struct tc_driver tgafb_tc_driver = {
133 .id_table = tgafb_tc_table,
134 .driver = {
135 .name = "tgafb",
136 .bus = &tc_bus_type,
137 .probe = tgafb_tc_register,
138 .remove = tgafb_tc_unregister,
139 },
140 };
141
tgafb_tc_register(struct device *dev)142 static int tgafb_tc_register(struct device *dev)
143 {
144 int status = tgafb_register(dev);
145 if (!status)
146 get_device(dev);
147 return status;
148 }
149
tgafb_tc_unregister(struct device *dev)150 static int tgafb_tc_unregister(struct device *dev)
151 {
152 put_device(dev);
153 tgafb_unregister(dev);
154 return 0;
155 }
156 #endif /* CONFIG_TC */
157
158
159 /**
160 * tgafb_check_var - Optional function. Validates a var passed in.
161 * @var: frame buffer variable screen structure
162 * @info: frame buffer structure that represents a single frame buffer
163 */
164 static int
tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)165 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
166 {
167 struct tga_par *par = (struct tga_par *)info->par;
168
169 if (!var->pixclock)
170 return -EINVAL;
171
172 if (par->tga_type == TGA_TYPE_8PLANE) {
173 if (var->bits_per_pixel != 8)
174 return -EINVAL;
175 } else {
176 if (var->bits_per_pixel != 32)
177 return -EINVAL;
178 }
179 var->red.length = var->green.length = var->blue.length = 8;
180 if (var->bits_per_pixel == 32) {
181 var->red.offset = 16;
182 var->green.offset = 8;
183 var->blue.offset = 0;
184 }
185
186 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
187 return -EINVAL;
188 if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len)
189 return -EINVAL;
190 if (var->nonstd)
191 return -EINVAL;
192 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
193 return -EINVAL;
194 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
195 return -EINVAL;
196
197 /* Some of the acceleration routines assume the line width is
198 a multiple of 8 bytes. */
199 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8)
200 return -EINVAL;
201
202 return 0;
203 }
204
205 /**
206 * tgafb_set_par - Optional function. Alters the hardware state.
207 * @info: frame buffer structure that represents a single frame buffer
208 */
209 static int
tgafb_set_par(struct fb_info *info)210 tgafb_set_par(struct fb_info *info)
211 {
212 static unsigned int const deep_presets[4] = {
213 0x00004000,
214 0x0000440d,
215 0xffffffff,
216 0x0000441d
217 };
218 static unsigned int const rasterop_presets[4] = {
219 0x00000003,
220 0x00000303,
221 0xffffffff,
222 0x00000303
223 };
224 static unsigned int const mode_presets[4] = {
225 0x00000000,
226 0x00000300,
227 0xffffffff,
228 0x00000300
229 };
230 static unsigned int const base_addr_presets[4] = {
231 0x00000000,
232 0x00000001,
233 0xffffffff,
234 0x00000001
235 };
236
237 struct tga_par *par = (struct tga_par *) info->par;
238 int tga_bus_pci = dev_is_pci(par->dev);
239 int tga_bus_tc = TGA_BUS_TC(par->dev);
240 u32 htimings, vtimings, pll_freq;
241 u8 tga_type;
242 int i;
243
244 /* Encode video timings. */
245 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
246 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
247 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
248 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
249 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
250 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
251 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
252 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
253 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
254
255 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
256 htimings |= TGA_HORIZ_POLARITY;
257 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
258 vtimings |= TGA_VERT_POLARITY;
259
260 par->htimings = htimings;
261 par->vtimings = vtimings;
262
263 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
264
265 /* Store other useful values in par. */
266 par->xres = info->var.xres;
267 par->yres = info->var.yres;
268 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
269 par->bits_per_pixel = info->var.bits_per_pixel;
270 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
271
272 tga_type = par->tga_type;
273
274 /* First, disable video. */
275 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
276
277 /* Write the DEEP register. */
278 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
279 continue;
280 mb();
281 TGA_WRITE_REG(par, deep_presets[tga_type] |
282 (par->sync_on_green ? 0x0 : 0x00010000),
283 TGA_DEEP_REG);
284 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
285 continue;
286 mb();
287
288 /* Write some more registers. */
289 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
290 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
291 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
292
293 /* Calculate & write the PLL. */
294 tgafb_set_pll(par, pll_freq);
295
296 /* Write some more registers. */
297 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
298 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
299
300 /* Init video timing regs. */
301 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
302 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
303
304 /* Initialise RAMDAC. */
305 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
306
307 /* Init BT485 RAMDAC registers. */
308 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
309 BT485_CMD_0);
310 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
311 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
312 BT485_WRITE(par, 0x40, BT485_CMD_1);
313 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
314 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
315
316 /* Fill palette registers. */
317 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
318 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
319
320 for (i = 0; i < 256 * 3; i += 4) {
321 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
322 TGA_RAMDAC_REG);
323 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
324 TGA_RAMDAC_REG);
325 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
326 TGA_RAMDAC_REG);
327 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
328 TGA_RAMDAC_REG);
329 }
330
331 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
332
333 /* Init BT459 RAMDAC registers. */
334 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
335 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
336 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
337 (par->sync_on_green ? 0xc0 : 0x40));
338
339 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
340
341 /* Fill the palette. */
342 BT459_LOAD_ADDR(par, 0x0000);
343 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
344
345 for (i = 0; i < 256 * 3; i += 4) {
346 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
347 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
348 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
349 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
350 }
351
352 } else { /* 24-plane or 24plusZ */
353
354 /* Init BT463 RAMDAC registers. */
355 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
356 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
357 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
358 (par->sync_on_green ? 0xc0 : 0x40));
359
360 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
361 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
362 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
363 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
364
365 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
366 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
367 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
368 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
369
370 /* Fill the palette. */
371 BT463_LOAD_ADDR(par, 0x0000);
372 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
373
374 #ifdef CONFIG_HW_CONSOLE
375 for (i = 0; i < 16; i++) {
376 int j = color_table[i];
377
378 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
379 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
380 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
381 }
382 for (i = 0; i < 512 * 3; i += 4) {
383 #else
384 for (i = 0; i < 528 * 3; i += 4) {
385 #endif
386 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
387 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
388 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
389 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
390 }
391
392 /* Fill window type table after start of vertical retrace. */
393 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
394 continue;
395 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
396 mb();
397 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
398 continue;
399 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
400
401 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
402 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
403
404 for (i = 0; i < 16; i++) {
405 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
406 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
407 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
408 }
409
410 }
411
412 /* Finally, enable video scan (and pray for the monitor... :-) */
413 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
414
415 return 0;
416 }
417
418 #define DIFFCHECK(X) \
419 do { \
420 if (m <= 0x3f) { \
421 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
422 if (delta < 0) \
423 delta = -delta; \
424 if (delta < min_diff) \
425 min_diff = delta, vm = m, va = a, vr = r; \
426 } \
427 } while (0)
428
429 static void
430 tgafb_set_pll(struct tga_par *par, int f)
431 {
432 int n, shift, base, min_diff, target;
433 int r,a,m,vm = 34, va = 1, vr = 30;
434
435 for (r = 0 ; r < 12 ; r++)
436 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
437
438 if (f > TGA_PLL_MAX_FREQ)
439 f = TGA_PLL_MAX_FREQ;
440
441 if (f >= TGA_PLL_MAX_FREQ / 2)
442 shift = 0;
443 else if (f >= TGA_PLL_MAX_FREQ / 4)
444 shift = 1;
445 else
446 shift = 2;
447
448 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
449 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
450
451 for (r = 0 ; r < 10 ; r++)
452 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
453
454 if (f <= 120000) {
455 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
457 }
458 else if (f <= 200000) {
459 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
460 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
461 }
462 else {
463 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
464 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
465 }
466
467 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
468 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
469 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
470 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
472 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
473
474 target = (f << shift) / TGA_PLL_BASE_FREQ;
475 min_diff = TGA_PLL_MAX_FREQ;
476
477 r = 7 / target;
478 if (!r) r = 1;
479
480 base = target * r;
481 while (base < 449) {
482 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
483 m = ((n + 3) / 7) - 1;
484 a = 0;
485 DIFFCHECK((m + 1) * 7);
486 m++;
487 DIFFCHECK((m + 1) * 7);
488 m = (n / 6) - 1;
489 if ((a = n % 6))
490 DIFFCHECK(n);
491 }
492 r++;
493 base += target;
494 }
495
496 vr--;
497
498 for (r = 0; r < 8; r++)
499 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
500 for (r = 0; r < 8 ; r++)
501 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
502 for (r = 0; r < 7 ; r++)
503 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
504 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
505 }
506
507
508 /**
509 * tgafb_setcolreg - Optional function. Sets a color register.
510 * @regno: boolean, 0 copy local, 1 get_user() function
511 * @red: frame buffer colormap structure
512 * @green: The green value which can be up to 16 bits wide
513 * @blue: The blue value which can be up to 16 bits wide.
514 * @transp: If supported the alpha value which can be up to 16 bits wide.
515 * @info: frame buffer info structure
516 */
517 static int
518 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
519 unsigned transp, struct fb_info *info)
520 {
521 struct tga_par *par = (struct tga_par *) info->par;
522 int tga_bus_pci = dev_is_pci(par->dev);
523 int tga_bus_tc = TGA_BUS_TC(par->dev);
524
525 if (regno > 255)
526 return 1;
527 red >>= 8;
528 green >>= 8;
529 blue >>= 8;
530
531 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
532 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
533 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
534 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
535 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
536 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
537 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
538 BT459_LOAD_ADDR(par, regno);
539 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
540 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
541 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
542 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
543 } else {
544 if (regno < 16) {
545 u32 value = (regno << 16) | (regno << 8) | regno;
546 ((u32 *)info->pseudo_palette)[regno] = value;
547 }
548 BT463_LOAD_ADDR(par, regno);
549 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
550 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
551 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
552 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
553 }
554
555 return 0;
556 }
557
558
559 /**
560 * tgafb_blank - Optional function. Blanks the display.
561 * @blank_mode: the blank mode we want.
562 * @info: frame buffer structure that represents a single frame buffer
563 */
564 static int
565 tgafb_blank(int blank, struct fb_info *info)
566 {
567 struct tga_par *par = (struct tga_par *) info->par;
568 u32 vhcr, vvcr, vvvr;
569 unsigned long flags;
570
571 local_irq_save(flags);
572
573 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
574 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
575 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
576 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
577
578 switch (blank) {
579 case FB_BLANK_UNBLANK: /* Unblanking */
580 if (par->vesa_blanked) {
581 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
582 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
583 par->vesa_blanked = 0;
584 }
585 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
586 break;
587
588 case FB_BLANK_NORMAL: /* Normal blanking */
589 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
590 TGA_VALID_REG);
591 break;
592
593 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
594 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
595 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
596 par->vesa_blanked = 1;
597 break;
598
599 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
600 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
601 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
602 par->vesa_blanked = 1;
603 break;
604
605 case FB_BLANK_POWERDOWN: /* Poweroff */
606 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
607 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
608 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
609 par->vesa_blanked = 1;
610 break;
611 }
612
613 local_irq_restore(flags);
614 return 0;
615 }
616
617
618 /*
619 * Acceleration.
620 */
621
622 static void
623 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
624 {
625 struct tga_par *par = (struct tga_par *) info->par;
626 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
627 unsigned long rincr, line_length, shift, pos, is8bpp;
628 unsigned long i, j;
629 const unsigned char *data;
630 void __iomem *regs_base;
631 void __iomem *fb_base;
632
633 is8bpp = info->var.bits_per_pixel == 8;
634
635 dx = image->dx;
636 dy = image->dy;
637 width = image->width;
638 height = image->height;
639 vxres = info->var.xres_virtual;
640 vyres = info->var.yres_virtual;
641 line_length = info->fix.line_length;
642 rincr = (width + 7) / 8;
643
644 /* A shift below cannot cope with. */
645 if (unlikely(width == 0))
646 return;
647 /* Crop the image to the screen. */
648 if (dx > vxres || dy > vyres)
649 return;
650 if (dx + width > vxres)
651 width = vxres - dx;
652 if (dy + height > vyres)
653 height = vyres - dy;
654
655 regs_base = par->tga_regs_base;
656 fb_base = par->tga_fb_base;
657
658 /* Expand the color values to fill 32-bits. */
659 /* ??? Would be nice to notice colour changes elsewhere, so
660 that we can do this only when necessary. */
661 fgcolor = image->fg_color;
662 bgcolor = image->bg_color;
663 if (is8bpp) {
664 fgcolor |= fgcolor << 8;
665 fgcolor |= fgcolor << 16;
666 bgcolor |= bgcolor << 8;
667 bgcolor |= bgcolor << 16;
668 } else {
669 if (fgcolor < 16)
670 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
671 if (bgcolor < 16)
672 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
673 }
674 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
675 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
676
677 /* Acquire proper alignment; set up the PIXELMASK register
678 so that we only write the proper character cell. */
679 pos = dy * line_length;
680 if (is8bpp) {
681 pos += dx;
682 shift = pos & 3;
683 pos &= -4;
684 } else {
685 pos += dx * 4;
686 shift = (pos & 7) >> 2;
687 pos &= -8;
688 }
689
690 data = (const unsigned char *) image->data;
691
692 /* Enable opaque stipple mode. */
693 __raw_writel((is8bpp
694 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
695 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
696 regs_base + TGA_MODE_REG);
697
698 if (width + shift <= 32) {
699 unsigned long bwidth;
700
701 /* Handle common case of imaging a single character, in
702 a font less than or 32 pixels wide. */
703
704 /* Avoid a shift by 32; width > 0 implied. */
705 pixelmask = (2ul << (width - 1)) - 1;
706 pixelmask <<= shift;
707 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
708 wmb();
709
710 bwidth = (width + 7) / 8;
711
712 for (i = 0; i < height; ++i) {
713 u32 mask = 0;
714
715 /* The image data is bit big endian; we need
716 little endian. */
717 for (j = 0; j < bwidth; ++j)
718 mask |= bitrev8(data[j]) << (j * 8);
719
720 __raw_writel(mask << shift, fb_base + pos);
721
722 pos += line_length;
723 data += rincr;
724 }
725 wmb();
726 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
727 } else if (shift == 0) {
728 unsigned long pos0 = pos;
729 const unsigned char *data0 = data;
730 unsigned long bincr = (is8bpp ? 8 : 8*4);
731 unsigned long bwidth;
732
733 /* Handle another common case in which accel_putcs
734 generates a large bitmap, which happens to be aligned.
735 Allow the tail to be misaligned. This case is
736 interesting because we've not got to hold partial
737 bytes across the words being written. */
738
739 wmb();
740
741 bwidth = (width / 8) & -4;
742 for (i = 0; i < height; ++i) {
743 for (j = 0; j < bwidth; j += 4) {
744 u32 mask = 0;
745 mask |= bitrev8(data[j+0]) << (0 * 8);
746 mask |= bitrev8(data[j+1]) << (1 * 8);
747 mask |= bitrev8(data[j+2]) << (2 * 8);
748 mask |= bitrev8(data[j+3]) << (3 * 8);
749 __raw_writel(mask, fb_base + pos + j*bincr);
750 }
751 pos += line_length;
752 data += rincr;
753 }
754 wmb();
755
756 pixelmask = (1ul << (width & 31)) - 1;
757 if (pixelmask) {
758 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
759 wmb();
760
761 pos = pos0 + bwidth*bincr;
762 data = data0 + bwidth;
763 bwidth = ((width & 31) + 7) / 8;
764
765 for (i = 0; i < height; ++i) {
766 u32 mask = 0;
767 for (j = 0; j < bwidth; ++j)
768 mask |= bitrev8(data[j]) << (j * 8);
769 __raw_writel(mask, fb_base + pos);
770 pos += line_length;
771 data += rincr;
772 }
773 wmb();
774 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
775 }
776 } else {
777 unsigned long pos0 = pos;
778 const unsigned char *data0 = data;
779 unsigned long bincr = (is8bpp ? 8 : 8*4);
780 unsigned long bwidth;
781
782 /* Finally, handle the generic case of misaligned start.
783 Here we split the write into 16-bit spans. This allows
784 us to use only one pixel mask, instead of four as would
785 be required by writing 24-bit spans. */
786
787 pixelmask = 0xffff << shift;
788 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
789 wmb();
790
791 bwidth = (width / 8) & -2;
792 for (i = 0; i < height; ++i) {
793 for (j = 0; j < bwidth; j += 2) {
794 u32 mask = 0;
795 mask |= bitrev8(data[j+0]) << (0 * 8);
796 mask |= bitrev8(data[j+1]) << (1 * 8);
797 mask <<= shift;
798 __raw_writel(mask, fb_base + pos + j*bincr);
799 }
800 pos += line_length;
801 data += rincr;
802 }
803 wmb();
804
805 pixelmask = ((1ul << (width & 15)) - 1) << shift;
806 if (pixelmask) {
807 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
808 wmb();
809
810 pos = pos0 + bwidth*bincr;
811 data = data0 + bwidth;
812 bwidth = (width & 15) > 8;
813
814 for (i = 0; i < height; ++i) {
815 u32 mask = bitrev8(data[0]);
816 if (bwidth)
817 mask |= bitrev8(data[1]) << 8;
818 mask <<= shift;
819 __raw_writel(mask, fb_base + pos);
820 pos += line_length;
821 data += rincr;
822 }
823 wmb();
824 }
825 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
826 }
827
828 /* Disable opaque stipple mode. */
829 __raw_writel((is8bpp
830 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
831 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
832 regs_base + TGA_MODE_REG);
833 }
834
835 static void
836 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
837 {
838 struct tga_par *par = (struct tga_par *) info->par;
839 u32 color, dx, dy, width, height, vxres, vyres;
840 u32 *palette = ((u32 *)info->pseudo_palette);
841 unsigned long pos, line_length, i, j;
842 const unsigned char *data;
843 void __iomem *regs_base, *fb_base;
844
845 dx = image->dx;
846 dy = image->dy;
847 width = image->width;
848 height = image->height;
849 vxres = info->var.xres_virtual;
850 vyres = info->var.yres_virtual;
851 line_length = info->fix.line_length;
852
853 /* Crop the image to the screen. */
854 if (dx > vxres || dy > vyres)
855 return;
856 if (dx + width > vxres)
857 width = vxres - dx;
858 if (dy + height > vyres)
859 height = vyres - dy;
860
861 regs_base = par->tga_regs_base;
862 fb_base = par->tga_fb_base;
863
864 pos = dy * line_length + (dx * 4);
865 data = image->data;
866
867 /* Now copy the image, color_expanding via the palette. */
868 for (i = 0; i < height; i++) {
869 for (j = 0; j < width; j++) {
870 color = palette[*data++];
871 __raw_writel(color, fb_base + pos + j*4);
872 }
873 pos += line_length;
874 }
875 }
876
877 /**
878 * tgafb_imageblit - REQUIRED function. Can use generic routines if
879 * non acclerated hardware and packed pixel based.
880 * Copies a image from system memory to the screen.
881 *
882 * @info: frame buffer structure that represents a single frame buffer
883 * @image: structure defining the image.
884 */
885 static void
886 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
887 {
888 unsigned int is8bpp = info->var.bits_per_pixel == 8;
889
890 /* If a mono image, regardless of FB depth, go do it. */
891 if (image->depth == 1) {
892 tgafb_mono_imageblit(info, image);
893 return;
894 }
895
896 /* For copies that aren't pixel expansion, there's little we
897 can do better than the generic code. */
898 /* ??? There is a DMA write mode; I wonder if that could be
899 made to pull the data from the image buffer... */
900 if (image->depth == info->var.bits_per_pixel) {
901 cfb_imageblit(info, image);
902 return;
903 }
904
905 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
906 if (!is8bpp && image->depth == 8) {
907 tgafb_clut_imageblit(info, image);
908 return;
909 }
910
911 /* Silently return... */
912 }
913
914 /**
915 * tgafb_fillrect - REQUIRED function. Can use generic routines if
916 * non acclerated hardware and packed pixel based.
917 * Draws a rectangle on the screen.
918 *
919 * @info: frame buffer structure that represents a single frame buffer
920 * @rect: structure defining the rectagle and operation.
921 */
922 static void
923 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
924 {
925 struct tga_par *par = (struct tga_par *) info->par;
926 int is8bpp = info->var.bits_per_pixel == 8;
927 u32 dx, dy, width, height, vxres, vyres, color;
928 unsigned long pos, align, line_length, i, j;
929 void __iomem *regs_base;
930 void __iomem *fb_base;
931
932 dx = rect->dx;
933 dy = rect->dy;
934 width = rect->width;
935 height = rect->height;
936 vxres = info->var.xres_virtual;
937 vyres = info->var.yres_virtual;
938 line_length = info->fix.line_length;
939 regs_base = par->tga_regs_base;
940 fb_base = par->tga_fb_base;
941
942 /* Crop the rectangle to the screen. */
943 if (dx > vxres || dy > vyres || !width || !height)
944 return;
945 if (dx + width > vxres)
946 width = vxres - dx;
947 if (dy + height > vyres)
948 height = vyres - dy;
949
950 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
951
952 /* ??? We could implement ROP_XOR with opaque fill mode
953 and a RasterOp setting of GXxor, but as far as I can
954 tell, this mode is not actually used in the kernel.
955 Thus I am ignoring it for now. */
956 if (rect->rop != ROP_COPY) {
957 cfb_fillrect(info, rect);
958 return;
959 }
960
961 /* Expand the color value to fill 8 pixels. */
962 color = rect->color;
963 if (is8bpp) {
964 color |= color << 8;
965 color |= color << 16;
966 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
967 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
968 } else {
969 if (color < 16)
970 color = ((u32 *)info->pseudo_palette)[color];
971 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
972 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
973 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
974 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
975 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
976 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
977 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
978 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
979 }
980
981 /* The DATA register holds the fill mask for block fill mode.
982 Since we're not stippling, this is all ones. */
983 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
984
985 /* Enable block fill mode. */
986 __raw_writel((is8bpp
987 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
988 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
989 regs_base + TGA_MODE_REG);
990 wmb();
991
992 /* We can fill 2k pixels per operation. Notice blocks that fit
993 the width of the screen so that we can take advantage of this
994 and fill more than one line per write. */
995 if (width == line_length) {
996 width *= height;
997 height = 1;
998 }
999
1000 /* The write into the frame buffer must be aligned to 4 bytes,
1001 but we are allowed to encode the offset within the word in
1002 the data word written. */
1003 align = (pos & 3) << 16;
1004 pos &= -4;
1005
1006 if (width <= 2048) {
1007 u32 data;
1008
1009 data = (width - 1) | align;
1010
1011 for (i = 0; i < height; ++i) {
1012 __raw_writel(data, fb_base + pos);
1013 pos += line_length;
1014 }
1015 } else {
1016 unsigned long Bpp = (is8bpp ? 1 : 4);
1017 unsigned long nwidth = width & -2048;
1018 u32 fdata, ldata;
1019
1020 fdata = (2048 - 1) | align;
1021 ldata = ((width & 2047) - 1) | align;
1022
1023 for (i = 0; i < height; ++i) {
1024 for (j = 0; j < nwidth; j += 2048)
1025 __raw_writel(fdata, fb_base + pos + j*Bpp);
1026 if (j < width)
1027 __raw_writel(ldata, fb_base + pos + j*Bpp);
1028 pos += line_length;
1029 }
1030 }
1031 wmb();
1032
1033 /* Disable block fill mode. */
1034 __raw_writel((is8bpp
1035 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
1036 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
1037 regs_base + TGA_MODE_REG);
1038 }
1039
1040 /**
1041 * tgafb_copyarea - REQUIRED function. Can use generic routines if
1042 * non acclerated hardware and packed pixel based.
1043 * Copies on area of the screen to another area.
1044 *
1045 * @info: frame buffer structure that represents a single frame buffer
1046 * @area: structure defining the source and destination.
1047 */
1048
1049 /* Handle the special case of copying entire lines, e.g. during scrolling.
1050 We can avoid a lot of needless computation in this case. In the 8bpp
1051 case we need to use the COPY64 registers instead of mask writes into
1052 the frame buffer to achieve maximum performance. */
1053
1054 static inline void
1055 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
1056 u32 height, u32 width)
1057 {
1058 struct tga_par *par = (struct tga_par *) info->par;
1059 void __iomem *tga_regs = par->tga_regs_base;
1060 unsigned long dpos, spos, i, n64;
1061
1062 /* Set up the MODE and PIXELSHIFT registers. */
1063 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1064 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1065 wmb();
1066
1067 n64 = (height * width) / 64;
1068
1069 if (sy < dy) {
1070 spos = (sy + height) * width;
1071 dpos = (dy + height) * width;
1072
1073 for (i = 0; i < n64; ++i) {
1074 spos -= 64;
1075 dpos -= 64;
1076 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1077 wmb();
1078 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1079 wmb();
1080 }
1081 } else {
1082 spos = sy * width;
1083 dpos = dy * width;
1084
1085 for (i = 0; i < n64; ++i) {
1086 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1087 wmb();
1088 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1089 wmb();
1090 spos += 64;
1091 dpos += 64;
1092 }
1093 }
1094
1095 /* Reset the MODE register to normal. */
1096 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1097 }
1098
1099 static inline void
1100 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
1101 u32 height, u32 width)
1102 {
1103 struct tga_par *par = (struct tga_par *) info->par;
1104 void __iomem *tga_regs = par->tga_regs_base;
1105 void __iomem *tga_fb = par->tga_fb_base;
1106 void __iomem *src;
1107 void __iomem *dst;
1108 unsigned long i, n16;
1109
1110 /* Set up the MODE and PIXELSHIFT registers. */
1111 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1112 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1113 wmb();
1114
1115 n16 = (height * width) / 16;
1116
1117 if (sy < dy) {
1118 src = tga_fb + (sy + height) * width * 4;
1119 dst = tga_fb + (dy + height) * width * 4;
1120
1121 for (i = 0; i < n16; ++i) {
1122 src -= 64;
1123 dst -= 64;
1124 __raw_writel(0xffff, src);
1125 wmb();
1126 __raw_writel(0xffff, dst);
1127 wmb();
1128 }
1129 } else {
1130 src = tga_fb + sy * width * 4;
1131 dst = tga_fb + dy * width * 4;
1132
1133 for (i = 0; i < n16; ++i) {
1134 __raw_writel(0xffff, src);
1135 wmb();
1136 __raw_writel(0xffff, dst);
1137 wmb();
1138 src += 64;
1139 dst += 64;
1140 }
1141 }
1142
1143 /* Reset the MODE register to normal. */
1144 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1145 }
1146
1147 /* The (almost) general case of backward copy in 8bpp mode. */
1148 static inline void
1149 copyarea_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1150 u32 height, u32 width, u32 line_length,
1151 const struct fb_copyarea *area)
1152 {
1153 struct tga_par *par = (struct tga_par *) info->par;
1154 unsigned i, yincr;
1155 int depos, sepos, backward, last_step, step;
1156 u32 mask_last;
1157 unsigned n32;
1158 void __iomem *tga_regs;
1159 void __iomem *tga_fb;
1160
1161 /* Do acceleration only if we are aligned on 8 pixels */
1162 if ((dx | sx | width) & 7) {
1163 cfb_copyarea(info, area);
1164 return;
1165 }
1166
1167 yincr = line_length;
1168 if (dy > sy) {
1169 dy += height - 1;
1170 sy += height - 1;
1171 yincr = -yincr;
1172 }
1173 backward = dy == sy && dx > sx && dx < sx + width;
1174
1175 /* Compute the offsets and alignments in the frame buffer.
1176 More than anything else, these control how we do copies. */
1177 depos = dy * line_length + dx;
1178 sepos = sy * line_length + sx;
1179 if (backward) {
1180 depos += width;
1181 sepos += width;
1182 }
1183
1184 /* Next copy full words at a time. */
1185 n32 = width / 32;
1186 last_step = width % 32;
1187
1188 /* Finally copy the unaligned head of the span. */
1189 mask_last = (1ul << last_step) - 1;
1190
1191 if (!backward) {
1192 step = 32;
1193 last_step = 32;
1194 } else {
1195 step = -32;
1196 last_step = -last_step;
1197 sepos -= 32;
1198 depos -= 32;
1199 }
1200
1201 tga_regs = par->tga_regs_base;
1202 tga_fb = par->tga_fb_base;
1203
1204 /* Set up the MODE and PIXELSHIFT registers. */
1205 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1206 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1207 wmb();
1208
1209 for (i = 0; i < height; ++i) {
1210 unsigned long j;
1211 void __iomem *sfb;
1212 void __iomem *dfb;
1213
1214 sfb = tga_fb + sepos;
1215 dfb = tga_fb + depos;
1216
1217 for (j = 0; j < n32; j++) {
1218 if (j < 2 && j + 1 < n32 && !backward &&
1219 !(((unsigned long)sfb | (unsigned long)dfb) & 63)) {
1220 do {
1221 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1222 wmb();
1223 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1224 wmb();
1225 sfb += 64;
1226 dfb += 64;
1227 j += 2;
1228 } while (j + 1 < n32);
1229 j--;
1230 continue;
1231 }
1232 __raw_writel(0xffffffff, sfb);
1233 wmb();
1234 __raw_writel(0xffffffff, dfb);
1235 wmb();
1236 sfb += step;
1237 dfb += step;
1238 }
1239
1240 if (mask_last) {
1241 sfb += last_step - step;
1242 dfb += last_step - step;
1243 __raw_writel(mask_last, sfb);
1244 wmb();
1245 __raw_writel(mask_last, dfb);
1246 wmb();
1247 }
1248
1249 sepos += yincr;
1250 depos += yincr;
1251 }
1252
1253 /* Reset the MODE register to normal. */
1254 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1255 }
1256
1257 static void
1258 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1259 {
1260 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1261 unsigned long line_length, bpp;
1262
1263 dx = area->dx;
1264 dy = area->dy;
1265 width = area->width;
1266 height = area->height;
1267 sx = area->sx;
1268 sy = area->sy;
1269 vxres = info->var.xres_virtual;
1270 vyres = info->var.yres_virtual;
1271 line_length = info->fix.line_length;
1272
1273 /* The top left corners must be in the virtual screen. */
1274 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1275 return;
1276
1277 /* Clip the destination. */
1278 if (dx + width > vxres)
1279 width = vxres - dx;
1280 if (dy + height > vyres)
1281 height = vyres - dy;
1282
1283 /* The source must be completely inside the virtual screen. */
1284 if (sx + width > vxres || sy + height > vyres)
1285 return;
1286
1287 bpp = info->var.bits_per_pixel;
1288
1289 /* Detect copies of the entire line. */
1290 if (!(line_length & 63) && width * (bpp >> 3) == line_length) {
1291 if (bpp == 8)
1292 copyarea_line_8bpp(info, dy, sy, height, width);
1293 else
1294 copyarea_line_32bpp(info, dy, sy, height, width);
1295 }
1296
1297 /* ??? The documentation is unclear to me exactly how the pixelshift
1298 register works in 32bpp mode. Since I don't have hardware to test,
1299 give up for now and fall back on the generic routines. */
1300 else if (bpp == 32)
1301 cfb_copyarea(info, area);
1302
1303 else
1304 copyarea_8bpp(info, dx, dy, sx, sy, height,
1305 width, line_length, area);
1306 }
1307
1308
1309 /*
1310 * Initialisation
1311 */
1312
1313 static void
1314 tgafb_init_fix(struct fb_info *info)
1315 {
1316 struct tga_par *par = (struct tga_par *)info->par;
1317 int tga_bus_pci = dev_is_pci(par->dev);
1318 int tga_bus_tc = TGA_BUS_TC(par->dev);
1319 u8 tga_type = par->tga_type;
1320 const char *tga_type_name = NULL;
1321 unsigned memory_size;
1322
1323 switch (tga_type) {
1324 case TGA_TYPE_8PLANE:
1325 if (tga_bus_pci)
1326 tga_type_name = "Digital ZLXp-E1";
1327 if (tga_bus_tc)
1328 tga_type_name = "Digital ZLX-E1";
1329 memory_size = 2097152;
1330 break;
1331 case TGA_TYPE_24PLANE:
1332 if (tga_bus_pci)
1333 tga_type_name = "Digital ZLXp-E2";
1334 if (tga_bus_tc)
1335 tga_type_name = "Digital ZLX-E2";
1336 memory_size = 8388608;
1337 break;
1338 case TGA_TYPE_24PLUSZ:
1339 if (tga_bus_pci)
1340 tga_type_name = "Digital ZLXp-E3";
1341 if (tga_bus_tc)
1342 tga_type_name = "Digital ZLX-E3";
1343 memory_size = 16777216;
1344 break;
1345 }
1346 if (!tga_type_name) {
1347 tga_type_name = "Unknown";
1348 memory_size = 16777216;
1349 }
1350
1351 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1352
1353 info->fix.type = FB_TYPE_PACKED_PIXELS;
1354 info->fix.type_aux = 0;
1355 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1356 ? FB_VISUAL_PSEUDOCOLOR
1357 : FB_VISUAL_DIRECTCOLOR);
1358
1359 info->fix.smem_start = (size_t) par->tga_fb_base;
1360 info->fix.smem_len = memory_size;
1361 info->fix.mmio_start = (size_t) par->tga_regs_base;
1362 info->fix.mmio_len = 512;
1363
1364 info->fix.xpanstep = 0;
1365 info->fix.ypanstep = 0;
1366 info->fix.ywrapstep = 0;
1367
1368 info->fix.accel = FB_ACCEL_DEC_TGA;
1369
1370 /*
1371 * These are needed by fb_set_logo_truepalette(), so we
1372 * set them here for 24-plane cards.
1373 */
1374 if (tga_type != TGA_TYPE_8PLANE) {
1375 info->var.red.length = 8;
1376 info->var.green.length = 8;
1377 info->var.blue.length = 8;
1378 info->var.red.offset = 16;
1379 info->var.green.offset = 8;
1380 info->var.blue.offset = 0;
1381 }
1382 }
1383
1384 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1385 {
1386 /* We just use this to catch switches out of graphics mode. */
1387 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
1388 return 0;
1389 }
1390
1391 static int tgafb_register(struct device *dev)
1392 {
1393 static const struct fb_videomode modedb_tc = {
1394 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
1395 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
1396 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
1397 };
1398
1399 static unsigned int const fb_offset_presets[4] = {
1400 TGA_8PLANE_FB_OFFSET,
1401 TGA_24PLANE_FB_OFFSET,
1402 0xffffffff,
1403 TGA_24PLUSZ_FB_OFFSET
1404 };
1405
1406 const struct fb_videomode *modedb_tga = NULL;
1407 resource_size_t bar0_start = 0, bar0_len = 0;
1408 const char *mode_option_tga = NULL;
1409 int tga_bus_pci = dev_is_pci(dev);
1410 int tga_bus_tc = TGA_BUS_TC(dev);
1411 unsigned int modedbsize_tga = 0;
1412 void __iomem *mem_base;
1413 struct fb_info *info;
1414 struct tga_par *par;
1415 u8 tga_type;
1416 int ret = 0;
1417
1418 /* Enable device in PCI config. */
1419 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
1420 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1421 return -ENODEV;
1422 }
1423
1424 /* Allocate the fb and par structures. */
1425 info = framebuffer_alloc(sizeof(struct tga_par), dev);
1426 if (!info)
1427 return -ENOMEM;
1428
1429 par = info->par;
1430 dev_set_drvdata(dev, info);
1431
1432 /* Request the mem regions. */
1433 ret = -ENODEV;
1434 if (tga_bus_pci) {
1435 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1436 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1437 }
1438 if (tga_bus_tc) {
1439 bar0_start = to_tc_dev(dev)->resource.start;
1440 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1441 }
1442 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1443 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1444 goto err0;
1445 }
1446
1447 /* Map the framebuffer. */
1448 mem_base = ioremap(bar0_start, bar0_len);
1449 if (!mem_base) {
1450 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1451 goto err1;
1452 }
1453
1454 /* Grab info about the card. */
1455 tga_type = (readl(mem_base) >> 12) & 0x0f;
1456 par->dev = dev;
1457 par->tga_mem_base = mem_base;
1458 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1459 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1460 par->tga_type = tga_type;
1461 if (tga_bus_pci)
1462 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1463 if (tga_bus_tc)
1464 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1465
1466 /* Setup framebuffer. */
1467 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1468 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1469 info->fbops = &tgafb_ops;
1470 info->screen_base = par->tga_fb_base;
1471 info->pseudo_palette = par->palette;
1472
1473 /* This should give a reasonable default video mode. */
1474 if (tga_bus_pci) {
1475 mode_option_tga = mode_option_pci;
1476 }
1477 if (tga_bus_tc) {
1478 mode_option_tga = mode_option_tc;
1479 modedb_tga = &modedb_tc;
1480 modedbsize_tga = 1;
1481 }
1482
1483 tgafb_init_fix(info);
1484
1485 ret = fb_find_mode(&info->var, info,
1486 mode_option ? mode_option : mode_option_tga,
1487 modedb_tga, modedbsize_tga, NULL,
1488 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1489 if (ret == 0 || ret == 4) {
1490 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1491 ret = -EINVAL;
1492 goto err1;
1493 }
1494
1495 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1496 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1497 ret = -ENOMEM;
1498 goto err1;
1499 }
1500
1501 tgafb_set_par(info);
1502
1503 if (register_framebuffer(info) < 0) {
1504 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1505 ret = -EINVAL;
1506 goto err2;
1507 }
1508
1509 if (tga_bus_pci) {
1510 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1511 par->tga_chip_rev);
1512 pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
1513 to_pci_dev(dev)->bus->number,
1514 PCI_SLOT(to_pci_dev(dev)->devfn),
1515 PCI_FUNC(to_pci_dev(dev)->devfn));
1516 }
1517 if (tga_bus_tc)
1518 pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
1519 par->tga_chip_rev);
1520 fb_info(info, "%s frame buffer device at 0x%lx\n",
1521 info->fix.id, (long)bar0_start);
1522
1523 return 0;
1524
1525 err2:
1526 fb_dealloc_cmap(&info->cmap);
1527 err1:
1528 if (mem_base)
1529 iounmap(mem_base);
1530 release_mem_region(bar0_start, bar0_len);
1531 err0:
1532 framebuffer_release(info);
1533 return ret;
1534 }
1535
1536 static void tgafb_unregister(struct device *dev)
1537 {
1538 resource_size_t bar0_start = 0, bar0_len = 0;
1539 int tga_bus_pci = dev_is_pci(dev);
1540 int tga_bus_tc = TGA_BUS_TC(dev);
1541 struct fb_info *info = NULL;
1542 struct tga_par *par;
1543
1544 info = dev_get_drvdata(dev);
1545 if (!info)
1546 return;
1547
1548 par = info->par;
1549 unregister_framebuffer(info);
1550 fb_dealloc_cmap(&info->cmap);
1551 iounmap(par->tga_mem_base);
1552 if (tga_bus_pci) {
1553 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1554 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1555 }
1556 if (tga_bus_tc) {
1557 bar0_start = to_tc_dev(dev)->resource.start;
1558 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1559 }
1560 release_mem_region(bar0_start, bar0_len);
1561 framebuffer_release(info);
1562 }
1563
1564 static void tgafb_exit(void)
1565 {
1566 tc_unregister_driver(&tgafb_tc_driver);
1567 pci_unregister_driver(&tgafb_pci_driver);
1568 }
1569
1570 #ifndef MODULE
1571 static int tgafb_setup(char *arg)
1572 {
1573 char *this_opt;
1574
1575 if (arg && *arg) {
1576 while ((this_opt = strsep(&arg, ","))) {
1577 if (!*this_opt)
1578 continue;
1579 if (!strncmp(this_opt, "mode:", 5))
1580 mode_option = this_opt+5;
1581 else
1582 printk(KERN_ERR
1583 "tgafb: unknown parameter %s\n",
1584 this_opt);
1585 }
1586 }
1587
1588 return 0;
1589 }
1590 #endif /* !MODULE */
1591
1592 static int tgafb_init(void)
1593 {
1594 int status;
1595 #ifndef MODULE
1596 char *option = NULL;
1597
1598 if (fb_get_options("tgafb", &option))
1599 return -ENODEV;
1600 tgafb_setup(option);
1601 #endif
1602 status = pci_register_driver(&tgafb_pci_driver);
1603 if (!status)
1604 status = tc_register_driver(&tgafb_tc_driver);
1605 return status;
1606 }
1607
1608 /*
1609 * Modularisation
1610 */
1611
1612 module_init(tgafb_init);
1613 module_exit(tgafb_exit);
1614
1615 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
1616 MODULE_LICENSE("GPL");
1617