1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 *
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 *
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
10 */
11
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
24 #include <linux/of.h>
25 #include <linux/of_irq.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/types.h>
37 #include <dt-bindings/pinctrl/bcm2835.h>
38
39 #define MODULE_NAME "pinctrl-bcm2835"
40 #define BCM2835_NUM_GPIOS 54
41 #define BCM2711_NUM_GPIOS 58
42 #define BCM2835_NUM_BANKS 2
43 #define BCM2835_NUM_IRQS 3
44
45 /* GPIO register offsets */
46 #define GPFSEL0 0x0 /* Function Select */
47 #define GPSET0 0x1c /* Pin Output Set */
48 #define GPCLR0 0x28 /* Pin Output Clear */
49 #define GPLEV0 0x34 /* Pin Level */
50 #define GPEDS0 0x40 /* Pin Event Detect Status */
51 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
52 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
53 #define GPHEN0 0x64 /* Pin High Detect Enable */
54 #define GPLEN0 0x70 /* Pin Low Detect Enable */
55 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
56 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
57 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
58 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
59 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
60
61 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p) (((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p) ((p) / 32)
64 #define GPIO_REG_SHIFT(p) ((p) % 32)
65
66 #define PUD_2711_MASK 0x3
67 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
68 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
69
70 /* argument: bcm2835_pinconf_pull */
71 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
72
73 #define BCM2711_PULL_NONE 0x0
74 #define BCM2711_PULL_UP 0x1
75 #define BCM2711_PULL_DOWN 0x2
76
77 struct bcm2835_pinctrl {
78 struct device *dev;
79 void __iomem *base;
80 int *wake_irq;
81
82 /* note: locking assumes each bank will have its own unsigned long */
83 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
84 unsigned int irq_type[BCM2711_NUM_GPIOS];
85
86 struct pinctrl_dev *pctl_dev;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_desc pctl_desc;
89 struct pinctrl_gpio_range gpio_range;
90
91 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
92 };
93
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
97 BCM2835_GPIO_PIN(0),
98 BCM2835_GPIO_PIN(1),
99 BCM2835_GPIO_PIN(2),
100 BCM2835_GPIO_PIN(3),
101 BCM2835_GPIO_PIN(4),
102 BCM2835_GPIO_PIN(5),
103 BCM2835_GPIO_PIN(6),
104 BCM2835_GPIO_PIN(7),
105 BCM2835_GPIO_PIN(8),
106 BCM2835_GPIO_PIN(9),
107 BCM2835_GPIO_PIN(10),
108 BCM2835_GPIO_PIN(11),
109 BCM2835_GPIO_PIN(12),
110 BCM2835_GPIO_PIN(13),
111 BCM2835_GPIO_PIN(14),
112 BCM2835_GPIO_PIN(15),
113 BCM2835_GPIO_PIN(16),
114 BCM2835_GPIO_PIN(17),
115 BCM2835_GPIO_PIN(18),
116 BCM2835_GPIO_PIN(19),
117 BCM2835_GPIO_PIN(20),
118 BCM2835_GPIO_PIN(21),
119 BCM2835_GPIO_PIN(22),
120 BCM2835_GPIO_PIN(23),
121 BCM2835_GPIO_PIN(24),
122 BCM2835_GPIO_PIN(25),
123 BCM2835_GPIO_PIN(26),
124 BCM2835_GPIO_PIN(27),
125 BCM2835_GPIO_PIN(28),
126 BCM2835_GPIO_PIN(29),
127 BCM2835_GPIO_PIN(30),
128 BCM2835_GPIO_PIN(31),
129 BCM2835_GPIO_PIN(32),
130 BCM2835_GPIO_PIN(33),
131 BCM2835_GPIO_PIN(34),
132 BCM2835_GPIO_PIN(35),
133 BCM2835_GPIO_PIN(36),
134 BCM2835_GPIO_PIN(37),
135 BCM2835_GPIO_PIN(38),
136 BCM2835_GPIO_PIN(39),
137 BCM2835_GPIO_PIN(40),
138 BCM2835_GPIO_PIN(41),
139 BCM2835_GPIO_PIN(42),
140 BCM2835_GPIO_PIN(43),
141 BCM2835_GPIO_PIN(44),
142 BCM2835_GPIO_PIN(45),
143 BCM2835_GPIO_PIN(46),
144 BCM2835_GPIO_PIN(47),
145 BCM2835_GPIO_PIN(48),
146 BCM2835_GPIO_PIN(49),
147 BCM2835_GPIO_PIN(50),
148 BCM2835_GPIO_PIN(51),
149 BCM2835_GPIO_PIN(52),
150 BCM2835_GPIO_PIN(53),
151 BCM2835_GPIO_PIN(54),
152 BCM2835_GPIO_PIN(55),
153 BCM2835_GPIO_PIN(56),
154 BCM2835_GPIO_PIN(57),
155 };
156
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
159 "gpio0",
160 "gpio1",
161 "gpio2",
162 "gpio3",
163 "gpio4",
164 "gpio5",
165 "gpio6",
166 "gpio7",
167 "gpio8",
168 "gpio9",
169 "gpio10",
170 "gpio11",
171 "gpio12",
172 "gpio13",
173 "gpio14",
174 "gpio15",
175 "gpio16",
176 "gpio17",
177 "gpio18",
178 "gpio19",
179 "gpio20",
180 "gpio21",
181 "gpio22",
182 "gpio23",
183 "gpio24",
184 "gpio25",
185 "gpio26",
186 "gpio27",
187 "gpio28",
188 "gpio29",
189 "gpio30",
190 "gpio31",
191 "gpio32",
192 "gpio33",
193 "gpio34",
194 "gpio35",
195 "gpio36",
196 "gpio37",
197 "gpio38",
198 "gpio39",
199 "gpio40",
200 "gpio41",
201 "gpio42",
202 "gpio43",
203 "gpio44",
204 "gpio45",
205 "gpio46",
206 "gpio47",
207 "gpio48",
208 "gpio49",
209 "gpio50",
210 "gpio51",
211 "gpio52",
212 "gpio53",
213 "gpio54",
214 "gpio55",
215 "gpio56",
216 "gpio57",
217 };
218
219 enum bcm2835_fsel {
220 BCM2835_FSEL_COUNT = 8,
221 BCM2835_FSEL_MASK = 0x7,
222 };
223
224 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
225 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
226 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
227 [BCM2835_FSEL_ALT0] = "alt0",
228 [BCM2835_FSEL_ALT1] = "alt1",
229 [BCM2835_FSEL_ALT2] = "alt2",
230 [BCM2835_FSEL_ALT3] = "alt3",
231 [BCM2835_FSEL_ALT4] = "alt4",
232 [BCM2835_FSEL_ALT5] = "alt5",
233 };
234
235 static const char * const irq_type_names[] = {
236 [IRQ_TYPE_NONE] = "none",
237 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
238 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
239 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
240 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
241 [IRQ_TYPE_LEVEL_LOW] = "level-low",
242 };
243
bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
245 {
246 return readl(pc->base + reg);
247 }
248
bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg, u32 val)249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
250 u32 val)
251 {
252 writel(val, pc->base + reg);
253 }
254
bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg, unsigned bit)255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
256 unsigned bit)
257 {
258 reg += GPIO_REG_OFFSET(bit) * 4;
259 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
260 }
261
262 /* note NOT a read/modify/write cycle */
bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc, unsigned reg, unsigned bit)263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
264 unsigned reg, unsigned bit)
265 {
266 reg += GPIO_REG_OFFSET(bit) * 4;
267 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
268 }
269
bcm2835_pinctrl_fsel_get( struct bcm2835_pinctrl *pc, unsigned pin)270 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
271 struct bcm2835_pinctrl *pc, unsigned pin)
272 {
273 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
274 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
275
276 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
277 bcm2835_functions[status]);
278
279 return status;
280 }
281
bcm2835_pinctrl_fsel_set( struct bcm2835_pinctrl *pc, unsigned pin, enum bcm2835_fsel fsel)282 static inline void bcm2835_pinctrl_fsel_set(
283 struct bcm2835_pinctrl *pc, unsigned pin,
284 enum bcm2835_fsel fsel)
285 {
286 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
287 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
288
289 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
290 bcm2835_functions[cur]);
291
292 if (cur == fsel)
293 return;
294
295 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
296 /* always transition through GPIO_IN */
297 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
299
300 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
301 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
302 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
303 }
304
305 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
306 val |= fsel << FSEL_SHIFT(pin);
307
308 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
309 bcm2835_functions[fsel]);
310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
311 }
312
bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)313 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
314 {
315 return pinctrl_gpio_direction_input(chip->base + offset);
316 }
317
bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)318 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
319 {
320 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
321
322 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
323 }
324
bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)325 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
326 {
327 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
329
330 /* Alternative function doesn't clearly provide a direction */
331 if (fsel > BCM2835_FSEL_GPIO_OUT)
332 return -EINVAL;
333
334 if (fsel == BCM2835_FSEL_GPIO_IN)
335 return GPIO_LINE_DIRECTION_IN;
336
337 return GPIO_LINE_DIRECTION_OUT;
338 }
339
bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)340 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
341 {
342 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
343
344 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
345 }
346
bcm2835_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)347 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
348 unsigned offset, int value)
349 {
350 bcm2835_gpio_set(chip, offset, value);
351 return pinctrl_gpio_direction_output(chip->base + offset);
352 }
353
bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc, struct device_node *np)354 static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
355 struct device_node *np)
356 {
357 struct pinctrl_dev *pctldev = of_pinctrl_get(np);
358
359 if (!pctldev)
360 return 0;
361
362 return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
363 gc->ngpio);
364 }
365
366 static const struct gpio_chip bcm2835_gpio_chip = {
367 .label = MODULE_NAME,
368 .owner = THIS_MODULE,
369 .request = gpiochip_generic_request,
370 .free = gpiochip_generic_free,
371 .direction_input = bcm2835_gpio_direction_input,
372 .direction_output = bcm2835_gpio_direction_output,
373 .get_direction = bcm2835_gpio_get_direction,
374 .get = bcm2835_gpio_get,
375 .set = bcm2835_gpio_set,
376 .set_config = gpiochip_generic_config,
377 .base = -1,
378 .ngpio = BCM2835_NUM_GPIOS,
379 .can_sleep = false,
380 .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
381 };
382
383 static const struct gpio_chip bcm2711_gpio_chip = {
384 .label = "pinctrl-bcm2711",
385 .owner = THIS_MODULE,
386 .request = gpiochip_generic_request,
387 .free = gpiochip_generic_free,
388 .direction_input = bcm2835_gpio_direction_input,
389 .direction_output = bcm2835_gpio_direction_output,
390 .get_direction = bcm2835_gpio_get_direction,
391 .get = bcm2835_gpio_get,
392 .set = bcm2835_gpio_set,
393 .set_config = gpiochip_generic_config,
394 .base = -1,
395 .ngpio = BCM2711_NUM_GPIOS,
396 .can_sleep = false,
397 .of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
398 };
399
bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, unsigned int bank, u32 mask)400 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
401 unsigned int bank, u32 mask)
402 {
403 unsigned long events;
404 unsigned offset;
405 unsigned gpio;
406
407 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
408 events &= mask;
409 events &= pc->enabled_irq_map[bank];
410 for_each_set_bit(offset, &events, 32) {
411 gpio = (32 * bank) + offset;
412 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
413 gpio));
414 }
415 }
416
bcm2835_gpio_irq_handler(struct irq_desc *desc)417 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
418 {
419 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
420 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
421 struct irq_chip *host_chip = irq_desc_get_chip(desc);
422 int irq = irq_desc_get_irq(desc);
423 int group;
424 int i;
425
426 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
427 if (chip->irq.parents[i] == irq) {
428 group = i;
429 break;
430 }
431 }
432 /* This should not happen, every IRQ has a bank */
433 if (i == BCM2835_NUM_IRQS)
434 BUG();
435
436 chained_irq_enter(host_chip, desc);
437
438 switch (group) {
439 case 0: /* IRQ0 covers GPIOs 0-27 */
440 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
441 break;
442 case 1: /* IRQ1 covers GPIOs 28-45 */
443 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
444 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
445 break;
446 case 2: /* IRQ2 covers GPIOs 46-57 */
447 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
448 break;
449 }
450
451 chained_irq_exit(host_chip, desc);
452 }
453
bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)454 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
455 {
456 return IRQ_HANDLED;
457 }
458
__bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, unsigned reg, unsigned offset, bool enable)459 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
460 unsigned reg, unsigned offset, bool enable)
461 {
462 u32 value;
463 reg += GPIO_REG_OFFSET(offset) * 4;
464 value = bcm2835_gpio_rd(pc, reg);
465 if (enable)
466 value |= BIT(GPIO_REG_SHIFT(offset));
467 else
468 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
469 bcm2835_gpio_wr(pc, reg, value);
470 }
471
472 /* fast path for IRQ handler */
bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, unsigned offset, bool enable)473 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
474 unsigned offset, bool enable)
475 {
476 switch (pc->irq_type[offset]) {
477 case IRQ_TYPE_EDGE_RISING:
478 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
479 break;
480
481 case IRQ_TYPE_EDGE_FALLING:
482 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
483 break;
484
485 case IRQ_TYPE_EDGE_BOTH:
486 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
487 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
488 break;
489
490 case IRQ_TYPE_LEVEL_HIGH:
491 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
492 break;
493
494 case IRQ_TYPE_LEVEL_LOW:
495 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
496 break;
497 }
498 }
499
bcm2835_gpio_irq_enable(struct irq_data *data)500 static void bcm2835_gpio_irq_enable(struct irq_data *data)
501 {
502 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
503 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
504 unsigned gpio = irqd_to_hwirq(data);
505 unsigned offset = GPIO_REG_SHIFT(gpio);
506 unsigned bank = GPIO_REG_OFFSET(gpio);
507 unsigned long flags;
508
509 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
510 set_bit(offset, &pc->enabled_irq_map[bank]);
511 bcm2835_gpio_irq_config(pc, gpio, true);
512 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
513 }
514
bcm2835_gpio_irq_disable(struct irq_data *data)515 static void bcm2835_gpio_irq_disable(struct irq_data *data)
516 {
517 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
518 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
519 unsigned gpio = irqd_to_hwirq(data);
520 unsigned offset = GPIO_REG_SHIFT(gpio);
521 unsigned bank = GPIO_REG_OFFSET(gpio);
522 unsigned long flags;
523
524 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
525 bcm2835_gpio_irq_config(pc, gpio, false);
526 /* Clear events that were latched prior to clearing event sources */
527 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
528 clear_bit(offset, &pc->enabled_irq_map[bank]);
529 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
530 }
531
__bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc, unsigned offset, unsigned int type)532 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
533 unsigned offset, unsigned int type)
534 {
535 switch (type) {
536 case IRQ_TYPE_NONE:
537 case IRQ_TYPE_EDGE_RISING:
538 case IRQ_TYPE_EDGE_FALLING:
539 case IRQ_TYPE_EDGE_BOTH:
540 case IRQ_TYPE_LEVEL_HIGH:
541 case IRQ_TYPE_LEVEL_LOW:
542 pc->irq_type[offset] = type;
543 break;
544
545 default:
546 return -EINVAL;
547 }
548 return 0;
549 }
550
551 /* slower path for reconfiguring IRQ type */
__bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc, unsigned offset, unsigned int type)552 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
553 unsigned offset, unsigned int type)
554 {
555 switch (type) {
556 case IRQ_TYPE_NONE:
557 if (pc->irq_type[offset] != type) {
558 bcm2835_gpio_irq_config(pc, offset, false);
559 pc->irq_type[offset] = type;
560 }
561 break;
562
563 case IRQ_TYPE_EDGE_RISING:
564 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
565 /* RISING already enabled, disable FALLING */
566 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
567 bcm2835_gpio_irq_config(pc, offset, false);
568 pc->irq_type[offset] = type;
569 } else if (pc->irq_type[offset] != type) {
570 bcm2835_gpio_irq_config(pc, offset, false);
571 pc->irq_type[offset] = type;
572 bcm2835_gpio_irq_config(pc, offset, true);
573 }
574 break;
575
576 case IRQ_TYPE_EDGE_FALLING:
577 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
578 /* FALLING already enabled, disable RISING */
579 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
580 bcm2835_gpio_irq_config(pc, offset, false);
581 pc->irq_type[offset] = type;
582 } else if (pc->irq_type[offset] != type) {
583 bcm2835_gpio_irq_config(pc, offset, false);
584 pc->irq_type[offset] = type;
585 bcm2835_gpio_irq_config(pc, offset, true);
586 }
587 break;
588
589 case IRQ_TYPE_EDGE_BOTH:
590 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
591 /* RISING already enabled, enable FALLING too */
592 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
593 bcm2835_gpio_irq_config(pc, offset, true);
594 pc->irq_type[offset] = type;
595 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
596 /* FALLING already enabled, enable RISING too */
597 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
598 bcm2835_gpio_irq_config(pc, offset, true);
599 pc->irq_type[offset] = type;
600 } else if (pc->irq_type[offset] != type) {
601 bcm2835_gpio_irq_config(pc, offset, false);
602 pc->irq_type[offset] = type;
603 bcm2835_gpio_irq_config(pc, offset, true);
604 }
605 break;
606
607 case IRQ_TYPE_LEVEL_HIGH:
608 case IRQ_TYPE_LEVEL_LOW:
609 if (pc->irq_type[offset] != type) {
610 bcm2835_gpio_irq_config(pc, offset, false);
611 pc->irq_type[offset] = type;
612 bcm2835_gpio_irq_config(pc, offset, true);
613 }
614 break;
615
616 default:
617 return -EINVAL;
618 }
619 return 0;
620 }
621
bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)622 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
623 {
624 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
625 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
626 unsigned gpio = irqd_to_hwirq(data);
627 unsigned offset = GPIO_REG_SHIFT(gpio);
628 unsigned bank = GPIO_REG_OFFSET(gpio);
629 unsigned long flags;
630 int ret;
631
632 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
633
634 if (test_bit(offset, &pc->enabled_irq_map[bank]))
635 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
636 else
637 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
638
639 if (type & IRQ_TYPE_EDGE_BOTH)
640 irq_set_handler_locked(data, handle_edge_irq);
641 else
642 irq_set_handler_locked(data, handle_level_irq);
643
644 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
645
646 return ret;
647 }
648
bcm2835_gpio_irq_ack(struct irq_data *data)649 static void bcm2835_gpio_irq_ack(struct irq_data *data)
650 {
651 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
652 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
653 unsigned gpio = irqd_to_hwirq(data);
654
655 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
656 }
657
bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)658 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
659 {
660 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
661 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
662 unsigned gpio = irqd_to_hwirq(data);
663 unsigned int irqgroup;
664 int ret = -EINVAL;
665
666 if (!pc->wake_irq)
667 return ret;
668
669 if (gpio <= 27)
670 irqgroup = 0;
671 else if (gpio >= 28 && gpio <= 45)
672 irqgroup = 1;
673 else if (gpio >= 46 && gpio <= 57)
674 irqgroup = 2;
675 else
676 return ret;
677
678 if (on)
679 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
680 else
681 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
682
683 return ret;
684 }
685
686 static struct irq_chip bcm2835_gpio_irq_chip = {
687 .name = MODULE_NAME,
688 .irq_enable = bcm2835_gpio_irq_enable,
689 .irq_disable = bcm2835_gpio_irq_disable,
690 .irq_set_type = bcm2835_gpio_irq_set_type,
691 .irq_ack = bcm2835_gpio_irq_ack,
692 .irq_mask = bcm2835_gpio_irq_disable,
693 .irq_unmask = bcm2835_gpio_irq_enable,
694 .irq_set_wake = bcm2835_gpio_irq_set_wake,
695 .flags = IRQCHIP_MASK_ON_SUSPEND,
696 };
697
bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)698 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
699 {
700 return BCM2835_NUM_GPIOS;
701 }
702
bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev, unsigned selector)703 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
704 unsigned selector)
705 {
706 return bcm2835_gpio_groups[selector];
707 }
708
bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins)709 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
710 unsigned selector,
711 const unsigned **pins,
712 unsigned *num_pins)
713 {
714 *pins = &bcm2835_gpio_pins[selector].number;
715 *num_pins = 1;
716
717 return 0;
718 }
719
bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset)720 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
721 struct seq_file *s,
722 unsigned offset)
723 {
724 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
725 struct gpio_chip *chip = &pc->gpio_chip;
726 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
727 const char *fname = bcm2835_functions[fsel];
728 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
729 int irq = irq_find_mapping(chip->irq.domain, offset);
730
731 seq_printf(s, "function %s in %s; irq %d (%s)",
732 fname, value ? "hi" : "lo",
733 irq, irq_type_names[pc->irq_type[offset]]);
734 }
735
bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *maps, unsigned num_maps)736 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
737 struct pinctrl_map *maps, unsigned num_maps)
738 {
739 int i;
740
741 for (i = 0; i < num_maps; i++)
742 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
743 kfree(maps[i].data.configs.configs);
744
745 kfree(maps);
746 }
747
bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc, struct device_node *np, u32 pin, u32 fnum, struct pinctrl_map **maps)748 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
749 struct device_node *np, u32 pin, u32 fnum,
750 struct pinctrl_map **maps)
751 {
752 struct pinctrl_map *map = *maps;
753
754 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
755 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
756 return -EINVAL;
757 }
758
759 map->type = PIN_MAP_TYPE_MUX_GROUP;
760 map->data.mux.group = bcm2835_gpio_groups[pin];
761 map->data.mux.function = bcm2835_functions[fnum];
762 (*maps)++;
763
764 return 0;
765 }
766
bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc, struct device_node *np, u32 pin, u32 pull, struct pinctrl_map **maps)767 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
768 struct device_node *np, u32 pin, u32 pull,
769 struct pinctrl_map **maps)
770 {
771 struct pinctrl_map *map = *maps;
772 unsigned long *configs;
773
774 if (pull > 2) {
775 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
776 return -EINVAL;
777 }
778
779 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
780 if (!configs)
781 return -ENOMEM;
782 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
783
784 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
785 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
786 map->data.configs.configs = configs;
787 map->data.configs.num_configs = 1;
788 (*maps)++;
789
790 return 0;
791 }
792
bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np, struct pinctrl_map **map, unsigned int *num_maps)793 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
794 struct device_node *np,
795 struct pinctrl_map **map, unsigned int *num_maps)
796 {
797 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
798 struct property *pins, *funcs, *pulls;
799 int num_pins, num_funcs, num_pulls, maps_per_pin;
800 struct pinctrl_map *maps, *cur_map;
801 int i, err;
802 u32 pin, func, pull;
803
804 /* Check for generic binding in this node */
805 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
806 if (err || *num_maps)
807 return err;
808
809 /* Generic binding did not find anything continue with legacy parse */
810 pins = of_find_property(np, "brcm,pins", NULL);
811 if (!pins) {
812 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
813 return -EINVAL;
814 }
815
816 funcs = of_find_property(np, "brcm,function", NULL);
817 pulls = of_find_property(np, "brcm,pull", NULL);
818
819 if (!funcs && !pulls) {
820 dev_err(pc->dev,
821 "%pOF: neither brcm,function nor brcm,pull specified\n",
822 np);
823 return -EINVAL;
824 }
825
826 num_pins = pins->length / 4;
827 num_funcs = funcs ? (funcs->length / 4) : 0;
828 num_pulls = pulls ? (pulls->length / 4) : 0;
829
830 if (num_funcs > 1 && num_funcs != num_pins) {
831 dev_err(pc->dev,
832 "%pOF: brcm,function must have 1 or %d entries\n",
833 np, num_pins);
834 return -EINVAL;
835 }
836
837 if (num_pulls > 1 && num_pulls != num_pins) {
838 dev_err(pc->dev,
839 "%pOF: brcm,pull must have 1 or %d entries\n",
840 np, num_pins);
841 return -EINVAL;
842 }
843
844 maps_per_pin = 0;
845 if (num_funcs)
846 maps_per_pin++;
847 if (num_pulls)
848 maps_per_pin++;
849 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
850 GFP_KERNEL);
851 if (!maps)
852 return -ENOMEM;
853
854 for (i = 0; i < num_pins; i++) {
855 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
856 if (err)
857 goto out;
858 if (pin >= pc->pctl_desc.npins) {
859 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
860 np, pin);
861 err = -EINVAL;
862 goto out;
863 }
864
865 if (num_funcs) {
866 err = of_property_read_u32_index(np, "brcm,function",
867 (num_funcs > 1) ? i : 0, &func);
868 if (err)
869 goto out;
870 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
871 func, &cur_map);
872 if (err)
873 goto out;
874 }
875 if (num_pulls) {
876 err = of_property_read_u32_index(np, "brcm,pull",
877 (num_pulls > 1) ? i : 0, &pull);
878 if (err)
879 goto out;
880 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
881 pull, &cur_map);
882 if (err)
883 goto out;
884 }
885 }
886
887 *map = maps;
888 *num_maps = num_pins * maps_per_pin;
889
890 return 0;
891
892 out:
893 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
894 return err;
895 }
896
897 static const struct pinctrl_ops bcm2835_pctl_ops = {
898 .get_groups_count = bcm2835_pctl_get_groups_count,
899 .get_group_name = bcm2835_pctl_get_group_name,
900 .get_group_pins = bcm2835_pctl_get_group_pins,
901 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
902 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
903 .dt_free_map = bcm2835_pctl_dt_free_map,
904 };
905
bcm2835_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)906 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
907 unsigned offset)
908 {
909 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
910
911 /* disable by setting to GPIO_IN */
912 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
913 return 0;
914 }
915
bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)916 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
917 {
918 return BCM2835_FSEL_COUNT;
919 }
920
bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev, unsigned selector)921 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
922 unsigned selector)
923 {
924 return bcm2835_functions[selector];
925 }
926
bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev, unsigned selector, const char * const **groups, unsigned * const num_groups)927 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
928 unsigned selector,
929 const char * const **groups,
930 unsigned * const num_groups)
931 {
932 /* every pin can do every function */
933 *groups = bcm2835_gpio_groups;
934 *num_groups = BCM2835_NUM_GPIOS;
935
936 return 0;
937 }
938
bcm2835_pmx_set(struct pinctrl_dev *pctldev, unsigned func_selector, unsigned group_selector)939 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
940 unsigned func_selector,
941 unsigned group_selector)
942 {
943 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
944
945 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
946
947 return 0;
948 }
949
bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset)950 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
951 struct pinctrl_gpio_range *range,
952 unsigned offset)
953 {
954 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
955
956 /* disable by setting to GPIO_IN */
957 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
958 }
959
bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset, bool input)960 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
961 struct pinctrl_gpio_range *range,
962 unsigned offset,
963 bool input)
964 {
965 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
966 enum bcm2835_fsel fsel = input ?
967 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
968
969 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
970
971 return 0;
972 }
973
974 static const struct pinmux_ops bcm2835_pmx_ops = {
975 .free = bcm2835_pmx_free,
976 .get_functions_count = bcm2835_pmx_get_functions_count,
977 .get_function_name = bcm2835_pmx_get_function_name,
978 .get_function_groups = bcm2835_pmx_get_function_groups,
979 .set_mux = bcm2835_pmx_set,
980 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
981 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
982 };
983
bcm2835_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *config)984 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
985 unsigned pin, unsigned long *config)
986 {
987 /* No way to read back config in HW */
988 return -ENOTSUPP;
989 }
990
bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, unsigned int pin, unsigned int arg)991 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
992 unsigned int pin, unsigned int arg)
993 {
994 u32 off, bit;
995
996 off = GPIO_REG_OFFSET(pin);
997 bit = GPIO_REG_SHIFT(pin);
998
999 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1000 /*
1001 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1002 * But the VideoCore firmware delay for this operation
1003 * based nearly on the same amount of VPU cycles and this clock
1004 * runs at 250 MHz.
1005 */
1006 udelay(1);
1007 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1008 udelay(1);
1009 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1010 }
1011
bcm2835_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs)1012 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1013 unsigned int pin, unsigned long *configs,
1014 unsigned int num_configs)
1015 {
1016 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1017 u32 param, arg;
1018 int i;
1019
1020 for (i = 0; i < num_configs; i++) {
1021 param = pinconf_to_config_param(configs[i]);
1022 arg = pinconf_to_config_argument(configs[i]);
1023
1024 switch (param) {
1025 /* Set legacy brcm,pull */
1026 case BCM2835_PINCONF_PARAM_PULL:
1027 bcm2835_pull_config_set(pc, pin, arg);
1028 break;
1029
1030 /* Set pull generic bindings */
1031 case PIN_CONFIG_BIAS_DISABLE:
1032 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1033 break;
1034
1035 case PIN_CONFIG_BIAS_PULL_DOWN:
1036 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1037 break;
1038
1039 case PIN_CONFIG_BIAS_PULL_UP:
1040 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1041 break;
1042
1043 /* Set output-high or output-low */
1044 case PIN_CONFIG_OUTPUT:
1045 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1046 break;
1047
1048 default:
1049 return -ENOTSUPP;
1050
1051 } /* switch param type */
1052 } /* for each config */
1053
1054 return 0;
1055 }
1056
1057 static const struct pinconf_ops bcm2835_pinconf_ops = {
1058 .is_generic = true,
1059 .pin_config_get = bcm2835_pinconf_get,
1060 .pin_config_set = bcm2835_pinconf_set,
1061 };
1062
bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, unsigned int pin, unsigned int arg)1063 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1064 unsigned int pin, unsigned int arg)
1065 {
1066 u32 shifter;
1067 u32 value;
1068 u32 off;
1069
1070 off = PUD_2711_REG_OFFSET(pin);
1071 shifter = PUD_2711_REG_SHIFT(pin);
1072
1073 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1074 value &= ~(PUD_2711_MASK << shifter);
1075 value |= (arg << shifter);
1076 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1077 }
1078
bcm2711_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs)1079 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1080 unsigned int pin, unsigned long *configs,
1081 unsigned int num_configs)
1082 {
1083 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1084 u32 param, arg;
1085 int i;
1086
1087 for (i = 0; i < num_configs; i++) {
1088 param = pinconf_to_config_param(configs[i]);
1089 arg = pinconf_to_config_argument(configs[i]);
1090
1091 switch (param) {
1092 /* convert legacy brcm,pull */
1093 case BCM2835_PINCONF_PARAM_PULL:
1094 if (arg == BCM2835_PUD_UP)
1095 arg = BCM2711_PULL_UP;
1096 else if (arg == BCM2835_PUD_DOWN)
1097 arg = BCM2711_PULL_DOWN;
1098 else
1099 arg = BCM2711_PULL_NONE;
1100
1101 bcm2711_pull_config_set(pc, pin, arg);
1102 break;
1103
1104 /* Set pull generic bindings */
1105 case PIN_CONFIG_BIAS_DISABLE:
1106 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1107 break;
1108 case PIN_CONFIG_BIAS_PULL_DOWN:
1109 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1110 break;
1111 case PIN_CONFIG_BIAS_PULL_UP:
1112 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1113 break;
1114
1115 /* Set output-high or output-low */
1116 case PIN_CONFIG_OUTPUT:
1117 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1118 break;
1119
1120 default:
1121 return -ENOTSUPP;
1122 }
1123 } /* for each config */
1124
1125 return 0;
1126 }
1127
1128 static const struct pinconf_ops bcm2711_pinconf_ops = {
1129 .is_generic = true,
1130 .pin_config_get = bcm2835_pinconf_get,
1131 .pin_config_set = bcm2711_pinconf_set,
1132 };
1133
1134 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1135 .name = MODULE_NAME,
1136 .pins = bcm2835_gpio_pins,
1137 .npins = BCM2835_NUM_GPIOS,
1138 .pctlops = &bcm2835_pctl_ops,
1139 .pmxops = &bcm2835_pmx_ops,
1140 .confops = &bcm2835_pinconf_ops,
1141 .owner = THIS_MODULE,
1142 };
1143
1144 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1145 .name = "pinctrl-bcm2711",
1146 .pins = bcm2835_gpio_pins,
1147 .npins = BCM2711_NUM_GPIOS,
1148 .pctlops = &bcm2835_pctl_ops,
1149 .pmxops = &bcm2835_pmx_ops,
1150 .confops = &bcm2711_pinconf_ops,
1151 .owner = THIS_MODULE,
1152 };
1153
1154 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1155 .name = MODULE_NAME,
1156 .npins = BCM2835_NUM_GPIOS,
1157 };
1158
1159 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1160 .name = "pinctrl-bcm2711",
1161 .npins = BCM2711_NUM_GPIOS,
1162 };
1163
1164 struct bcm_plat_data {
1165 const struct gpio_chip *gpio_chip;
1166 const struct pinctrl_desc *pctl_desc;
1167 const struct pinctrl_gpio_range *gpio_range;
1168 };
1169
1170 static const struct bcm_plat_data bcm2835_plat_data = {
1171 .gpio_chip = &bcm2835_gpio_chip,
1172 .pctl_desc = &bcm2835_pinctrl_desc,
1173 .gpio_range = &bcm2835_pinctrl_gpio_range,
1174 };
1175
1176 static const struct bcm_plat_data bcm2711_plat_data = {
1177 .gpio_chip = &bcm2711_gpio_chip,
1178 .pctl_desc = &bcm2711_pinctrl_desc,
1179 .gpio_range = &bcm2711_pinctrl_gpio_range,
1180 };
1181
1182 static const struct of_device_id bcm2835_pinctrl_match[] = {
1183 {
1184 .compatible = "brcm,bcm2835-gpio",
1185 .data = &bcm2835_plat_data,
1186 },
1187 {
1188 .compatible = "brcm,bcm2711-gpio",
1189 .data = &bcm2711_plat_data,
1190 },
1191 {
1192 .compatible = "brcm,bcm7211-gpio",
1193 .data = &bcm2711_plat_data,
1194 },
1195 {}
1196 };
1197
bcm2835_pinctrl_probe(struct platform_device *pdev)1198 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1199 {
1200 struct device *dev = &pdev->dev;
1201 struct device_node *np = dev->of_node;
1202 const struct bcm_plat_data *pdata;
1203 struct bcm2835_pinctrl *pc;
1204 struct gpio_irq_chip *girq;
1205 struct resource iomem;
1206 int err, i;
1207 const struct of_device_id *match;
1208 int is_7211 = 0;
1209
1210 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1211 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1212
1213 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1214 if (!pc)
1215 return -ENOMEM;
1216
1217 platform_set_drvdata(pdev, pc);
1218 pc->dev = dev;
1219
1220 err = of_address_to_resource(np, 0, &iomem);
1221 if (err) {
1222 dev_err(dev, "could not get IO memory\n");
1223 return err;
1224 }
1225
1226 pc->base = devm_ioremap_resource(dev, &iomem);
1227 if (IS_ERR(pc->base))
1228 return PTR_ERR(pc->base);
1229
1230 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1231 if (!match)
1232 return -EINVAL;
1233
1234 pdata = match->data;
1235 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1236
1237 pc->gpio_chip = *pdata->gpio_chip;
1238 pc->gpio_chip.parent = dev;
1239 pc->gpio_chip.of_node = np;
1240
1241 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1242 unsigned long events;
1243 unsigned offset;
1244
1245 /* clear event detection flags */
1246 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1247 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1248 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1249 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1250 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1251 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1252
1253 /* clear all the events */
1254 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1255 for_each_set_bit(offset, &events, 32)
1256 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1257
1258 raw_spin_lock_init(&pc->irq_lock[i]);
1259 }
1260
1261 pc->pctl_desc = *pdata->pctl_desc;
1262 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1263 if (IS_ERR(pc->pctl_dev)) {
1264 gpiochip_remove(&pc->gpio_chip);
1265 return PTR_ERR(pc->pctl_dev);
1266 }
1267
1268 pc->gpio_range = *pdata->gpio_range;
1269 pc->gpio_range.base = pc->gpio_chip.base;
1270 pc->gpio_range.gc = &pc->gpio_chip;
1271 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1272
1273 girq = &pc->gpio_chip.irq;
1274 girq->chip = &bcm2835_gpio_irq_chip;
1275 girq->parent_handler = bcm2835_gpio_irq_handler;
1276 girq->num_parents = BCM2835_NUM_IRQS;
1277 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1278 sizeof(*girq->parents),
1279 GFP_KERNEL);
1280 if (!girq->parents) {
1281 err = -ENOMEM;
1282 goto out_remove;
1283 }
1284
1285 if (is_7211) {
1286 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1287 sizeof(*pc->wake_irq),
1288 GFP_KERNEL);
1289 if (!pc->wake_irq) {
1290 err = -ENOMEM;
1291 goto out_remove;
1292 }
1293 }
1294
1295 /*
1296 * Use the same handler for all groups: this is necessary
1297 * since we use one gpiochip to cover all lines - the
1298 * irq handler then needs to figure out which group and
1299 * bank that was firing the IRQ and look up the per-group
1300 * and bank data.
1301 */
1302 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1303 int len;
1304 char *name;
1305
1306 girq->parents[i] = irq_of_parse_and_map(np, i);
1307 if (!is_7211)
1308 continue;
1309
1310 /* Skip over the all banks interrupts */
1311 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1312 BCM2835_NUM_IRQS + 1);
1313
1314 len = strlen(dev_name(pc->dev)) + 16;
1315 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1316 if (!name) {
1317 err = -ENOMEM;
1318 goto out_remove;
1319 }
1320
1321 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1322
1323 /* These are optional interrupts */
1324 err = devm_request_irq(dev, pc->wake_irq[i],
1325 bcm2835_gpio_wake_irq_handler,
1326 IRQF_SHARED, name, pc);
1327 if (err)
1328 dev_warn(dev, "unable to request wake IRQ %d\n",
1329 pc->wake_irq[i]);
1330 }
1331
1332 girq->default_type = IRQ_TYPE_NONE;
1333 girq->handler = handle_level_irq;
1334
1335 err = gpiochip_add_data(&pc->gpio_chip, pc);
1336 if (err) {
1337 dev_err(dev, "could not add GPIO chip\n");
1338 goto out_remove;
1339 }
1340
1341 return 0;
1342
1343 out_remove:
1344 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1345 return err;
1346 }
1347
1348 static struct platform_driver bcm2835_pinctrl_driver = {
1349 .probe = bcm2835_pinctrl_probe,
1350 .driver = {
1351 .name = MODULE_NAME,
1352 .of_match_table = bcm2835_pinctrl_match,
1353 .suppress_bind_attrs = true,
1354 },
1355 };
1356 builtin_platform_driver(bcm2835_pinctrl_driver);
1357