1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2017 NXP
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/perf_event.h>
17 #include <linux/slab.h>
18
19 #define COUNTER_CNTL 0x0
20 #define COUNTER_READ 0x20
21
22 #define COUNTER_DPCR1 0x30
23
24 #define CNTL_OVER 0x1
25 #define CNTL_CLEAR 0x2
26 #define CNTL_EN 0x4
27 #define CNTL_EN_MASK 0xFFFFFFFB
28 #define CNTL_CLEAR_MASK 0xFFFFFFFD
29 #define CNTL_OVER_MASK 0xFFFFFFFE
30
31 #define CNTL_CSV_SHIFT 24
32 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT)
33
34 #define EVENT_CYCLES_ID 0
35 #define EVENT_CYCLES_COUNTER 0
36 #define NUM_COUNTERS 4
37
38 #define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
39
40 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
41
42 #define DDR_PERF_DEV_NAME "imx8_ddr"
43 #define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
44
45 static DEFINE_IDA(ddr_ida);
46
47 /* DDR Perf hardware feature */
48 #define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */
49 #define DDR_CAP_AXI_ID_FILTER_ENHANCED 0x3 /* support enhanced AXI ID filter */
50
51 struct fsl_ddr_devtype_data {
52 unsigned int quirks; /* quirks needed for different DDR Perf core */
53 };
54
55 static const struct fsl_ddr_devtype_data imx8_devtype_data;
56
57 static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
58 .quirks = DDR_CAP_AXI_ID_FILTER,
59 };
60
61 static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
62 .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
63 };
64
65 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
69 { /* sentinel */ }
70 };
71 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
72
73 struct ddr_pmu {
74 struct pmu pmu;
75 void __iomem *base;
76 unsigned int cpu;
77 struct hlist_node node;
78 struct device *dev;
79 struct perf_event *events[NUM_COUNTERS];
80 int active_events;
81 enum cpuhp_state cpuhp_state;
82 const struct fsl_ddr_devtype_data *devtype_data;
83 int irq;
84 int id;
85 int active_counter;
86 };
87
88 enum ddr_perf_filter_capabilities {
89 PERF_CAP_AXI_ID_FILTER = 0,
90 PERF_CAP_AXI_ID_FILTER_ENHANCED,
91 PERF_CAP_AXI_ID_FEAT_MAX,
92 };
93
ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap)94 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap)
95 {
96 u32 quirks = pmu->devtype_data->quirks;
97
98 switch (cap) {
99 case PERF_CAP_AXI_ID_FILTER:
100 return !!(quirks & DDR_CAP_AXI_ID_FILTER);
101 case PERF_CAP_AXI_ID_FILTER_ENHANCED:
102 quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED;
103 return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED;
104 default:
105 WARN(1, "unknown filter cap %d\n", cap);
106 }
107
108 return 0;
109 }
110
ddr_perf_filter_cap_show(struct device *dev, struct device_attribute *attr, char *buf)111 static ssize_t ddr_perf_filter_cap_show(struct device *dev,
112 struct device_attribute *attr,
113 char *buf)
114 {
115 struct ddr_pmu *pmu = dev_get_drvdata(dev);
116 struct dev_ext_attribute *ea =
117 container_of(attr, struct dev_ext_attribute, attr);
118 int cap = (long)ea->var;
119
120 return snprintf(buf, PAGE_SIZE, "%u\n",
121 ddr_perf_filter_cap_get(pmu, cap));
122 }
123
124 #define PERF_EXT_ATTR_ENTRY(_name, _func, _var) \
125 (&((struct dev_ext_attribute) { \
126 __ATTR(_name, 0444, _func, NULL), (void *)_var \
127 }).attr.attr)
128
129 #define PERF_FILTER_EXT_ATTR_ENTRY(_name, _var) \
130 PERF_EXT_ATTR_ENTRY(_name, ddr_perf_filter_cap_show, _var)
131
132 static struct attribute *ddr_perf_filter_cap_attr[] = {
133 PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER),
134 PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED),
135 NULL,
136 };
137
138 static struct attribute_group ddr_perf_filter_cap_attr_group = {
139 .name = "caps",
140 .attrs = ddr_perf_filter_cap_attr,
141 };
142
ddr_perf_cpumask_show(struct device *dev, struct device_attribute *attr, char *buf)143 static ssize_t ddr_perf_cpumask_show(struct device *dev,
144 struct device_attribute *attr, char *buf)
145 {
146 struct ddr_pmu *pmu = dev_get_drvdata(dev);
147
148 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
149 }
150
151 static struct device_attribute ddr_perf_cpumask_attr =
152 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
153
154 static struct attribute *ddr_perf_cpumask_attrs[] = {
155 &ddr_perf_cpumask_attr.attr,
156 NULL,
157 };
158
159 static struct attribute_group ddr_perf_cpumask_attr_group = {
160 .attrs = ddr_perf_cpumask_attrs,
161 };
162
163 static ssize_t
ddr_pmu_event_show(struct device *dev, struct device_attribute *attr, char *page)164 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr,
165 char *page)
166 {
167 struct perf_pmu_events_attr *pmu_attr;
168
169 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
170 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
171 }
172
173 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \
174 (&((struct perf_pmu_events_attr[]) { \
175 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
176 .id = _id, } \
177 })[0].attr.attr)
178
179 static struct attribute *ddr_perf_events_attrs[] = {
180 IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID),
181 IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01),
182 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
183 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
184 IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
185 IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
186 IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
187 IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
188 IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
189 IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
190 IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
191 IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
192 IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
193 IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
194 IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
195 IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
196 IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
197 IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
198 IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
199 IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
200 IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
201 IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31),
202 IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32),
203 IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
204 IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
205 IMX8_DDR_PMU_EVENT_ATTR(read, 0x35),
206 IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
207 IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37),
208 IMX8_DDR_PMU_EVENT_ATTR(write, 0x38),
209 IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
210 IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
211 IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
212 NULL,
213 };
214
215 static struct attribute_group ddr_perf_events_attr_group = {
216 .name = "events",
217 .attrs = ddr_perf_events_attrs,
218 };
219
220 PMU_FORMAT_ATTR(event, "config:0-7");
221 PMU_FORMAT_ATTR(axi_id, "config1:0-15");
222 PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
223
224 static struct attribute *ddr_perf_format_attrs[] = {
225 &format_attr_event.attr,
226 &format_attr_axi_id.attr,
227 &format_attr_axi_mask.attr,
228 NULL,
229 };
230
231 static struct attribute_group ddr_perf_format_attr_group = {
232 .name = "format",
233 .attrs = ddr_perf_format_attrs,
234 };
235
236 static const struct attribute_group *attr_groups[] = {
237 &ddr_perf_events_attr_group,
238 &ddr_perf_format_attr_group,
239 &ddr_perf_cpumask_attr_group,
240 &ddr_perf_filter_cap_attr_group,
241 NULL,
242 };
243
ddr_perf_is_filtered(struct perf_event *event)244 static bool ddr_perf_is_filtered(struct perf_event *event)
245 {
246 return event->attr.config == 0x41 || event->attr.config == 0x42;
247 }
248
ddr_perf_filter_val(struct perf_event *event)249 static u32 ddr_perf_filter_val(struct perf_event *event)
250 {
251 return event->attr.config1;
252 }
253
ddr_perf_filters_compatible(struct perf_event *a, struct perf_event *b)254 static bool ddr_perf_filters_compatible(struct perf_event *a,
255 struct perf_event *b)
256 {
257 if (!ddr_perf_is_filtered(a))
258 return true;
259 if (!ddr_perf_is_filtered(b))
260 return true;
261 return ddr_perf_filter_val(a) == ddr_perf_filter_val(b);
262 }
263
ddr_perf_is_enhanced_filtered(struct perf_event *event)264 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event)
265 {
266 unsigned int filt;
267 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
268
269 filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED;
270 return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) &&
271 ddr_perf_is_filtered(event);
272 }
273
ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)274 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
275 {
276 int i;
277
278 /*
279 * Always map cycle event to counter 0
280 * Cycles counter is dedicated for cycle event
281 * can't used for the other events
282 */
283 if (event == EVENT_CYCLES_ID) {
284 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
285 return EVENT_CYCLES_COUNTER;
286 else
287 return -ENOENT;
288 }
289
290 for (i = 1; i < NUM_COUNTERS; i++) {
291 if (pmu->events[i] == NULL)
292 return i;
293 }
294
295 return -ENOENT;
296 }
297
ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)298 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
299 {
300 pmu->events[counter] = NULL;
301 }
302
ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)303 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
304 {
305 struct perf_event *event = pmu->events[counter];
306 void __iomem *base = pmu->base;
307
308 /*
309 * return bytes instead of bursts from ddr transaction for
310 * axid-read and axid-write event if PMU core supports enhanced
311 * filter.
312 */
313 base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 :
314 COUNTER_READ;
315 return readl_relaxed(base + counter * 4);
316 }
317
ddr_perf_event_init(struct perf_event *event)318 static int ddr_perf_event_init(struct perf_event *event)
319 {
320 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
321 struct hw_perf_event *hwc = &event->hw;
322 struct perf_event *sibling;
323
324 if (event->attr.type != event->pmu->type)
325 return -ENOENT;
326
327 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
328 return -EOPNOTSUPP;
329
330 if (event->cpu < 0) {
331 dev_warn(pmu->dev, "Can't provide per-task data!\n");
332 return -EOPNOTSUPP;
333 }
334
335 /*
336 * We must NOT create groups containing mixed PMUs, although software
337 * events are acceptable (for example to create a CCN group
338 * periodically read when a hrtimer aka cpu-clock leader triggers).
339 */
340 if (event->group_leader->pmu != event->pmu &&
341 !is_software_event(event->group_leader))
342 return -EINVAL;
343
344 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
345 if (!ddr_perf_filters_compatible(event, event->group_leader))
346 return -EINVAL;
347 for_each_sibling_event(sibling, event->group_leader) {
348 if (!ddr_perf_filters_compatible(event, sibling))
349 return -EINVAL;
350 }
351 }
352
353 for_each_sibling_event(sibling, event->group_leader) {
354 if (sibling->pmu != event->pmu &&
355 !is_software_event(sibling))
356 return -EINVAL;
357 }
358
359 event->cpu = pmu->cpu;
360 hwc->idx = -1;
361
362 return 0;
363 }
364
365
ddr_perf_event_update(struct perf_event *event)366 static void ddr_perf_event_update(struct perf_event *event)
367 {
368 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
369 struct hw_perf_event *hwc = &event->hw;
370 u64 delta, prev_raw_count, new_raw_count;
371 int counter = hwc->idx;
372
373 do {
374 prev_raw_count = local64_read(&hwc->prev_count);
375 new_raw_count = ddr_perf_read_counter(pmu, counter);
376 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
377 new_raw_count) != prev_raw_count);
378
379 delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
380
381 local64_add(delta, &event->count);
382 }
383
ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, int counter, bool enable)384 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
385 int counter, bool enable)
386 {
387 u8 reg = counter * 4 + COUNTER_CNTL;
388 int val;
389
390 if (enable) {
391 /*
392 * cycle counter is special which should firstly write 0 then
393 * write 1 into CLEAR bit to clear it. Other counters only
394 * need write 0 into CLEAR bit and it turns out to be 1 by
395 * hardware. Below enable flow is harmless for all counters.
396 */
397 writel(0, pmu->base + reg);
398 val = CNTL_EN | CNTL_CLEAR;
399 val |= FIELD_PREP(CNTL_CSV_MASK, config);
400 writel(val, pmu->base + reg);
401 } else {
402 /* Disable counter */
403 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
404 writel(val, pmu->base + reg);
405 }
406 }
407
ddr_perf_event_start(struct perf_event *event, int flags)408 static void ddr_perf_event_start(struct perf_event *event, int flags)
409 {
410 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
411 struct hw_perf_event *hwc = &event->hw;
412 int counter = hwc->idx;
413
414 local64_set(&hwc->prev_count, 0);
415
416 ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
417
418 if (!pmu->active_counter++)
419 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID,
420 EVENT_CYCLES_COUNTER, true);
421
422 hwc->state = 0;
423 }
424
ddr_perf_event_add(struct perf_event *event, int flags)425 static int ddr_perf_event_add(struct perf_event *event, int flags)
426 {
427 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
428 struct hw_perf_event *hwc = &event->hw;
429 int counter;
430 int cfg = event->attr.config;
431 int cfg1 = event->attr.config1;
432
433 if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
434 int i;
435
436 for (i = 1; i < NUM_COUNTERS; i++) {
437 if (pmu->events[i] &&
438 !ddr_perf_filters_compatible(event, pmu->events[i]))
439 return -EINVAL;
440 }
441
442 if (ddr_perf_is_filtered(event)) {
443 /* revert axi id masking(axi_mask) value */
444 cfg1 ^= AXI_MASKING_REVERT;
445 writel(cfg1, pmu->base + COUNTER_DPCR1);
446 }
447 }
448
449 counter = ddr_perf_alloc_counter(pmu, cfg);
450 if (counter < 0) {
451 dev_dbg(pmu->dev, "There are not enough counters\n");
452 return -EOPNOTSUPP;
453 }
454
455 pmu->events[counter] = event;
456 pmu->active_events++;
457 hwc->idx = counter;
458
459 hwc->state |= PERF_HES_STOPPED;
460
461 if (flags & PERF_EF_START)
462 ddr_perf_event_start(event, flags);
463
464 return 0;
465 }
466
ddr_perf_event_stop(struct perf_event *event, int flags)467 static void ddr_perf_event_stop(struct perf_event *event, int flags)
468 {
469 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
470 struct hw_perf_event *hwc = &event->hw;
471 int counter = hwc->idx;
472
473 ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
474 ddr_perf_event_update(event);
475
476 if (!--pmu->active_counter)
477 ddr_perf_counter_enable(pmu, EVENT_CYCLES_ID,
478 EVENT_CYCLES_COUNTER, false);
479
480 hwc->state |= PERF_HES_STOPPED;
481 }
482
ddr_perf_event_del(struct perf_event *event, int flags)483 static void ddr_perf_event_del(struct perf_event *event, int flags)
484 {
485 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
486 struct hw_perf_event *hwc = &event->hw;
487 int counter = hwc->idx;
488
489 ddr_perf_event_stop(event, PERF_EF_UPDATE);
490
491 ddr_perf_free_counter(pmu, counter);
492 pmu->active_events--;
493 hwc->idx = -1;
494 }
495
ddr_perf_pmu_enable(struct pmu *pmu)496 static void ddr_perf_pmu_enable(struct pmu *pmu)
497 {
498 }
499
ddr_perf_pmu_disable(struct pmu *pmu)500 static void ddr_perf_pmu_disable(struct pmu *pmu)
501 {
502 }
503
ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, struct device *dev)504 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
505 struct device *dev)
506 {
507 *pmu = (struct ddr_pmu) {
508 .pmu = (struct pmu) {
509 .module = THIS_MODULE,
510 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
511 .task_ctx_nr = perf_invalid_context,
512 .attr_groups = attr_groups,
513 .event_init = ddr_perf_event_init,
514 .add = ddr_perf_event_add,
515 .del = ddr_perf_event_del,
516 .start = ddr_perf_event_start,
517 .stop = ddr_perf_event_stop,
518 .read = ddr_perf_event_update,
519 .pmu_enable = ddr_perf_pmu_enable,
520 .pmu_disable = ddr_perf_pmu_disable,
521 },
522 .base = base,
523 .dev = dev,
524 };
525
526 pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
527 return pmu->id;
528 }
529
ddr_perf_irq_handler(int irq, void *p)530 static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
531 {
532 int i;
533 struct ddr_pmu *pmu = (struct ddr_pmu *) p;
534 struct perf_event *event, *cycle_event = NULL;
535
536 /* all counter will stop if cycle counter disabled */
537 ddr_perf_counter_enable(pmu,
538 EVENT_CYCLES_ID,
539 EVENT_CYCLES_COUNTER,
540 false);
541 /*
542 * When the cycle counter overflows, all counters are stopped,
543 * and an IRQ is raised. If any other counter overflows, it
544 * continues counting, and no IRQ is raised.
545 *
546 * Cycles occur at least 4 times as often as other events, so we
547 * can update all events on a cycle counter overflow and not
548 * lose events.
549 *
550 */
551 for (i = 0; i < NUM_COUNTERS; i++) {
552
553 if (!pmu->events[i])
554 continue;
555
556 event = pmu->events[i];
557
558 ddr_perf_event_update(event);
559
560 if (event->hw.idx == EVENT_CYCLES_COUNTER)
561 cycle_event = event;
562 }
563
564 ddr_perf_counter_enable(pmu,
565 EVENT_CYCLES_ID,
566 EVENT_CYCLES_COUNTER,
567 true);
568 if (cycle_event)
569 ddr_perf_event_update(cycle_event);
570
571 return IRQ_HANDLED;
572 }
573
ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)574 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
575 {
576 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
577 int target;
578
579 if (cpu != pmu->cpu)
580 return 0;
581
582 target = cpumask_any_but(cpu_online_mask, cpu);
583 if (target >= nr_cpu_ids)
584 return 0;
585
586 perf_pmu_migrate_context(&pmu->pmu, cpu, target);
587 pmu->cpu = target;
588
589 WARN_ON(irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu)));
590
591 return 0;
592 }
593
ddr_perf_probe(struct platform_device *pdev)594 static int ddr_perf_probe(struct platform_device *pdev)
595 {
596 struct ddr_pmu *pmu;
597 struct device_node *np;
598 void __iomem *base;
599 char *name;
600 int num;
601 int ret;
602 int irq;
603
604 base = devm_platform_ioremap_resource(pdev, 0);
605 if (IS_ERR(base))
606 return PTR_ERR(base);
607
608 np = pdev->dev.of_node;
609
610 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
611 if (!pmu)
612 return -ENOMEM;
613
614 num = ddr_perf_init(pmu, base, &pdev->dev);
615
616 platform_set_drvdata(pdev, pmu);
617
618 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
619 num);
620 if (!name) {
621 ret = -ENOMEM;
622 goto cpuhp_state_err;
623 }
624
625 pmu->devtype_data = of_device_get_match_data(&pdev->dev);
626
627 pmu->cpu = raw_smp_processor_id();
628 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
629 DDR_CPUHP_CB_NAME,
630 NULL,
631 ddr_perf_offline_cpu);
632
633 if (ret < 0) {
634 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n");
635 goto cpuhp_state_err;
636 }
637
638 pmu->cpuhp_state = ret;
639
640 /* Register the pmu instance for cpu hotplug */
641 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
642 if (ret) {
643 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
644 goto cpuhp_instance_err;
645 }
646
647 /* Request irq */
648 irq = of_irq_get(np, 0);
649 if (irq < 0) {
650 dev_err(&pdev->dev, "Failed to get irq: %d", irq);
651 ret = irq;
652 goto ddr_perf_err;
653 }
654
655 ret = devm_request_irq(&pdev->dev, irq,
656 ddr_perf_irq_handler,
657 IRQF_NOBALANCING | IRQF_NO_THREAD,
658 DDR_CPUHP_CB_NAME,
659 pmu);
660 if (ret < 0) {
661 dev_err(&pdev->dev, "Request irq failed: %d", ret);
662 goto ddr_perf_err;
663 }
664
665 pmu->irq = irq;
666 ret = irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu));
667 if (ret) {
668 dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
669 goto ddr_perf_err;
670 }
671
672 ret = perf_pmu_register(&pmu->pmu, name, -1);
673 if (ret)
674 goto ddr_perf_err;
675
676 return 0;
677
678 ddr_perf_err:
679 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
680 cpuhp_instance_err:
681 cpuhp_remove_multi_state(pmu->cpuhp_state);
682 cpuhp_state_err:
683 ida_simple_remove(&ddr_ida, pmu->id);
684 dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
685 return ret;
686 }
687
ddr_perf_remove(struct platform_device *pdev)688 static int ddr_perf_remove(struct platform_device *pdev)
689 {
690 struct ddr_pmu *pmu = platform_get_drvdata(pdev);
691
692 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
693 cpuhp_remove_multi_state(pmu->cpuhp_state);
694 irq_set_affinity_hint(pmu->irq, NULL);
695
696 perf_pmu_unregister(&pmu->pmu);
697
698 ida_simple_remove(&ddr_ida, pmu->id);
699 return 0;
700 }
701
702 static struct platform_driver imx_ddr_pmu_driver = {
703 .driver = {
704 .name = "imx-ddr-pmu",
705 .of_match_table = imx_ddr_pmu_dt_ids,
706 .suppress_bind_attrs = true,
707 },
708 .probe = ddr_perf_probe,
709 .remove = ddr_perf_remove,
710 };
711
712 module_platform_driver(imx_ddr_pmu_driver);
713 MODULE_LICENSE("GPL v2");
714