1// SPDX-License-Identifier: GPL-2.0 2/* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7#include <linux/acpi.h> 8#include <linux/aer.h> 9#include <linux/async.h> 10#include <linux/blkdev.h> 11#include <linux/blk-mq.h> 12#include <linux/blk-mq-pci.h> 13#include <linux/dmi.h> 14#include <linux/init.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/mm.h> 18#include <linux/module.h> 19#include <linux/mutex.h> 20#include <linux/once.h> 21#include <linux/pci.h> 22#include <linux/suspend.h> 23#include <linux/t10-pi.h> 24#include <linux/types.h> 25#include <linux/io-64-nonatomic-lo-hi.h> 26#include <linux/io-64-nonatomic-hi-lo.h> 27#include <linux/sed-opal.h> 28#include <linux/pci-p2pdma.h> 29 30#include "trace.h" 31#include "nvme.h" 32 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 35 36#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 37 38/* 39 * These can be higher, but we need to ensure that any command doesn't 40 * require an sg allocation that needs more than a page of data. 41 */ 42#define NVME_MAX_KB_SZ 4096 43#define NVME_MAX_SEGS 127 44 45static int use_threaded_interrupts; 46module_param(use_threaded_interrupts, int, 0); 47 48static bool use_cmb_sqes = true; 49module_param(use_cmb_sqes, bool, 0444); 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 51 52static unsigned int max_host_mem_size_mb = 128; 53module_param(max_host_mem_size_mb, uint, 0444); 54MODULE_PARM_DESC(max_host_mem_size_mb, 55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 56 57static unsigned int sgl_threshold = SZ_32K; 58module_param(sgl_threshold, uint, 0644); 59MODULE_PARM_DESC(sgl_threshold, 60 "Use SGLs when average request segment size is larger or equal to " 61 "this size. Use 0 to disable SGLs."); 62 63static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 64static const struct kernel_param_ops io_queue_depth_ops = { 65 .set = io_queue_depth_set, 66 .get = param_get_uint, 67}; 68 69static unsigned int io_queue_depth = 1024; 70module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 71MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 72 73static int io_queue_count_set(const char *val, const struct kernel_param *kp) 74{ 75 unsigned int n; 76 int ret; 77 78 ret = kstrtouint(val, 10, &n); 79 if (ret != 0 || n > num_possible_cpus()) 80 return -EINVAL; 81 return param_set_uint(val, kp); 82} 83 84static const struct kernel_param_ops io_queue_count_ops = { 85 .set = io_queue_count_set, 86 .get = param_get_uint, 87}; 88 89static unsigned int write_queues; 90module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 91MODULE_PARM_DESC(write_queues, 92 "Number of queues to use for writes. If not set, reads and writes " 93 "will share a queue set."); 94 95static unsigned int poll_queues; 96module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 97MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 98 99static bool noacpi; 100module_param(noacpi, bool, 0444); 101MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 102 103struct nvme_dev; 104struct nvme_queue; 105 106static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 107static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 108 109/* 110 * Represents an NVM Express device. Each nvme_dev is a PCI function. 111 */ 112struct nvme_dev { 113 struct nvme_queue *queues; 114 struct blk_mq_tag_set tagset; 115 struct blk_mq_tag_set admin_tagset; 116 u32 __iomem *dbs; 117 struct device *dev; 118 struct dma_pool *prp_page_pool; 119 struct dma_pool *prp_small_pool; 120 unsigned online_queues; 121 unsigned max_qid; 122 unsigned io_queues[HCTX_MAX_TYPES]; 123 unsigned int num_vecs; 124 u32 q_depth; 125 int io_sqes; 126 u32 db_stride; 127 void __iomem *bar; 128 unsigned long bar_mapped_size; 129 struct work_struct remove_work; 130 struct mutex shutdown_lock; 131 bool subsystem; 132 u64 cmb_size; 133 bool cmb_use_sqes; 134 u32 cmbsz; 135 u32 cmbloc; 136 struct nvme_ctrl ctrl; 137 u32 last_ps; 138 139 mempool_t *iod_mempool; 140 141 /* shadow doorbell buffer support: */ 142 __le32 *dbbuf_dbs; 143 dma_addr_t dbbuf_dbs_dma_addr; 144 __le32 *dbbuf_eis; 145 dma_addr_t dbbuf_eis_dma_addr; 146 147 /* host memory buffer support: */ 148 u64 host_mem_size; 149 u32 nr_host_mem_descs; 150 dma_addr_t host_mem_descs_dma; 151 struct nvme_host_mem_buf_desc *host_mem_descs; 152 void **host_mem_desc_bufs; 153 unsigned int nr_allocated_queues; 154 unsigned int nr_write_queues; 155 unsigned int nr_poll_queues; 156}; 157 158static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 159{ 160 int ret; 161 u32 n; 162 163 ret = kstrtou32(val, 10, &n); 164 if (ret != 0 || n < 2) 165 return -EINVAL; 166 167 return param_set_uint(val, kp); 168} 169 170static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171{ 172 return qid * 2 * stride; 173} 174 175static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176{ 177 return (qid * 2 + 1) * stride; 178} 179 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 181{ 182 return container_of(ctrl, struct nvme_dev, ctrl); 183} 184 185/* 186 * An NVM Express queue. Each device has at least two (one for admin 187 * commands and one for I/O commands). 188 */ 189struct nvme_queue { 190 struct nvme_dev *dev; 191 spinlock_t sq_lock; 192 void *sq_cmds; 193 /* only used for poll queues: */ 194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 195 struct nvme_completion *cqes; 196 dma_addr_t sq_dma_addr; 197 dma_addr_t cq_dma_addr; 198 u32 __iomem *q_db; 199 u32 q_depth; 200 u16 cq_vector; 201 u16 sq_tail; 202 u16 last_sq_tail; 203 u16 cq_head; 204 u16 qid; 205 u8 cq_phase; 206 u8 sqes; 207 unsigned long flags; 208#define NVMEQ_ENABLED 0 209#define NVMEQ_SQ_CMB 1 210#define NVMEQ_DELETE_ERROR 2 211#define NVMEQ_POLLED 3 212 __le32 *dbbuf_sq_db; 213 __le32 *dbbuf_cq_db; 214 __le32 *dbbuf_sq_ei; 215 __le32 *dbbuf_cq_ei; 216 struct completion delete_done; 217}; 218 219/* 220 * The nvme_iod describes the data in an I/O. 221 * 222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 223 * to the actual struct scatterlist. 224 */ 225struct nvme_iod { 226 struct nvme_request req; 227 struct nvme_command cmd; 228 struct nvme_queue *nvmeq; 229 bool use_sgl; 230 int aborted; 231 int npages; /* In the PRP list. 0 means small pool in use */ 232 int nents; /* Used in scatterlist */ 233 dma_addr_t first_dma; 234 unsigned int dma_len; /* length of single DMA segment mapping */ 235 dma_addr_t meta_dma; 236 struct scatterlist *sg; 237}; 238 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 240{ 241 return dev->nr_allocated_queues * 8 * dev->db_stride; 242} 243 244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 245{ 246 unsigned int mem_size = nvme_dbbuf_size(dev); 247 248 if (dev->dbbuf_dbs) 249 return 0; 250 251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 252 &dev->dbbuf_dbs_dma_addr, 253 GFP_KERNEL); 254 if (!dev->dbbuf_dbs) 255 return -ENOMEM; 256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 257 &dev->dbbuf_eis_dma_addr, 258 GFP_KERNEL); 259 if (!dev->dbbuf_eis) { 260 dma_free_coherent(dev->dev, mem_size, 261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 262 dev->dbbuf_dbs = NULL; 263 return -ENOMEM; 264 } 265 266 return 0; 267} 268 269static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 270{ 271 unsigned int mem_size = nvme_dbbuf_size(dev); 272 273 if (dev->dbbuf_dbs) { 274 dma_free_coherent(dev->dev, mem_size, 275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 276 dev->dbbuf_dbs = NULL; 277 } 278 if (dev->dbbuf_eis) { 279 dma_free_coherent(dev->dev, mem_size, 280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 281 dev->dbbuf_eis = NULL; 282 } 283} 284 285static void nvme_dbbuf_init(struct nvme_dev *dev, 286 struct nvme_queue *nvmeq, int qid) 287{ 288 if (!dev->dbbuf_dbs || !qid) 289 return; 290 291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 295} 296 297static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 298{ 299 if (!nvmeq->qid) 300 return; 301 302 nvmeq->dbbuf_sq_db = NULL; 303 nvmeq->dbbuf_cq_db = NULL; 304 nvmeq->dbbuf_sq_ei = NULL; 305 nvmeq->dbbuf_cq_ei = NULL; 306} 307 308static void nvme_dbbuf_set(struct nvme_dev *dev) 309{ 310 struct nvme_command c; 311 unsigned int i; 312 313 if (!dev->dbbuf_dbs) 314 return; 315 316 memset(&c, 0, sizeof(c)); 317 c.dbbuf.opcode = nvme_admin_dbbuf; 318 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 319 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 320 321 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 322 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 323 /* Free memory and continue on */ 324 nvme_dbbuf_dma_free(dev); 325 326 for (i = 1; i <= dev->online_queues; i++) 327 nvme_dbbuf_free(&dev->queues[i]); 328 } 329} 330 331static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 332{ 333 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 334} 335 336/* Update dbbuf and return true if an MMIO is required */ 337static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db, 338 volatile __le32 *dbbuf_ei) 339{ 340 if (dbbuf_db) { 341 u16 old_value, event_idx; 342 343 /* 344 * Ensure that the queue is written before updating 345 * the doorbell in memory 346 */ 347 wmb(); 348 349 old_value = le32_to_cpu(*dbbuf_db); 350 *dbbuf_db = cpu_to_le32(value); 351 352 /* 353 * Ensure that the doorbell is updated before reading the event 354 * index from memory. The controller needs to provide similar 355 * ordering to ensure the envent index is updated before reading 356 * the doorbell. 357 */ 358 mb(); 359 360 event_idx = le32_to_cpu(*dbbuf_ei); 361 if (!nvme_dbbuf_need_event(event_idx, value, old_value)) 362 return false; 363 } 364 365 return true; 366} 367 368/* 369 * Will slightly overestimate the number of pages needed. This is OK 370 * as it only leads to a small amount of wasted memory for the lifetime of 371 * the I/O. 372 */ 373static int nvme_pci_npages_prp(void) 374{ 375 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; 376 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); 377 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); 378} 379 380/* 381 * Calculates the number of pages needed for the SGL segments. For example a 4k 382 * page can accommodate 256 SGL descriptors. 383 */ 384static int nvme_pci_npages_sgl(void) 385{ 386 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 387 NVME_CTRL_PAGE_SIZE); 388} 389 390static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 391 unsigned int hctx_idx) 392{ 393 struct nvme_dev *dev = data; 394 struct nvme_queue *nvmeq = &dev->queues[0]; 395 396 WARN_ON(hctx_idx != 0); 397 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 398 399 hctx->driver_data = nvmeq; 400 return 0; 401} 402 403static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 404 unsigned int hctx_idx) 405{ 406 struct nvme_dev *dev = data; 407 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 408 409 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 410 hctx->driver_data = nvmeq; 411 return 0; 412} 413 414static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 415 unsigned int hctx_idx, unsigned int numa_node) 416{ 417 struct nvme_dev *dev = set->driver_data; 418 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 419 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 420 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 421 422 BUG_ON(!nvmeq); 423 iod->nvmeq = nvmeq; 424 425 nvme_req(req)->ctrl = &dev->ctrl; 426 return 0; 427} 428 429static int queue_irq_offset(struct nvme_dev *dev) 430{ 431 /* if we have more than 1 vec, admin queue offsets us by 1 */ 432 if (dev->num_vecs > 1) 433 return 1; 434 435 return 0; 436} 437 438static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 439{ 440 struct nvme_dev *dev = set->driver_data; 441 int i, qoff, offset; 442 443 offset = queue_irq_offset(dev); 444 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 445 struct blk_mq_queue_map *map = &set->map[i]; 446 447 map->nr_queues = dev->io_queues[i]; 448 if (!map->nr_queues) { 449 BUG_ON(i == HCTX_TYPE_DEFAULT); 450 continue; 451 } 452 453 /* 454 * The poll queue(s) doesn't have an IRQ (and hence IRQ 455 * affinity), so use the regular blk-mq cpu mapping 456 */ 457 map->queue_offset = qoff; 458 if (i != HCTX_TYPE_POLL && offset) 459 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 460 else 461 blk_mq_map_queues(map); 462 qoff += map->nr_queues; 463 offset += map->nr_queues; 464 } 465 466 return 0; 467} 468 469/* 470 * Write sq tail if we are asked to, or if the next command would wrap. 471 */ 472static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 473{ 474 if (!write_sq) { 475 u16 next_tail = nvmeq->sq_tail + 1; 476 477 if (next_tail == nvmeq->q_depth) 478 next_tail = 0; 479 if (next_tail != nvmeq->last_sq_tail) 480 return; 481 } 482 483 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 484 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 485 writel(nvmeq->sq_tail, nvmeq->q_db); 486 nvmeq->last_sq_tail = nvmeq->sq_tail; 487} 488 489/** 490 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 491 * @nvmeq: The queue to use 492 * @cmd: The command to send 493 * @write_sq: whether to write to the SQ doorbell 494 */ 495static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 496 bool write_sq) 497{ 498 spin_lock(&nvmeq->sq_lock); 499 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 500 cmd, sizeof(*cmd)); 501 if (++nvmeq->sq_tail == nvmeq->q_depth) 502 nvmeq->sq_tail = 0; 503 nvme_write_sq_db(nvmeq, write_sq); 504 spin_unlock(&nvmeq->sq_lock); 505} 506 507static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 508{ 509 struct nvme_queue *nvmeq = hctx->driver_data; 510 511 spin_lock(&nvmeq->sq_lock); 512 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 513 nvme_write_sq_db(nvmeq, true); 514 spin_unlock(&nvmeq->sq_lock); 515} 516 517static void **nvme_pci_iod_list(struct request *req) 518{ 519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 520 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 521} 522 523static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 524{ 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526 int nseg = blk_rq_nr_phys_segments(req); 527 unsigned int avg_seg_size; 528 529 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 530 531 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 532 return false; 533 if (!iod->nvmeq->qid) 534 return false; 535 if (!sgl_threshold || avg_seg_size < sgl_threshold) 536 return false; 537 return true; 538} 539 540static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 541{ 542 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 543 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 544 dma_addr_t dma_addr = iod->first_dma; 545 int i; 546 547 for (i = 0; i < iod->npages; i++) { 548 __le64 *prp_list = nvme_pci_iod_list(req)[i]; 549 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 550 551 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 552 dma_addr = next_dma_addr; 553 } 554 555} 556 557static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 558{ 559 const int last_sg = SGES_PER_PAGE - 1; 560 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 561 dma_addr_t dma_addr = iod->first_dma; 562 int i; 563 564 for (i = 0; i < iod->npages; i++) { 565 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 566 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 567 568 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 569 dma_addr = next_dma_addr; 570 } 571 572} 573 574static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 575{ 576 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 577 578 if (is_pci_p2pdma_page(sg_page(iod->sg))) 579 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 580 rq_dma_dir(req)); 581 else 582 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 583} 584 585static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 586{ 587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 588 589 if (iod->dma_len) { 590 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 591 rq_dma_dir(req)); 592 return; 593 } 594 595 WARN_ON_ONCE(!iod->nents); 596 597 nvme_unmap_sg(dev, req); 598 if (iod->npages == 0) 599 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 600 iod->first_dma); 601 else if (iod->use_sgl) 602 nvme_free_sgls(dev, req); 603 else 604 nvme_free_prps(dev, req); 605 mempool_free(iod->sg, dev->iod_mempool); 606} 607 608static void nvme_print_sgl(struct scatterlist *sgl, int nents) 609{ 610 int i; 611 struct scatterlist *sg; 612 613 for_each_sg(sgl, sg, nents, i) { 614 dma_addr_t phys = sg_phys(sg); 615 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 616 "dma_address:%pad dma_length:%d\n", 617 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 618 sg_dma_len(sg)); 619 } 620} 621 622static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 623 struct request *req, struct nvme_rw_command *cmnd) 624{ 625 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 626 struct dma_pool *pool; 627 int length = blk_rq_payload_bytes(req); 628 struct scatterlist *sg = iod->sg; 629 int dma_len = sg_dma_len(sg); 630 u64 dma_addr = sg_dma_address(sg); 631 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 632 __le64 *prp_list; 633 void **list = nvme_pci_iod_list(req); 634 dma_addr_t prp_dma; 635 int nprps, i; 636 637 length -= (NVME_CTRL_PAGE_SIZE - offset); 638 if (length <= 0) { 639 iod->first_dma = 0; 640 goto done; 641 } 642 643 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 644 if (dma_len) { 645 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 646 } else { 647 sg = sg_next(sg); 648 dma_addr = sg_dma_address(sg); 649 dma_len = sg_dma_len(sg); 650 } 651 652 if (length <= NVME_CTRL_PAGE_SIZE) { 653 iod->first_dma = dma_addr; 654 goto done; 655 } 656 657 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 658 if (nprps <= (256 / 8)) { 659 pool = dev->prp_small_pool; 660 iod->npages = 0; 661 } else { 662 pool = dev->prp_page_pool; 663 iod->npages = 1; 664 } 665 666 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 667 if (!prp_list) { 668 iod->first_dma = dma_addr; 669 iod->npages = -1; 670 return BLK_STS_RESOURCE; 671 } 672 list[0] = prp_list; 673 iod->first_dma = prp_dma; 674 i = 0; 675 for (;;) { 676 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 677 __le64 *old_prp_list = prp_list; 678 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 679 if (!prp_list) 680 goto free_prps; 681 list[iod->npages++] = prp_list; 682 prp_list[0] = old_prp_list[i - 1]; 683 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 684 i = 1; 685 } 686 prp_list[i++] = cpu_to_le64(dma_addr); 687 dma_len -= NVME_CTRL_PAGE_SIZE; 688 dma_addr += NVME_CTRL_PAGE_SIZE; 689 length -= NVME_CTRL_PAGE_SIZE; 690 if (length <= 0) 691 break; 692 if (dma_len > 0) 693 continue; 694 if (unlikely(dma_len < 0)) 695 goto bad_sgl; 696 sg = sg_next(sg); 697 dma_addr = sg_dma_address(sg); 698 dma_len = sg_dma_len(sg); 699 } 700done: 701 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 702 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 703 return BLK_STS_OK; 704free_prps: 705 nvme_free_prps(dev, req); 706 return BLK_STS_RESOURCE; 707bad_sgl: 708 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 709 "Invalid SGL for payload:%d nents:%d\n", 710 blk_rq_payload_bytes(req), iod->nents); 711 return BLK_STS_IOERR; 712} 713 714static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 715 struct scatterlist *sg) 716{ 717 sge->addr = cpu_to_le64(sg_dma_address(sg)); 718 sge->length = cpu_to_le32(sg_dma_len(sg)); 719 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 720} 721 722static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 723 dma_addr_t dma_addr, int entries) 724{ 725 sge->addr = cpu_to_le64(dma_addr); 726 if (entries < SGES_PER_PAGE) { 727 sge->length = cpu_to_le32(entries * sizeof(*sge)); 728 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 729 } else { 730 sge->length = cpu_to_le32(NVME_CTRL_PAGE_SIZE); 731 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 732 } 733} 734 735static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 736 struct request *req, struct nvme_rw_command *cmd, int entries) 737{ 738 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 739 struct dma_pool *pool; 740 struct nvme_sgl_desc *sg_list; 741 struct scatterlist *sg = iod->sg; 742 dma_addr_t sgl_dma; 743 int i = 0; 744 745 /* setting the transfer type as SGL */ 746 cmd->flags = NVME_CMD_SGL_METABUF; 747 748 if (entries == 1) { 749 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 750 return BLK_STS_OK; 751 } 752 753 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 754 pool = dev->prp_small_pool; 755 iod->npages = 0; 756 } else { 757 pool = dev->prp_page_pool; 758 iod->npages = 1; 759 } 760 761 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 762 if (!sg_list) { 763 iod->npages = -1; 764 return BLK_STS_RESOURCE; 765 } 766 767 nvme_pci_iod_list(req)[0] = sg_list; 768 iod->first_dma = sgl_dma; 769 770 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 771 772 do { 773 if (i == SGES_PER_PAGE) { 774 struct nvme_sgl_desc *old_sg_desc = sg_list; 775 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 776 777 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 778 if (!sg_list) 779 goto free_sgls; 780 781 i = 0; 782 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 783 sg_list[i++] = *link; 784 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 785 } 786 787 nvme_pci_sgl_set_data(&sg_list[i++], sg); 788 sg = sg_next(sg); 789 } while (--entries > 0); 790 791 return BLK_STS_OK; 792free_sgls: 793 nvme_free_sgls(dev, req); 794 return BLK_STS_RESOURCE; 795} 796 797static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 798 struct request *req, struct nvme_rw_command *cmnd, 799 struct bio_vec *bv) 800{ 801 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 802 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 803 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 804 805 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 806 if (dma_mapping_error(dev->dev, iod->first_dma)) 807 return BLK_STS_RESOURCE; 808 iod->dma_len = bv->bv_len; 809 810 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 811 if (bv->bv_len > first_prp_len) 812 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 813 else 814 cmnd->dptr.prp2 = 0; 815 return BLK_STS_OK; 816} 817 818static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 819 struct request *req, struct nvme_rw_command *cmnd, 820 struct bio_vec *bv) 821{ 822 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 823 824 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 825 if (dma_mapping_error(dev->dev, iod->first_dma)) 826 return BLK_STS_RESOURCE; 827 iod->dma_len = bv->bv_len; 828 829 cmnd->flags = NVME_CMD_SGL_METABUF; 830 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 831 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 832 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 833 return BLK_STS_OK; 834} 835 836static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 837 struct nvme_command *cmnd) 838{ 839 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 840 blk_status_t ret = BLK_STS_RESOURCE; 841 int nr_mapped; 842 843 if (blk_rq_nr_phys_segments(req) == 1) { 844 struct bio_vec bv = req_bvec(req); 845 846 if (!is_pci_p2pdma_page(bv.bv_page)) { 847 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 848 return nvme_setup_prp_simple(dev, req, 849 &cmnd->rw, &bv); 850 851 if (iod->nvmeq->qid && sgl_threshold && 852 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 853 return nvme_setup_sgl_simple(dev, req, 854 &cmnd->rw, &bv); 855 } 856 } 857 858 iod->dma_len = 0; 859 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 860 if (!iod->sg) 861 return BLK_STS_RESOURCE; 862 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 863 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 864 if (!iod->nents) 865 goto out_free_sg; 866 867 if (is_pci_p2pdma_page(sg_page(iod->sg))) 868 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 869 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 870 else 871 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 872 rq_dma_dir(req), DMA_ATTR_NO_WARN); 873 if (!nr_mapped) 874 goto out_free_sg; 875 876 iod->use_sgl = nvme_pci_use_sgls(dev, req); 877 if (iod->use_sgl) 878 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 879 else 880 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 881 if (ret != BLK_STS_OK) 882 goto out_unmap_sg; 883 return BLK_STS_OK; 884 885out_unmap_sg: 886 nvme_unmap_sg(dev, req); 887out_free_sg: 888 mempool_free(iod->sg, dev->iod_mempool); 889 return ret; 890} 891 892static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 893 struct nvme_command *cmnd) 894{ 895 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 896 897 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 898 rq_dma_dir(req), 0); 899 if (dma_mapping_error(dev->dev, iod->meta_dma)) 900 return BLK_STS_IOERR; 901 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 902 return BLK_STS_OK; 903} 904 905/* 906 * NOTE: ns is NULL when called on the admin queue. 907 */ 908static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 909 const struct blk_mq_queue_data *bd) 910{ 911 struct nvme_ns *ns = hctx->queue->queuedata; 912 struct nvme_queue *nvmeq = hctx->driver_data; 913 struct nvme_dev *dev = nvmeq->dev; 914 struct request *req = bd->rq; 915 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 916 struct nvme_command *cmnd = &iod->cmd; 917 blk_status_t ret; 918 919 iod->aborted = 0; 920 iod->npages = -1; 921 iod->nents = 0; 922 923 /* 924 * We should not need to do this, but we're still using this to 925 * ensure we can drain requests on a dying queue. 926 */ 927 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 928 return BLK_STS_IOERR; 929 930 ret = nvme_setup_cmd(ns, req, cmnd); 931 if (ret) 932 return ret; 933 934 if (blk_rq_nr_phys_segments(req)) { 935 ret = nvme_map_data(dev, req, cmnd); 936 if (ret) 937 goto out_free_cmd; 938 } 939 940 if (blk_integrity_rq(req)) { 941 ret = nvme_map_metadata(dev, req, cmnd); 942 if (ret) 943 goto out_unmap_data; 944 } 945 946 blk_mq_start_request(req); 947 nvme_submit_cmd(nvmeq, cmnd, bd->last); 948 return BLK_STS_OK; 949out_unmap_data: 950 if (blk_rq_nr_phys_segments(req)) 951 nvme_unmap_data(dev, req); 952out_free_cmd: 953 nvme_cleanup_cmd(req); 954 return ret; 955} 956 957static void nvme_pci_complete_rq(struct request *req) 958{ 959 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 960 struct nvme_dev *dev = iod->nvmeq->dev; 961 962 if (blk_integrity_rq(req)) 963 dma_unmap_page(dev->dev, iod->meta_dma, 964 rq_integrity_vec(req)->bv_len, rq_dma_dir(req)); 965 966 if (blk_rq_nr_phys_segments(req)) 967 nvme_unmap_data(dev, req); 968 nvme_complete_rq(req); 969} 970 971/* We read the CQE phase first to check if the rest of the entry is valid */ 972static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 973{ 974 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 975 976 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 977} 978 979static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 980{ 981 u16 head = nvmeq->cq_head; 982 983 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 984 nvmeq->dbbuf_cq_ei)) 985 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 986} 987 988static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 989{ 990 if (!nvmeq->qid) 991 return nvmeq->dev->admin_tagset.tags[0]; 992 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 993} 994 995static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 996{ 997 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 998 __u16 command_id = READ_ONCE(cqe->command_id); 999 struct request *req; 1000 1001 /* 1002 * AEN requests are special as they don't time out and can 1003 * survive any kind of queue freeze and often don't respond to 1004 * aborts. We don't even bother to allocate a struct request 1005 * for them but rather special case them here. 1006 */ 1007 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1008 nvme_complete_async_event(&nvmeq->dev->ctrl, 1009 cqe->status, &cqe->result); 1010 return; 1011 } 1012 1013 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1014 if (unlikely(!req)) { 1015 dev_warn(nvmeq->dev->ctrl.device, 1016 "invalid id %d completed on queue %d\n", 1017 command_id, le16_to_cpu(cqe->sq_id)); 1018 return; 1019 } 1020 1021 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1022 if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 1023 nvme_pci_complete_rq(req); 1024} 1025 1026static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1027{ 1028 u32 tmp = nvmeq->cq_head + 1; 1029 1030 if (tmp == nvmeq->q_depth) { 1031 nvmeq->cq_head = 0; 1032 nvmeq->cq_phase ^= 1; 1033 } else { 1034 nvmeq->cq_head = tmp; 1035 } 1036} 1037 1038static inline int nvme_process_cq(struct nvme_queue *nvmeq) 1039{ 1040 int found = 0; 1041 1042 while (nvme_cqe_pending(nvmeq)) { 1043 found++; 1044 /* 1045 * load-load control dependency between phase and the rest of 1046 * the cqe requires a full read memory barrier 1047 */ 1048 dma_rmb(); 1049 nvme_handle_cqe(nvmeq, nvmeq->cq_head); 1050 nvme_update_cq_head(nvmeq); 1051 } 1052 1053 if (found) 1054 nvme_ring_cq_doorbell(nvmeq); 1055 return found; 1056} 1057 1058static irqreturn_t nvme_irq(int irq, void *data) 1059{ 1060 struct nvme_queue *nvmeq = data; 1061 irqreturn_t ret = IRQ_NONE; 1062 1063 /* 1064 * The rmb/wmb pair ensures we see all updates from a previous run of 1065 * the irq handler, even if that was on another CPU. 1066 */ 1067 rmb(); 1068 if (nvme_process_cq(nvmeq)) 1069 ret = IRQ_HANDLED; 1070 wmb(); 1071 1072 return ret; 1073} 1074 1075static irqreturn_t nvme_irq_check(int irq, void *data) 1076{ 1077 struct nvme_queue *nvmeq = data; 1078 1079 if (nvme_cqe_pending(nvmeq)) 1080 return IRQ_WAKE_THREAD; 1081 return IRQ_NONE; 1082} 1083 1084/* 1085 * Poll for completions for any interrupt driven queue 1086 * Can be called from any context. 1087 */ 1088static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1089{ 1090 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1091 1092 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1093 1094 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1095 nvme_process_cq(nvmeq); 1096 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1097} 1098 1099static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1100{ 1101 struct nvme_queue *nvmeq = hctx->driver_data; 1102 bool found; 1103 1104 if (!nvme_cqe_pending(nvmeq)) 1105 return 0; 1106 1107 spin_lock(&nvmeq->cq_poll_lock); 1108 found = nvme_process_cq(nvmeq); 1109 spin_unlock(&nvmeq->cq_poll_lock); 1110 1111 return found; 1112} 1113 1114static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1115{ 1116 struct nvme_dev *dev = to_nvme_dev(ctrl); 1117 struct nvme_queue *nvmeq = &dev->queues[0]; 1118 struct nvme_command c; 1119 1120 memset(&c, 0, sizeof(c)); 1121 c.common.opcode = nvme_admin_async_event; 1122 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1123 nvme_submit_cmd(nvmeq, &c, true); 1124} 1125 1126static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1127{ 1128 struct nvme_command c; 1129 1130 memset(&c, 0, sizeof(c)); 1131 c.delete_queue.opcode = opcode; 1132 c.delete_queue.qid = cpu_to_le16(id); 1133 1134 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1135} 1136 1137static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1138 struct nvme_queue *nvmeq, s16 vector) 1139{ 1140 struct nvme_command c; 1141 int flags = NVME_QUEUE_PHYS_CONTIG; 1142 1143 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1144 flags |= NVME_CQ_IRQ_ENABLED; 1145 1146 /* 1147 * Note: we (ab)use the fact that the prp fields survive if no data 1148 * is attached to the request. 1149 */ 1150 memset(&c, 0, sizeof(c)); 1151 c.create_cq.opcode = nvme_admin_create_cq; 1152 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1153 c.create_cq.cqid = cpu_to_le16(qid); 1154 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1155 c.create_cq.cq_flags = cpu_to_le16(flags); 1156 c.create_cq.irq_vector = cpu_to_le16(vector); 1157 1158 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1159} 1160 1161static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1162 struct nvme_queue *nvmeq) 1163{ 1164 struct nvme_ctrl *ctrl = &dev->ctrl; 1165 struct nvme_command c; 1166 int flags = NVME_QUEUE_PHYS_CONTIG; 1167 1168 /* 1169 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1170 * set. Since URGENT priority is zeroes, it makes all queues 1171 * URGENT. 1172 */ 1173 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1174 flags |= NVME_SQ_PRIO_MEDIUM; 1175 1176 /* 1177 * Note: we (ab)use the fact that the prp fields survive if no data 1178 * is attached to the request. 1179 */ 1180 memset(&c, 0, sizeof(c)); 1181 c.create_sq.opcode = nvme_admin_create_sq; 1182 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1183 c.create_sq.sqid = cpu_to_le16(qid); 1184 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1185 c.create_sq.sq_flags = cpu_to_le16(flags); 1186 c.create_sq.cqid = cpu_to_le16(qid); 1187 1188 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1189} 1190 1191static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1192{ 1193 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1194} 1195 1196static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1197{ 1198 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1199} 1200 1201static void abort_endio(struct request *req, blk_status_t error) 1202{ 1203 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1204 struct nvme_queue *nvmeq = iod->nvmeq; 1205 1206 dev_warn(nvmeq->dev->ctrl.device, 1207 "Abort status: 0x%x", nvme_req(req)->status); 1208 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1209 blk_mq_free_request(req); 1210} 1211 1212static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1213{ 1214 /* If true, indicates loss of adapter communication, possibly by a 1215 * NVMe Subsystem reset. 1216 */ 1217 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1218 1219 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1220 switch (dev->ctrl.state) { 1221 case NVME_CTRL_RESETTING: 1222 case NVME_CTRL_CONNECTING: 1223 return false; 1224 default: 1225 break; 1226 } 1227 1228 /* We shouldn't reset unless the controller is on fatal error state 1229 * _or_ if we lost the communication with it. 1230 */ 1231 if (!(csts & NVME_CSTS_CFS) && !nssro) 1232 return false; 1233 1234 return true; 1235} 1236 1237static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1238{ 1239 /* Read a config register to help see what died. */ 1240 u16 pci_status; 1241 int result; 1242 1243 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1244 &pci_status); 1245 if (result == PCIBIOS_SUCCESSFUL) 1246 dev_warn(dev->ctrl.device, 1247 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1248 csts, pci_status); 1249 else 1250 dev_warn(dev->ctrl.device, 1251 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1252 csts, result); 1253} 1254 1255static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1256{ 1257 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1258 struct nvme_queue *nvmeq = iod->nvmeq; 1259 struct nvme_dev *dev = nvmeq->dev; 1260 struct request *abort_req; 1261 struct nvme_command cmd; 1262 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1263 1264 /* If PCI error recovery process is happening, we cannot reset or 1265 * the recovery mechanism will surely fail. 1266 */ 1267 mb(); 1268 if (pci_channel_offline(to_pci_dev(dev->dev))) 1269 return BLK_EH_RESET_TIMER; 1270 1271 /* 1272 * Reset immediately if the controller is failed 1273 */ 1274 if (nvme_should_reset(dev, csts)) { 1275 nvme_warn_reset(dev, csts); 1276 nvme_dev_disable(dev, false); 1277 nvme_reset_ctrl(&dev->ctrl); 1278 return BLK_EH_DONE; 1279 } 1280 1281 /* 1282 * Did we miss an interrupt? 1283 */ 1284 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1285 nvme_poll(req->mq_hctx); 1286 else 1287 nvme_poll_irqdisable(nvmeq); 1288 1289 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { 1290 dev_warn(dev->ctrl.device, 1291 "I/O %d QID %d timeout, completion polled\n", 1292 req->tag, nvmeq->qid); 1293 return BLK_EH_DONE; 1294 } 1295 1296 /* 1297 * Shutdown immediately if controller times out while starting. The 1298 * reset work will see the pci device disabled when it gets the forced 1299 * cancellation error. All outstanding requests are completed on 1300 * shutdown, so we return BLK_EH_DONE. 1301 */ 1302 switch (dev->ctrl.state) { 1303 case NVME_CTRL_CONNECTING: 1304 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1305 fallthrough; 1306 case NVME_CTRL_DELETING: 1307 dev_warn_ratelimited(dev->ctrl.device, 1308 "I/O %d QID %d timeout, disable controller\n", 1309 req->tag, nvmeq->qid); 1310 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1311 nvme_dev_disable(dev, true); 1312 return BLK_EH_DONE; 1313 case NVME_CTRL_RESETTING: 1314 return BLK_EH_RESET_TIMER; 1315 default: 1316 break; 1317 } 1318 1319 /* 1320 * Shutdown the controller immediately and schedule a reset if the 1321 * command was already aborted once before and still hasn't been 1322 * returned to the driver, or if this is the admin queue. 1323 */ 1324 if (!nvmeq->qid || iod->aborted) { 1325 dev_warn(dev->ctrl.device, 1326 "I/O %d QID %d timeout, reset controller\n", 1327 req->tag, nvmeq->qid); 1328 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1329 nvme_dev_disable(dev, false); 1330 nvme_reset_ctrl(&dev->ctrl); 1331 1332 return BLK_EH_DONE; 1333 } 1334 1335 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1336 atomic_inc(&dev->ctrl.abort_limit); 1337 return BLK_EH_RESET_TIMER; 1338 } 1339 iod->aborted = 1; 1340 1341 memset(&cmd, 0, sizeof(cmd)); 1342 cmd.abort.opcode = nvme_admin_abort_cmd; 1343 cmd.abort.cid = nvme_cid(req); 1344 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1345 1346 dev_warn(nvmeq->dev->ctrl.device, 1347 "I/O %d QID %d timeout, aborting\n", 1348 req->tag, nvmeq->qid); 1349 1350 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1351 BLK_MQ_REQ_NOWAIT); 1352 if (IS_ERR(abort_req)) { 1353 atomic_inc(&dev->ctrl.abort_limit); 1354 return BLK_EH_RESET_TIMER; 1355 } 1356 1357 abort_req->end_io_data = NULL; 1358 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1359 1360 /* 1361 * The aborted req will be completed on receiving the abort req. 1362 * We enable the timer again. If hit twice, it'll cause a device reset, 1363 * as the device then is in a faulty state. 1364 */ 1365 return BLK_EH_RESET_TIMER; 1366} 1367 1368static void nvme_free_queue(struct nvme_queue *nvmeq) 1369{ 1370 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1371 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1372 if (!nvmeq->sq_cmds) 1373 return; 1374 1375 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1376 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1377 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1378 } else { 1379 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1380 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1381 } 1382} 1383 1384static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1385{ 1386 int i; 1387 1388 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1389 dev->ctrl.queue_count--; 1390 nvme_free_queue(&dev->queues[i]); 1391 } 1392} 1393 1394/** 1395 * nvme_suspend_queue - put queue into suspended state 1396 * @nvmeq: queue to suspend 1397 */ 1398static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1399{ 1400 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1401 return 1; 1402 1403 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1404 mb(); 1405 1406 nvmeq->dev->online_queues--; 1407 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1408 nvme_stop_admin_queue(&nvmeq->dev->ctrl); 1409 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1410 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1411 return 0; 1412} 1413 1414static void nvme_suspend_io_queues(struct nvme_dev *dev) 1415{ 1416 int i; 1417 1418 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1419 nvme_suspend_queue(&dev->queues[i]); 1420} 1421 1422static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1423{ 1424 struct nvme_queue *nvmeq = &dev->queues[0]; 1425 1426 if (shutdown) 1427 nvme_shutdown_ctrl(&dev->ctrl); 1428 else 1429 nvme_disable_ctrl(&dev->ctrl); 1430 1431 nvme_poll_irqdisable(nvmeq); 1432} 1433 1434/* 1435 * Called only on a device that has been disabled and after all other threads 1436 * that can check this device's completion queues have synced, except 1437 * nvme_poll(). This is the last chance for the driver to see a natural 1438 * completion before nvme_cancel_request() terminates all incomplete requests. 1439 */ 1440static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1441{ 1442 int i; 1443 1444 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1445 spin_lock(&dev->queues[i].cq_poll_lock); 1446 nvme_process_cq(&dev->queues[i]); 1447 spin_unlock(&dev->queues[i].cq_poll_lock); 1448 } 1449} 1450 1451static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1452 int entry_size) 1453{ 1454 int q_depth = dev->q_depth; 1455 unsigned q_size_aligned = roundup(q_depth * entry_size, 1456 NVME_CTRL_PAGE_SIZE); 1457 1458 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1459 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1460 1461 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1462 q_depth = div_u64(mem_per_q, entry_size); 1463 1464 /* 1465 * Ensure the reduced q_depth is above some threshold where it 1466 * would be better to map queues in system memory with the 1467 * original depth 1468 */ 1469 if (q_depth < 64) 1470 return -ENOMEM; 1471 } 1472 1473 return q_depth; 1474} 1475 1476static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1477 int qid) 1478{ 1479 struct pci_dev *pdev = to_pci_dev(dev->dev); 1480 1481 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1482 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1483 if (nvmeq->sq_cmds) { 1484 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1485 nvmeq->sq_cmds); 1486 if (nvmeq->sq_dma_addr) { 1487 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1488 return 0; 1489 } 1490 1491 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1492 } 1493 } 1494 1495 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1496 &nvmeq->sq_dma_addr, GFP_KERNEL); 1497 if (!nvmeq->sq_cmds) 1498 return -ENOMEM; 1499 return 0; 1500} 1501 1502static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1503{ 1504 struct nvme_queue *nvmeq = &dev->queues[qid]; 1505 1506 if (dev->ctrl.queue_count > qid) 1507 return 0; 1508 1509 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1510 nvmeq->q_depth = depth; 1511 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1512 &nvmeq->cq_dma_addr, GFP_KERNEL); 1513 if (!nvmeq->cqes) 1514 goto free_nvmeq; 1515 1516 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1517 goto free_cqdma; 1518 1519 nvmeq->dev = dev; 1520 spin_lock_init(&nvmeq->sq_lock); 1521 spin_lock_init(&nvmeq->cq_poll_lock); 1522 nvmeq->cq_head = 0; 1523 nvmeq->cq_phase = 1; 1524 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1525 nvmeq->qid = qid; 1526 dev->ctrl.queue_count++; 1527 1528 return 0; 1529 1530 free_cqdma: 1531 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1532 nvmeq->cq_dma_addr); 1533 free_nvmeq: 1534 return -ENOMEM; 1535} 1536 1537static int queue_request_irq(struct nvme_queue *nvmeq) 1538{ 1539 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1540 int nr = nvmeq->dev->ctrl.instance; 1541 1542 if (use_threaded_interrupts) { 1543 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1544 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1545 } else { 1546 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1547 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1548 } 1549} 1550 1551static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1552{ 1553 struct nvme_dev *dev = nvmeq->dev; 1554 1555 nvmeq->sq_tail = 0; 1556 nvmeq->last_sq_tail = 0; 1557 nvmeq->cq_head = 0; 1558 nvmeq->cq_phase = 1; 1559 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1560 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1561 nvme_dbbuf_init(dev, nvmeq, qid); 1562 dev->online_queues++; 1563 wmb(); /* ensure the first interrupt sees the initialization */ 1564} 1565 1566static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1567{ 1568 struct nvme_dev *dev = nvmeq->dev; 1569 int result; 1570 u16 vector = 0; 1571 1572 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1573 1574 /* 1575 * A queue's vector matches the queue identifier unless the controller 1576 * has only one vector available. 1577 */ 1578 if (!polled) 1579 vector = dev->num_vecs == 1 ? 0 : qid; 1580 else 1581 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1582 1583 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1584 if (result) 1585 return result; 1586 1587 result = adapter_alloc_sq(dev, qid, nvmeq); 1588 if (result < 0) 1589 return result; 1590 if (result) 1591 goto release_cq; 1592 1593 nvmeq->cq_vector = vector; 1594 nvme_init_queue(nvmeq, qid); 1595 1596 if (!polled) { 1597 result = queue_request_irq(nvmeq); 1598 if (result < 0) 1599 goto release_sq; 1600 } 1601 1602 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1603 return result; 1604 1605release_sq: 1606 dev->online_queues--; 1607 adapter_delete_sq(dev, qid); 1608release_cq: 1609 adapter_delete_cq(dev, qid); 1610 return result; 1611} 1612 1613static const struct blk_mq_ops nvme_mq_admin_ops = { 1614 .queue_rq = nvme_queue_rq, 1615 .complete = nvme_pci_complete_rq, 1616 .init_hctx = nvme_admin_init_hctx, 1617 .init_request = nvme_init_request, 1618 .timeout = nvme_timeout, 1619}; 1620 1621static const struct blk_mq_ops nvme_mq_ops = { 1622 .queue_rq = nvme_queue_rq, 1623 .complete = nvme_pci_complete_rq, 1624 .commit_rqs = nvme_commit_rqs, 1625 .init_hctx = nvme_init_hctx, 1626 .init_request = nvme_init_request, 1627 .map_queues = nvme_pci_map_queues, 1628 .timeout = nvme_timeout, 1629 .poll = nvme_poll, 1630}; 1631 1632static void nvme_dev_remove_admin(struct nvme_dev *dev) 1633{ 1634 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1635 /* 1636 * If the controller was reset during removal, it's possible 1637 * user requests may be waiting on a stopped queue. Start the 1638 * queue to flush these to completion. 1639 */ 1640 nvme_start_admin_queue(&dev->ctrl); 1641 blk_cleanup_queue(dev->ctrl.admin_q); 1642 blk_mq_free_tag_set(&dev->admin_tagset); 1643 } 1644} 1645 1646static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1647{ 1648 if (!dev->ctrl.admin_q) { 1649 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1650 dev->admin_tagset.nr_hw_queues = 1; 1651 1652 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1653 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1654 dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1655 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1656 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1657 dev->admin_tagset.driver_data = dev; 1658 1659 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1660 return -ENOMEM; 1661 dev->ctrl.admin_tagset = &dev->admin_tagset; 1662 1663 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1664 if (IS_ERR(dev->ctrl.admin_q)) { 1665 blk_mq_free_tag_set(&dev->admin_tagset); 1666 dev->ctrl.admin_q = NULL; 1667 return -ENOMEM; 1668 } 1669 if (!blk_get_queue(dev->ctrl.admin_q)) { 1670 nvme_dev_remove_admin(dev); 1671 dev->ctrl.admin_q = NULL; 1672 return -ENODEV; 1673 } 1674 } else 1675 nvme_start_admin_queue(&dev->ctrl); 1676 1677 return 0; 1678} 1679 1680static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1681{ 1682 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1683} 1684 1685static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1686{ 1687 struct pci_dev *pdev = to_pci_dev(dev->dev); 1688 1689 if (size <= dev->bar_mapped_size) 1690 return 0; 1691 if (size > pci_resource_len(pdev, 0)) 1692 return -ENOMEM; 1693 if (dev->bar) 1694 iounmap(dev->bar); 1695 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1696 if (!dev->bar) { 1697 dev->bar_mapped_size = 0; 1698 return -ENOMEM; 1699 } 1700 dev->bar_mapped_size = size; 1701 dev->dbs = dev->bar + NVME_REG_DBS; 1702 1703 return 0; 1704} 1705 1706static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1707{ 1708 int result; 1709 u32 aqa; 1710 struct nvme_queue *nvmeq; 1711 1712 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1713 if (result < 0) 1714 return result; 1715 1716 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1717 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1718 1719 if (dev->subsystem && 1720 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1721 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1722 1723 result = nvme_disable_ctrl(&dev->ctrl); 1724 if (result < 0) 1725 return result; 1726 1727 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1728 if (result) 1729 return result; 1730 1731 dev->ctrl.numa_node = dev_to_node(dev->dev); 1732 1733 nvmeq = &dev->queues[0]; 1734 aqa = nvmeq->q_depth - 1; 1735 aqa |= aqa << 16; 1736 1737 writel(aqa, dev->bar + NVME_REG_AQA); 1738 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1739 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1740 1741 result = nvme_enable_ctrl(&dev->ctrl); 1742 if (result) 1743 return result; 1744 1745 nvmeq->cq_vector = 0; 1746 nvme_init_queue(nvmeq, 0); 1747 result = queue_request_irq(nvmeq); 1748 if (result) { 1749 dev->online_queues--; 1750 return result; 1751 } 1752 1753 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1754 return result; 1755} 1756 1757static int nvme_create_io_queues(struct nvme_dev *dev) 1758{ 1759 unsigned i, max, rw_queues; 1760 int ret = 0; 1761 1762 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1763 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1764 ret = -ENOMEM; 1765 break; 1766 } 1767 } 1768 1769 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1770 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1771 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1772 dev->io_queues[HCTX_TYPE_READ]; 1773 } else { 1774 rw_queues = max; 1775 } 1776 1777 for (i = dev->online_queues; i <= max; i++) { 1778 bool polled = i > rw_queues; 1779 1780 ret = nvme_create_queue(&dev->queues[i], i, polled); 1781 if (ret) 1782 break; 1783 } 1784 1785 /* 1786 * Ignore failing Create SQ/CQ commands, we can continue with less 1787 * than the desired amount of queues, and even a controller without 1788 * I/O queues can still be used to issue admin commands. This might 1789 * be useful to upgrade a buggy firmware for example. 1790 */ 1791 return ret >= 0 ? 0 : ret; 1792} 1793 1794static ssize_t nvme_cmb_show(struct device *dev, 1795 struct device_attribute *attr, 1796 char *buf) 1797{ 1798 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1799 1800 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1801 ndev->cmbloc, ndev->cmbsz); 1802} 1803static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1804 1805static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1806{ 1807 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1808 1809 return 1ULL << (12 + 4 * szu); 1810} 1811 1812static u32 nvme_cmb_size(struct nvme_dev *dev) 1813{ 1814 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1815} 1816 1817static void nvme_map_cmb(struct nvme_dev *dev) 1818{ 1819 u64 size, offset; 1820 resource_size_t bar_size; 1821 struct pci_dev *pdev = to_pci_dev(dev->dev); 1822 int bar; 1823 1824 if (dev->cmb_size) 1825 return; 1826 1827 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1828 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1829 1830 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1831 if (!dev->cmbsz) 1832 return; 1833 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1834 1835 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1836 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1837 bar = NVME_CMB_BIR(dev->cmbloc); 1838 bar_size = pci_resource_len(pdev, bar); 1839 1840 if (offset > bar_size) 1841 return; 1842 1843 /* 1844 * Tell the controller about the host side address mapping the CMB, 1845 * and enable CMB decoding for the NVMe 1.4+ scheme: 1846 */ 1847 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1848 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1849 (pci_bus_address(pdev, bar) + offset), 1850 dev->bar + NVME_REG_CMBMSC); 1851 } 1852 1853 /* 1854 * Controllers may support a CMB size larger than their BAR, 1855 * for example, due to being behind a bridge. Reduce the CMB to 1856 * the reported size of the BAR 1857 */ 1858 if (size > bar_size - offset) 1859 size = bar_size - offset; 1860 1861 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1862 dev_warn(dev->ctrl.device, 1863 "failed to register the CMB\n"); 1864 return; 1865 } 1866 1867 dev->cmb_size = size; 1868 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1869 1870 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1871 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1872 pci_p2pmem_publish(pdev, true); 1873 1874 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1875 &dev_attr_cmb.attr, NULL)) 1876 dev_warn(dev->ctrl.device, 1877 "failed to add sysfs attribute for CMB\n"); 1878} 1879 1880static inline void nvme_release_cmb(struct nvme_dev *dev) 1881{ 1882 if (dev->cmb_size) { 1883 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1884 &dev_attr_cmb.attr, NULL); 1885 dev->cmb_size = 0; 1886 } 1887} 1888 1889static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1890{ 1891 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1892 u64 dma_addr = dev->host_mem_descs_dma; 1893 struct nvme_command c; 1894 int ret; 1895 1896 memset(&c, 0, sizeof(c)); 1897 c.features.opcode = nvme_admin_set_features; 1898 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1899 c.features.dword11 = cpu_to_le32(bits); 1900 c.features.dword12 = cpu_to_le32(host_mem_size); 1901 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1902 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1903 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1904 1905 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1906 if (ret) { 1907 dev_warn(dev->ctrl.device, 1908 "failed to set host mem (err %d, flags %#x).\n", 1909 ret, bits); 1910 } 1911 return ret; 1912} 1913 1914static void nvme_free_host_mem(struct nvme_dev *dev) 1915{ 1916 int i; 1917 1918 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1919 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1920 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 1921 1922 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1923 le64_to_cpu(desc->addr), 1924 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1925 } 1926 1927 kfree(dev->host_mem_desc_bufs); 1928 dev->host_mem_desc_bufs = NULL; 1929 dma_free_coherent(dev->dev, 1930 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1931 dev->host_mem_descs, dev->host_mem_descs_dma); 1932 dev->host_mem_descs = NULL; 1933 dev->nr_host_mem_descs = 0; 1934} 1935 1936static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1937 u32 chunk_size) 1938{ 1939 struct nvme_host_mem_buf_desc *descs; 1940 u32 max_entries, len; 1941 dma_addr_t descs_dma; 1942 int i = 0; 1943 void **bufs; 1944 u64 size, tmp; 1945 1946 tmp = (preferred + chunk_size - 1); 1947 do_div(tmp, chunk_size); 1948 max_entries = tmp; 1949 1950 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1951 max_entries = dev->ctrl.hmmaxd; 1952 1953 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1954 &descs_dma, GFP_KERNEL); 1955 if (!descs) 1956 goto out; 1957 1958 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1959 if (!bufs) 1960 goto out_free_descs; 1961 1962 for (size = 0; size < preferred && i < max_entries; size += len) { 1963 dma_addr_t dma_addr; 1964 1965 len = min_t(u64, chunk_size, preferred - size); 1966 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1967 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1968 if (!bufs[i]) 1969 break; 1970 1971 descs[i].addr = cpu_to_le64(dma_addr); 1972 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 1973 i++; 1974 } 1975 1976 if (!size) 1977 goto out_free_bufs; 1978 1979 dev->nr_host_mem_descs = i; 1980 dev->host_mem_size = size; 1981 dev->host_mem_descs = descs; 1982 dev->host_mem_descs_dma = descs_dma; 1983 dev->host_mem_desc_bufs = bufs; 1984 return 0; 1985 1986out_free_bufs: 1987 while (--i >= 0) { 1988 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 1989 1990 dma_free_attrs(dev->dev, size, bufs[i], 1991 le64_to_cpu(descs[i].addr), 1992 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1993 } 1994 1995 kfree(bufs); 1996out_free_descs: 1997 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1998 descs_dma); 1999out: 2000 dev->host_mem_descs = NULL; 2001 return -ENOMEM; 2002} 2003 2004static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 2005{ 2006 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 2007 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 2008 u64 chunk_size; 2009 2010 /* start big and work our way down */ 2011 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2012 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2013 if (!min || dev->host_mem_size >= min) 2014 return 0; 2015 nvme_free_host_mem(dev); 2016 } 2017 } 2018 2019 return -ENOMEM; 2020} 2021 2022static int nvme_setup_host_mem(struct nvme_dev *dev) 2023{ 2024 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2025 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2026 u64 min = (u64)dev->ctrl.hmmin * 4096; 2027 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2028 int ret; 2029 2030 preferred = min(preferred, max); 2031 if (min > max) { 2032 dev_warn(dev->ctrl.device, 2033 "min host memory (%lld MiB) above limit (%d MiB).\n", 2034 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2035 nvme_free_host_mem(dev); 2036 return 0; 2037 } 2038 2039 /* 2040 * If we already have a buffer allocated check if we can reuse it. 2041 */ 2042 if (dev->host_mem_descs) { 2043 if (dev->host_mem_size >= min) 2044 enable_bits |= NVME_HOST_MEM_RETURN; 2045 else 2046 nvme_free_host_mem(dev); 2047 } 2048 2049 if (!dev->host_mem_descs) { 2050 if (nvme_alloc_host_mem(dev, min, preferred)) { 2051 dev_warn(dev->ctrl.device, 2052 "failed to allocate host memory buffer.\n"); 2053 return 0; /* controller must work without HMB */ 2054 } 2055 2056 dev_info(dev->ctrl.device, 2057 "allocated %lld MiB host memory buffer.\n", 2058 dev->host_mem_size >> ilog2(SZ_1M)); 2059 } 2060 2061 ret = nvme_set_host_mem(dev, enable_bits); 2062 if (ret) 2063 nvme_free_host_mem(dev); 2064 return ret; 2065} 2066 2067/* 2068 * nirqs is the number of interrupts available for write and read 2069 * queues. The core already reserved an interrupt for the admin queue. 2070 */ 2071static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2072{ 2073 struct nvme_dev *dev = affd->priv; 2074 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2075 2076 /* 2077 * If there is no interrupt available for queues, ensure that 2078 * the default queue is set to 1. The affinity set size is 2079 * also set to one, but the irq core ignores it for this case. 2080 * 2081 * If only one interrupt is available or 'write_queue' == 0, combine 2082 * write and read queues. 2083 * 2084 * If 'write_queues' > 0, ensure it leaves room for at least one read 2085 * queue. 2086 */ 2087 if (!nrirqs) { 2088 nrirqs = 1; 2089 nr_read_queues = 0; 2090 } else if (nrirqs == 1 || !nr_write_queues) { 2091 nr_read_queues = 0; 2092 } else if (nr_write_queues >= nrirqs) { 2093 nr_read_queues = 1; 2094 } else { 2095 nr_read_queues = nrirqs - nr_write_queues; 2096 } 2097 2098 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2099 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2100 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2101 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2102 affd->nr_sets = nr_read_queues ? 2 : 1; 2103} 2104 2105static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2106{ 2107 struct pci_dev *pdev = to_pci_dev(dev->dev); 2108 struct irq_affinity affd = { 2109 .pre_vectors = 1, 2110 .calc_sets = nvme_calc_irq_sets, 2111 .priv = dev, 2112 }; 2113 unsigned int irq_queues, poll_queues; 2114 2115 /* 2116 * Poll queues don't need interrupts, but we need at least one I/O queue 2117 * left over for non-polled I/O. 2118 */ 2119 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2120 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2121 2122 /* 2123 * Initialize for the single interrupt case, will be updated in 2124 * nvme_calc_irq_sets(). 2125 */ 2126 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2127 dev->io_queues[HCTX_TYPE_READ] = 0; 2128 2129 /* 2130 * We need interrupts for the admin queue and each non-polled I/O queue, 2131 * but some Apple controllers require all queues to use the first 2132 * vector. 2133 */ 2134 irq_queues = 1; 2135 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2136 irq_queues += (nr_io_queues - poll_queues); 2137 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2138 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2139} 2140 2141static void nvme_disable_io_queues(struct nvme_dev *dev) 2142{ 2143 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2144 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2145} 2146 2147static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2148{ 2149 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2150} 2151 2152static int nvme_setup_io_queues(struct nvme_dev *dev) 2153{ 2154 struct nvme_queue *adminq = &dev->queues[0]; 2155 struct pci_dev *pdev = to_pci_dev(dev->dev); 2156 unsigned int nr_io_queues; 2157 unsigned long size; 2158 int result; 2159 2160 /* 2161 * Sample the module parameters once at reset time so that we have 2162 * stable values to work with. 2163 */ 2164 dev->nr_write_queues = write_queues; 2165 dev->nr_poll_queues = poll_queues; 2166 2167 /* 2168 * If tags are shared with admin queue (Apple bug), then 2169 * make sure we only use one IO queue. 2170 */ 2171 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2172 nr_io_queues = 1; 2173 else 2174 nr_io_queues = min(nvme_max_io_queues(dev), 2175 dev->nr_allocated_queues - 1); 2176 2177 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2178 if (result < 0) 2179 return result; 2180 2181 if (nr_io_queues == 0) 2182 return 0; 2183 2184 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2185 2186 if (dev->cmb_use_sqes) { 2187 result = nvme_cmb_qdepth(dev, nr_io_queues, 2188 sizeof(struct nvme_command)); 2189 if (result > 0) 2190 dev->q_depth = result; 2191 else 2192 dev->cmb_use_sqes = false; 2193 } 2194 2195 do { 2196 size = db_bar_size(dev, nr_io_queues); 2197 result = nvme_remap_bar(dev, size); 2198 if (!result) 2199 break; 2200 if (!--nr_io_queues) 2201 return -ENOMEM; 2202 } while (1); 2203 adminq->q_db = dev->dbs; 2204 2205 retry: 2206 /* Deregister the admin queue's interrupt */ 2207 pci_free_irq(pdev, 0, adminq); 2208 2209 /* 2210 * If we enable msix early due to not intx, disable it again before 2211 * setting up the full range we need. 2212 */ 2213 pci_free_irq_vectors(pdev); 2214 2215 result = nvme_setup_irqs(dev, nr_io_queues); 2216 if (result <= 0) 2217 return -EIO; 2218 2219 dev->num_vecs = result; 2220 result = max(result - 1, 1); 2221 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2222 2223 /* 2224 * Should investigate if there's a performance win from allocating 2225 * more queues than interrupt vectors; it might allow the submission 2226 * path to scale better, even if the receive path is limited by the 2227 * number of interrupts. 2228 */ 2229 result = queue_request_irq(adminq); 2230 if (result) 2231 return result; 2232 set_bit(NVMEQ_ENABLED, &adminq->flags); 2233 2234 result = nvme_create_io_queues(dev); 2235 if (result || dev->online_queues < 2) 2236 return result; 2237 2238 if (dev->online_queues - 1 < dev->max_qid) { 2239 nr_io_queues = dev->online_queues - 1; 2240 nvme_disable_io_queues(dev); 2241 nvme_suspend_io_queues(dev); 2242 goto retry; 2243 } 2244 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2245 dev->io_queues[HCTX_TYPE_DEFAULT], 2246 dev->io_queues[HCTX_TYPE_READ], 2247 dev->io_queues[HCTX_TYPE_POLL]); 2248 return 0; 2249} 2250 2251static void nvme_del_queue_end(struct request *req, blk_status_t error) 2252{ 2253 struct nvme_queue *nvmeq = req->end_io_data; 2254 2255 blk_mq_free_request(req); 2256 complete(&nvmeq->delete_done); 2257} 2258 2259static void nvme_del_cq_end(struct request *req, blk_status_t error) 2260{ 2261 struct nvme_queue *nvmeq = req->end_io_data; 2262 2263 if (error) 2264 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2265 2266 nvme_del_queue_end(req, error); 2267} 2268 2269static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2270{ 2271 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2272 struct request *req; 2273 struct nvme_command cmd; 2274 2275 memset(&cmd, 0, sizeof(cmd)); 2276 cmd.delete_queue.opcode = opcode; 2277 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2278 2279 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2280 if (IS_ERR(req)) 2281 return PTR_ERR(req); 2282 2283 req->end_io_data = nvmeq; 2284 2285 init_completion(&nvmeq->delete_done); 2286 blk_execute_rq_nowait(q, NULL, req, false, 2287 opcode == nvme_admin_delete_cq ? 2288 nvme_del_cq_end : nvme_del_queue_end); 2289 return 0; 2290} 2291 2292static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2293{ 2294 int nr_queues = dev->online_queues - 1, sent = 0; 2295 unsigned long timeout; 2296 2297 retry: 2298 timeout = ADMIN_TIMEOUT; 2299 while (nr_queues > 0) { 2300 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2301 break; 2302 nr_queues--; 2303 sent++; 2304 } 2305 while (sent) { 2306 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2307 2308 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2309 timeout); 2310 if (timeout == 0) 2311 return false; 2312 2313 sent--; 2314 if (nr_queues) 2315 goto retry; 2316 } 2317 return true; 2318} 2319 2320static void nvme_dev_add(struct nvme_dev *dev) 2321{ 2322 int ret; 2323 2324 if (!dev->ctrl.tagset) { 2325 dev->tagset.ops = &nvme_mq_ops; 2326 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2327 dev->tagset.nr_maps = 2; /* default + read */ 2328 if (dev->io_queues[HCTX_TYPE_POLL]) 2329 dev->tagset.nr_maps++; 2330 dev->tagset.timeout = NVME_IO_TIMEOUT; 2331 dev->tagset.numa_node = dev->ctrl.numa_node; 2332 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 2333 BLK_MQ_MAX_DEPTH) - 1; 2334 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2335 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2336 dev->tagset.driver_data = dev; 2337 2338 /* 2339 * Some Apple controllers requires tags to be unique 2340 * across admin and IO queue, so reserve the first 32 2341 * tags of the IO queue. 2342 */ 2343 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2344 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2345 2346 ret = blk_mq_alloc_tag_set(&dev->tagset); 2347 if (ret) { 2348 dev_warn(dev->ctrl.device, 2349 "IO queues tagset allocation failed %d\n", ret); 2350 return; 2351 } 2352 dev->ctrl.tagset = &dev->tagset; 2353 } else { 2354 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2355 2356 /* Free previously allocated queues that are no longer usable */ 2357 nvme_free_queues(dev, dev->online_queues); 2358 } 2359 2360 nvme_dbbuf_set(dev); 2361} 2362 2363static int nvme_pci_enable(struct nvme_dev *dev) 2364{ 2365 int result = -ENOMEM; 2366 struct pci_dev *pdev = to_pci_dev(dev->dev); 2367 2368 if (pci_enable_device_mem(pdev)) 2369 return result; 2370 2371 pci_set_master(pdev); 2372 2373 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2374 goto disable; 2375 2376 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2377 result = -ENODEV; 2378 goto disable; 2379 } 2380 2381 /* 2382 * Some devices and/or platforms don't advertise or work with INTx 2383 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2384 * adjust this later. 2385 */ 2386 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2387 if (result < 0) 2388 return result; 2389 2390 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2391 2392 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2393 io_queue_depth); 2394 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2395 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2396 dev->dbs = dev->bar + 4096; 2397 2398 /* 2399 * Some Apple controllers require a non-standard SQE size. 2400 * Interestingly they also seem to ignore the CC:IOSQES register 2401 * so we don't bother updating it here. 2402 */ 2403 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2404 dev->io_sqes = 7; 2405 else 2406 dev->io_sqes = NVME_NVM_IOSQES; 2407 2408 /* 2409 * Temporary fix for the Apple controller found in the MacBook8,1 and 2410 * some MacBook7,1 to avoid controller resets and data loss. 2411 */ 2412 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2413 dev->q_depth = 2; 2414 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2415 "set queue depth=%u to work around controller resets\n", 2416 dev->q_depth); 2417 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2418 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2419 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2420 dev->q_depth = 64; 2421 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2422 "set queue depth=%u\n", dev->q_depth); 2423 } 2424 2425 /* 2426 * Controllers with the shared tags quirk need the IO queue to be 2427 * big enough so that we get 32 tags for the admin queue 2428 */ 2429 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2430 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2431 dev->q_depth = NVME_AQ_DEPTH + 2; 2432 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2433 dev->q_depth); 2434 } 2435 2436 2437 nvme_map_cmb(dev); 2438 2439 pci_enable_pcie_error_reporting(pdev); 2440 pci_save_state(pdev); 2441 return 0; 2442 2443 disable: 2444 pci_disable_device(pdev); 2445 return result; 2446} 2447 2448static void nvme_dev_unmap(struct nvme_dev *dev) 2449{ 2450 if (dev->bar) 2451 iounmap(dev->bar); 2452 pci_release_mem_regions(to_pci_dev(dev->dev)); 2453} 2454 2455static void nvme_pci_disable(struct nvme_dev *dev) 2456{ 2457 struct pci_dev *pdev = to_pci_dev(dev->dev); 2458 2459 pci_free_irq_vectors(pdev); 2460 2461 if (pci_is_enabled(pdev)) { 2462 pci_disable_pcie_error_reporting(pdev); 2463 pci_disable_device(pdev); 2464 } 2465} 2466 2467static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2468{ 2469 bool dead = true, freeze = false; 2470 struct pci_dev *pdev = to_pci_dev(dev->dev); 2471 2472 mutex_lock(&dev->shutdown_lock); 2473 if (pci_is_enabled(pdev)) { 2474 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2475 2476 if (dev->ctrl.state == NVME_CTRL_LIVE || 2477 dev->ctrl.state == NVME_CTRL_RESETTING) { 2478 freeze = true; 2479 nvme_start_freeze(&dev->ctrl); 2480 } 2481 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2482 pdev->error_state != pci_channel_io_normal); 2483 } 2484 2485 /* 2486 * Give the controller a chance to complete all entered requests if 2487 * doing a safe shutdown. 2488 */ 2489 if (!dead && shutdown && freeze) 2490 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2491 2492 nvme_stop_queues(&dev->ctrl); 2493 2494 if (!dead && dev->ctrl.queue_count > 0) { 2495 nvme_disable_io_queues(dev); 2496 nvme_disable_admin_queue(dev, shutdown); 2497 } 2498 nvme_suspend_io_queues(dev); 2499 nvme_suspend_queue(&dev->queues[0]); 2500 nvme_pci_disable(dev); 2501 nvme_reap_pending_cqes(dev); 2502 2503 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2504 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2505 blk_mq_tagset_wait_completed_request(&dev->tagset); 2506 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2507 2508 /* 2509 * The driver will not be starting up queues again if shutting down so 2510 * must flush all entered requests to their failed completion to avoid 2511 * deadlocking blk-mq hot-cpu notifier. 2512 */ 2513 if (shutdown) { 2514 nvme_start_queues(&dev->ctrl); 2515 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2516 nvme_start_admin_queue(&dev->ctrl); 2517 } 2518 mutex_unlock(&dev->shutdown_lock); 2519} 2520 2521static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2522{ 2523 if (!nvme_wait_reset(&dev->ctrl)) 2524 return -EBUSY; 2525 nvme_dev_disable(dev, shutdown); 2526 return 0; 2527} 2528 2529static int nvme_setup_prp_pools(struct nvme_dev *dev) 2530{ 2531 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2532 NVME_CTRL_PAGE_SIZE, 2533 NVME_CTRL_PAGE_SIZE, 0); 2534 if (!dev->prp_page_pool) 2535 return -ENOMEM; 2536 2537 /* Optimisation for I/Os between 4k and 128k */ 2538 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2539 256, 256, 0); 2540 if (!dev->prp_small_pool) { 2541 dma_pool_destroy(dev->prp_page_pool); 2542 return -ENOMEM; 2543 } 2544 return 0; 2545} 2546 2547static void nvme_release_prp_pools(struct nvme_dev *dev) 2548{ 2549 dma_pool_destroy(dev->prp_page_pool); 2550 dma_pool_destroy(dev->prp_small_pool); 2551} 2552 2553static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2554{ 2555 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 2556 size_t alloc_size = sizeof(__le64 *) * npages + 2557 sizeof(struct scatterlist) * NVME_MAX_SEGS; 2558 2559 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2560 dev->iod_mempool = mempool_create_node(1, 2561 mempool_kmalloc, mempool_kfree, 2562 (void *)alloc_size, GFP_KERNEL, 2563 dev_to_node(dev->dev)); 2564 if (!dev->iod_mempool) 2565 return -ENOMEM; 2566 return 0; 2567} 2568 2569static void nvme_free_tagset(struct nvme_dev *dev) 2570{ 2571 if (dev->tagset.tags) 2572 blk_mq_free_tag_set(&dev->tagset); 2573 dev->ctrl.tagset = NULL; 2574} 2575 2576/* pairs with nvme_pci_alloc_dev */ 2577static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2578{ 2579 struct nvme_dev *dev = to_nvme_dev(ctrl); 2580 2581 nvme_dbbuf_dma_free(dev); 2582 nvme_free_tagset(dev); 2583 if (dev->ctrl.admin_q) 2584 blk_put_queue(dev->ctrl.admin_q); 2585 free_opal_dev(dev->ctrl.opal_dev); 2586 mempool_destroy(dev->iod_mempool); 2587 put_device(dev->dev); 2588 kfree(dev->queues); 2589 kfree(dev); 2590} 2591 2592static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2593{ 2594 /* 2595 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2596 * may be holding this pci_dev's device lock. 2597 */ 2598 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2599 nvme_get_ctrl(&dev->ctrl); 2600 nvme_dev_disable(dev, false); 2601 nvme_kill_queues(&dev->ctrl); 2602 if (!queue_work(nvme_wq, &dev->remove_work)) 2603 nvme_put_ctrl(&dev->ctrl); 2604} 2605 2606static void nvme_reset_work(struct work_struct *work) 2607{ 2608 struct nvme_dev *dev = 2609 container_of(work, struct nvme_dev, ctrl.reset_work); 2610 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2611 int result; 2612 2613 if (dev->ctrl.state != NVME_CTRL_RESETTING) { 2614 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2615 dev->ctrl.state); 2616 result = -ENODEV; 2617 goto out; 2618 } 2619 2620 /* 2621 * If we're called to reset a live controller first shut it down before 2622 * moving on. 2623 */ 2624 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2625 nvme_dev_disable(dev, false); 2626 nvme_sync_queues(&dev->ctrl); 2627 2628 mutex_lock(&dev->shutdown_lock); 2629 result = nvme_pci_enable(dev); 2630 if (result) 2631 goto out_unlock; 2632 2633 result = nvme_pci_configure_admin_queue(dev); 2634 if (result) 2635 goto out_unlock; 2636 2637 result = nvme_alloc_admin_tags(dev); 2638 if (result) 2639 goto out_unlock; 2640 2641 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2642 2643 /* 2644 * Limit the max command size to prevent iod->sg allocations going 2645 * over a single page. 2646 */ 2647 dev->ctrl.max_hw_sectors = min_t(u32, 2648 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2649 dev->ctrl.max_segments = NVME_MAX_SEGS; 2650 2651 /* 2652 * Don't limit the IOMMU merged segment size. 2653 */ 2654 dma_set_max_seg_size(dev->dev, 0xffffffff); 2655 2656 mutex_unlock(&dev->shutdown_lock); 2657 2658 /* 2659 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2660 * initializing procedure here. 2661 */ 2662 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2663 dev_warn(dev->ctrl.device, 2664 "failed to mark controller CONNECTING\n"); 2665 result = -EBUSY; 2666 goto out; 2667 } 2668 2669 /* 2670 * We do not support an SGL for metadata (yet), so we are limited to a 2671 * single integrity segment for the separate metadata pointer. 2672 */ 2673 dev->ctrl.max_integrity_segments = 1; 2674 2675 result = nvme_init_identify(&dev->ctrl); 2676 if (result) 2677 goto out; 2678 2679 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2680 if (!dev->ctrl.opal_dev) 2681 dev->ctrl.opal_dev = 2682 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2683 else if (was_suspend) 2684 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2685 } else { 2686 free_opal_dev(dev->ctrl.opal_dev); 2687 dev->ctrl.opal_dev = NULL; 2688 } 2689 2690 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2691 result = nvme_dbbuf_dma_alloc(dev); 2692 if (result) 2693 dev_warn(dev->dev, 2694 "unable to allocate dma for dbbuf\n"); 2695 } 2696 2697 if (dev->ctrl.hmpre) { 2698 result = nvme_setup_host_mem(dev); 2699 if (result < 0) 2700 goto out; 2701 } 2702 2703 result = nvme_setup_io_queues(dev); 2704 if (result) 2705 goto out; 2706 2707 /* 2708 * Keep the controller around but remove all namespaces if we don't have 2709 * any working I/O queue. 2710 */ 2711 if (dev->online_queues < 2) { 2712 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2713 nvme_kill_queues(&dev->ctrl); 2714 nvme_remove_namespaces(&dev->ctrl); 2715 nvme_free_tagset(dev); 2716 } else { 2717 nvme_start_queues(&dev->ctrl); 2718 nvme_wait_freeze(&dev->ctrl); 2719 nvme_dev_add(dev); 2720 nvme_unfreeze(&dev->ctrl); 2721 } 2722 2723 /* 2724 * If only admin queue live, keep it to do further investigation or 2725 * recovery. 2726 */ 2727 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2728 dev_warn(dev->ctrl.device, 2729 "failed to mark controller live state\n"); 2730 result = -ENODEV; 2731 goto out; 2732 } 2733 2734 nvme_start_ctrl(&dev->ctrl); 2735 return; 2736 2737 out_unlock: 2738 mutex_unlock(&dev->shutdown_lock); 2739 out: 2740 if (result) 2741 dev_warn(dev->ctrl.device, 2742 "Removing after probe failure status: %d\n", result); 2743 nvme_remove_dead_ctrl(dev); 2744} 2745 2746static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2747{ 2748 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2749 struct pci_dev *pdev = to_pci_dev(dev->dev); 2750 2751 if (pci_get_drvdata(pdev)) 2752 device_release_driver(&pdev->dev); 2753 nvme_put_ctrl(&dev->ctrl); 2754} 2755 2756static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2757{ 2758 *val = readl(to_nvme_dev(ctrl)->bar + off); 2759 return 0; 2760} 2761 2762static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2763{ 2764 writel(val, to_nvme_dev(ctrl)->bar + off); 2765 return 0; 2766} 2767 2768static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2769{ 2770 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2771 return 0; 2772} 2773 2774static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2775{ 2776 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2777 2778 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2779} 2780 2781static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2782 .name = "pcie", 2783 .module = THIS_MODULE, 2784 .flags = NVME_F_METADATA_SUPPORTED | 2785 NVME_F_PCI_P2PDMA, 2786 .reg_read32 = nvme_pci_reg_read32, 2787 .reg_write32 = nvme_pci_reg_write32, 2788 .reg_read64 = nvme_pci_reg_read64, 2789 .free_ctrl = nvme_pci_free_ctrl, 2790 .submit_async_event = nvme_pci_submit_async_event, 2791 .get_address = nvme_pci_get_address, 2792}; 2793 2794static int nvme_dev_map(struct nvme_dev *dev) 2795{ 2796 struct pci_dev *pdev = to_pci_dev(dev->dev); 2797 2798 if (pci_request_mem_regions(pdev, "nvme")) 2799 return -ENODEV; 2800 2801 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2802 goto release; 2803 2804 return 0; 2805 release: 2806 pci_release_mem_regions(pdev); 2807 return -ENODEV; 2808} 2809 2810static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2811{ 2812 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2813 /* 2814 * Several Samsung devices seem to drop off the PCIe bus 2815 * randomly when APST is on and uses the deepest sleep state. 2816 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2817 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2818 * 950 PRO 256GB", but it seems to be restricted to two Dell 2819 * laptops. 2820 */ 2821 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2822 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2823 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2824 return NVME_QUIRK_NO_DEEPEST_PS; 2825 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2826 /* 2827 * Samsung SSD 960 EVO drops off the PCIe bus after system 2828 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2829 * within few minutes after bootup on a Coffee Lake board - 2830 * ASUS PRIME Z370-A 2831 */ 2832 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2833 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2834 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2835 return NVME_QUIRK_NO_APST; 2836 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2837 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2838 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2839 /* 2840 * Forcing to use host managed nvme power settings for 2841 * lowest idle power with quick resume latency on 2842 * Samsung and Toshiba SSDs based on suspend behavior 2843 * on Coffee Lake board for LENOVO C640 2844 */ 2845 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2846 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2847 return NVME_QUIRK_SIMPLE_SUSPEND; 2848 } 2849 2850 return 0; 2851} 2852 2853static void nvme_async_probe(void *data, async_cookie_t cookie) 2854{ 2855 struct nvme_dev *dev = data; 2856 2857 flush_work(&dev->ctrl.reset_work); 2858 flush_work(&dev->ctrl.scan_work); 2859 nvme_put_ctrl(&dev->ctrl); 2860} 2861 2862static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 2863 const struct pci_device_id *id) 2864{ 2865 unsigned long quirks = id->driver_data; 2866 int node = dev_to_node(&pdev->dev); 2867 struct nvme_dev *dev; 2868 int ret = -ENOMEM; 2869 2870 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2871 if (!dev) 2872 return ERR_PTR(-ENOMEM); 2873 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2874 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2875 mutex_init(&dev->shutdown_lock); 2876 2877 dev->nr_write_queues = write_queues; 2878 dev->nr_poll_queues = poll_queues; 2879 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 2880 dev->queues = kcalloc_node(dev->nr_allocated_queues, 2881 sizeof(struct nvme_queue), GFP_KERNEL, node); 2882 if (!dev->queues) 2883 goto out_free_dev; 2884 2885 dev->dev = get_device(&pdev->dev); 2886 2887 quirks |= check_vendor_combination_bug(pdev); 2888 if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2889 /* 2890 * Some systems use a bios work around to ask for D3 on 2891 * platforms that support kernel managed suspend. 2892 */ 2893 dev_info(&pdev->dev, 2894 "platform quirk: setting simple suspend\n"); 2895 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2896 } 2897 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2898 quirks); 2899 if (ret) 2900 goto out_put_device; 2901 return dev; 2902 2903out_put_device: 2904 put_device(dev->dev); 2905 kfree(dev->queues); 2906out_free_dev: 2907 kfree(dev); 2908 return ERR_PTR(ret); 2909} 2910 2911static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2912{ 2913 struct nvme_dev *dev; 2914 int result = -ENOMEM; 2915 2916 dev = nvme_pci_alloc_dev(pdev, id); 2917 if (IS_ERR(dev)) 2918 return PTR_ERR(dev); 2919 2920 result = nvme_dev_map(dev); 2921 if (result) 2922 goto out_uninit_ctrl; 2923 2924 result = nvme_setup_prp_pools(dev); 2925 if (result) 2926 goto out_dev_unmap; 2927 2928 result = nvme_pci_alloc_iod_mempool(dev); 2929 if (result) 2930 goto out_release_prp_pools; 2931 2932 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2933 pci_set_drvdata(pdev, dev); 2934 2935 nvme_reset_ctrl(&dev->ctrl); 2936 async_schedule(nvme_async_probe, dev); 2937 return 0; 2938 2939out_release_prp_pools: 2940 nvme_release_prp_pools(dev); 2941out_dev_unmap: 2942 nvme_dev_unmap(dev); 2943out_uninit_ctrl: 2944 nvme_uninit_ctrl(&dev->ctrl); 2945 return result; 2946} 2947 2948static void nvme_reset_prepare(struct pci_dev *pdev) 2949{ 2950 struct nvme_dev *dev = pci_get_drvdata(pdev); 2951 2952 /* 2953 * We don't need to check the return value from waiting for the reset 2954 * state as pci_dev device lock is held, making it impossible to race 2955 * with ->remove(). 2956 */ 2957 nvme_disable_prepare_reset(dev, false); 2958 nvme_sync_queues(&dev->ctrl); 2959} 2960 2961static void nvme_reset_done(struct pci_dev *pdev) 2962{ 2963 struct nvme_dev *dev = pci_get_drvdata(pdev); 2964 2965 if (!nvme_try_sched_reset(&dev->ctrl)) 2966 flush_work(&dev->ctrl.reset_work); 2967} 2968 2969static void nvme_shutdown(struct pci_dev *pdev) 2970{ 2971 struct nvme_dev *dev = pci_get_drvdata(pdev); 2972 2973 nvme_disable_prepare_reset(dev, true); 2974} 2975 2976/* 2977 * The driver's remove may be called on a device in a partially initialized 2978 * state. This function must not have any dependencies on the device state in 2979 * order to proceed. 2980 */ 2981static void nvme_remove(struct pci_dev *pdev) 2982{ 2983 struct nvme_dev *dev = pci_get_drvdata(pdev); 2984 2985 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2986 pci_set_drvdata(pdev, NULL); 2987 2988 if (!pci_device_is_present(pdev)) { 2989 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2990 nvme_dev_disable(dev, true); 2991 } 2992 2993 flush_work(&dev->ctrl.reset_work); 2994 nvme_stop_ctrl(&dev->ctrl); 2995 nvme_remove_namespaces(&dev->ctrl); 2996 nvme_dev_disable(dev, true); 2997 nvme_release_cmb(dev); 2998 nvme_free_host_mem(dev); 2999 nvme_dev_remove_admin(dev); 3000 nvme_free_queues(dev, 0); 3001 nvme_release_prp_pools(dev); 3002 nvme_dev_unmap(dev); 3003 nvme_uninit_ctrl(&dev->ctrl); 3004} 3005 3006#ifdef CONFIG_PM_SLEEP 3007static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3008{ 3009 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3010} 3011 3012static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3013{ 3014 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3015} 3016 3017static int nvme_resume(struct device *dev) 3018{ 3019 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3020 struct nvme_ctrl *ctrl = &ndev->ctrl; 3021 3022 if (ndev->last_ps == U32_MAX || 3023 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3024 return nvme_try_sched_reset(&ndev->ctrl); 3025 return 0; 3026} 3027 3028static int nvme_suspend(struct device *dev) 3029{ 3030 struct pci_dev *pdev = to_pci_dev(dev); 3031 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3032 struct nvme_ctrl *ctrl = &ndev->ctrl; 3033 int ret = -EBUSY; 3034 3035 ndev->last_ps = U32_MAX; 3036 3037 /* 3038 * The platform does not remove power for a kernel managed suspend so 3039 * use host managed nvme power settings for lowest idle power if 3040 * possible. This should have quicker resume latency than a full device 3041 * shutdown. But if the firmware is involved after the suspend or the 3042 * device does not support any non-default power states, shut down the 3043 * device fully. 3044 * 3045 * If ASPM is not enabled for the device, shut down the device and allow 3046 * the PCI bus layer to put it into D3 in order to take the PCIe link 3047 * down, so as to allow the platform to achieve its minimum low-power 3048 * state (which may not be possible if the link is up). 3049 * 3050 * If a host memory buffer is enabled, shut down the device as the NVMe 3051 * specification allows the device to access the host memory buffer in 3052 * host DRAM from all power states, but hosts will fail access to DRAM 3053 * during S3. 3054 */ 3055 if (pm_suspend_via_firmware() || !ctrl->npss || 3056 !pcie_aspm_enabled(pdev) || 3057 ndev->nr_host_mem_descs || 3058 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3059 return nvme_disable_prepare_reset(ndev, true); 3060 3061 nvme_start_freeze(ctrl); 3062 nvme_wait_freeze(ctrl); 3063 nvme_sync_queues(ctrl); 3064 3065 if (ctrl->state != NVME_CTRL_LIVE) 3066 goto unfreeze; 3067 3068 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3069 if (ret < 0) 3070 goto unfreeze; 3071 3072 /* 3073 * A saved state prevents pci pm from generically controlling the 3074 * device's power. If we're using protocol specific settings, we don't 3075 * want pci interfering. 3076 */ 3077 pci_save_state(pdev); 3078 3079 ret = nvme_set_power_state(ctrl, ctrl->npss); 3080 if (ret < 0) 3081 goto unfreeze; 3082 3083 if (ret) { 3084 /* discard the saved state */ 3085 pci_load_saved_state(pdev, NULL); 3086 3087 /* 3088 * Clearing npss forces a controller reset on resume. The 3089 * correct value will be rediscovered then. 3090 */ 3091 ret = nvme_disable_prepare_reset(ndev, true); 3092 ctrl->npss = 0; 3093 } 3094unfreeze: 3095 nvme_unfreeze(ctrl); 3096 return ret; 3097} 3098 3099static int nvme_simple_suspend(struct device *dev) 3100{ 3101 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3102 3103 return nvme_disable_prepare_reset(ndev, true); 3104} 3105 3106static int nvme_simple_resume(struct device *dev) 3107{ 3108 struct pci_dev *pdev = to_pci_dev(dev); 3109 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3110 3111 return nvme_try_sched_reset(&ndev->ctrl); 3112} 3113 3114static const struct dev_pm_ops nvme_dev_pm_ops = { 3115 .suspend = nvme_suspend, 3116 .resume = nvme_resume, 3117 .freeze = nvme_simple_suspend, 3118 .thaw = nvme_simple_resume, 3119 .poweroff = nvme_simple_suspend, 3120 .restore = nvme_simple_resume, 3121}; 3122#endif /* CONFIG_PM_SLEEP */ 3123 3124static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3125 pci_channel_state_t state) 3126{ 3127 struct nvme_dev *dev = pci_get_drvdata(pdev); 3128 3129 /* 3130 * A frozen channel requires a reset. When detected, this method will 3131 * shutdown the controller to quiesce. The controller will be restarted 3132 * after the slot reset through driver's slot_reset callback. 3133 */ 3134 switch (state) { 3135 case pci_channel_io_normal: 3136 return PCI_ERS_RESULT_CAN_RECOVER; 3137 case pci_channel_io_frozen: 3138 dev_warn(dev->ctrl.device, 3139 "frozen state error detected, reset controller\n"); 3140 nvme_dev_disable(dev, false); 3141 return PCI_ERS_RESULT_NEED_RESET; 3142 case pci_channel_io_perm_failure: 3143 dev_warn(dev->ctrl.device, 3144 "failure state error detected, request disconnect\n"); 3145 return PCI_ERS_RESULT_DISCONNECT; 3146 } 3147 return PCI_ERS_RESULT_NEED_RESET; 3148} 3149 3150static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3151{ 3152 struct nvme_dev *dev = pci_get_drvdata(pdev); 3153 3154 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3155 pci_restore_state(pdev); 3156 nvme_reset_ctrl(&dev->ctrl); 3157 return PCI_ERS_RESULT_RECOVERED; 3158} 3159 3160static void nvme_error_resume(struct pci_dev *pdev) 3161{ 3162 struct nvme_dev *dev = pci_get_drvdata(pdev); 3163 3164 flush_work(&dev->ctrl.reset_work); 3165} 3166 3167static const struct pci_error_handlers nvme_err_handler = { 3168 .error_detected = nvme_error_detected, 3169 .slot_reset = nvme_slot_reset, 3170 .resume = nvme_error_resume, 3171 .reset_prepare = nvme_reset_prepare, 3172 .reset_done = nvme_reset_done, 3173}; 3174 3175static const struct pci_device_id nvme_id_table[] = { 3176 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3177 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3178 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3179 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3180 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3181 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3182 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3183 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3184 NVME_QUIRK_DEALLOCATE_ZEROES | 3185 NVME_QUIRK_IGNORE_DEV_SUBNQN | 3186 NVME_QUIRK_BOGUS_NID, }, 3187 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3188 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3189 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3190 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3191 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3192 NVME_QUIRK_MEDIUM_PRIO_SQ | 3193 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3194 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3195 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3196 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3197 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3198 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3199 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3200 NVME_QUIRK_BOGUS_NID, }, 3201 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3202 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3203 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3204 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 3205 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3206 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3207 NVME_QUIRK_NO_NS_DESC_LIST, }, 3208 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3209 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3210 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3211 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3212 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3213 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3214 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3215 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3216 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3217 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3218 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3219 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3220 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3221 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3222 NVME_QUIRK_BOGUS_NID, }, 3223 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3224 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3225 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3226 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3227 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3228 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3229 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3230 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3231 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3232 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3233 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3234 NVME_QUIRK_BOGUS_NID, }, 3235 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3236 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3237 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3238 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3239 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3240 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3241 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3242 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3243 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3244 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3245 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3246 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3247 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3248 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3249 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3250 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3251 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3252 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3253 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3254 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3255 NVME_QUIRK_128_BYTES_SQES | 3256 NVME_QUIRK_SHARED_TAGS | 3257 NVME_QUIRK_SKIP_CID_GEN }, 3258 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3259 { 0, } 3260}; 3261MODULE_DEVICE_TABLE(pci, nvme_id_table); 3262 3263static struct pci_driver nvme_driver = { 3264 .name = "nvme", 3265 .id_table = nvme_id_table, 3266 .probe = nvme_probe, 3267 .remove = nvme_remove, 3268 .shutdown = nvme_shutdown, 3269#ifdef CONFIG_PM_SLEEP 3270 .driver = { 3271 .pm = &nvme_dev_pm_ops, 3272 }, 3273#endif 3274 .sriov_configure = pci_sriov_configure_simple, 3275 .err_handler = &nvme_err_handler, 3276}; 3277 3278static int __init nvme_init(void) 3279{ 3280 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3281 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3282 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3283 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3284 3285 return pci_register_driver(&nvme_driver); 3286} 3287 3288static void __exit nvme_exit(void) 3289{ 3290 pci_unregister_driver(&nvme_driver); 3291 flush_workqueue(nvme_wq); 3292} 3293 3294MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3295MODULE_LICENSE("GPL"); 3296MODULE_VERSION("1.0"); 3297module_init(nvme_init); 3298module_exit(nvme_exit); 3299