1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Driver for Microsemi VSC85xx PHYs
4  *
5  * Author: Nagaraju Lakkaraju
6  * License: Dual MIT/GPL
7  * Copyright (c) 2016 Microsemi Corporation
8  */
9 
10 #include <linux/firmware.h>
11 #include <linux/jiffies.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mdio.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/of.h>
18 #include <linux/netdevice.h>
19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
20 
21 #include "mscc.h"
22 
23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
24 	{
25 		.string	= "phy_receive_errors",
26 		.reg	= MSCC_PHY_ERR_RX_CNT,
27 		.page	= MSCC_PHY_PAGE_STANDARD,
28 		.mask	= ERR_CNT_MASK,
29 	}, {
30 		.string	= "phy_false_carrier",
31 		.reg	= MSCC_PHY_ERR_FALSE_CARRIER_CNT,
32 		.page	= MSCC_PHY_PAGE_STANDARD,
33 		.mask	= ERR_CNT_MASK,
34 	}, {
35 		.string	= "phy_cu_media_link_disconnect",
36 		.reg	= MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
37 		.page	= MSCC_PHY_PAGE_STANDARD,
38 		.mask	= ERR_CNT_MASK,
39 	}, {
40 		.string	= "phy_cu_media_crc_good_count",
41 		.reg	= MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
42 		.page	= MSCC_PHY_PAGE_EXTENDED,
43 		.mask	= VALID_CRC_CNT_CRC_MASK,
44 	}, {
45 		.string	= "phy_cu_media_crc_error_count",
46 		.reg	= MSCC_PHY_EXT_PHY_CNTL_4,
47 		.page	= MSCC_PHY_PAGE_EXTENDED,
48 		.mask	= ERR_CNT_MASK,
49 	},
50 };
51 
52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
53 	{
54 		.string	= "phy_receive_errors",
55 		.reg	= MSCC_PHY_ERR_RX_CNT,
56 		.page	= MSCC_PHY_PAGE_STANDARD,
57 		.mask	= ERR_CNT_MASK,
58 	}, {
59 		.string	= "phy_false_carrier",
60 		.reg	= MSCC_PHY_ERR_FALSE_CARRIER_CNT,
61 		.page	= MSCC_PHY_PAGE_STANDARD,
62 		.mask	= ERR_CNT_MASK,
63 	}, {
64 		.string	= "phy_cu_media_link_disconnect",
65 		.reg	= MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
66 		.page	= MSCC_PHY_PAGE_STANDARD,
67 		.mask	= ERR_CNT_MASK,
68 	}, {
69 		.string	= "phy_cu_media_crc_good_count",
70 		.reg	= MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
71 		.page	= MSCC_PHY_PAGE_EXTENDED,
72 		.mask	= VALID_CRC_CNT_CRC_MASK,
73 	}, {
74 		.string	= "phy_cu_media_crc_error_count",
75 		.reg	= MSCC_PHY_EXT_PHY_CNTL_4,
76 		.page	= MSCC_PHY_PAGE_EXTENDED,
77 		.mask	= ERR_CNT_MASK,
78 	}, {
79 		.string	= "phy_serdes_tx_good_pkt_count",
80 		.reg	= MSCC_PHY_SERDES_TX_VALID_CNT,
81 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
82 		.mask	= VALID_CRC_CNT_CRC_MASK,
83 	}, {
84 		.string	= "phy_serdes_tx_bad_crc_count",
85 		.reg	= MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
86 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
87 		.mask	= ERR_CNT_MASK,
88 	}, {
89 		.string	= "phy_serdes_rx_good_pkt_count",
90 		.reg	= MSCC_PHY_SERDES_RX_VALID_CNT,
91 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
92 		.mask	= VALID_CRC_CNT_CRC_MASK,
93 	}, {
94 		.string	= "phy_serdes_rx_bad_crc_count",
95 		.reg	= MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
96 		.page	= MSCC_PHY_PAGE_EXTENDED_3,
97 		.mask	= ERR_CNT_MASK,
98 	},
99 };
100 
101 #if IS_ENABLED(CONFIG_OF_MDIO)
102 static const struct vsc8531_edge_rate_table edge_table[] = {
103 	{MSCC_VDDMAC_3300, { 0, 2,  4,  7, 10, 17, 29, 53} },
104 	{MSCC_VDDMAC_2500, { 0, 3,  6, 10, 14, 23, 37, 63} },
105 	{MSCC_VDDMAC_1800, { 0, 5,  9, 16, 23, 35, 52, 76} },
106 	{MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
107 };
108 #endif
109 
vsc85xx_phy_read_page(struct phy_device *phydev)110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
111 {
112 	return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
113 }
114 
vsc85xx_phy_write_page(struct phy_device *phydev, int page)115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
116 {
117 	return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
118 }
119 
vsc85xx_get_sset_count(struct phy_device *phydev)120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
121 {
122 	struct vsc8531_private *priv = phydev->priv;
123 
124 	if (!priv)
125 		return 0;
126 
127 	return priv->nstats;
128 }
129 
vsc85xx_get_strings(struct phy_device *phydev, u8 *data)130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
131 {
132 	struct vsc8531_private *priv = phydev->priv;
133 	int i;
134 
135 	if (!priv)
136 		return;
137 
138 	for (i = 0; i < priv->nstats; i++)
139 		strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
140 			ETH_GSTRING_LEN);
141 }
142 
vsc85xx_get_stat(struct phy_device *phydev, int i)143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
144 {
145 	struct vsc8531_private *priv = phydev->priv;
146 	int val;
147 
148 	val = phy_read_paged(phydev, priv->hw_stats[i].page,
149 			     priv->hw_stats[i].reg);
150 	if (val < 0)
151 		return U64_MAX;
152 
153 	val = val & priv->hw_stats[i].mask;
154 	priv->stats[i] += val;
155 
156 	return priv->stats[i];
157 }
158 
vsc85xx_get_stats(struct phy_device *phydev, struct ethtool_stats *stats, u64 *data)159 static void vsc85xx_get_stats(struct phy_device *phydev,
160 			      struct ethtool_stats *stats, u64 *data)
161 {
162 	struct vsc8531_private *priv = phydev->priv;
163 	int i;
164 
165 	if (!priv)
166 		return;
167 
168 	for (i = 0; i < priv->nstats; i++)
169 		data[i] = vsc85xx_get_stat(phydev, i);
170 }
171 
vsc85xx_led_cntl_set(struct phy_device *phydev, u8 led_num, u8 mode)172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
173 				u8 led_num,
174 				u8 mode)
175 {
176 	int rc;
177 	u16 reg_val;
178 
179 	mutex_lock(&phydev->lock);
180 	reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
181 	reg_val &= ~LED_MODE_SEL_MASK(led_num);
182 	reg_val |= LED_MODE_SEL(led_num, (u16)mode);
183 	rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
184 	mutex_unlock(&phydev->lock);
185 
186 	return rc;
187 }
188 
vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
190 {
191 	u16 reg_val;
192 
193 	reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
194 	if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
195 		*mdix = ETH_TP_MDI_X;
196 	else
197 		*mdix = ETH_TP_MDI;
198 
199 	return 0;
200 }
201 
vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
203 {
204 	int rc;
205 	u16 reg_val;
206 
207 	reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
208 	if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
209 		reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
210 			    DISABLE_POLARITY_CORR_MASK  |
211 			    DISABLE_HP_AUTO_MDIX_MASK);
212 	} else {
213 		reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
214 			     DISABLE_POLARITY_CORR_MASK  |
215 			     DISABLE_HP_AUTO_MDIX_MASK);
216 	}
217 	rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
218 	if (rc)
219 		return rc;
220 
221 	reg_val = 0;
222 
223 	if (mdix == ETH_TP_MDI)
224 		reg_val = FORCE_MDI_CROSSOVER_MDI;
225 	else if (mdix == ETH_TP_MDI_X)
226 		reg_val = FORCE_MDI_CROSSOVER_MDIX;
227 
228 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
229 			      MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
230 			      reg_val);
231 	if (rc < 0)
232 		return rc;
233 
234 	return genphy_restart_aneg(phydev);
235 }
236 
vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
238 {
239 	int reg_val;
240 
241 	reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
242 				 MSCC_PHY_ACTIPHY_CNTL);
243 	if (reg_val < 0)
244 		return reg_val;
245 
246 	reg_val &= DOWNSHIFT_CNTL_MASK;
247 	if (!(reg_val & DOWNSHIFT_EN))
248 		*count = DOWNSHIFT_DEV_DISABLE;
249 	else
250 		*count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
251 
252 	return 0;
253 }
254 
vsc85xx_downshift_set(struct phy_device *phydev, u8 count)255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
256 {
257 	if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
258 		/* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
259 		count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
260 	} else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
261 		phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
262 		return -ERANGE;
263 	} else if (count) {
264 		/* Downshift count is either 2,3,4 or 5 */
265 		count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
266 	}
267 
268 	return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
269 				MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
270 				count);
271 }
272 
vsc85xx_wol_set(struct phy_device *phydev, struct ethtool_wolinfo *wol)273 static int vsc85xx_wol_set(struct phy_device *phydev,
274 			   struct ethtool_wolinfo *wol)
275 {
276 	int rc;
277 	u16 reg_val;
278 	u8  i;
279 	u16 pwd[3] = {0, 0, 0};
280 	struct ethtool_wolinfo *wol_conf = wol;
281 	u8 *mac_addr = phydev->attached_dev->dev_addr;
282 
283 	mutex_lock(&phydev->lock);
284 	rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
285 	if (rc < 0) {
286 		rc = phy_restore_page(phydev, rc, rc);
287 		goto out_unlock;
288 	}
289 
290 	if (wol->wolopts & WAKE_MAGIC) {
291 		/* Store the device address for the magic packet */
292 		for (i = 0; i < ARRAY_SIZE(pwd); i++)
293 			pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
294 				 mac_addr[5 - i * 2];
295 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
296 		__phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
297 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
298 	} else {
299 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
300 		__phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
301 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
302 	}
303 
304 	if (wol_conf->wolopts & WAKE_MAGICSECURE) {
305 		for (i = 0; i < ARRAY_SIZE(pwd); i++)
306 			pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
307 				 wol_conf->sopass[5 - i * 2];
308 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
309 		__phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
310 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
311 	} else {
312 		__phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
313 		__phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
314 		__phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
315 	}
316 
317 	reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
318 	if (wol_conf->wolopts & WAKE_MAGICSECURE)
319 		reg_val |= SECURE_ON_ENABLE;
320 	else
321 		reg_val &= ~SECURE_ON_ENABLE;
322 	__phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
323 
324 	rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
325 	if (rc < 0)
326 		goto out_unlock;
327 
328 	if (wol->wolopts & WAKE_MAGIC) {
329 		/* Enable the WOL interrupt */
330 		reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
331 		reg_val |= MII_VSC85XX_INT_MASK_WOL;
332 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
333 		if (rc)
334 			goto out_unlock;
335 	} else {
336 		/* Disable the WOL interrupt */
337 		reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
338 		reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
339 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
340 		if (rc)
341 			goto out_unlock;
342 	}
343 	/* Clear WOL iterrupt status */
344 	reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
345 
346 out_unlock:
347 	mutex_unlock(&phydev->lock);
348 
349 	return rc;
350 }
351 
vsc85xx_wol_get(struct phy_device *phydev, struct ethtool_wolinfo *wol)352 static void vsc85xx_wol_get(struct phy_device *phydev,
353 			    struct ethtool_wolinfo *wol)
354 {
355 	int rc;
356 	u16 reg_val;
357 	u8  i;
358 	u16 pwd[3] = {0, 0, 0};
359 	struct ethtool_wolinfo *wol_conf = wol;
360 
361 	mutex_lock(&phydev->lock);
362 	rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
363 	if (rc < 0)
364 		goto out_unlock;
365 
366 	reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
367 	if (reg_val & SECURE_ON_ENABLE)
368 		wol_conf->wolopts |= WAKE_MAGICSECURE;
369 	if (wol_conf->wolopts & WAKE_MAGICSECURE) {
370 		pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
371 		pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
372 		pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
373 		for (i = 0; i < ARRAY_SIZE(pwd); i++) {
374 			wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
375 			wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
376 							    >> 8;
377 		}
378 	}
379 
380 out_unlock:
381 	phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
382 	mutex_unlock(&phydev->lock);
383 }
384 
385 #if IS_ENABLED(CONFIG_OF_MDIO)
vsc85xx_edge_rate_magic_get(struct phy_device *phydev)386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
387 {
388 	u32 vdd, sd;
389 	int i, j;
390 	struct device *dev = &phydev->mdio.dev;
391 	struct device_node *of_node = dev->of_node;
392 	u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
393 
394 	if (!of_node)
395 		return -ENODEV;
396 
397 	if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
398 		vdd = MSCC_VDDMAC_3300;
399 
400 	if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
401 		sd = 0;
402 
403 	for (i = 0; i < ARRAY_SIZE(edge_table); i++)
404 		if (edge_table[i].vddmac == vdd)
405 			for (j = 0; j < sd_array_size; j++)
406 				if (edge_table[i].slowdown[j] == sd)
407 					return (sd_array_size - j - 1);
408 
409 	return -EINVAL;
410 }
411 
vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led, u32 default_mode)412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
413 				   char *led,
414 				   u32 default_mode)
415 {
416 	struct vsc8531_private *priv = phydev->priv;
417 	struct device *dev = &phydev->mdio.dev;
418 	struct device_node *of_node = dev->of_node;
419 	u32 led_mode;
420 	int err;
421 
422 	if (!of_node)
423 		return -ENODEV;
424 
425 	led_mode = default_mode;
426 	err = of_property_read_u32(of_node, led, &led_mode);
427 	if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
428 		phydev_err(phydev, "DT %s invalid\n", led);
429 		return -EINVAL;
430 	}
431 
432 	return led_mode;
433 }
434 
435 #else
vsc85xx_edge_rate_magic_get(struct phy_device *phydev)436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
437 {
438 	return 0;
439 }
440 
vsc85xx_dt_led_mode_get(struct phy_device *phydev, char *led, u8 default_mode)441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
442 				   char *led,
443 				   u8 default_mode)
444 {
445 	return default_mode;
446 }
447 #endif /* CONFIG_OF_MDIO */
448 
vsc85xx_dt_led_modes_get(struct phy_device *phydev, u32 *default_mode)449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
450 				    u32 *default_mode)
451 {
452 	struct vsc8531_private *priv = phydev->priv;
453 	char led_dt_prop[28];
454 	int i, ret;
455 
456 	for (i = 0; i < priv->nleds; i++) {
457 		ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
458 		if (ret < 0)
459 			return ret;
460 
461 		ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
462 					      default_mode[i]);
463 		if (ret < 0)
464 			return ret;
465 		priv->leds_mode[i] = ret;
466 	}
467 
468 	return 0;
469 }
470 
vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
472 {
473 	int rc;
474 
475 	mutex_lock(&phydev->lock);
476 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
477 			      MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
478 			      edge_rate << EDGE_RATE_CNTL_POS);
479 	mutex_unlock(&phydev->lock);
480 
481 	return rc;
482 }
483 
vsc85xx_mac_if_set(struct phy_device *phydev, phy_interface_t interface)484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
485 			      phy_interface_t interface)
486 {
487 	int rc;
488 	u16 reg_val;
489 
490 	mutex_lock(&phydev->lock);
491 	reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
492 	reg_val &= ~(MAC_IF_SELECTION_MASK);
493 	switch (interface) {
494 	case PHY_INTERFACE_MODE_RGMII_TXID:
495 	case PHY_INTERFACE_MODE_RGMII_RXID:
496 	case PHY_INTERFACE_MODE_RGMII_ID:
497 	case PHY_INTERFACE_MODE_RGMII:
498 		reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
499 		break;
500 	case PHY_INTERFACE_MODE_RMII:
501 		reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
502 		break;
503 	case PHY_INTERFACE_MODE_MII:
504 	case PHY_INTERFACE_MODE_GMII:
505 		reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
506 		break;
507 	default:
508 		rc = -EINVAL;
509 		goto out_unlock;
510 	}
511 	rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
512 	if (rc)
513 		goto out_unlock;
514 
515 	rc = genphy_soft_reset(phydev);
516 
517 out_unlock:
518 	mutex_unlock(&phydev->lock);
519 
520 	return rc;
521 }
522 
523 /* Set the RGMII RX and TX clock skews individually, according to the PHY
524  * interface type, to:
525  *  * 0.2 ns (their default, and lowest, hardware value) if delays should
526  *    not be enabled
527  *  * 2.0 ns (which causes the data to be sampled at exactly half way between
528  *    clock transitions at 1000 Mbps) if delays should be enabled
529  */
vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl, u16 rgmii_rx_delay_mask, u16 rgmii_tx_delay_mask)530 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl,
531 				     u16 rgmii_rx_delay_mask,
532 				     u16 rgmii_tx_delay_mask)
533 {
534 	u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
535 	u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
536 	u16 reg_val = 0;
537 	u16 mask = 0;
538 	int rc = 0;
539 
540 	/* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit
541 	 * to be unset for all PHY modes, so do that as part of the paged
542 	 * register modification.
543 	 * For some family members (like VSC8530/31/40/41) this bit is reserved
544 	 * and read-only, and the RX clock is enabled by default.
545 	 */
546 	if (rgmii_cntl == VSC8502_RGMII_CNTL)
547 		mask |= VSC8502_RGMII_RX_CLK_DISABLE;
548 
549 	if (phy_interface_is_rgmii(phydev))
550 		mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask;
551 
552 	mutex_lock(&phydev->lock);
553 
554 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
555 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
556 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
557 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
558 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
559 		reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
560 
561 	if (mask)
562 		rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
563 				      rgmii_cntl, mask, reg_val);
564 
565 	mutex_unlock(&phydev->lock);
566 
567 	return rc;
568 }
569 
vsc85xx_default_config(struct phy_device *phydev)570 static int vsc85xx_default_config(struct phy_device *phydev)
571 {
572 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
573 
574 	return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL,
575 					 VSC8502_RGMII_RX_DELAY_MASK,
576 					 VSC8502_RGMII_TX_DELAY_MASK);
577 }
578 
vsc85xx_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data)579 static int vsc85xx_get_tunable(struct phy_device *phydev,
580 			       struct ethtool_tunable *tuna, void *data)
581 {
582 	switch (tuna->id) {
583 	case ETHTOOL_PHY_DOWNSHIFT:
584 		return vsc85xx_downshift_get(phydev, (u8 *)data);
585 	default:
586 		return -EINVAL;
587 	}
588 }
589 
vsc85xx_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data)590 static int vsc85xx_set_tunable(struct phy_device *phydev,
591 			       struct ethtool_tunable *tuna,
592 			       const void *data)
593 {
594 	switch (tuna->id) {
595 	case ETHTOOL_PHY_DOWNSHIFT:
596 		return vsc85xx_downshift_set(phydev, *(u8 *)data);
597 	default:
598 		return -EINVAL;
599 	}
600 }
601 
602 /* mdiobus lock should be locked when using this function */
vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)603 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
604 {
605 	__phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
606 	__phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
607 	__phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
608 }
609 
vsc8531_pre_init_seq_set(struct phy_device *phydev)610 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
611 {
612 	int rc;
613 	static const struct reg_val init_seq[] = {
614 		{0x0f90, 0x00688980},
615 		{0x0696, 0x00000003},
616 		{0x07fa, 0x0050100f},
617 		{0x1686, 0x00000004},
618 	};
619 	unsigned int i;
620 	int oldpage;
621 
622 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
623 			      MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
624 			      SMI_BROADCAST_WR_EN);
625 	if (rc < 0)
626 		return rc;
627 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
628 			      MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
629 	if (rc < 0)
630 		return rc;
631 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
632 			      MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
633 	if (rc < 0)
634 		return rc;
635 	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
636 			      MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
637 	if (rc < 0)
638 		return rc;
639 
640 	mutex_lock(&phydev->lock);
641 	oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
642 	if (oldpage < 0)
643 		goto out_unlock;
644 
645 	for (i = 0; i < ARRAY_SIZE(init_seq); i++)
646 		vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
647 
648 out_unlock:
649 	oldpage = phy_restore_page(phydev, oldpage, oldpage);
650 	mutex_unlock(&phydev->lock);
651 
652 	return oldpage;
653 }
654 
vsc85xx_eee_init_seq_set(struct phy_device *phydev)655 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
656 {
657 	static const struct reg_val init_eee[] = {
658 		{0x0f82, 0x0012b00a},
659 		{0x1686, 0x00000004},
660 		{0x168c, 0x00d2c46f},
661 		{0x17a2, 0x00000620},
662 		{0x16a0, 0x00eeffdd},
663 		{0x16a6, 0x00071448},
664 		{0x16a4, 0x0013132f},
665 		{0x16a8, 0x00000000},
666 		{0x0ffc, 0x00c0a028},
667 		{0x0fe8, 0x0091b06c},
668 		{0x0fea, 0x00041600},
669 		{0x0f80, 0x00000af4},
670 		{0x0fec, 0x00901809},
671 		{0x0fee, 0x0000a6a1},
672 		{0x0ffe, 0x00b01007},
673 		{0x16b0, 0x00eeff00},
674 		{0x16b2, 0x00007000},
675 		{0x16b4, 0x00000814},
676 	};
677 	unsigned int i;
678 	int oldpage;
679 
680 	mutex_lock(&phydev->lock);
681 	oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
682 	if (oldpage < 0)
683 		goto out_unlock;
684 
685 	for (i = 0; i < ARRAY_SIZE(init_eee); i++)
686 		vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
687 
688 out_unlock:
689 	oldpage = phy_restore_page(phydev, oldpage, oldpage);
690 	mutex_unlock(&phydev->lock);
691 
692 	return oldpage;
693 }
694 
695 /* phydev->bus->mdio_lock should be locked when using this function */
phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)696 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
697 {
698 	if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
699 		dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
700 		dump_stack();
701 	}
702 
703 	return __phy_package_write(phydev, regnum, val);
704 }
705 
706 /* phydev->bus->mdio_lock should be locked when using this function */
phy_base_read(struct phy_device *phydev, u32 regnum)707 static int phy_base_read(struct phy_device *phydev, u32 regnum)
708 {
709 	if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
710 		dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
711 		dump_stack();
712 	}
713 
714 	return __phy_package_read(phydev, regnum);
715 }
716 
vsc85xx_csr_read(struct phy_device *phydev, enum csr_target target, u32 reg)717 static u32 vsc85xx_csr_read(struct phy_device *phydev,
718 			    enum csr_target target, u32 reg)
719 {
720 	unsigned long deadline;
721 	u32 val, val_l, val_h;
722 
723 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
724 
725 	/* CSR registers are grouped under different Target IDs.
726 	 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
727 	 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
728 	 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
729 	 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
730 	 */
731 
732 	/* Setup the Target ID */
733 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
734 		       MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
735 
736 	if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
737 		/* non-MACsec access */
738 		target &= 0x3;
739 	else
740 		target = 0;
741 
742 	/* Trigger CSR Action - Read into the CSR's */
743 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
744 		       MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
745 		       MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
746 		       MSCC_PHY_CSR_CNTL_19_TARGET(target));
747 
748 	/* Wait for register access*/
749 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
750 	do {
751 		usleep_range(500, 1000);
752 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
753 	} while (time_before(jiffies, deadline) &&
754 		!(val & MSCC_PHY_CSR_CNTL_19_CMD));
755 
756 	if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
757 		return 0xffffffff;
758 
759 	/* Read the Least Significant Word (LSW) (17) */
760 	val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
761 
762 	/* Read the Most Significant Word (MSW) (18) */
763 	val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
764 
765 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
766 		       MSCC_PHY_PAGE_STANDARD);
767 
768 	return (val_h << 16) | val_l;
769 }
770 
vsc85xx_csr_write(struct phy_device *phydev, enum csr_target target, u32 reg, u32 val)771 static int vsc85xx_csr_write(struct phy_device *phydev,
772 			     enum csr_target target, u32 reg, u32 val)
773 {
774 	unsigned long deadline;
775 
776 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
777 
778 	/* CSR registers are grouped under different Target IDs.
779 	 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
780 	 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
781 	 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
782 	 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
783 	 */
784 
785 	/* Setup the Target ID */
786 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
787 		       MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
788 
789 	/* Write the Least Significant Word (LSW) (17) */
790 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
791 
792 	/* Write the Most Significant Word (MSW) (18) */
793 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
794 
795 	if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
796 		/* non-MACsec access */
797 		target &= 0x3;
798 	else
799 		target = 0;
800 
801 	/* Trigger CSR Action - Write into the CSR's */
802 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
803 		       MSCC_PHY_CSR_CNTL_19_CMD |
804 		       MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
805 		       MSCC_PHY_CSR_CNTL_19_TARGET(target));
806 
807 	/* Wait for register access */
808 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
809 	do {
810 		usleep_range(500, 1000);
811 		val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
812 	} while (time_before(jiffies, deadline) &&
813 		 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
814 
815 	if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
816 		return -ETIMEDOUT;
817 
818 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
819 		       MSCC_PHY_PAGE_STANDARD);
820 
821 	return 0;
822 }
823 
824 /* bus->mdio_lock should be locked when using this function */
vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)825 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
826 {
827 	phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
828 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
829 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
830 }
831 
832 /* bus->mdio_lock should be locked when using this function */
vsc8584_cmd(struct phy_device *phydev, u16 val)833 static int vsc8584_cmd(struct phy_device *phydev, u16 val)
834 {
835 	unsigned long deadline;
836 	u16 reg_val;
837 
838 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
839 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
840 
841 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
842 
843 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
844 	do {
845 		reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
846 	} while (time_before(jiffies, deadline) &&
847 		 (reg_val & PROC_CMD_NCOMPLETED) &&
848 		 !(reg_val & PROC_CMD_FAILED));
849 
850 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
851 
852 	if (reg_val & PROC_CMD_FAILED)
853 		return -EIO;
854 
855 	if (reg_val & PROC_CMD_NCOMPLETED)
856 		return -ETIMEDOUT;
857 
858 	return 0;
859 }
860 
861 /* bus->mdio_lock should be locked when using this function */
vsc8584_micro_deassert_reset(struct phy_device *phydev, bool patch_en)862 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
863 					bool patch_en)
864 {
865 	u32 enable, release;
866 
867 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
868 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
869 
870 	enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
871 	release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
872 		MICRO_CLK_EN;
873 
874 	if (patch_en) {
875 		enable |= MICRO_PATCH_EN;
876 		release |= MICRO_PATCH_EN;
877 
878 		/* Clear all patches */
879 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
880 	}
881 
882 	/* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
883 	 * override and addr. auto-incr; operate at 125 MHz
884 	 */
885 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
886 	/* Release 8051 Micro SW reset */
887 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
888 
889 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
890 
891 	return 0;
892 }
893 
894 /* bus->mdio_lock should be locked when using this function */
vsc8584_micro_assert_reset(struct phy_device *phydev)895 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
896 {
897 	int ret;
898 	u16 reg;
899 
900 	ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
901 	if (ret)
902 		return ret;
903 
904 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
905 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
906 
907 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
908 	reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
909 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
910 
911 	phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
912 	phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
913 
914 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
915 	reg |= EN_PATCH_RAM_TRAP_ADDR(4);
916 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
917 
918 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
919 
920 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
921 	reg &= ~MICRO_NSOFT_RESET;
922 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
923 
924 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
925 		       PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
926 		       PROC_CMD_READ);
927 
928 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
929 	reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
930 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
931 
932 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
933 
934 	return 0;
935 }
936 
937 /* bus->mdio_lock should be locked when using this function */
vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, u16 *crc)938 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
939 			      u16 *crc)
940 {
941 	int ret;
942 
943 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
944 
945 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
946 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
947 
948 	/* Start Micro command */
949 	ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
950 	if (ret)
951 		goto out;
952 
953 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
954 
955 	*crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
956 
957 out:
958 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
959 
960 	return ret;
961 }
962 
963 /* bus->mdio_lock should be locked when using this function */
vsc8584_patch_fw(struct phy_device *phydev, const struct firmware *fw)964 static int vsc8584_patch_fw(struct phy_device *phydev,
965 			    const struct firmware *fw)
966 {
967 	int i, ret;
968 
969 	ret = vsc8584_micro_assert_reset(phydev);
970 	if (ret) {
971 		dev_err(&phydev->mdio.dev,
972 			"%s: failed to assert reset of micro\n", __func__);
973 		return ret;
974 	}
975 
976 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
977 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
978 
979 	/* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
980 	 * Disable the 8051 Micro clock
981 	 */
982 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
983 		       AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
984 		       MICRO_CLK_DIVIDE(2));
985 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
986 		       INT_MEM_DATA(2));
987 	phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
988 
989 	for (i = 0; i < fw->size; i++)
990 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
991 			       INT_MEM_WRITE_EN | fw->data[i]);
992 
993 	/* Clear internal memory access */
994 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
995 
996 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
997 
998 	return 0;
999 }
1000 
1001 /* bus->mdio_lock should be locked when using this function */
vsc8574_is_serdes_init(struct phy_device *phydev)1002 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1003 {
1004 	u16 reg;
1005 	bool ret;
1006 
1007 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1008 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
1009 
1010 	reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1011 	if (reg != 0x3eb7) {
1012 		ret = false;
1013 		goto out;
1014 	}
1015 
1016 	reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1017 	if (reg != 0x4012) {
1018 		ret = false;
1019 		goto out;
1020 	}
1021 
1022 	reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1023 	if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1024 		ret = false;
1025 		goto out;
1026 	}
1027 
1028 	reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1029 	if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM |  DW8051_CLK_EN |
1030 	     MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1031 		ret = false;
1032 		goto out;
1033 	}
1034 
1035 	ret = true;
1036 out:
1037 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1038 
1039 	return ret;
1040 }
1041 
1042 /* bus->mdio_lock should be locked when using this function */
vsc8574_config_pre_init(struct phy_device *phydev)1043 static int vsc8574_config_pre_init(struct phy_device *phydev)
1044 {
1045 	static const struct reg_val pre_init1[] = {
1046 		{0x0fae, 0x000401bd},
1047 		{0x0fac, 0x000f000f},
1048 		{0x17a0, 0x00a0f147},
1049 		{0x0fe4, 0x00052f54},
1050 		{0x1792, 0x0027303d},
1051 		{0x07fe, 0x00000704},
1052 		{0x0fe0, 0x00060150},
1053 		{0x0f82, 0x0012b00a},
1054 		{0x0f80, 0x00000d74},
1055 		{0x02e0, 0x00000012},
1056 		{0x03a2, 0x00050208},
1057 		{0x03b2, 0x00009186},
1058 		{0x0fb0, 0x000e3700},
1059 		{0x1688, 0x00049f81},
1060 		{0x0fd2, 0x0000ffff},
1061 		{0x168a, 0x00039fa2},
1062 		{0x1690, 0x0020640b},
1063 		{0x0258, 0x00002220},
1064 		{0x025a, 0x00002a20},
1065 		{0x025c, 0x00003060},
1066 		{0x025e, 0x00003fa0},
1067 		{0x03a6, 0x0000e0f0},
1068 		{0x0f92, 0x00001489},
1069 		{0x16a2, 0x00007000},
1070 		{0x16a6, 0x00071448},
1071 		{0x16a0, 0x00eeffdd},
1072 		{0x0fe8, 0x0091b06c},
1073 		{0x0fea, 0x00041600},
1074 		{0x16b0, 0x00eeff00},
1075 		{0x16b2, 0x00007000},
1076 		{0x16b4, 0x00000814},
1077 		{0x0f90, 0x00688980},
1078 		{0x03a4, 0x0000d8f0},
1079 		{0x0fc0, 0x00000400},
1080 		{0x07fa, 0x0050100f},
1081 		{0x0796, 0x00000003},
1082 		{0x07f8, 0x00c3ff98},
1083 		{0x0fa4, 0x0018292a},
1084 		{0x168c, 0x00d2c46f},
1085 		{0x17a2, 0x00000620},
1086 		{0x16a4, 0x0013132f},
1087 		{0x16a8, 0x00000000},
1088 		{0x0ffc, 0x00c0a028},
1089 		{0x0fec, 0x00901c09},
1090 		{0x0fee, 0x0004a6a1},
1091 		{0x0ffe, 0x00b01807},
1092 	};
1093 	static const struct reg_val pre_init2[] = {
1094 		{0x0486, 0x0008a518},
1095 		{0x0488, 0x006dc696},
1096 		{0x048a, 0x00000912},
1097 		{0x048e, 0x00000db6},
1098 		{0x049c, 0x00596596},
1099 		{0x049e, 0x00000514},
1100 		{0x04a2, 0x00410280},
1101 		{0x04a4, 0x00000000},
1102 		{0x04a6, 0x00000000},
1103 		{0x04a8, 0x00000000},
1104 		{0x04aa, 0x00000000},
1105 		{0x04ae, 0x007df7dd},
1106 		{0x04b0, 0x006d95d4},
1107 		{0x04b2, 0x00492410},
1108 	};
1109 	struct device *dev = &phydev->mdio.dev;
1110 	const struct firmware *fw;
1111 	unsigned int i;
1112 	u16 crc, reg;
1113 	bool serdes_init;
1114 	int ret;
1115 
1116 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1117 
1118 	/* all writes below are broadcasted to all PHYs in the same package */
1119 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1120 	reg |= SMI_BROADCAST_WR_EN;
1121 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1122 
1123 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1124 
1125 	/* The below register writes are tweaking analog and electrical
1126 	 * configuration that were determined through characterization by PHY
1127 	 * engineers. These don't mean anything more than "these are the best
1128 	 * values".
1129 	 */
1130 	phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1131 
1132 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1133 
1134 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1135 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1136 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1137 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1138 
1139 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1140 	reg |= TR_CLK_DISABLE;
1141 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1142 
1143 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1144 
1145 	for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1146 		vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1147 
1148 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1149 
1150 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1151 
1152 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1153 
1154 	for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1155 		vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1156 
1157 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1158 
1159 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1160 	reg &= ~TR_CLK_DISABLE;
1161 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1162 
1163 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1164 
1165 	/* end of write broadcasting */
1166 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1167 	reg &= ~SMI_BROADCAST_WR_EN;
1168 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1169 
1170 	ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1171 	if (ret) {
1172 		dev_err(dev, "failed to load firmware %s, ret: %d\n",
1173 			MSCC_VSC8574_REVB_INT8051_FW, ret);
1174 		return ret;
1175 	}
1176 
1177 	/* Add one byte to size for the one added by the patch_fw function */
1178 	ret = vsc8584_get_fw_crc(phydev,
1179 				 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1180 				 fw->size + 1, &crc);
1181 	if (ret)
1182 		goto out;
1183 
1184 	if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1185 		serdes_init = vsc8574_is_serdes_init(phydev);
1186 
1187 		if (!serdes_init) {
1188 			ret = vsc8584_micro_assert_reset(phydev);
1189 			if (ret) {
1190 				dev_err(dev,
1191 					"%s: failed to assert reset of micro\n",
1192 					__func__);
1193 				goto out;
1194 			}
1195 		}
1196 	} else {
1197 		dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1198 
1199 		serdes_init = false;
1200 
1201 		if (vsc8584_patch_fw(phydev, fw))
1202 			dev_warn(dev,
1203 				 "failed to patch FW, expect non-optimal device\n");
1204 	}
1205 
1206 	if (!serdes_init) {
1207 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1208 			       MSCC_PHY_PAGE_EXTENDED_GPIO);
1209 
1210 		phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1211 		phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1212 		phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1213 			       EN_PATCH_RAM_TRAP_ADDR(1));
1214 
1215 		vsc8584_micro_deassert_reset(phydev, false);
1216 
1217 		/* Add one byte to size for the one added by the patch_fw
1218 		 * function
1219 		 */
1220 		ret = vsc8584_get_fw_crc(phydev,
1221 					 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1222 					 fw->size + 1, &crc);
1223 		if (ret)
1224 			goto out;
1225 
1226 		if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1227 			dev_warn(dev,
1228 				 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1229 	}
1230 
1231 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1232 		       MSCC_PHY_PAGE_EXTENDED_GPIO);
1233 
1234 	ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1235 			  PROC_CMD_PHY_INIT);
1236 
1237 out:
1238 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1239 
1240 	release_firmware(fw);
1241 
1242 	return ret;
1243 }
1244 
1245 /* Access LCPLL Cfg_2 */
vsc8584_pll5g_cfg2_wr(struct phy_device *phydev, bool disable_fsm)1246 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev,
1247 				  bool disable_fsm)
1248 {
1249 	u32 rd_dat;
1250 
1251 	rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
1252 	rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS);
1253 	rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS);
1254 	vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat);
1255 }
1256 
1257 /* trigger a read to the spcified MCB */
vsc8584_mcb_rd_trig(struct phy_device *phydev, u32 mcb_reg_addr, u8 mcb_slave_num)1258 static int vsc8584_mcb_rd_trig(struct phy_device *phydev,
1259 			       u32 mcb_reg_addr, u8 mcb_slave_num)
1260 {
1261 	u32 rd_dat = 0;
1262 
1263 	/* read MCB */
1264 	vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1265 			  (0x40000000 | (1L << mcb_slave_num)));
1266 
1267 	return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1268 				 !(rd_dat & 0x40000000),
1269 				 4000, 200000, 0,
1270 				 phydev, MACRO_CTRL, mcb_reg_addr);
1271 }
1272 
1273 /* trigger a write to the spcified MCB */
vsc8584_mcb_wr_trig(struct phy_device *phydev, u32 mcb_reg_addr, u8 mcb_slave_num)1274 static int vsc8584_mcb_wr_trig(struct phy_device *phydev,
1275 			       u32 mcb_reg_addr,
1276 			       u8 mcb_slave_num)
1277 {
1278 	u32 rd_dat = 0;
1279 
1280 	/* write back MCB */
1281 	vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1282 			  (0x80000000 | (1L << mcb_slave_num)));
1283 
1284 	return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1285 				 !(rd_dat & 0x80000000),
1286 				 4000, 200000, 0,
1287 				 phydev, MACRO_CTRL, mcb_reg_addr);
1288 }
1289 
1290 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */
vsc8584_pll5g_reset(struct phy_device *phydev)1291 static int vsc8584_pll5g_reset(struct phy_device *phydev)
1292 {
1293 	bool dis_fsm;
1294 	int ret = 0;
1295 
1296 	ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1297 	if (ret < 0)
1298 		goto done;
1299 	dis_fsm = 1;
1300 
1301 	/* Reset LCPLL */
1302 	vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1303 
1304 	/* write back LCPLL MCB */
1305 	ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1306 	if (ret < 0)
1307 		goto done;
1308 
1309 	/* 10 mSec sleep while LCPLL is hold in reset */
1310 	usleep_range(10000, 20000);
1311 
1312 	/* read LCPLL MCB into CSRs */
1313 	ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1314 	if (ret < 0)
1315 		goto done;
1316 	dis_fsm = 0;
1317 
1318 	/* Release the Reset of LCPLL */
1319 	vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1320 
1321 	/* write back LCPLL MCB */
1322 	ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1323 	if (ret < 0)
1324 		goto done;
1325 
1326 	usleep_range(110000, 200000);
1327 done:
1328 	return ret;
1329 }
1330 
1331 /* bus->mdio_lock should be locked when using this function */
vsc8584_config_pre_init(struct phy_device *phydev)1332 static int vsc8584_config_pre_init(struct phy_device *phydev)
1333 {
1334 	static const struct reg_val pre_init1[] = {
1335 		{0x07fa, 0x0050100f},
1336 		{0x1688, 0x00049f81},
1337 		{0x0f90, 0x00688980},
1338 		{0x03a4, 0x0000d8f0},
1339 		{0x0fc0, 0x00000400},
1340 		{0x0f82, 0x0012b002},
1341 		{0x1686, 0x00000004},
1342 		{0x168c, 0x00d2c46f},
1343 		{0x17a2, 0x00000620},
1344 		{0x16a0, 0x00eeffdd},
1345 		{0x16a6, 0x00071448},
1346 		{0x16a4, 0x0013132f},
1347 		{0x16a8, 0x00000000},
1348 		{0x0ffc, 0x00c0a028},
1349 		{0x0fe8, 0x0091b06c},
1350 		{0x0fea, 0x00041600},
1351 		{0x0f80, 0x00fffaff},
1352 		{0x0fec, 0x00901809},
1353 		{0x0ffe, 0x00b01007},
1354 		{0x16b0, 0x00eeff00},
1355 		{0x16b2, 0x00007000},
1356 		{0x16b4, 0x00000814},
1357 	};
1358 	static const struct reg_val pre_init2[] = {
1359 		{0x0486, 0x0008a518},
1360 		{0x0488, 0x006dc696},
1361 		{0x048a, 0x00000912},
1362 	};
1363 	const struct firmware *fw;
1364 	struct device *dev = &phydev->mdio.dev;
1365 	unsigned int i;
1366 	u16 crc, reg;
1367 	int ret;
1368 
1369 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1370 
1371 	/* all writes below are broadcasted to all PHYs in the same package */
1372 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1373 	reg |= SMI_BROADCAST_WR_EN;
1374 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1375 
1376 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1377 
1378 	reg = phy_base_read(phydev,  MSCC_PHY_BYPASS_CONTROL);
1379 	reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1380 	phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1381 
1382 	/* The below register writes are tweaking analog and electrical
1383 	 * configuration that were determined through characterization by PHY
1384 	 * engineers. These don't mean anything more than "these are the best
1385 	 * values".
1386 	 */
1387 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1388 
1389 	phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1390 
1391 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1392 
1393 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1394 
1395 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1396 	reg |= TR_CLK_DISABLE;
1397 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1398 
1399 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1400 
1401 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1402 
1403 	reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1404 	reg &= ~0x007f;
1405 	reg |= 0x0019;
1406 	phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1407 
1408 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1409 
1410 	for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1411 		vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1412 
1413 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1414 
1415 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1416 
1417 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1418 
1419 	for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1420 		vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1421 
1422 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1423 
1424 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1425 	reg &= ~TR_CLK_DISABLE;
1426 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1427 
1428 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1429 
1430 	/* end of write broadcasting */
1431 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1432 	reg &= ~SMI_BROADCAST_WR_EN;
1433 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1434 
1435 	ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1436 	if (ret) {
1437 		dev_err(dev, "failed to load firmware %s, ret: %d\n",
1438 			MSCC_VSC8584_REVB_INT8051_FW, ret);
1439 		return ret;
1440 	}
1441 
1442 	/* Add one byte to size for the one added by the patch_fw function */
1443 	ret = vsc8584_get_fw_crc(phydev,
1444 				 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1445 				 fw->size + 1, &crc);
1446 	if (ret)
1447 		goto out;
1448 
1449 	if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1450 		dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1451 		if (vsc8584_patch_fw(phydev, fw))
1452 			dev_warn(dev,
1453 				 "failed to patch FW, expect non-optimal device\n");
1454 	}
1455 
1456 	vsc8584_micro_deassert_reset(phydev, false);
1457 
1458 	/* Add one byte to size for the one added by the patch_fw function */
1459 	ret = vsc8584_get_fw_crc(phydev,
1460 				 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1461 				 fw->size + 1, &crc);
1462 	if (ret)
1463 		goto out;
1464 
1465 	if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1466 		dev_warn(dev,
1467 			 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1468 
1469 	ret = vsc8584_micro_assert_reset(phydev);
1470 	if (ret)
1471 		goto out;
1472 
1473 	vsc8584_micro_deassert_reset(phydev, true);
1474 
1475 out:
1476 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1477 
1478 	release_firmware(fw);
1479 
1480 	return ret;
1481 }
1482 
vsc8584_get_base_addr(struct phy_device *phydev)1483 static void vsc8584_get_base_addr(struct phy_device *phydev)
1484 {
1485 	struct vsc8531_private *vsc8531 = phydev->priv;
1486 	u16 val, addr;
1487 
1488 	phy_lock_mdio_bus(phydev);
1489 	__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1490 
1491 	addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1492 	addr >>= PHY_CNTL_4_ADDR_POS;
1493 
1494 	val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1495 
1496 	__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1497 	phy_unlock_mdio_bus(phydev);
1498 
1499 	/* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1500 	 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1501 	 * the base PHY for timestamping operations.
1502 	 */
1503 	vsc8531->ts_base_addr = phydev->mdio.addr;
1504 	vsc8531->ts_base_phy = addr;
1505 
1506 	if (val & PHY_ADDR_REVERSED) {
1507 		vsc8531->base_addr = phydev->mdio.addr + addr;
1508 		if (addr > 1) {
1509 			vsc8531->ts_base_addr += 2;
1510 			vsc8531->ts_base_phy += 2;
1511 		}
1512 	} else {
1513 		vsc8531->base_addr = phydev->mdio.addr - addr;
1514 		if (addr > 1) {
1515 			vsc8531->ts_base_addr -= 2;
1516 			vsc8531->ts_base_phy -= 2;
1517 		}
1518 	}
1519 
1520 	vsc8531->addr = addr;
1521 }
1522 
vsc8584_config_init(struct phy_device *phydev)1523 static int vsc8584_config_init(struct phy_device *phydev)
1524 {
1525 	struct vsc8531_private *vsc8531 = phydev->priv;
1526 	int ret, i;
1527 	u16 val;
1528 
1529 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1530 
1531 	phy_lock_mdio_bus(phydev);
1532 
1533 	/* Some parts of the init sequence are identical for every PHY in the
1534 	 * package. Some parts are modifying the GPIO register bank which is a
1535 	 * set of registers that are affecting all PHYs, a few resetting the
1536 	 * microprocessor common to all PHYs. The CRC check responsible of the
1537 	 * checking the firmware within the 8051 microprocessor can only be
1538 	 * accessed via the PHY whose internal address in the package is 0.
1539 	 * All PHYs' interrupts mask register has to be zeroed before enabling
1540 	 * any PHY's interrupt in this register.
1541 	 * For all these reasons, we need to do the init sequence once and only
1542 	 * once whatever is the first PHY in the package that is initialized and
1543 	 * do the correct init sequence for all PHYs that are package-critical
1544 	 * in this pre-init function.
1545 	 */
1546 	if (phy_package_init_once(phydev)) {
1547 		/* The following switch statement assumes that the lowest
1548 		 * nibble of the phy_id_mask is always 0. This works because
1549 		 * the lowest nibble of the PHY_ID's below are also 0.
1550 		 */
1551 		WARN_ON(phydev->drv->phy_id_mask & 0xf);
1552 
1553 		switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1554 		case PHY_ID_VSC8504:
1555 		case PHY_ID_VSC8552:
1556 		case PHY_ID_VSC8572:
1557 		case PHY_ID_VSC8574:
1558 			ret = vsc8574_config_pre_init(phydev);
1559 			break;
1560 		case PHY_ID_VSC856X:
1561 		case PHY_ID_VSC8575:
1562 		case PHY_ID_VSC8582:
1563 		case PHY_ID_VSC8584:
1564 			ret = vsc8584_config_pre_init(phydev);
1565 			break;
1566 		default:
1567 			ret = -EINVAL;
1568 			break;
1569 		}
1570 
1571 		if (ret)
1572 			goto err;
1573 	}
1574 
1575 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1576 			     MSCC_PHY_PAGE_EXTENDED_GPIO);
1577 	if (ret)
1578 		goto err;
1579 
1580 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1581 	val &= ~MAC_CFG_MASK;
1582 	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1583 		val |= MAC_CFG_QSGMII;
1584 	} else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1585 		val |= MAC_CFG_SGMII;
1586 	} else if (phy_interface_is_rgmii(phydev)) {
1587 		val |= MAC_CFG_RGMII;
1588 	} else {
1589 		ret = -EINVAL;
1590 		goto err;
1591 	}
1592 
1593 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1594 	if (ret)
1595 		goto err;
1596 
1597 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1598 			     MSCC_PHY_PAGE_STANDARD);
1599 	if (ret)
1600 		goto err;
1601 
1602 	if (!phy_interface_is_rgmii(phydev)) {
1603 		val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1604 			PROC_CMD_READ_MOD_WRITE_PORT;
1605 		if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1606 			val |= PROC_CMD_QSGMII_MAC;
1607 		else
1608 			val |= PROC_CMD_SGMII_MAC;
1609 
1610 		ret = vsc8584_cmd(phydev, val);
1611 		if (ret)
1612 			goto err;
1613 
1614 		usleep_range(10000, 20000);
1615 	}
1616 
1617 	/* Disable SerDes for 100Base-FX */
1618 	ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1619 			  PROC_CMD_FIBER_PORT(vsc8531->addr) |
1620 			  PROC_CMD_FIBER_DISABLE |
1621 			  PROC_CMD_READ_MOD_WRITE_PORT |
1622 			  PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1623 	if (ret)
1624 		goto err;
1625 
1626 	/* Disable SerDes for 1000Base-X */
1627 	ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1628 			  PROC_CMD_FIBER_PORT(vsc8531->addr) |
1629 			  PROC_CMD_FIBER_DISABLE |
1630 			  PROC_CMD_READ_MOD_WRITE_PORT |
1631 			  PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1632 	if (ret)
1633 		goto err;
1634 
1635 	phy_unlock_mdio_bus(phydev);
1636 
1637 	ret = vsc8584_macsec_init(phydev);
1638 	if (ret)
1639 		return ret;
1640 
1641 	ret = vsc8584_ptp_init(phydev);
1642 	if (ret)
1643 		return ret;
1644 
1645 	val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1646 	val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1647 	val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1648 	       (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1649 	ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1650 	if (ret)
1651 		return ret;
1652 
1653 	ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL,
1654 					VSC8572_RGMII_RX_DELAY_MASK,
1655 					VSC8572_RGMII_TX_DELAY_MASK);
1656 	if (ret)
1657 		return ret;
1658 
1659 	ret = genphy_soft_reset(phydev);
1660 	if (ret)
1661 		return ret;
1662 
1663 	for (i = 0; i < vsc8531->nleds; i++) {
1664 		ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1665 		if (ret)
1666 			return ret;
1667 	}
1668 
1669 	return 0;
1670 
1671 err:
1672 	phy_unlock_mdio_bus(phydev);
1673 	return ret;
1674 }
1675 
vsc8584_handle_interrupt(struct phy_device *phydev)1676 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1677 {
1678 	irqreturn_t ret;
1679 	int irq_status;
1680 
1681 	irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1682 	if (irq_status < 0)
1683 		return IRQ_NONE;
1684 
1685 	/* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1686 	 * irq_status would be 0.
1687 	 */
1688 	ret = vsc8584_handle_ts_interrupt(phydev);
1689 	if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1690 		return ret;
1691 
1692 	if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1693 		vsc8584_handle_macsec_interrupt(phydev);
1694 
1695 	if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1696 		phy_mac_interrupt(phydev);
1697 
1698 	return IRQ_HANDLED;
1699 }
1700 
vsc85xx_config_init(struct phy_device *phydev)1701 static int vsc85xx_config_init(struct phy_device *phydev)
1702 {
1703 	int rc, i, phy_id;
1704 	struct vsc8531_private *vsc8531 = phydev->priv;
1705 
1706 	rc = vsc85xx_default_config(phydev);
1707 	if (rc)
1708 		return rc;
1709 
1710 	rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1711 	if (rc)
1712 		return rc;
1713 
1714 	rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1715 	if (rc)
1716 		return rc;
1717 
1718 	phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1719 	if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1720 	    PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1721 		rc = vsc8531_pre_init_seq_set(phydev);
1722 		if (rc)
1723 			return rc;
1724 	}
1725 
1726 	rc = vsc85xx_eee_init_seq_set(phydev);
1727 	if (rc)
1728 		return rc;
1729 
1730 	for (i = 0; i < vsc8531->nleds; i++) {
1731 		rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1732 		if (rc)
1733 			return rc;
1734 	}
1735 
1736 	return 0;
1737 }
1738 
vsc8584_did_interrupt(struct phy_device *phydev)1739 static int vsc8584_did_interrupt(struct phy_device *phydev)
1740 {
1741 	int rc = 0;
1742 
1743 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
1744 		rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1745 
1746 	return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK;
1747 }
1748 
vsc8514_config_pre_init(struct phy_device *phydev)1749 static int vsc8514_config_pre_init(struct phy_device *phydev)
1750 {
1751 	/* These are the settings to override the silicon default
1752 	 * values to handle hardware performance of PHY. They
1753 	 * are set at Power-On state and remain until PHY Reset.
1754 	 */
1755 	static const struct reg_val pre_init1[] = {
1756 		{0x0f90, 0x00688980},
1757 		{0x0786, 0x00000003},
1758 		{0x07fa, 0x0050100f},
1759 		{0x0f82, 0x0012b002},
1760 		{0x1686, 0x00000004},
1761 		{0x168c, 0x00d2c46f},
1762 		{0x17a2, 0x00000620},
1763 		{0x16a0, 0x00eeffdd},
1764 		{0x16a6, 0x00071448},
1765 		{0x16a4, 0x0013132f},
1766 		{0x16a8, 0x00000000},
1767 		{0x0ffc, 0x00c0a028},
1768 		{0x0fe8, 0x0091b06c},
1769 		{0x0fea, 0x00041600},
1770 		{0x0f80, 0x00fffaff},
1771 		{0x0fec, 0x00901809},
1772 		{0x0ffe, 0x00b01007},
1773 		{0x16b0, 0x00eeff00},
1774 		{0x16b2, 0x00007000},
1775 		{0x16b4, 0x00000814},
1776 	};
1777 	struct device *dev = &phydev->mdio.dev;
1778 	unsigned int i;
1779 	u16 reg;
1780 	int ret;
1781 
1782 	ret = vsc8584_pll5g_reset(phydev);
1783 	if (ret < 0) {
1784 		dev_err(dev, "failed LCPLL reset, ret: %d\n", ret);
1785 		return ret;
1786 	}
1787 
1788 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1789 
1790 	/* all writes below are broadcasted to all PHYs in the same package */
1791 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1792 	reg |= SMI_BROADCAST_WR_EN;
1793 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1794 
1795 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1796 
1797 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1798 	reg |= BIT(15);
1799 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1800 
1801 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1802 
1803 	for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1804 		vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1805 
1806 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1807 
1808 	reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1809 	reg &= ~BIT(15);
1810 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1811 
1812 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1813 
1814 	reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1815 	reg &= ~SMI_BROADCAST_WR_EN;
1816 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1817 
1818 	return 0;
1819 }
1820 
__phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, u32 op)1821 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1822 			       u32 op)
1823 {
1824 	unsigned long deadline;
1825 	u32 val;
1826 	int ret;
1827 
1828 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1829 				op | (1 << mcb));
1830 	if (ret)
1831 		return -EINVAL;
1832 
1833 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1834 	do {
1835 		usleep_range(500, 1000);
1836 		val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1837 
1838 		if (val == 0xffffffff)
1839 			return -EIO;
1840 
1841 	} while (time_before(jiffies, deadline) && (val & op));
1842 
1843 	if (val & op)
1844 		return -ETIMEDOUT;
1845 
1846 	return 0;
1847 }
1848 
1849 /* Trigger a read to the specified MCB */
phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)1850 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1851 {
1852 	return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1853 }
1854 
1855 /* Trigger a write to the specified MCB */
phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)1856 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1857 {
1858 	return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1859 }
1860 
vsc8514_config_init(struct phy_device *phydev)1861 static int vsc8514_config_init(struct phy_device *phydev)
1862 {
1863 	struct vsc8531_private *vsc8531 = phydev->priv;
1864 	unsigned long deadline;
1865 	int ret, i;
1866 	u16 val;
1867 	u32 reg;
1868 
1869 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1870 
1871 	phy_lock_mdio_bus(phydev);
1872 
1873 	/* Some parts of the init sequence are identical for every PHY in the
1874 	 * package. Some parts are modifying the GPIO register bank which is a
1875 	 * set of registers that are affecting all PHYs, a few resetting the
1876 	 * microprocessor common to all PHYs.
1877 	 * All PHYs' interrupts mask register has to be zeroed before enabling
1878 	 * any PHY's interrupt in this register.
1879 	 * For all these reasons, we need to do the init sequence once and only
1880 	 * once whatever is the first PHY in the package that is initialized and
1881 	 * do the correct init sequence for all PHYs that are package-critical
1882 	 * in this pre-init function.
1883 	 */
1884 	if (phy_package_init_once(phydev))
1885 		vsc8514_config_pre_init(phydev);
1886 
1887 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1888 			     MSCC_PHY_PAGE_EXTENDED_GPIO);
1889 	if (ret)
1890 		goto err;
1891 
1892 	val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1893 
1894 	val &= ~MAC_CFG_MASK;
1895 	val |= MAC_CFG_QSGMII;
1896 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1897 	if (ret)
1898 		goto err;
1899 
1900 	ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1901 			     MSCC_PHY_PAGE_STANDARD);
1902 	if (ret)
1903 		goto err;
1904 
1905 	ret = vsc8584_cmd(phydev,
1906 			  PROC_CMD_MCB_ACCESS_MAC_CONF |
1907 			  PROC_CMD_RST_CONF_PORT |
1908 			  PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1909 	if (ret)
1910 		goto err;
1911 
1912 	/* 6g mcb */
1913 	phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1914 	/* lcpll mcb */
1915 	phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1916 	/* pll5gcfg0 */
1917 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1918 				PHY_S6G_PLL5G_CFG0, 0x7036f145);
1919 	if (ret)
1920 		goto err;
1921 
1922 	phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0);
1923 	/* pllcfg */
1924 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1925 				PHY_S6G_PLL_CFG,
1926 				(3 << PHY_S6G_PLL_ENA_OFFS_POS) |
1927 				(120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS)
1928 				| (0 << PHY_S6G_PLL_FSM_ENA_POS));
1929 	if (ret)
1930 		goto err;
1931 
1932 	/* commoncfg */
1933 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1934 				PHY_S6G_COMMON_CFG,
1935 				(0 << PHY_S6G_SYS_RST_POS) |
1936 				(0 << PHY_S6G_ENA_LANE_POS) |
1937 				(0 << PHY_S6G_ENA_LOOP_POS) |
1938 				(0 << PHY_S6G_QRATE_POS) |
1939 				(3 << PHY_S6G_IF_MODE_POS));
1940 	if (ret)
1941 		goto err;
1942 
1943 	/* misccfg */
1944 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1945 				PHY_S6G_MISC_CFG, 1);
1946 	if (ret)
1947 		goto err;
1948 
1949 	/* gpcfg */
1950 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1951 				PHY_S6G_GPC_CFG, 768);
1952 	if (ret)
1953 		goto err;
1954 
1955 	phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0);
1956 
1957 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1958 	do {
1959 		usleep_range(500, 1000);
1960 		phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1961 				   0); /* read 6G MCB into CSRs */
1962 		reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1963 				       PHY_S6G_PLL_STATUS);
1964 		if (reg == 0xffffffff) {
1965 			phy_unlock_mdio_bus(phydev);
1966 			return -EIO;
1967 		}
1968 
1969 	} while (time_before(jiffies, deadline) && (reg & BIT(12)));
1970 
1971 	if (reg & BIT(12)) {
1972 		phy_unlock_mdio_bus(phydev);
1973 		return -ETIMEDOUT;
1974 	}
1975 
1976 	/* misccfg */
1977 	ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET,
1978 				PHY_S6G_MISC_CFG, 0);
1979 	if (ret)
1980 		goto err;
1981 
1982 	phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0);
1983 
1984 	deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1985 	do {
1986 		usleep_range(500, 1000);
1987 		phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG,
1988 				   0); /* read 6G MCB into CSRs */
1989 		reg = vsc85xx_csr_read(phydev, PHY_MCB_TARGET,
1990 				       PHY_S6G_IB_STATUS0);
1991 		if (reg == 0xffffffff) {
1992 			phy_unlock_mdio_bus(phydev);
1993 			return -EIO;
1994 		}
1995 
1996 	} while (time_before(jiffies, deadline) && !(reg & BIT(8)));
1997 
1998 	if (!(reg & BIT(8))) {
1999 		phy_unlock_mdio_bus(phydev);
2000 		return -ETIMEDOUT;
2001 	}
2002 
2003 	phy_unlock_mdio_bus(phydev);
2004 
2005 	ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2006 			 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
2007 
2008 	if (ret)
2009 		return ret;
2010 
2011 	ret = genphy_soft_reset(phydev);
2012 
2013 	if (ret)
2014 		return ret;
2015 
2016 	for (i = 0; i < vsc8531->nleds; i++) {
2017 		ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2018 		if (ret)
2019 			return ret;
2020 	}
2021 
2022 	return ret;
2023 
2024 err:
2025 	phy_unlock_mdio_bus(phydev);
2026 	return ret;
2027 }
2028 
vsc85xx_ack_interrupt(struct phy_device *phydev)2029 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2030 {
2031 	int rc = 0;
2032 
2033 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2034 		rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2035 
2036 	return (rc < 0) ? rc : 0;
2037 }
2038 
vsc85xx_config_intr(struct phy_device *phydev)2039 static int vsc85xx_config_intr(struct phy_device *phydev)
2040 {
2041 	int rc;
2042 
2043 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2044 		vsc8584_config_macsec_intr(phydev);
2045 		vsc8584_config_ts_intr(phydev);
2046 
2047 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2048 			       MII_VSC85XX_INT_MASK_MASK);
2049 	} else {
2050 		rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2051 		if (rc < 0)
2052 			return rc;
2053 		rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2054 	}
2055 
2056 	return rc;
2057 }
2058 
vsc85xx_config_aneg(struct phy_device *phydev)2059 static int vsc85xx_config_aneg(struct phy_device *phydev)
2060 {
2061 	int rc;
2062 
2063 	rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2064 	if (rc < 0)
2065 		return rc;
2066 
2067 	return genphy_config_aneg(phydev);
2068 }
2069 
vsc85xx_read_status(struct phy_device *phydev)2070 static int vsc85xx_read_status(struct phy_device *phydev)
2071 {
2072 	int rc;
2073 
2074 	rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2075 	if (rc < 0)
2076 		return rc;
2077 
2078 	return genphy_read_status(phydev);
2079 }
2080 
vsc8514_probe(struct phy_device *phydev)2081 static int vsc8514_probe(struct phy_device *phydev)
2082 {
2083 	struct vsc8531_private *vsc8531;
2084 	u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2085 	   VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2086 	   VSC8531_DUPLEX_COLLISION};
2087 
2088 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2089 	if (!vsc8531)
2090 		return -ENOMEM;
2091 
2092 	phydev->priv = vsc8531;
2093 
2094 	vsc8584_get_base_addr(phydev);
2095 	devm_phy_package_join(&phydev->mdio.dev, phydev,
2096 			      vsc8531->base_addr, 0);
2097 
2098 	vsc8531->nleds = 4;
2099 	vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2100 	vsc8531->hw_stats = vsc85xx_hw_stats;
2101 	vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2102 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2103 				      sizeof(u64), GFP_KERNEL);
2104 	if (!vsc8531->stats)
2105 		return -ENOMEM;
2106 
2107 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2108 }
2109 
vsc8574_probe(struct phy_device *phydev)2110 static int vsc8574_probe(struct phy_device *phydev)
2111 {
2112 	struct vsc8531_private *vsc8531;
2113 	u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2114 	   VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2115 	   VSC8531_DUPLEX_COLLISION};
2116 
2117 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2118 	if (!vsc8531)
2119 		return -ENOMEM;
2120 
2121 	phydev->priv = vsc8531;
2122 
2123 	vsc8584_get_base_addr(phydev);
2124 	devm_phy_package_join(&phydev->mdio.dev, phydev,
2125 			      vsc8531->base_addr, 0);
2126 
2127 	vsc8531->nleds = 4;
2128 	vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2129 	vsc8531->hw_stats = vsc8584_hw_stats;
2130 	vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2131 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2132 				      sizeof(u64), GFP_KERNEL);
2133 	if (!vsc8531->stats)
2134 		return -ENOMEM;
2135 
2136 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2137 }
2138 
vsc8584_probe(struct phy_device *phydev)2139 static int vsc8584_probe(struct phy_device *phydev)
2140 {
2141 	struct vsc8531_private *vsc8531;
2142 	u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2143 	   VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2144 	   VSC8531_DUPLEX_COLLISION};
2145 	int ret;
2146 
2147 	if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2148 		dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2149 		return -ENOTSUPP;
2150 	}
2151 
2152 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2153 	if (!vsc8531)
2154 		return -ENOMEM;
2155 
2156 	phydev->priv = vsc8531;
2157 
2158 	vsc8584_get_base_addr(phydev);
2159 	devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2160 			      sizeof(struct vsc85xx_shared_private));
2161 
2162 	vsc8531->nleds = 4;
2163 	vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2164 	vsc8531->hw_stats = vsc8584_hw_stats;
2165 	vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2166 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2167 				      sizeof(u64), GFP_KERNEL);
2168 	if (!vsc8531->stats)
2169 		return -ENOMEM;
2170 
2171 	if (phy_package_probe_once(phydev)) {
2172 		ret = vsc8584_ptp_probe_once(phydev);
2173 		if (ret)
2174 			return ret;
2175 	}
2176 
2177 	ret = vsc8584_ptp_probe(phydev);
2178 	if (ret)
2179 		return ret;
2180 
2181 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2182 }
2183 
vsc85xx_probe(struct phy_device *phydev)2184 static int vsc85xx_probe(struct phy_device *phydev)
2185 {
2186 	struct vsc8531_private *vsc8531;
2187 	int rate_magic;
2188 	u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2189 	   VSC8531_LINK_100_ACTIVITY};
2190 
2191 	rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2192 	if (rate_magic < 0)
2193 		return rate_magic;
2194 
2195 	vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2196 	if (!vsc8531)
2197 		return -ENOMEM;
2198 
2199 	phydev->priv = vsc8531;
2200 
2201 	vsc8531->rate_magic = rate_magic;
2202 	vsc8531->nleds = 2;
2203 	vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2204 	vsc8531->hw_stats = vsc85xx_hw_stats;
2205 	vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2206 	vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2207 				      sizeof(u64), GFP_KERNEL);
2208 	if (!vsc8531->stats)
2209 		return -ENOMEM;
2210 
2211 	return vsc85xx_dt_led_modes_get(phydev, default_mode);
2212 }
2213 
2214 /* Microsemi VSC85xx PHYs */
2215 static struct phy_driver vsc85xx_driver[] = {
2216 {
2217 	.phy_id		= PHY_ID_VSC8502,
2218 	.name		= "Microsemi GE VSC8502 SyncE",
2219 	.phy_id_mask	= 0xfffffff0,
2220 	/* PHY_BASIC_FEATURES */
2221 	.soft_reset	= &genphy_soft_reset,
2222 	.config_init	= &vsc85xx_config_init,
2223 	.config_aneg    = &vsc85xx_config_aneg,
2224 	.read_status	= &vsc85xx_read_status,
2225 	.ack_interrupt	= &vsc85xx_ack_interrupt,
2226 	.config_intr	= &vsc85xx_config_intr,
2227 	.suspend	= &genphy_suspend,
2228 	.resume		= &genphy_resume,
2229 	.probe		= &vsc85xx_probe,
2230 	.set_wol	= &vsc85xx_wol_set,
2231 	.get_wol	= &vsc85xx_wol_get,
2232 	.get_tunable	= &vsc85xx_get_tunable,
2233 	.set_tunable	= &vsc85xx_set_tunable,
2234 	.read_page	= &vsc85xx_phy_read_page,
2235 	.write_page	= &vsc85xx_phy_write_page,
2236 	.get_sset_count = &vsc85xx_get_sset_count,
2237 	.get_strings    = &vsc85xx_get_strings,
2238 	.get_stats      = &vsc85xx_get_stats,
2239 },
2240 {
2241 	.phy_id		= PHY_ID_VSC8504,
2242 	.name		= "Microsemi GE VSC8504 SyncE",
2243 	.phy_id_mask	= 0xfffffff0,
2244 	/* PHY_GBIT_FEATURES */
2245 	.soft_reset	= &genphy_soft_reset,
2246 	.config_init    = &vsc8584_config_init,
2247 	.config_aneg    = &vsc85xx_config_aneg,
2248 	.aneg_done	= &genphy_aneg_done,
2249 	.read_status	= &vsc85xx_read_status,
2250 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2251 	.config_intr    = &vsc85xx_config_intr,
2252 	.did_interrupt  = &vsc8584_did_interrupt,
2253 	.suspend	= &genphy_suspend,
2254 	.resume		= &genphy_resume,
2255 	.probe		= &vsc8574_probe,
2256 	.set_wol	= &vsc85xx_wol_set,
2257 	.get_wol	= &vsc85xx_wol_get,
2258 	.get_tunable	= &vsc85xx_get_tunable,
2259 	.set_tunable	= &vsc85xx_set_tunable,
2260 	.read_page	= &vsc85xx_phy_read_page,
2261 	.write_page	= &vsc85xx_phy_write_page,
2262 	.get_sset_count = &vsc85xx_get_sset_count,
2263 	.get_strings    = &vsc85xx_get_strings,
2264 	.get_stats      = &vsc85xx_get_stats,
2265 },
2266 {
2267 	.phy_id		= PHY_ID_VSC8514,
2268 	.name		= "Microsemi GE VSC8514 SyncE",
2269 	.phy_id_mask	= 0xfffffff0,
2270 	.soft_reset	= &genphy_soft_reset,
2271 	.config_init    = &vsc8514_config_init,
2272 	.config_aneg    = &vsc85xx_config_aneg,
2273 	.read_status	= &vsc85xx_read_status,
2274 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2275 	.config_intr    = &vsc85xx_config_intr,
2276 	.suspend	= &genphy_suspend,
2277 	.resume		= &genphy_resume,
2278 	.probe		= &vsc8514_probe,
2279 	.set_wol	= &vsc85xx_wol_set,
2280 	.get_wol	= &vsc85xx_wol_get,
2281 	.get_tunable	= &vsc85xx_get_tunable,
2282 	.set_tunable	= &vsc85xx_set_tunable,
2283 	.read_page      = &vsc85xx_phy_read_page,
2284 	.write_page     = &vsc85xx_phy_write_page,
2285 	.get_sset_count = &vsc85xx_get_sset_count,
2286 	.get_strings    = &vsc85xx_get_strings,
2287 	.get_stats      = &vsc85xx_get_stats,
2288 },
2289 {
2290 	.phy_id		= PHY_ID_VSC8530,
2291 	.name		= "Microsemi FE VSC8530",
2292 	.phy_id_mask	= 0xfffffff0,
2293 	/* PHY_BASIC_FEATURES */
2294 	.soft_reset	= &genphy_soft_reset,
2295 	.config_init	= &vsc85xx_config_init,
2296 	.config_aneg    = &vsc85xx_config_aneg,
2297 	.read_status	= &vsc85xx_read_status,
2298 	.ack_interrupt	= &vsc85xx_ack_interrupt,
2299 	.config_intr	= &vsc85xx_config_intr,
2300 	.suspend	= &genphy_suspend,
2301 	.resume		= &genphy_resume,
2302 	.probe		= &vsc85xx_probe,
2303 	.set_wol	= &vsc85xx_wol_set,
2304 	.get_wol	= &vsc85xx_wol_get,
2305 	.get_tunable	= &vsc85xx_get_tunable,
2306 	.set_tunable	= &vsc85xx_set_tunable,
2307 	.read_page	= &vsc85xx_phy_read_page,
2308 	.write_page	= &vsc85xx_phy_write_page,
2309 	.get_sset_count = &vsc85xx_get_sset_count,
2310 	.get_strings    = &vsc85xx_get_strings,
2311 	.get_stats      = &vsc85xx_get_stats,
2312 },
2313 {
2314 	.phy_id		= PHY_ID_VSC8531,
2315 	.name		= "Microsemi VSC8531",
2316 	.phy_id_mask    = 0xfffffff0,
2317 	/* PHY_GBIT_FEATURES */
2318 	.soft_reset	= &genphy_soft_reset,
2319 	.config_init    = &vsc85xx_config_init,
2320 	.config_aneg    = &vsc85xx_config_aneg,
2321 	.read_status	= &vsc85xx_read_status,
2322 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2323 	.config_intr    = &vsc85xx_config_intr,
2324 	.suspend	= &genphy_suspend,
2325 	.resume		= &genphy_resume,
2326 	.probe		= &vsc85xx_probe,
2327 	.set_wol	= &vsc85xx_wol_set,
2328 	.get_wol	= &vsc85xx_wol_get,
2329 	.get_tunable	= &vsc85xx_get_tunable,
2330 	.set_tunable	= &vsc85xx_set_tunable,
2331 	.read_page	= &vsc85xx_phy_read_page,
2332 	.write_page	= &vsc85xx_phy_write_page,
2333 	.get_sset_count = &vsc85xx_get_sset_count,
2334 	.get_strings    = &vsc85xx_get_strings,
2335 	.get_stats      = &vsc85xx_get_stats,
2336 },
2337 {
2338 	.phy_id		= PHY_ID_VSC8540,
2339 	.name		= "Microsemi FE VSC8540 SyncE",
2340 	.phy_id_mask	= 0xfffffff0,
2341 	/* PHY_BASIC_FEATURES */
2342 	.soft_reset	= &genphy_soft_reset,
2343 	.config_init	= &vsc85xx_config_init,
2344 	.config_aneg	= &vsc85xx_config_aneg,
2345 	.read_status	= &vsc85xx_read_status,
2346 	.ack_interrupt	= &vsc85xx_ack_interrupt,
2347 	.config_intr	= &vsc85xx_config_intr,
2348 	.suspend	= &genphy_suspend,
2349 	.resume		= &genphy_resume,
2350 	.probe		= &vsc85xx_probe,
2351 	.set_wol	= &vsc85xx_wol_set,
2352 	.get_wol	= &vsc85xx_wol_get,
2353 	.get_tunable	= &vsc85xx_get_tunable,
2354 	.set_tunable	= &vsc85xx_set_tunable,
2355 	.read_page	= &vsc85xx_phy_read_page,
2356 	.write_page	= &vsc85xx_phy_write_page,
2357 	.get_sset_count = &vsc85xx_get_sset_count,
2358 	.get_strings    = &vsc85xx_get_strings,
2359 	.get_stats      = &vsc85xx_get_stats,
2360 },
2361 {
2362 	.phy_id		= PHY_ID_VSC8541,
2363 	.name		= "Microsemi VSC8541 SyncE",
2364 	.phy_id_mask    = 0xfffffff0,
2365 	/* PHY_GBIT_FEATURES */
2366 	.soft_reset	= &genphy_soft_reset,
2367 	.config_init    = &vsc85xx_config_init,
2368 	.config_aneg    = &vsc85xx_config_aneg,
2369 	.read_status	= &vsc85xx_read_status,
2370 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2371 	.config_intr    = &vsc85xx_config_intr,
2372 	.suspend	= &genphy_suspend,
2373 	.resume		= &genphy_resume,
2374 	.probe		= &vsc85xx_probe,
2375 	.set_wol	= &vsc85xx_wol_set,
2376 	.get_wol	= &vsc85xx_wol_get,
2377 	.get_tunable	= &vsc85xx_get_tunable,
2378 	.set_tunable	= &vsc85xx_set_tunable,
2379 	.read_page	= &vsc85xx_phy_read_page,
2380 	.write_page	= &vsc85xx_phy_write_page,
2381 	.get_sset_count = &vsc85xx_get_sset_count,
2382 	.get_strings    = &vsc85xx_get_strings,
2383 	.get_stats      = &vsc85xx_get_stats,
2384 },
2385 {
2386 	.phy_id		= PHY_ID_VSC8552,
2387 	.name		= "Microsemi GE VSC8552 SyncE",
2388 	.phy_id_mask	= 0xfffffff0,
2389 	/* PHY_GBIT_FEATURES */
2390 	.soft_reset	= &genphy_soft_reset,
2391 	.config_init    = &vsc8584_config_init,
2392 	.config_aneg    = &vsc85xx_config_aneg,
2393 	.read_status	= &vsc85xx_read_status,
2394 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2395 	.config_intr    = &vsc85xx_config_intr,
2396 	.did_interrupt  = &vsc8584_did_interrupt,
2397 	.suspend	= &genphy_suspend,
2398 	.resume		= &genphy_resume,
2399 	.probe		= &vsc8574_probe,
2400 	.set_wol	= &vsc85xx_wol_set,
2401 	.get_wol	= &vsc85xx_wol_get,
2402 	.get_tunable	= &vsc85xx_get_tunable,
2403 	.set_tunable	= &vsc85xx_set_tunable,
2404 	.read_page	= &vsc85xx_phy_read_page,
2405 	.write_page	= &vsc85xx_phy_write_page,
2406 	.get_sset_count = &vsc85xx_get_sset_count,
2407 	.get_strings    = &vsc85xx_get_strings,
2408 	.get_stats      = &vsc85xx_get_stats,
2409 },
2410 {
2411 	.phy_id		= PHY_ID_VSC856X,
2412 	.name		= "Microsemi GE VSC856X SyncE",
2413 	.phy_id_mask	= 0xfffffff0,
2414 	/* PHY_GBIT_FEATURES */
2415 	.soft_reset	= &genphy_soft_reset,
2416 	.config_init    = &vsc8584_config_init,
2417 	.config_aneg    = &vsc85xx_config_aneg,
2418 	.read_status	= &vsc85xx_read_status,
2419 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2420 	.config_intr    = &vsc85xx_config_intr,
2421 	.did_interrupt  = &vsc8584_did_interrupt,
2422 	.suspend	= &genphy_suspend,
2423 	.resume		= &genphy_resume,
2424 	.probe		= &vsc8584_probe,
2425 	.get_tunable	= &vsc85xx_get_tunable,
2426 	.set_tunable	= &vsc85xx_set_tunable,
2427 	.read_page	= &vsc85xx_phy_read_page,
2428 	.write_page	= &vsc85xx_phy_write_page,
2429 	.get_sset_count = &vsc85xx_get_sset_count,
2430 	.get_strings    = &vsc85xx_get_strings,
2431 	.get_stats      = &vsc85xx_get_stats,
2432 },
2433 {
2434 	.phy_id		= PHY_ID_VSC8572,
2435 	.name		= "Microsemi GE VSC8572 SyncE",
2436 	.phy_id_mask	= 0xfffffff0,
2437 	/* PHY_GBIT_FEATURES */
2438 	.soft_reset	= &genphy_soft_reset,
2439 	.config_init    = &vsc8584_config_init,
2440 	.config_aneg    = &vsc85xx_config_aneg,
2441 	.aneg_done	= &genphy_aneg_done,
2442 	.read_status	= &vsc85xx_read_status,
2443 	.handle_interrupt = &vsc8584_handle_interrupt,
2444 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2445 	.config_intr    = &vsc85xx_config_intr,
2446 	.did_interrupt  = &vsc8584_did_interrupt,
2447 	.suspend	= &genphy_suspend,
2448 	.resume		= &genphy_resume,
2449 	.probe		= &vsc8574_probe,
2450 	.set_wol	= &vsc85xx_wol_set,
2451 	.get_wol	= &vsc85xx_wol_get,
2452 	.get_tunable	= &vsc85xx_get_tunable,
2453 	.set_tunable	= &vsc85xx_set_tunable,
2454 	.read_page	= &vsc85xx_phy_read_page,
2455 	.write_page	= &vsc85xx_phy_write_page,
2456 	.get_sset_count = &vsc85xx_get_sset_count,
2457 	.get_strings    = &vsc85xx_get_strings,
2458 	.get_stats      = &vsc85xx_get_stats,
2459 },
2460 {
2461 	.phy_id		= PHY_ID_VSC8574,
2462 	.name		= "Microsemi GE VSC8574 SyncE",
2463 	.phy_id_mask	= 0xfffffff0,
2464 	/* PHY_GBIT_FEATURES */
2465 	.soft_reset	= &genphy_soft_reset,
2466 	.config_init    = &vsc8584_config_init,
2467 	.config_aneg    = &vsc85xx_config_aneg,
2468 	.aneg_done	= &genphy_aneg_done,
2469 	.read_status	= &vsc85xx_read_status,
2470 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2471 	.config_intr    = &vsc85xx_config_intr,
2472 	.did_interrupt  = &vsc8584_did_interrupt,
2473 	.suspend	= &genphy_suspend,
2474 	.resume		= &genphy_resume,
2475 	.probe		= &vsc8574_probe,
2476 	.set_wol	= &vsc85xx_wol_set,
2477 	.get_wol	= &vsc85xx_wol_get,
2478 	.get_tunable	= &vsc85xx_get_tunable,
2479 	.set_tunable	= &vsc85xx_set_tunable,
2480 	.read_page	= &vsc85xx_phy_read_page,
2481 	.write_page	= &vsc85xx_phy_write_page,
2482 	.get_sset_count = &vsc85xx_get_sset_count,
2483 	.get_strings    = &vsc85xx_get_strings,
2484 	.get_stats      = &vsc85xx_get_stats,
2485 },
2486 {
2487 	.phy_id		= PHY_ID_VSC8575,
2488 	.name		= "Microsemi GE VSC8575 SyncE",
2489 	.phy_id_mask	= 0xfffffff0,
2490 	/* PHY_GBIT_FEATURES */
2491 	.soft_reset	= &genphy_soft_reset,
2492 	.config_init    = &vsc8584_config_init,
2493 	.config_aneg    = &vsc85xx_config_aneg,
2494 	.aneg_done	= &genphy_aneg_done,
2495 	.read_status	= &vsc85xx_read_status,
2496 	.handle_interrupt = &vsc8584_handle_interrupt,
2497 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2498 	.config_intr    = &vsc85xx_config_intr,
2499 	.did_interrupt  = &vsc8584_did_interrupt,
2500 	.suspend	= &genphy_suspend,
2501 	.resume		= &genphy_resume,
2502 	.probe		= &vsc8584_probe,
2503 	.get_tunable	= &vsc85xx_get_tunable,
2504 	.set_tunable	= &vsc85xx_set_tunable,
2505 	.read_page	= &vsc85xx_phy_read_page,
2506 	.write_page	= &vsc85xx_phy_write_page,
2507 	.get_sset_count = &vsc85xx_get_sset_count,
2508 	.get_strings    = &vsc85xx_get_strings,
2509 	.get_stats      = &vsc85xx_get_stats,
2510 },
2511 {
2512 	.phy_id		= PHY_ID_VSC8582,
2513 	.name		= "Microsemi GE VSC8582 SyncE",
2514 	.phy_id_mask	= 0xfffffff0,
2515 	/* PHY_GBIT_FEATURES */
2516 	.soft_reset	= &genphy_soft_reset,
2517 	.config_init    = &vsc8584_config_init,
2518 	.config_aneg    = &vsc85xx_config_aneg,
2519 	.aneg_done	= &genphy_aneg_done,
2520 	.read_status	= &vsc85xx_read_status,
2521 	.handle_interrupt = &vsc8584_handle_interrupt,
2522 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2523 	.config_intr    = &vsc85xx_config_intr,
2524 	.did_interrupt  = &vsc8584_did_interrupt,
2525 	.suspend	= &genphy_suspend,
2526 	.resume		= &genphy_resume,
2527 	.probe		= &vsc8584_probe,
2528 	.get_tunable	= &vsc85xx_get_tunable,
2529 	.set_tunable	= &vsc85xx_set_tunable,
2530 	.read_page	= &vsc85xx_phy_read_page,
2531 	.write_page	= &vsc85xx_phy_write_page,
2532 	.get_sset_count = &vsc85xx_get_sset_count,
2533 	.get_strings    = &vsc85xx_get_strings,
2534 	.get_stats      = &vsc85xx_get_stats,
2535 },
2536 {
2537 	.phy_id		= PHY_ID_VSC8584,
2538 	.name		= "Microsemi GE VSC8584 SyncE",
2539 	.phy_id_mask	= 0xfffffff0,
2540 	/* PHY_GBIT_FEATURES */
2541 	.soft_reset	= &genphy_soft_reset,
2542 	.config_init    = &vsc8584_config_init,
2543 	.config_aneg    = &vsc85xx_config_aneg,
2544 	.aneg_done	= &genphy_aneg_done,
2545 	.read_status	= &vsc85xx_read_status,
2546 	.handle_interrupt = &vsc8584_handle_interrupt,
2547 	.ack_interrupt  = &vsc85xx_ack_interrupt,
2548 	.config_intr    = &vsc85xx_config_intr,
2549 	.did_interrupt  = &vsc8584_did_interrupt,
2550 	.suspend	= &genphy_suspend,
2551 	.resume		= &genphy_resume,
2552 	.probe		= &vsc8584_probe,
2553 	.get_tunable	= &vsc85xx_get_tunable,
2554 	.set_tunable	= &vsc85xx_set_tunable,
2555 	.read_page	= &vsc85xx_phy_read_page,
2556 	.write_page	= &vsc85xx_phy_write_page,
2557 	.get_sset_count = &vsc85xx_get_sset_count,
2558 	.get_strings    = &vsc85xx_get_strings,
2559 	.get_stats      = &vsc85xx_get_stats,
2560 	.link_change_notify = &vsc85xx_link_change_notify,
2561 }
2562 
2563 };
2564 
2565 module_phy_driver(vsc85xx_driver);
2566 
2567 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2568 	{ PHY_ID_VSC8502, 0xfffffff0, },
2569 	{ PHY_ID_VSC8504, 0xfffffff0, },
2570 	{ PHY_ID_VSC8514, 0xfffffff0, },
2571 	{ PHY_ID_VSC8530, 0xfffffff0, },
2572 	{ PHY_ID_VSC8531, 0xfffffff0, },
2573 	{ PHY_ID_VSC8540, 0xfffffff0, },
2574 	{ PHY_ID_VSC8541, 0xfffffff0, },
2575 	{ PHY_ID_VSC8552, 0xfffffff0, },
2576 	{ PHY_ID_VSC856X, 0xfffffff0, },
2577 	{ PHY_ID_VSC8572, 0xfffffff0, },
2578 	{ PHY_ID_VSC8574, 0xfffffff0, },
2579 	{ PHY_ID_VSC8575, 0xfffffff0, },
2580 	{ PHY_ID_VSC8582, 0xfffffff0, },
2581 	{ PHY_ID_VSC8584, 0xfffffff0, },
2582 	{ }
2583 };
2584 
2585 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2586 
2587 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2588 MODULE_AUTHOR("Nagaraju Lakkaraju");
2589 MODULE_LICENSE("Dual MIT/GPL");
2590 
2591 MODULE_FIRMWARE(MSCC_VSC8584_REVB_INT8051_FW);
2592 MODULE_FIRMWARE(MSCC_VSC8574_REVB_INT8051_FW);
2593