1// SPDX-License-Identifier: GPL-2.0-only 2/**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2012-2013 Solarflare Communications Inc. 5 */ 6 7#include "net_driver.h" 8#include "rx_common.h" 9#include "tx_common.h" 10#include "ef10_regs.h" 11#include "io.h" 12#include "mcdi.h" 13#include "mcdi_pcol.h" 14#include "mcdi_port.h" 15#include "mcdi_port_common.h" 16#include "mcdi_functions.h" 17#include "nic.h" 18#include "mcdi_filters.h" 19#include "workarounds.h" 20#include "selftest.h" 21#include "ef10_sriov.h" 22#include <linux/in.h> 23#include <linux/jhash.h> 24#include <linux/wait.h> 25#include <linux/workqueue.h> 26#include <net/udp_tunnel.h> 27 28/* Hardware control for EF10 architecture including 'Huntington'. */ 29 30#define EFX_EF10_DRVGEN_EV 7 31enum { 32 EFX_EF10_TEST = 1, 33 EFX_EF10_REFILL, 34}; 35 36/* VLAN list entry */ 37struct efx_ef10_vlan { 38 struct list_head list; 39 u16 vid; 40}; 41 42static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading); 43static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels; 44 45static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 46{ 47 efx_dword_t reg; 48 49 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 50 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 51 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 52} 53 54/* On all EF10s up to and including SFC9220 (Medford1), all PFs use BAR 0 for 55 * I/O space and BAR 2(&3) for memory. On SFC9250 (Medford2), there is no I/O 56 * bar; PFs use BAR 0/1 for memory. 57 */ 58static unsigned int efx_ef10_pf_mem_bar(struct efx_nic *efx) 59{ 60 switch (efx->pci_dev->device) { 61 case 0x0b03: /* SFC9250 PF */ 62 return 0; 63 default: 64 return 2; 65 } 66} 67 68/* All VFs use BAR 0/1 for memory */ 69static unsigned int efx_ef10_vf_mem_bar(struct efx_nic *efx) 70{ 71 return 0; 72} 73 74static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 75{ 76 int bar; 77 78 bar = efx->type->mem_bar(efx); 79 return resource_size(&efx->pci_dev->resource[bar]); 80} 81 82static bool efx_ef10_is_vf(struct efx_nic *efx) 83{ 84 return efx->type->is_vf; 85} 86 87#ifdef CONFIG_SFC_SRIOV 88static int efx_ef10_get_vf_index(struct efx_nic *efx) 89{ 90 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN); 91 struct efx_ef10_nic_data *nic_data = efx->nic_data; 92 size_t outlen; 93 int rc; 94 95 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf, 96 sizeof(outbuf), &outlen); 97 if (rc) 98 return rc; 99 if (outlen < sizeof(outbuf)) 100 return -EIO; 101 102 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF); 103 return 0; 104} 105#endif 106 107static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 108{ 109 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V4_OUT_LEN); 110 struct efx_ef10_nic_data *nic_data = efx->nic_data; 111 size_t outlen; 112 int rc; 113 114 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 115 116 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 117 outbuf, sizeof(outbuf), &outlen); 118 if (rc) 119 return rc; 120 if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) { 121 netif_err(efx, drv, efx->net_dev, 122 "unable to read datapath firmware capabilities\n"); 123 return -EIO; 124 } 125 126 nic_data->datapath_caps = 127 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 128 129 if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) { 130 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 131 GET_CAPABILITIES_V2_OUT_FLAGS2); 132 nic_data->piobuf_size = MCDI_WORD(outbuf, 133 GET_CAPABILITIES_V2_OUT_SIZE_PIO_BUFF); 134 } else { 135 nic_data->datapath_caps2 = 0; 136 nic_data->piobuf_size = ER_DZ_TX_PIOBUF_SIZE; 137 } 138 139 /* record the DPCPU firmware IDs to determine VEB vswitching support. 140 */ 141 nic_data->rx_dpcpu_fw_id = 142 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID); 143 nic_data->tx_dpcpu_fw_id = 144 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID); 145 146 if (!(nic_data->datapath_caps & 147 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 148 netif_err(efx, probe, efx->net_dev, 149 "current firmware does not support an RX prefix\n"); 150 return -ENODEV; 151 } 152 153 if (outlen >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) { 154 u8 vi_window_mode = MCDI_BYTE(outbuf, 155 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 156 157 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 158 if (rc) 159 return rc; 160 } else { 161 /* keep default VI stride */ 162 netif_dbg(efx, probe, efx->net_dev, 163 "firmware did not report VI window mode, assuming vi_stride = %u\n", 164 efx->vi_stride); 165 } 166 167 if (outlen >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 168 efx->num_mac_stats = MCDI_WORD(outbuf, 169 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 170 netif_dbg(efx, probe, efx->net_dev, 171 "firmware reports num_mac_stats = %u\n", 172 efx->num_mac_stats); 173 } else { 174 /* leave num_mac_stats as the default value, MC_CMD_MAC_NSTATS */ 175 netif_dbg(efx, probe, efx->net_dev, 176 "firmware did not report num_mac_stats, assuming %u\n", 177 efx->num_mac_stats); 178 } 179 180 return 0; 181} 182 183static void efx_ef10_read_licensed_features(struct efx_nic *efx) 184{ 185 MCDI_DECLARE_BUF(inbuf, MC_CMD_LICENSING_V3_IN_LEN); 186 MCDI_DECLARE_BUF(outbuf, MC_CMD_LICENSING_V3_OUT_LEN); 187 struct efx_ef10_nic_data *nic_data = efx->nic_data; 188 size_t outlen; 189 int rc; 190 191 MCDI_SET_DWORD(inbuf, LICENSING_V3_IN_OP, 192 MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE); 193 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_LICENSING_V3, inbuf, sizeof(inbuf), 194 outbuf, sizeof(outbuf), &outlen); 195 if (rc || (outlen < MC_CMD_LICENSING_V3_OUT_LEN)) 196 return; 197 198 nic_data->licensed_features = MCDI_QWORD(outbuf, 199 LICENSING_V3_OUT_LICENSED_FEATURES); 200} 201 202static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 203{ 204 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 205 int rc; 206 207 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 208 outbuf, sizeof(outbuf), NULL); 209 if (rc) 210 return rc; 211 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 212 return rc > 0 ? rc : -ERANGE; 213} 214 215static int efx_ef10_get_timer_workarounds(struct efx_nic *efx) 216{ 217 struct efx_ef10_nic_data *nic_data = efx->nic_data; 218 unsigned int implemented; 219 unsigned int enabled; 220 int rc; 221 222 nic_data->workaround_35388 = false; 223 nic_data->workaround_61265 = false; 224 225 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 226 227 if (rc == -ENOSYS) { 228 /* Firmware without GET_WORKAROUNDS - not a problem. */ 229 rc = 0; 230 } else if (rc == 0) { 231 /* Bug61265 workaround is always enabled if implemented. */ 232 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265) 233 nic_data->workaround_61265 = true; 234 235 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 236 nic_data->workaround_35388 = true; 237 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) { 238 /* Workaround is implemented but not enabled. 239 * Try to enable it. 240 */ 241 rc = efx_mcdi_set_workaround(efx, 242 MC_CMD_WORKAROUND_BUG35388, 243 true, NULL); 244 if (rc == 0) 245 nic_data->workaround_35388 = true; 246 /* If we failed to set the workaround just carry on. */ 247 rc = 0; 248 } 249 } 250 251 netif_dbg(efx, probe, efx->net_dev, 252 "workaround for bug 35388 is %sabled\n", 253 nic_data->workaround_35388 ? "en" : "dis"); 254 netif_dbg(efx, probe, efx->net_dev, 255 "workaround for bug 61265 is %sabled\n", 256 nic_data->workaround_61265 ? "en" : "dis"); 257 258 return rc; 259} 260 261static void efx_ef10_process_timer_config(struct efx_nic *efx, 262 const efx_dword_t *data) 263{ 264 unsigned int max_count; 265 266 if (EFX_EF10_WORKAROUND_61265(efx)) { 267 efx->timer_quantum_ns = MCDI_DWORD(data, 268 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS); 269 efx->timer_max_ns = MCDI_DWORD(data, 270 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS); 271 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 272 efx->timer_quantum_ns = MCDI_DWORD(data, 273 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT); 274 max_count = MCDI_DWORD(data, 275 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT); 276 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 277 } else { 278 efx->timer_quantum_ns = MCDI_DWORD(data, 279 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT); 280 max_count = MCDI_DWORD(data, 281 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT); 282 efx->timer_max_ns = max_count * efx->timer_quantum_ns; 283 } 284 285 netif_dbg(efx, probe, efx->net_dev, 286 "got timer properties from MC: quantum %u ns; max %u ns\n", 287 efx->timer_quantum_ns, efx->timer_max_ns); 288} 289 290static int efx_ef10_get_timer_config(struct efx_nic *efx) 291{ 292 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN); 293 int rc; 294 295 rc = efx_ef10_get_timer_workarounds(efx); 296 if (rc) 297 return rc; 298 299 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0, 300 outbuf, sizeof(outbuf), NULL); 301 302 if (rc == 0) { 303 efx_ef10_process_timer_config(efx, outbuf); 304 } else if (rc == -ENOSYS || rc == -EPERM) { 305 /* Not available - fall back to Huntington defaults. */ 306 unsigned int quantum; 307 308 rc = efx_ef10_get_sysclk_freq(efx); 309 if (rc < 0) 310 return rc; 311 312 quantum = 1536000 / rc; /* 1536 cycles */ 313 efx->timer_quantum_ns = quantum; 314 efx->timer_max_ns = efx->type->timer_period_max * quantum; 315 rc = 0; 316 } else { 317 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, 318 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN, 319 NULL, 0, rc); 320 } 321 322 return rc; 323} 324 325static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address) 326{ 327 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 328 size_t outlen; 329 int rc; 330 331 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 332 333 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 334 outbuf, sizeof(outbuf), &outlen); 335 if (rc) 336 return rc; 337 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 338 return -EIO; 339 340 ether_addr_copy(mac_address, 341 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 342 return 0; 343} 344 345static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address) 346{ 347 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN); 348 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX); 349 size_t outlen; 350 int num_addrs, rc; 351 352 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID, 353 EVB_PORT_ID_ASSIGNED); 354 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf, 355 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 356 357 if (rc) 358 return rc; 359 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) 360 return -EIO; 361 362 num_addrs = MCDI_DWORD(outbuf, 363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT); 364 365 WARN_ON(num_addrs != 1); 366 367 ether_addr_copy(mac_address, 368 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR)); 369 370 return 0; 371} 372 373static ssize_t efx_ef10_show_link_control_flag(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376{ 377 struct efx_nic *efx = dev_get_drvdata(dev); 378 379 return sprintf(buf, "%d\n", 380 ((efx->mcdi->fn_flags) & 381 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 382 ? 1 : 0); 383} 384 385static ssize_t efx_ef10_show_primary_flag(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388{ 389 struct efx_nic *efx = dev_get_drvdata(dev); 390 391 return sprintf(buf, "%d\n", 392 ((efx->mcdi->fn_flags) & 393 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY)) 394 ? 1 : 0); 395} 396 397static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid) 398{ 399 struct efx_ef10_nic_data *nic_data = efx->nic_data; 400 struct efx_ef10_vlan *vlan; 401 402 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 403 404 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 405 if (vlan->vid == vid) 406 return vlan; 407 } 408 409 return NULL; 410} 411 412static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid) 413{ 414 struct efx_ef10_nic_data *nic_data = efx->nic_data; 415 struct efx_ef10_vlan *vlan; 416 int rc; 417 418 mutex_lock(&nic_data->vlan_lock); 419 420 vlan = efx_ef10_find_vlan(efx, vid); 421 if (vlan) { 422 /* We add VID 0 on init. 8021q adds it on module init 423 * for all interfaces with VLAN filtring feature. 424 */ 425 if (vid == 0) 426 goto done_unlock; 427 netif_warn(efx, drv, efx->net_dev, 428 "VLAN %u already added\n", vid); 429 rc = -EALREADY; 430 goto fail_exist; 431 } 432 433 rc = -ENOMEM; 434 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 435 if (!vlan) 436 goto fail_alloc; 437 438 vlan->vid = vid; 439 440 list_add_tail(&vlan->list, &nic_data->vlan_list); 441 442 if (efx->filter_state) { 443 mutex_lock(&efx->mac_lock); 444 down_write(&efx->filter_sem); 445 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 446 up_write(&efx->filter_sem); 447 mutex_unlock(&efx->mac_lock); 448 if (rc) 449 goto fail_filter_add_vlan; 450 } 451 452done_unlock: 453 mutex_unlock(&nic_data->vlan_lock); 454 return 0; 455 456fail_filter_add_vlan: 457 list_del(&vlan->list); 458 kfree(vlan); 459fail_alloc: 460fail_exist: 461 mutex_unlock(&nic_data->vlan_lock); 462 return rc; 463} 464 465static void efx_ef10_del_vlan_internal(struct efx_nic *efx, 466 struct efx_ef10_vlan *vlan) 467{ 468 struct efx_ef10_nic_data *nic_data = efx->nic_data; 469 470 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock)); 471 472 if (efx->filter_state) { 473 down_write(&efx->filter_sem); 474 efx_mcdi_filter_del_vlan(efx, vlan->vid); 475 up_write(&efx->filter_sem); 476 } 477 478 list_del(&vlan->list); 479 kfree(vlan); 480} 481 482static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid) 483{ 484 struct efx_ef10_nic_data *nic_data = efx->nic_data; 485 struct efx_ef10_vlan *vlan; 486 int rc = 0; 487 488 /* 8021q removes VID 0 on module unload for all interfaces 489 * with VLAN filtering feature. We need to keep it to receive 490 * untagged traffic. 491 */ 492 if (vid == 0) 493 return 0; 494 495 mutex_lock(&nic_data->vlan_lock); 496 497 vlan = efx_ef10_find_vlan(efx, vid); 498 if (!vlan) { 499 netif_err(efx, drv, efx->net_dev, 500 "VLAN %u to be deleted not found\n", vid); 501 rc = -ENOENT; 502 } else { 503 efx_ef10_del_vlan_internal(efx, vlan); 504 } 505 506 mutex_unlock(&nic_data->vlan_lock); 507 508 return rc; 509} 510 511static void efx_ef10_cleanup_vlans(struct efx_nic *efx) 512{ 513 struct efx_ef10_nic_data *nic_data = efx->nic_data; 514 struct efx_ef10_vlan *vlan, *next_vlan; 515 516 mutex_lock(&nic_data->vlan_lock); 517 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list) 518 efx_ef10_del_vlan_internal(efx, vlan); 519 mutex_unlock(&nic_data->vlan_lock); 520} 521 522static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag, 523 NULL); 524static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL); 525 526static int efx_ef10_probe(struct efx_nic *efx) 527{ 528 struct efx_ef10_nic_data *nic_data; 529 int i, rc; 530 531 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 532 if (!nic_data) 533 return -ENOMEM; 534 efx->nic_data = nic_data; 535 536 /* we assume later that we can copy from this buffer in dwords */ 537 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 538 539 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 540 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 541 if (rc) 542 goto fail1; 543 544 /* Get the MC's warm boot count. In case it's rebooting right 545 * now, be prepared to retry. 546 */ 547 i = 0; 548 for (;;) { 549 rc = efx_ef10_get_warm_boot_count(efx); 550 if (rc >= 0) 551 break; 552 if (++i == 5) 553 goto fail2; 554 ssleep(1); 555 } 556 nic_data->warm_boot_count = rc; 557 558 /* In case we're recovering from a crash (kexec), we want to 559 * cancel any outstanding request by the previous user of this 560 * function. We send a special message using the least 561 * significant bits of the 'high' (doorbell) register. 562 */ 563 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 564 565 rc = efx_mcdi_init(efx); 566 if (rc) 567 goto fail2; 568 569 mutex_init(&nic_data->udp_tunnels_lock); 570 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 571 nic_data->udp_tunnels[i].type = 572 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 573 574 /* Reset (most) configuration for this function */ 575 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 576 if (rc) 577 goto fail3; 578 579 /* Enable event logging */ 580 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 581 if (rc) 582 goto fail3; 583 584 rc = device_create_file(&efx->pci_dev->dev, 585 &dev_attr_link_control_flag); 586 if (rc) 587 goto fail3; 588 589 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 590 if (rc) 591 goto fail4; 592 593 rc = efx_get_pf_index(efx, &nic_data->pf_index); 594 if (rc) 595 goto fail5; 596 597 rc = efx_ef10_init_datapath_caps(efx); 598 if (rc < 0) 599 goto fail5; 600 601 efx_ef10_read_licensed_features(efx); 602 603 /* We can have one VI for each vi_stride-byte region. 604 * However, until we use TX option descriptors we need up to four 605 * TX queues per channel for different checksumming combinations. 606 */ 607 if (nic_data->datapath_caps & 608 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN)) 609 efx->tx_queues_per_channel = 4; 610 else 611 efx->tx_queues_per_channel = 2; 612 efx->max_vis = efx_ef10_mem_map_size(efx) / efx->vi_stride; 613 if (!efx->max_vis) { 614 netif_err(efx, drv, efx->net_dev, "error determining max VIs\n"); 615 rc = -EIO; 616 goto fail5; 617 } 618 efx->max_channels = min_t(unsigned int, EFX_MAX_CHANNELS, 619 efx->max_vis / efx->tx_queues_per_channel); 620 efx->max_tx_channels = efx->max_channels; 621 if (WARN_ON(efx->max_channels == 0)) { 622 rc = -EIO; 623 goto fail5; 624 } 625 626 efx->rx_packet_len_offset = 627 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 628 629 if (nic_data->datapath_caps & 630 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_LBN)) 631 efx->net_dev->hw_features |= NETIF_F_RXFCS; 632 633 rc = efx_mcdi_port_get_number(efx); 634 if (rc < 0) 635 goto fail5; 636 efx->port_num = rc; 637 638 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr); 639 if (rc) 640 goto fail5; 641 642 rc = efx_ef10_get_timer_config(efx); 643 if (rc < 0) 644 goto fail5; 645 646 rc = efx_mcdi_mon_probe(efx); 647 if (rc && rc != -EPERM) 648 goto fail5; 649 650 efx_ptp_defer_probe_with_channel(efx); 651 652#ifdef CONFIG_SFC_SRIOV 653 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) { 654 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn; 655 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 656 657 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id); 658 } else 659#endif 660 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr); 661 662 INIT_LIST_HEAD(&nic_data->vlan_list); 663 mutex_init(&nic_data->vlan_lock); 664 665 /* Add unspecified VID to support VLAN filtering being disabled */ 666 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 667 if (rc) 668 goto fail_add_vid_unspec; 669 670 /* If VLAN filtering is enabled, we need VID 0 to get untagged 671 * traffic. It is added automatically if 8021q module is loaded, 672 * but we can't rely on it since module may be not loaded. 673 */ 674 rc = efx_ef10_add_vlan(efx, 0); 675 if (rc) 676 goto fail_add_vid_0; 677 678 if (nic_data->datapath_caps & 679 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) && 680 efx->mcdi->fn_flags & 681 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED)) 682 efx->net_dev->udp_tunnel_nic_info = &efx_ef10_udp_tunnels; 683 684 return 0; 685 686fail_add_vid_0: 687 efx_ef10_cleanup_vlans(efx); 688fail_add_vid_unspec: 689 mutex_destroy(&nic_data->vlan_lock); 690 efx_ptp_remove(efx); 691 efx_mcdi_mon_remove(efx); 692fail5: 693 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 694fail4: 695 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 696fail3: 697 efx_mcdi_detach(efx); 698 699 mutex_lock(&nic_data->udp_tunnels_lock); 700 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 701 (void)efx_ef10_set_udp_tnl_ports(efx, true); 702 mutex_unlock(&nic_data->udp_tunnels_lock); 703 mutex_destroy(&nic_data->udp_tunnels_lock); 704 705 efx_mcdi_fini(efx); 706fail2: 707 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 708fail1: 709 kfree(nic_data); 710 efx->nic_data = NULL; 711 return rc; 712} 713 714#ifdef EFX_USE_PIO 715 716static void efx_ef10_free_piobufs(struct efx_nic *efx) 717{ 718 struct efx_ef10_nic_data *nic_data = efx->nic_data; 719 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 720 unsigned int i; 721 int rc; 722 723 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 724 725 for (i = 0; i < nic_data->n_piobufs; i++) { 726 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 727 nic_data->piobuf_handle[i]); 728 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 729 NULL, 0, NULL); 730 WARN_ON(rc); 731 } 732 733 nic_data->n_piobufs = 0; 734} 735 736static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 737{ 738 struct efx_ef10_nic_data *nic_data = efx->nic_data; 739 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 740 unsigned int i; 741 size_t outlen; 742 int rc = 0; 743 744 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 745 746 for (i = 0; i < n; i++) { 747 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 748 outbuf, sizeof(outbuf), &outlen); 749 if (rc) { 750 /* Don't display the MC error if we didn't have space 751 * for a VF. 752 */ 753 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC)) 754 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF, 755 0, outbuf, outlen, rc); 756 break; 757 } 758 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 759 rc = -EIO; 760 break; 761 } 762 nic_data->piobuf_handle[i] = 763 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 764 netif_dbg(efx, probe, efx->net_dev, 765 "allocated PIO buffer %u handle %x\n", i, 766 nic_data->piobuf_handle[i]); 767 } 768 769 nic_data->n_piobufs = i; 770 if (rc) 771 efx_ef10_free_piobufs(efx); 772 return rc; 773} 774 775static int efx_ef10_link_piobufs(struct efx_nic *efx) 776{ 777 struct efx_ef10_nic_data *nic_data = efx->nic_data; 778 MCDI_DECLARE_BUF(inbuf, MC_CMD_LINK_PIOBUF_IN_LEN); 779 struct efx_channel *channel; 780 struct efx_tx_queue *tx_queue; 781 unsigned int offset, index; 782 int rc; 783 784 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 785 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 786 787 /* Link a buffer to each VI in the write-combining mapping */ 788 for (index = 0; index < nic_data->n_piobufs; ++index) { 789 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 790 nic_data->piobuf_handle[index]); 791 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 792 nic_data->pio_write_vi_base + index); 793 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 794 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 795 NULL, 0, NULL); 796 if (rc) { 797 netif_err(efx, drv, efx->net_dev, 798 "failed to link VI %u to PIO buffer %u (%d)\n", 799 nic_data->pio_write_vi_base + index, index, 800 rc); 801 goto fail; 802 } 803 netif_dbg(efx, probe, efx->net_dev, 804 "linked VI %u to PIO buffer %u\n", 805 nic_data->pio_write_vi_base + index, index); 806 } 807 808 /* Link a buffer to each TX queue */ 809 efx_for_each_channel(channel, efx) { 810 /* Extra channels, even those with TXQs (PTP), do not require 811 * PIO resources. 812 */ 813 if (!channel->type->want_pio || 814 channel->channel >= efx->xdp_channel_offset) 815 continue; 816 817 efx_for_each_channel_tx_queue(tx_queue, channel) { 818 /* We assign the PIO buffers to queues in 819 * reverse order to allow for the following 820 * special case. 821 */ 822 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 823 tx_queue->channel->channel - 1) * 824 efx_piobuf_size); 825 index = offset / nic_data->piobuf_size; 826 offset = offset % nic_data->piobuf_size; 827 828 /* When the host page size is 4K, the first 829 * host page in the WC mapping may be within 830 * the same VI page as the last TX queue. We 831 * can only link one buffer to each VI. 832 */ 833 if (tx_queue->queue == nic_data->pio_write_vi_base) { 834 BUG_ON(index != 0); 835 rc = 0; 836 } else { 837 MCDI_SET_DWORD(inbuf, 838 LINK_PIOBUF_IN_PIOBUF_HANDLE, 839 nic_data->piobuf_handle[index]); 840 MCDI_SET_DWORD(inbuf, 841 LINK_PIOBUF_IN_TXQ_INSTANCE, 842 tx_queue->queue); 843 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 844 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 845 NULL, 0, NULL); 846 } 847 848 if (rc) { 849 /* This is non-fatal; the TX path just 850 * won't use PIO for this queue 851 */ 852 netif_err(efx, drv, efx->net_dev, 853 "failed to link VI %u to PIO buffer %u (%d)\n", 854 tx_queue->queue, index, rc); 855 tx_queue->piobuf = NULL; 856 } else { 857 tx_queue->piobuf = 858 nic_data->pio_write_base + 859 index * efx->vi_stride + offset; 860 tx_queue->piobuf_offset = offset; 861 netif_dbg(efx, probe, efx->net_dev, 862 "linked VI %u to PIO buffer %u offset %x addr %p\n", 863 tx_queue->queue, index, 864 tx_queue->piobuf_offset, 865 tx_queue->piobuf); 866 } 867 } 868 } 869 870 return 0; 871 872fail: 873 /* inbuf was defined for MC_CMD_LINK_PIOBUF. We can use the same 874 * buffer for MC_CMD_UNLINK_PIOBUF because it's shorter. 875 */ 876 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_IN_LEN < MC_CMD_UNLINK_PIOBUF_IN_LEN); 877 while (index--) { 878 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 879 nic_data->pio_write_vi_base + index); 880 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 881 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 882 NULL, 0, NULL); 883 } 884 return rc; 885} 886 887static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 888{ 889 struct efx_channel *channel; 890 struct efx_tx_queue *tx_queue; 891 892 /* All our existing PIO buffers went away */ 893 efx_for_each_channel(channel, efx) 894 efx_for_each_channel_tx_queue(tx_queue, channel) 895 tx_queue->piobuf = NULL; 896} 897 898#else /* !EFX_USE_PIO */ 899 900static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 901{ 902 return n == 0 ? 0 : -ENOBUFS; 903} 904 905static int efx_ef10_link_piobufs(struct efx_nic *efx) 906{ 907 return 0; 908} 909 910static void efx_ef10_free_piobufs(struct efx_nic *efx) 911{ 912} 913 914static void efx_ef10_forget_old_piobufs(struct efx_nic *efx) 915{ 916} 917 918#endif /* EFX_USE_PIO */ 919 920static void efx_ef10_remove(struct efx_nic *efx) 921{ 922 struct efx_ef10_nic_data *nic_data = efx->nic_data; 923 int rc; 924 925#ifdef CONFIG_SFC_SRIOV 926 struct efx_ef10_nic_data *nic_data_pf; 927 struct pci_dev *pci_dev_pf; 928 struct efx_nic *efx_pf; 929 struct ef10_vf *vf; 930 931 if (efx->pci_dev->is_virtfn) { 932 pci_dev_pf = efx->pci_dev->physfn; 933 if (pci_dev_pf) { 934 efx_pf = pci_get_drvdata(pci_dev_pf); 935 nic_data_pf = efx_pf->nic_data; 936 vf = nic_data_pf->vf + nic_data->vf_index; 937 vf->efx = NULL; 938 } else 939 netif_info(efx, drv, efx->net_dev, 940 "Could not get the PF id from VF\n"); 941 } 942#endif 943 944 efx_ef10_cleanup_vlans(efx); 945 mutex_destroy(&nic_data->vlan_lock); 946 947 efx_ptp_remove(efx); 948 949 efx_mcdi_mon_remove(efx); 950 951 efx_mcdi_rx_free_indir_table(efx); 952 953 if (nic_data->wc_membase) 954 iounmap(nic_data->wc_membase); 955 956 rc = efx_mcdi_free_vis(efx); 957 WARN_ON(rc != 0); 958 959 if (!nic_data->must_restore_piobufs) 960 efx_ef10_free_piobufs(efx); 961 962 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag); 963 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag); 964 965 efx_mcdi_detach(efx); 966 967 memset(nic_data->udp_tunnels, 0, sizeof(nic_data->udp_tunnels)); 968 mutex_lock(&nic_data->udp_tunnels_lock); 969 (void)efx_ef10_set_udp_tnl_ports(efx, true); 970 mutex_unlock(&nic_data->udp_tunnels_lock); 971 972 mutex_destroy(&nic_data->udp_tunnels_lock); 973 974 efx_mcdi_fini(efx); 975 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 976 kfree(nic_data); 977} 978 979static int efx_ef10_probe_pf(struct efx_nic *efx) 980{ 981 return efx_ef10_probe(efx); 982} 983 984int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id, 985 u32 *port_flags, u32 *vadaptor_flags, 986 unsigned int *vlan_tags) 987{ 988 struct efx_ef10_nic_data *nic_data = efx->nic_data; 989 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN); 990 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN); 991 size_t outlen; 992 int rc; 993 994 if (nic_data->datapath_caps & 995 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) { 996 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID, 997 port_id); 998 999 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf), 1000 outbuf, sizeof(outbuf), &outlen); 1001 if (rc) 1002 return rc; 1003 1004 if (outlen < sizeof(outbuf)) { 1005 rc = -EIO; 1006 return rc; 1007 } 1008 } 1009 1010 if (port_flags) 1011 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS); 1012 if (vadaptor_flags) 1013 *vadaptor_flags = 1014 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS); 1015 if (vlan_tags) 1016 *vlan_tags = 1017 MCDI_DWORD(outbuf, 1018 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS); 1019 1020 return 0; 1021} 1022 1023int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id) 1024{ 1025 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN); 1026 1027 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); 1028 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf), 1029 NULL, 0, NULL); 1030} 1031 1032int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id) 1033{ 1034 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN); 1035 1036 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id); 1037 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf), 1038 NULL, 0, NULL); 1039} 1040 1041int efx_ef10_vport_add_mac(struct efx_nic *efx, 1042 unsigned int port_id, u8 *mac) 1043{ 1044 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN); 1045 1046 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id); 1047 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac); 1048 1049 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf, 1050 sizeof(inbuf), NULL, 0, NULL); 1051} 1052 1053int efx_ef10_vport_del_mac(struct efx_nic *efx, 1054 unsigned int port_id, u8 *mac) 1055{ 1056 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN); 1057 1058 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id); 1059 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac); 1060 1061 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf, 1062 sizeof(inbuf), NULL, 0, NULL); 1063} 1064 1065#ifdef CONFIG_SFC_SRIOV 1066static int efx_ef10_probe_vf(struct efx_nic *efx) 1067{ 1068 int rc; 1069 struct pci_dev *pci_dev_pf; 1070 1071 /* If the parent PF has no VF data structure, it doesn't know about this 1072 * VF so fail probe. The VF needs to be re-created. This can happen 1073 * if the PF driver is unloaded while the VF is assigned to a guest. 1074 */ 1075 pci_dev_pf = efx->pci_dev->physfn; 1076 if (pci_dev_pf) { 1077 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf); 1078 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data; 1079 1080 if (!nic_data_pf->vf) { 1081 netif_info(efx, drv, efx->net_dev, 1082 "The VF cannot link to its parent PF; " 1083 "please destroy and re-create the VF\n"); 1084 return -EBUSY; 1085 } 1086 } 1087 1088 rc = efx_ef10_probe(efx); 1089 if (rc) 1090 return rc; 1091 1092 rc = efx_ef10_get_vf_index(efx); 1093 if (rc) 1094 goto fail; 1095 1096 if (efx->pci_dev->is_virtfn) { 1097 if (efx->pci_dev->physfn) { 1098 struct efx_nic *efx_pf = 1099 pci_get_drvdata(efx->pci_dev->physfn); 1100 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data; 1101 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1102 1103 nic_data_p->vf[nic_data->vf_index].efx = efx; 1104 nic_data_p->vf[nic_data->vf_index].pci_dev = 1105 efx->pci_dev; 1106 } else 1107 netif_info(efx, drv, efx->net_dev, 1108 "Could not get the PF id from VF\n"); 1109 } 1110 1111 return 0; 1112 1113fail: 1114 efx_ef10_remove(efx); 1115 return rc; 1116} 1117#else 1118static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused))) 1119{ 1120 return 0; 1121} 1122#endif 1123 1124static int efx_ef10_alloc_vis(struct efx_nic *efx, 1125 unsigned int min_vis, unsigned int max_vis) 1126{ 1127 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1128 1129 return efx_mcdi_alloc_vis(efx, min_vis, max_vis, &nic_data->vi_base, 1130 &nic_data->n_allocated_vis); 1131} 1132 1133/* Note that the failure path of this function does not free 1134 * resources, as this will be done by efx_ef10_remove(). 1135 */ 1136static int efx_ef10_dimension_resources(struct efx_nic *efx) 1137{ 1138 unsigned int min_vis = max_t(unsigned int, efx->tx_queues_per_channel, 1139 efx_separate_tx_channels ? 2 : 1); 1140 unsigned int channel_vis, pio_write_vi_base, max_vis; 1141 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1142 unsigned int uc_mem_map_size, wc_mem_map_size; 1143 void __iomem *membase; 1144 int rc; 1145 1146 channel_vis = max(efx->n_channels, 1147 ((efx->n_tx_channels + efx->n_extra_tx_channels) * 1148 efx->tx_queues_per_channel) + 1149 efx->n_xdp_channels * efx->xdp_tx_per_channel); 1150 if (efx->max_vis && efx->max_vis < channel_vis) { 1151 netif_dbg(efx, drv, efx->net_dev, 1152 "Reducing channel VIs from %u to %u\n", 1153 channel_vis, efx->max_vis); 1154 channel_vis = efx->max_vis; 1155 } 1156 1157#ifdef EFX_USE_PIO 1158 /* Try to allocate PIO buffers if wanted and if the full 1159 * number of PIO buffers would be sufficient to allocate one 1160 * copy-buffer per TX channel. Failure is non-fatal, as there 1161 * are only a small number of PIO buffers shared between all 1162 * functions of the controller. 1163 */ 1164 if (efx_piobuf_size != 0 && 1165 nic_data->piobuf_size / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 1166 efx->n_tx_channels) { 1167 unsigned int n_piobufs = 1168 DIV_ROUND_UP(efx->n_tx_channels, 1169 nic_data->piobuf_size / efx_piobuf_size); 1170 1171 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 1172 if (rc == -ENOSPC) 1173 netif_dbg(efx, probe, efx->net_dev, 1174 "out of PIO buffers; cannot allocate more\n"); 1175 else if (rc == -EPERM) 1176 netif_dbg(efx, probe, efx->net_dev, 1177 "not permitted to allocate PIO buffers\n"); 1178 else if (rc) 1179 netif_err(efx, probe, efx->net_dev, 1180 "failed to allocate PIO buffers (%d)\n", rc); 1181 else 1182 netif_dbg(efx, probe, efx->net_dev, 1183 "allocated %u PIO buffers\n", n_piobufs); 1184 } 1185#else 1186 nic_data->n_piobufs = 0; 1187#endif 1188 1189 /* PIO buffers should be mapped with write-combining enabled, 1190 * and we want to make single UC and WC mappings rather than 1191 * several of each (in fact that's the only option if host 1192 * page size is >4K). So we may allocate some extra VIs just 1193 * for writing PIO buffers through. 1194 * 1195 * The UC mapping contains (channel_vis - 1) complete VIs and the 1196 * first 4K of the next VI. Then the WC mapping begins with 1197 * the remainder of this last VI. 1198 */ 1199 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * efx->vi_stride + 1200 ER_DZ_TX_PIOBUF); 1201 if (nic_data->n_piobufs) { 1202 /* pio_write_vi_base rounds down to give the number of complete 1203 * VIs inside the UC mapping. 1204 */ 1205 pio_write_vi_base = uc_mem_map_size / efx->vi_stride; 1206 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 1207 nic_data->n_piobufs) * 1208 efx->vi_stride) - 1209 uc_mem_map_size); 1210 max_vis = pio_write_vi_base + nic_data->n_piobufs; 1211 } else { 1212 pio_write_vi_base = 0; 1213 wc_mem_map_size = 0; 1214 max_vis = channel_vis; 1215 } 1216 1217 /* In case the last attached driver failed to free VIs, do it now */ 1218 rc = efx_mcdi_free_vis(efx); 1219 if (rc != 0) 1220 return rc; 1221 1222 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 1223 if (rc != 0) 1224 return rc; 1225 1226 if (nic_data->n_allocated_vis < channel_vis) { 1227 netif_info(efx, drv, efx->net_dev, 1228 "Could not allocate enough VIs to satisfy RSS" 1229 " requirements. Performance may not be optimal.\n"); 1230 /* We didn't get the VIs to populate our channels. 1231 * We could keep what we got but then we'd have more 1232 * interrupts than we need. 1233 * Instead calculate new max_channels and restart 1234 */ 1235 efx->max_channels = nic_data->n_allocated_vis; 1236 efx->max_tx_channels = 1237 nic_data->n_allocated_vis / efx->tx_queues_per_channel; 1238 1239 efx_mcdi_free_vis(efx); 1240 return -EAGAIN; 1241 } 1242 1243 /* If we didn't get enough VIs to map all the PIO buffers, free the 1244 * PIO buffers 1245 */ 1246 if (nic_data->n_piobufs && 1247 nic_data->n_allocated_vis < 1248 pio_write_vi_base + nic_data->n_piobufs) { 1249 netif_dbg(efx, probe, efx->net_dev, 1250 "%u VIs are not sufficient to map %u PIO buffers\n", 1251 nic_data->n_allocated_vis, nic_data->n_piobufs); 1252 efx_ef10_free_piobufs(efx); 1253 } 1254 1255 /* Shrink the original UC mapping of the memory BAR */ 1256 membase = ioremap(efx->membase_phys, uc_mem_map_size); 1257 if (!membase) { 1258 netif_err(efx, probe, efx->net_dev, 1259 "could not shrink memory BAR to %x\n", 1260 uc_mem_map_size); 1261 return -ENOMEM; 1262 } 1263 iounmap(efx->membase); 1264 efx->membase = membase; 1265 1266 /* Set up the WC mapping if needed */ 1267 if (wc_mem_map_size) { 1268 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 1269 uc_mem_map_size, 1270 wc_mem_map_size); 1271 if (!nic_data->wc_membase) { 1272 netif_err(efx, probe, efx->net_dev, 1273 "could not allocate WC mapping of size %x\n", 1274 wc_mem_map_size); 1275 return -ENOMEM; 1276 } 1277 nic_data->pio_write_vi_base = pio_write_vi_base; 1278 nic_data->pio_write_base = 1279 nic_data->wc_membase + 1280 (pio_write_vi_base * efx->vi_stride + ER_DZ_TX_PIOBUF - 1281 uc_mem_map_size); 1282 1283 rc = efx_ef10_link_piobufs(efx); 1284 if (rc) 1285 efx_ef10_free_piobufs(efx); 1286 } 1287 1288 netif_dbg(efx, probe, efx->net_dev, 1289 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 1290 &efx->membase_phys, efx->membase, uc_mem_map_size, 1291 nic_data->wc_membase, wc_mem_map_size); 1292 1293 return 0; 1294} 1295 1296static void efx_ef10_fini_nic(struct efx_nic *efx) 1297{ 1298 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1299 1300 spin_lock_bh(&efx->stats_lock); 1301 kfree(nic_data->mc_stats); 1302 nic_data->mc_stats = NULL; 1303 spin_unlock_bh(&efx->stats_lock); 1304} 1305 1306static int efx_ef10_init_nic(struct efx_nic *efx) 1307{ 1308 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1309 struct net_device *net_dev = efx->net_dev; 1310 netdev_features_t tun_feats, tso_feats; 1311 int rc; 1312 1313 if (nic_data->must_check_datapath_caps) { 1314 rc = efx_ef10_init_datapath_caps(efx); 1315 if (rc) 1316 return rc; 1317 nic_data->must_check_datapath_caps = false; 1318 } 1319 1320 if (efx->must_realloc_vis) { 1321 /* We cannot let the number of VIs change now */ 1322 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 1323 nic_data->n_allocated_vis); 1324 if (rc) 1325 return rc; 1326 efx->must_realloc_vis = false; 1327 } 1328 1329 nic_data->mc_stats = kmalloc(efx->num_mac_stats * sizeof(__le64), 1330 GFP_KERNEL); 1331 if (!nic_data->mc_stats) 1332 return -ENOMEM; 1333 1334 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 1335 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 1336 if (rc == 0) { 1337 rc = efx_ef10_link_piobufs(efx); 1338 if (rc) 1339 efx_ef10_free_piobufs(efx); 1340 } 1341 1342 /* Log an error on failure, but this is non-fatal. 1343 * Permission errors are less important - we've presumably 1344 * had the PIO buffer licence removed. 1345 */ 1346 if (rc == -EPERM) 1347 netif_dbg(efx, drv, efx->net_dev, 1348 "not permitted to restore PIO buffers\n"); 1349 else if (rc) 1350 netif_err(efx, drv, efx->net_dev, 1351 "failed to restore PIO buffers (%d)\n", rc); 1352 nic_data->must_restore_piobufs = false; 1353 } 1354 1355 /* encap features might change during reset if fw variant changed */ 1356 if (efx_has_cap(efx, VXLAN_NVGRE) && !efx_ef10_is_vf(efx)) 1357 net_dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1358 else 1359 net_dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 1360 1361 tun_feats = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | 1362 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM; 1363 tso_feats = NETIF_F_TSO | NETIF_F_TSO6; 1364 1365 if (efx_has_cap(efx, TX_TSO_V2_ENCAP)) { 1366 /* If this is first nic_init, or if it is a reset and a new fw 1367 * variant has added new features, enable them by default. 1368 * If the features are not new, maintain their current value. 1369 */ 1370 if (!(net_dev->hw_features & tun_feats)) 1371 net_dev->features |= tun_feats; 1372 net_dev->hw_enc_features |= tun_feats | tso_feats; 1373 net_dev->hw_features |= tun_feats; 1374 } else { 1375 net_dev->hw_enc_features &= ~(tun_feats | tso_feats); 1376 net_dev->hw_features &= ~tun_feats; 1377 net_dev->features &= ~tun_feats; 1378 } 1379 1380 /* don't fail init if RSS setup doesn't work */ 1381 rc = efx->type->rx_push_rss_config(efx, false, 1382 efx->rss_context.rx_indir_table, NULL); 1383 1384 return 0; 1385} 1386 1387static void efx_ef10_table_reset_mc_allocations(struct efx_nic *efx) 1388{ 1389 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1390#ifdef CONFIG_SFC_SRIOV 1391 unsigned int i; 1392#endif 1393 1394 /* All our allocations have been reset */ 1395 efx->must_realloc_vis = true; 1396 efx_mcdi_filter_table_reset_mc_allocations(efx); 1397 nic_data->must_restore_piobufs = true; 1398 efx_ef10_forget_old_piobufs(efx); 1399 efx->rss_context.context_id = EFX_MCDI_RSS_CONTEXT_INVALID; 1400 1401 /* Driver-created vswitches and vports must be re-created */ 1402 nic_data->must_probe_vswitching = true; 1403 efx->vport_id = EVB_PORT_ID_ASSIGNED; 1404#ifdef CONFIG_SFC_SRIOV 1405 if (nic_data->vf) 1406 for (i = 0; i < efx->vf_count; i++) 1407 nic_data->vf[i].vport_id = 0; 1408#endif 1409} 1410 1411static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason) 1412{ 1413 if (reason == RESET_TYPE_MC_FAILURE) 1414 return RESET_TYPE_DATAPATH; 1415 1416 return efx_mcdi_map_reset_reason(reason); 1417} 1418 1419static int efx_ef10_map_reset_flags(u32 *flags) 1420{ 1421 enum { 1422 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 1423 ETH_RESET_SHARED_SHIFT), 1424 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 1425 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 1426 ETH_RESET_PHY | ETH_RESET_MGMT) << 1427 ETH_RESET_SHARED_SHIFT) 1428 }; 1429 1430 /* We assume for now that our PCI function is permitted to 1431 * reset everything. 1432 */ 1433 1434 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 1435 *flags &= ~EF10_RESET_MC; 1436 return RESET_TYPE_WORLD; 1437 } 1438 1439 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 1440 *flags &= ~EF10_RESET_PORT; 1441 return RESET_TYPE_ALL; 1442 } 1443 1444 /* no invisible reset implemented */ 1445 1446 return -EINVAL; 1447} 1448 1449static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 1450{ 1451 int rc = efx_mcdi_reset(efx, reset_type); 1452 1453 /* Unprivileged functions return -EPERM, but need to return success 1454 * here so that the datapath is brought back up. 1455 */ 1456 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM) 1457 rc = 0; 1458 1459 /* If it was a port reset, trigger reallocation of MC resources. 1460 * Note that on an MC reset nothing needs to be done now because we'll 1461 * detect the MC reset later and handle it then. 1462 * For an FLR, we never get an MC reset event, but the MC has reset all 1463 * resources assigned to us, so we have to trigger reallocation now. 1464 */ 1465 if ((reset_type == RESET_TYPE_ALL || 1466 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 1467 efx_ef10_table_reset_mc_allocations(efx); 1468 return rc; 1469} 1470 1471#define EF10_DMA_STAT(ext_name, mcdi_name) \ 1472 [EF10_STAT_ ## ext_name] = \ 1473 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1474#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 1475 [EF10_STAT_ ## int_name] = \ 1476 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 1477#define EF10_OTHER_STAT(ext_name) \ 1478 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 1479 1480static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 1481 EF10_DMA_STAT(port_tx_bytes, TX_BYTES), 1482 EF10_DMA_STAT(port_tx_packets, TX_PKTS), 1483 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 1484 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS), 1485 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 1486 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 1487 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 1488 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 1489 EF10_DMA_STAT(port_tx_64, TX_64_PKTS), 1490 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 1491 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 1492 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 1493 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 1494 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 1495 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 1496 EF10_DMA_STAT(port_rx_bytes, RX_BYTES), 1497 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES), 1498 EF10_OTHER_STAT(port_rx_good_bytes), 1499 EF10_OTHER_STAT(port_rx_bad_bytes), 1500 EF10_DMA_STAT(port_rx_packets, RX_PKTS), 1501 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 1502 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 1503 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 1504 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS), 1505 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 1506 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 1507 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 1508 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 1509 EF10_DMA_STAT(port_rx_64, RX_64_PKTS), 1510 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 1511 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 1512 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 1513 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 1514 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 1515 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 1516 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 1517 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 1518 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 1519 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 1520 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 1521 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 1522 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 1523 EFX_GENERIC_SW_STAT(rx_noskb_drops), 1524 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 1525 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 1526 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 1527 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 1528 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB), 1529 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB), 1530 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING), 1531 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 1532 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 1533 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 1534 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS), 1535 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS), 1536 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS), 1537 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES), 1538 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS), 1539 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES), 1540 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS), 1541 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES), 1542 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS), 1543 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES), 1544 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW), 1545 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS), 1546 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES), 1547 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS), 1548 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES), 1549 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS), 1550 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES), 1551 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS), 1552 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES), 1553 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW), 1554 EF10_DMA_STAT(fec_uncorrected_errors, FEC_UNCORRECTED_ERRORS), 1555 EF10_DMA_STAT(fec_corrected_errors, FEC_CORRECTED_ERRORS), 1556 EF10_DMA_STAT(fec_corrected_symbols_lane0, FEC_CORRECTED_SYMBOLS_LANE0), 1557 EF10_DMA_STAT(fec_corrected_symbols_lane1, FEC_CORRECTED_SYMBOLS_LANE1), 1558 EF10_DMA_STAT(fec_corrected_symbols_lane2, FEC_CORRECTED_SYMBOLS_LANE2), 1559 EF10_DMA_STAT(fec_corrected_symbols_lane3, FEC_CORRECTED_SYMBOLS_LANE3), 1560 EF10_DMA_STAT(ctpio_vi_busy_fallback, CTPIO_VI_BUSY_FALLBACK), 1561 EF10_DMA_STAT(ctpio_long_write_success, CTPIO_LONG_WRITE_SUCCESS), 1562 EF10_DMA_STAT(ctpio_missing_dbell_fail, CTPIO_MISSING_DBELL_FAIL), 1563 EF10_DMA_STAT(ctpio_overflow_fail, CTPIO_OVERFLOW_FAIL), 1564 EF10_DMA_STAT(ctpio_underflow_fail, CTPIO_UNDERFLOW_FAIL), 1565 EF10_DMA_STAT(ctpio_timeout_fail, CTPIO_TIMEOUT_FAIL), 1566 EF10_DMA_STAT(ctpio_noncontig_wr_fail, CTPIO_NONCONTIG_WR_FAIL), 1567 EF10_DMA_STAT(ctpio_frm_clobber_fail, CTPIO_FRM_CLOBBER_FAIL), 1568 EF10_DMA_STAT(ctpio_invalid_wr_fail, CTPIO_INVALID_WR_FAIL), 1569 EF10_DMA_STAT(ctpio_vi_clobber_fallback, CTPIO_VI_CLOBBER_FALLBACK), 1570 EF10_DMA_STAT(ctpio_unqualified_fallback, CTPIO_UNQUALIFIED_FALLBACK), 1571 EF10_DMA_STAT(ctpio_runt_fallback, CTPIO_RUNT_FALLBACK), 1572 EF10_DMA_STAT(ctpio_success, CTPIO_SUCCESS), 1573 EF10_DMA_STAT(ctpio_fallback, CTPIO_FALLBACK), 1574 EF10_DMA_STAT(ctpio_poison, CTPIO_POISON), 1575 EF10_DMA_STAT(ctpio_erase, CTPIO_ERASE), 1576}; 1577 1578#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \ 1579 (1ULL << EF10_STAT_port_tx_packets) | \ 1580 (1ULL << EF10_STAT_port_tx_pause) | \ 1581 (1ULL << EF10_STAT_port_tx_unicast) | \ 1582 (1ULL << EF10_STAT_port_tx_multicast) | \ 1583 (1ULL << EF10_STAT_port_tx_broadcast) | \ 1584 (1ULL << EF10_STAT_port_rx_bytes) | \ 1585 (1ULL << \ 1586 EF10_STAT_port_rx_bytes_minus_good_bytes) | \ 1587 (1ULL << EF10_STAT_port_rx_good_bytes) | \ 1588 (1ULL << EF10_STAT_port_rx_bad_bytes) | \ 1589 (1ULL << EF10_STAT_port_rx_packets) | \ 1590 (1ULL << EF10_STAT_port_rx_good) | \ 1591 (1ULL << EF10_STAT_port_rx_bad) | \ 1592 (1ULL << EF10_STAT_port_rx_pause) | \ 1593 (1ULL << EF10_STAT_port_rx_control) | \ 1594 (1ULL << EF10_STAT_port_rx_unicast) | \ 1595 (1ULL << EF10_STAT_port_rx_multicast) | \ 1596 (1ULL << EF10_STAT_port_rx_broadcast) | \ 1597 (1ULL << EF10_STAT_port_rx_lt64) | \ 1598 (1ULL << EF10_STAT_port_rx_64) | \ 1599 (1ULL << EF10_STAT_port_rx_65_to_127) | \ 1600 (1ULL << EF10_STAT_port_rx_128_to_255) | \ 1601 (1ULL << EF10_STAT_port_rx_256_to_511) | \ 1602 (1ULL << EF10_STAT_port_rx_512_to_1023) |\ 1603 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\ 1604 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\ 1605 (1ULL << EF10_STAT_port_rx_gtjumbo) | \ 1606 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\ 1607 (1ULL << EF10_STAT_port_rx_overflow) | \ 1608 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\ 1609 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 1610 (1ULL << GENERIC_STAT_rx_noskb_drops)) 1611 1612/* On 7000 series NICs, these statistics are only provided by the 10G MAC. 1613 * For a 10G/40G switchable port we do not expose these because they might 1614 * not include all the packets they should. 1615 * On 8000 series NICs these statistics are always provided. 1616 */ 1617#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \ 1618 (1ULL << EF10_STAT_port_tx_lt64) | \ 1619 (1ULL << EF10_STAT_port_tx_64) | \ 1620 (1ULL << EF10_STAT_port_tx_65_to_127) |\ 1621 (1ULL << EF10_STAT_port_tx_128_to_255) |\ 1622 (1ULL << EF10_STAT_port_tx_256_to_511) |\ 1623 (1ULL << EF10_STAT_port_tx_512_to_1023) |\ 1624 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\ 1625 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo)) 1626 1627/* These statistics are only provided by the 40G MAC. For a 10G/40G 1628 * switchable port we do expose these because the errors will otherwise 1629 * be silent. 1630 */ 1631#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\ 1632 (1ULL << EF10_STAT_port_rx_length_error)) 1633 1634/* These statistics are only provided if the firmware supports the 1635 * capability PM_AND_RXDP_COUNTERS. 1636 */ 1637#define HUNT_PM_AND_RXDP_STAT_MASK ( \ 1638 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \ 1639 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \ 1640 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \ 1641 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \ 1642 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \ 1643 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \ 1644 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \ 1645 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \ 1646 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \ 1647 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \ 1648 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \ 1649 (1ULL << EF10_STAT_port_rx_dp_hlb_wait)) 1650 1651/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V2, 1652 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V2 in 1653 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1654 * These bits are in the second u64 of the raw mask. 1655 */ 1656#define EF10_FEC_STAT_MASK ( \ 1657 (1ULL << (EF10_STAT_fec_uncorrected_errors - 64)) | \ 1658 (1ULL << (EF10_STAT_fec_corrected_errors - 64)) | \ 1659 (1ULL << (EF10_STAT_fec_corrected_symbols_lane0 - 64)) | \ 1660 (1ULL << (EF10_STAT_fec_corrected_symbols_lane1 - 64)) | \ 1661 (1ULL << (EF10_STAT_fec_corrected_symbols_lane2 - 64)) | \ 1662 (1ULL << (EF10_STAT_fec_corrected_symbols_lane3 - 64))) 1663 1664/* These statistics are only provided if the NIC supports MC_CMD_MAC_STATS_V3, 1665 * indicated by returning a value >= MC_CMD_MAC_NSTATS_V3 in 1666 * MC_CMD_GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS. 1667 * These bits are in the second u64 of the raw mask. 1668 */ 1669#define EF10_CTPIO_STAT_MASK ( \ 1670 (1ULL << (EF10_STAT_ctpio_vi_busy_fallback - 64)) | \ 1671 (1ULL << (EF10_STAT_ctpio_long_write_success - 64)) | \ 1672 (1ULL << (EF10_STAT_ctpio_missing_dbell_fail - 64)) | \ 1673 (1ULL << (EF10_STAT_ctpio_overflow_fail - 64)) | \ 1674 (1ULL << (EF10_STAT_ctpio_underflow_fail - 64)) | \ 1675 (1ULL << (EF10_STAT_ctpio_timeout_fail - 64)) | \ 1676 (1ULL << (EF10_STAT_ctpio_noncontig_wr_fail - 64)) | \ 1677 (1ULL << (EF10_STAT_ctpio_frm_clobber_fail - 64)) | \ 1678 (1ULL << (EF10_STAT_ctpio_invalid_wr_fail - 64)) | \ 1679 (1ULL << (EF10_STAT_ctpio_vi_clobber_fallback - 64)) | \ 1680 (1ULL << (EF10_STAT_ctpio_unqualified_fallback - 64)) | \ 1681 (1ULL << (EF10_STAT_ctpio_runt_fallback - 64)) | \ 1682 (1ULL << (EF10_STAT_ctpio_success - 64)) | \ 1683 (1ULL << (EF10_STAT_ctpio_fallback - 64)) | \ 1684 (1ULL << (EF10_STAT_ctpio_poison - 64)) | \ 1685 (1ULL << (EF10_STAT_ctpio_erase - 64))) 1686 1687static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 1688{ 1689 u64 raw_mask = HUNT_COMMON_STAT_MASK; 1690 u32 port_caps = efx_mcdi_phy_get_caps(efx); 1691 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1692 1693 if (!(efx->mcdi->fn_flags & 1694 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL)) 1695 return 0; 1696 1697 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) { 1698 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 1699 /* 8000 series have everything even at 40G */ 1700 if (nic_data->datapath_caps2 & 1701 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN)) 1702 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1703 } else { 1704 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 1705 } 1706 1707 if (nic_data->datapath_caps & 1708 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 1709 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 1710 1711 return raw_mask; 1712} 1713 1714static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 1715{ 1716 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1717 u64 raw_mask[2]; 1718 1719 raw_mask[0] = efx_ef10_raw_stat_mask(efx); 1720 1721 /* Only show vadaptor stats when EVB capability is present */ 1722 if (nic_data->datapath_caps & 1723 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) { 1724 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1); 1725 raw_mask[1] = (1ULL << (EF10_STAT_V1_COUNT - 64)) - 1; 1726 } else { 1727 raw_mask[1] = 0; 1728 } 1729 /* Only show FEC stats when NIC supports MC_CMD_MAC_STATS_V2 */ 1730 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V2) 1731 raw_mask[1] |= EF10_FEC_STAT_MASK; 1732 1733 /* CTPIO stats appear in V3. Only show them on devices that actually 1734 * support CTPIO. Although this driver doesn't use CTPIO others might, 1735 * and we may be reporting the stats for the underlying port. 1736 */ 1737 if (efx->num_mac_stats >= MC_CMD_MAC_NSTATS_V3 && 1738 (nic_data->datapath_caps2 & 1739 (1 << MC_CMD_GET_CAPABILITIES_V4_OUT_CTPIO_LBN))) 1740 raw_mask[1] |= EF10_CTPIO_STAT_MASK; 1741 1742#if BITS_PER_LONG == 64 1743 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2); 1744 mask[0] = raw_mask[0]; 1745 mask[1] = raw_mask[1]; 1746#else 1747 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3); 1748 mask[0] = raw_mask[0] & 0xffffffff; 1749 mask[1] = raw_mask[0] >> 32; 1750 mask[2] = raw_mask[1] & 0xffffffff; 1751#endif 1752} 1753 1754static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 1755{ 1756 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1757 1758 efx_ef10_get_stat_mask(efx, mask); 1759 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1760 mask, names); 1761} 1762 1763static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats, 1764 struct rtnl_link_stats64 *core_stats) 1765{ 1766 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1767 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1768 u64 *stats = nic_data->stats; 1769 size_t stats_count = 0, index; 1770 1771 efx_ef10_get_stat_mask(efx, mask); 1772 1773 if (full_stats) { 1774 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 1775 if (efx_ef10_stat_desc[index].name) { 1776 *full_stats++ = stats[index]; 1777 ++stats_count; 1778 } 1779 } 1780 } 1781 1782 if (!core_stats) 1783 return stats_count; 1784 1785 if (nic_data->datapath_caps & 1786 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) { 1787 /* Use vadaptor stats. */ 1788 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] + 1789 stats[EF10_STAT_rx_multicast] + 1790 stats[EF10_STAT_rx_broadcast]; 1791 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] + 1792 stats[EF10_STAT_tx_multicast] + 1793 stats[EF10_STAT_tx_broadcast]; 1794 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] + 1795 stats[EF10_STAT_rx_multicast_bytes] + 1796 stats[EF10_STAT_rx_broadcast_bytes]; 1797 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] + 1798 stats[EF10_STAT_tx_multicast_bytes] + 1799 stats[EF10_STAT_tx_broadcast_bytes]; 1800 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] + 1801 stats[GENERIC_STAT_rx_noskb_drops]; 1802 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1803 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1804 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1805 core_stats->rx_errors = core_stats->rx_crc_errors; 1806 core_stats->tx_errors = stats[EF10_STAT_tx_bad]; 1807 } else { 1808 /* Use port stats. */ 1809 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets]; 1810 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets]; 1811 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes]; 1812 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes]; 1813 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] + 1814 stats[GENERIC_STAT_rx_nodesc_trunc] + 1815 stats[GENERIC_STAT_rx_noskb_drops]; 1816 core_stats->multicast = stats[EF10_STAT_port_rx_multicast]; 1817 core_stats->rx_length_errors = 1818 stats[EF10_STAT_port_rx_gtjumbo] + 1819 stats[EF10_STAT_port_rx_length_error]; 1820 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad]; 1821 core_stats->rx_frame_errors = 1822 stats[EF10_STAT_port_rx_align_error]; 1823 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow]; 1824 core_stats->rx_errors = (core_stats->rx_length_errors + 1825 core_stats->rx_crc_errors + 1826 core_stats->rx_frame_errors); 1827 } 1828 1829 return stats_count; 1830} 1831 1832static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats, 1833 struct rtnl_link_stats64 *core_stats) 1834{ 1835 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1836 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1837 u64 *stats = nic_data->stats; 1838 1839 efx_ef10_get_stat_mask(efx, mask); 1840 1841 /* If NIC was fini'd (probably resetting), then we can't read 1842 * updated stats right now. 1843 */ 1844 if (nic_data->mc_stats) { 1845 efx_nic_copy_stats(efx, nic_data->mc_stats); 1846 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 1847 mask, stats, nic_data->mc_stats, false); 1848 } 1849 1850 /* Update derived statistics */ 1851 efx_nic_fix_nodesc_drop_stat(efx, 1852 &stats[EF10_STAT_port_rx_nodesc_drops]); 1853 /* MC Firmware reads RX_BYTES and RX_GOOD_BYTES from the MAC. 1854 * It then calculates RX_BAD_BYTES and DMAs it to us with RX_BYTES. 1855 * We report these as port_rx_ stats. We are not given RX_GOOD_BYTES. 1856 * Here we calculate port_rx_good_bytes. 1857 */ 1858 stats[EF10_STAT_port_rx_good_bytes] = 1859 stats[EF10_STAT_port_rx_bytes] - 1860 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]; 1861 1862 /* The asynchronous reads used to calculate RX_BAD_BYTES in 1863 * MC Firmware are done such that we should not see an increase in 1864 * RX_BAD_BYTES when a good packet has arrived. Unfortunately this 1865 * does mean that the stat can decrease at times. Here we do not 1866 * update the stat unless it has increased or has gone to zero 1867 * (In the case of the NIC rebooting). 1868 * Please see Bug 33781 for a discussion of why things work this way. 1869 */ 1870 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes], 1871 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]); 1872 efx_update_sw_stats(efx, stats); 1873 1874 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1875} 1876 1877static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx) 1878 __must_hold(&efx->stats_lock) 1879{ 1880 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN); 1881 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1882 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 1883 __le64 generation_start, generation_end; 1884 u64 *stats = nic_data->stats; 1885 u32 dma_len = efx->num_mac_stats * sizeof(u64); 1886 struct efx_buffer stats_buf; 1887 __le64 *dma_stats; 1888 int rc; 1889 1890 spin_unlock_bh(&efx->stats_lock); 1891 1892 efx_ef10_get_stat_mask(efx, mask); 1893 1894 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_KERNEL); 1895 if (rc) { 1896 spin_lock_bh(&efx->stats_lock); 1897 return rc; 1898 } 1899 1900 dma_stats = stats_buf.addr; 1901 dma_stats[efx->num_mac_stats - 1] = EFX_MC_STATS_GENERATION_INVALID; 1902 1903 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr); 1904 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD, 1905 MAC_STATS_IN_DMA, 1); 1906 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len); 1907 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1908 1909 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf), 1910 NULL, 0, NULL); 1911 spin_lock_bh(&efx->stats_lock); 1912 if (rc) { 1913 /* Expect ENOENT if DMA queues have not been set up */ 1914 if (rc != -ENOENT || atomic_read(&efx->active_queues)) 1915 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS, 1916 sizeof(inbuf), NULL, 0, rc); 1917 goto out; 1918 } 1919 1920 generation_end = dma_stats[efx->num_mac_stats - 1]; 1921 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) { 1922 WARN_ON_ONCE(1); 1923 goto out; 1924 } 1925 rmb(); 1926 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 1927 stats, stats_buf.addr, false); 1928 rmb(); 1929 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 1930 if (generation_end != generation_start) { 1931 rc = -EAGAIN; 1932 goto out; 1933 } 1934 1935 efx_update_sw_stats(efx, stats); 1936out: 1937 /* releasing a DMA coherent buffer with BH disabled can panic */ 1938 spin_unlock_bh(&efx->stats_lock); 1939 efx_nic_free_buffer(efx, &stats_buf); 1940 spin_lock_bh(&efx->stats_lock); 1941 return rc; 1942} 1943 1944static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats, 1945 struct rtnl_link_stats64 *core_stats) 1946{ 1947 if (efx_ef10_try_update_nic_stats_vf(efx)) 1948 return 0; 1949 1950 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1951} 1952 1953static size_t efx_ef10_update_stats_atomic_vf(struct efx_nic *efx, u64 *full_stats, 1954 struct rtnl_link_stats64 *core_stats) 1955{ 1956 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1957 1958 /* In atomic context, cannot update HW stats. Just update the 1959 * software stats and return so the caller can continue. 1960 */ 1961 efx_update_sw_stats(efx, nic_data->stats); 1962 return efx_ef10_update_stats_common(efx, full_stats, core_stats); 1963} 1964 1965static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1966{ 1967 struct efx_nic *efx = channel->efx; 1968 unsigned int mode, usecs; 1969 efx_dword_t timer_cmd; 1970 1971 if (channel->irq_moderation_us) { 1972 mode = 3; 1973 usecs = channel->irq_moderation_us; 1974 } else { 1975 mode = 0; 1976 usecs = 0; 1977 } 1978 1979 if (EFX_EF10_WORKAROUND_61265(efx)) { 1980 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN); 1981 unsigned int ns = usecs * 1000; 1982 1983 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE, 1984 channel->channel); 1985 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns); 1986 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns); 1987 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode); 1988 1989 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR, 1990 inbuf, sizeof(inbuf), 0, NULL, 0); 1991 } else if (EFX_EF10_WORKAROUND_35388(efx)) { 1992 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 1993 1994 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1995 EFE_DD_EVQ_IND_TIMER_FLAGS, 1996 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1997 ERF_DD_EVQ_IND_TIMER_VAL, ticks); 1998 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1999 channel->channel); 2000 } else { 2001 unsigned int ticks = efx_usecs_to_ticks(efx, usecs); 2002 2003 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 2004 ERF_DZ_TC_TIMER_VAL, ticks, 2005 ERF_FZ_TC_TMR_REL_VAL, ticks); 2006 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 2007 channel->channel); 2008 } 2009} 2010 2011static void efx_ef10_get_wol_vf(struct efx_nic *efx, 2012 struct ethtool_wolinfo *wol) {} 2013 2014static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type) 2015{ 2016 return -EOPNOTSUPP; 2017} 2018 2019static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 2020{ 2021 wol->supported = 0; 2022 wol->wolopts = 0; 2023 memset(&wol->sopass, 0, sizeof(wol->sopass)); 2024} 2025 2026static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 2027{ 2028 if (type != 0) 2029 return -EINVAL; 2030 return 0; 2031} 2032 2033static void efx_ef10_mcdi_request(struct efx_nic *efx, 2034 const efx_dword_t *hdr, size_t hdr_len, 2035 const efx_dword_t *sdu, size_t sdu_len) 2036{ 2037 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2038 u8 *pdu = nic_data->mcdi_buf.addr; 2039 2040 memcpy(pdu, hdr, hdr_len); 2041 memcpy(pdu + hdr_len, sdu, sdu_len); 2042 wmb(); 2043 2044 /* The hardware provides 'low' and 'high' (doorbell) registers 2045 * for passing the 64-bit address of an MCDI request to 2046 * firmware. However the dwords are swapped by firmware. The 2047 * least significant bits of the doorbell are then 0 for all 2048 * MCDI requests due to alignment. 2049 */ 2050 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 2051 ER_DZ_MC_DB_LWRD); 2052 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 2053 ER_DZ_MC_DB_HWRD); 2054} 2055 2056static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 2057{ 2058 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2059 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 2060 2061 rmb(); 2062 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 2063} 2064 2065static void 2066efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 2067 size_t offset, size_t outlen) 2068{ 2069 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2070 const u8 *pdu = nic_data->mcdi_buf.addr; 2071 2072 memcpy(outbuf, pdu + offset, outlen); 2073} 2074 2075static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx) 2076{ 2077 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2078 2079 /* All our allocations have been reset */ 2080 efx_ef10_table_reset_mc_allocations(efx); 2081 2082 /* The datapath firmware might have been changed */ 2083 nic_data->must_check_datapath_caps = true; 2084 2085 /* MAC statistics have been cleared on the NIC; clear the local 2086 * statistic that we update with efx_update_diff_stat(). 2087 */ 2088 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0; 2089} 2090 2091static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 2092{ 2093 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2094 int rc; 2095 2096 rc = efx_ef10_get_warm_boot_count(efx); 2097 if (rc < 0) { 2098 /* The firmware is presumably in the process of 2099 * rebooting. However, we are supposed to report each 2100 * reboot just once, so we must only do that once we 2101 * can read and store the updated warm boot count. 2102 */ 2103 return 0; 2104 } 2105 2106 if (rc == nic_data->warm_boot_count) 2107 return 0; 2108 2109 nic_data->warm_boot_count = rc; 2110 efx_ef10_mcdi_reboot_detected(efx); 2111 2112 return -EIO; 2113} 2114 2115/* Handle an MSI interrupt 2116 * 2117 * Handle an MSI hardware interrupt. This routine schedules event 2118 * queue processing. No interrupt acknowledgement cycle is necessary. 2119 * Also, we never need to check that the interrupt is for us, since 2120 * MSI interrupts cannot be shared. 2121 */ 2122static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 2123{ 2124 struct efx_msi_context *context = dev_id; 2125 struct efx_nic *efx = context->efx; 2126 2127 netif_vdbg(efx, intr, efx->net_dev, 2128 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 2129 2130 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 2131 /* Note test interrupts */ 2132 if (context->index == efx->irq_level) 2133 efx->last_irq_cpu = raw_smp_processor_id(); 2134 2135 /* Schedule processing of the channel */ 2136 efx_schedule_channel_irq(efx->channel[context->index]); 2137 } 2138 2139 return IRQ_HANDLED; 2140} 2141 2142static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 2143{ 2144 struct efx_nic *efx = dev_id; 2145 bool soft_enabled = READ_ONCE(efx->irq_soft_enabled); 2146 struct efx_channel *channel; 2147 efx_dword_t reg; 2148 u32 queues; 2149 2150 /* Read the ISR which also ACKs the interrupts */ 2151 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 2152 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 2153 2154 if (queues == 0) 2155 return IRQ_NONE; 2156 2157 if (likely(soft_enabled)) { 2158 /* Note test interrupts */ 2159 if (queues & (1U << efx->irq_level)) 2160 efx->last_irq_cpu = raw_smp_processor_id(); 2161 2162 efx_for_each_channel(channel, efx) { 2163 if (queues & 1) 2164 efx_schedule_channel_irq(channel); 2165 queues >>= 1; 2166 } 2167 } 2168 2169 netif_vdbg(efx, intr, efx->net_dev, 2170 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 2171 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 2172 2173 return IRQ_HANDLED; 2174} 2175 2176static int efx_ef10_irq_test_generate(struct efx_nic *efx) 2177{ 2178 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 2179 2180 if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true, 2181 NULL) == 0) 2182 return -ENOTSUPP; 2183 2184 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 2185 2186 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 2187 return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 2188 inbuf, sizeof(inbuf), NULL, 0, NULL); 2189} 2190 2191static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 2192{ 2193 /* low two bits of label are what we want for type */ 2194 BUILD_BUG_ON((EFX_TXQ_TYPE_OUTER_CSUM | EFX_TXQ_TYPE_INNER_CSUM) != 3); 2195 tx_queue->type = tx_queue->label & 3; 2196 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 2197 (tx_queue->ptr_mask + 1) * 2198 sizeof(efx_qword_t), 2199 GFP_KERNEL); 2200} 2201 2202/* This writes to the TX_DESC_WPTR and also pushes data */ 2203static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 2204 const efx_qword_t *txd) 2205{ 2206 unsigned int write_ptr; 2207 efx_oword_t reg; 2208 2209 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2210 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 2211 reg.qword[0] = *txd; 2212 efx_writeo_page(tx_queue->efx, ®, 2213 ER_DZ_TX_DESC_UPD, tx_queue->queue); 2214} 2215 2216/* Add Firmware-Assisted TSO v2 option descriptors to a queue. 2217 */ 2218int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 2219 bool *data_mapped) 2220{ 2221 struct efx_tx_buffer *buffer; 2222 u16 inner_ipv4_id = 0; 2223 u16 outer_ipv4_id = 0; 2224 struct tcphdr *tcp; 2225 struct iphdr *ip; 2226 u16 ip_tot_len; 2227 u32 seqnum; 2228 u32 mss; 2229 2230 EFX_WARN_ON_ONCE_PARANOID(tx_queue->tso_version != 2); 2231 2232 mss = skb_shinfo(skb)->gso_size; 2233 2234 if (unlikely(mss < 4)) { 2235 WARN_ONCE(1, "MSS of %u is too small for TSO v2\n", mss); 2236 return -EINVAL; 2237 } 2238 2239 if (skb->encapsulation) { 2240 if (!tx_queue->tso_encap) 2241 return -EINVAL; 2242 ip = ip_hdr(skb); 2243 if (ip->version == 4) 2244 outer_ipv4_id = ntohs(ip->id); 2245 2246 ip = inner_ip_hdr(skb); 2247 tcp = inner_tcp_hdr(skb); 2248 } else { 2249 ip = ip_hdr(skb); 2250 tcp = tcp_hdr(skb); 2251 } 2252 2253 /* 8000-series EF10 hardware requires that IP Total Length be 2254 * greater than or equal to the value it will have in each segment 2255 * (which is at most mss + 208 + TCP header length), but also less 2256 * than (0x10000 - inner_network_header). Otherwise the TCP 2257 * checksum calculation will be broken for encapsulated packets. 2258 * We fill in ip->tot_len with 0xff30, which should satisfy the 2259 * first requirement unless the MSS is ridiculously large (which 2260 * should be impossible as the driver max MTU is 9216); it is 2261 * guaranteed to satisfy the second as we only attempt TSO if 2262 * inner_network_header <= 208. 2263 */ 2264 ip_tot_len = 0x10000 - EFX_TSO2_MAX_HDRLEN; 2265 EFX_WARN_ON_ONCE_PARANOID(mss + EFX_TSO2_MAX_HDRLEN + 2266 (tcp->doff << 2u) > ip_tot_len); 2267 2268 if (ip->version == 4) { 2269 ip->tot_len = htons(ip_tot_len); 2270 ip->check = 0; 2271 inner_ipv4_id = ntohs(ip->id); 2272 } else { 2273 ((struct ipv6hdr *)ip)->payload_len = htons(ip_tot_len); 2274 } 2275 2276 seqnum = ntohl(tcp->seq); 2277 2278 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2279 2280 buffer->flags = EFX_TX_BUF_OPTION; 2281 buffer->len = 0; 2282 buffer->unmap_len = 0; 2283 EFX_POPULATE_QWORD_5(buffer->option, 2284 ESF_DZ_TX_DESC_IS_OPT, 1, 2285 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2286 ESF_DZ_TX_TSO_OPTION_TYPE, 2287 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A, 2288 ESF_DZ_TX_TSO_IP_ID, inner_ipv4_id, 2289 ESF_DZ_TX_TSO_TCP_SEQNO, seqnum 2290 ); 2291 ++tx_queue->insert_count; 2292 2293 buffer = efx_tx_queue_get_insert_buffer(tx_queue); 2294 2295 buffer->flags = EFX_TX_BUF_OPTION; 2296 buffer->len = 0; 2297 buffer->unmap_len = 0; 2298 EFX_POPULATE_QWORD_5(buffer->option, 2299 ESF_DZ_TX_DESC_IS_OPT, 1, 2300 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_TSO, 2301 ESF_DZ_TX_TSO_OPTION_TYPE, 2302 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B, 2303 ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id, 2304 ESF_DZ_TX_TSO_TCP_MSS, mss 2305 ); 2306 ++tx_queue->insert_count; 2307 2308 return 0; 2309} 2310 2311static u32 efx_ef10_tso_versions(struct efx_nic *efx) 2312{ 2313 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2314 u32 tso_versions = 0; 2315 2316 if (nic_data->datapath_caps & 2317 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) 2318 tso_versions |= BIT(1); 2319 if (nic_data->datapath_caps2 & 2320 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN)) 2321 tso_versions |= BIT(2); 2322 return tso_versions; 2323} 2324 2325static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 2326{ 2327 bool csum_offload = tx_queue->type & EFX_TXQ_TYPE_OUTER_CSUM; 2328 bool inner_csum = tx_queue->type & EFX_TXQ_TYPE_INNER_CSUM; 2329 struct efx_channel *channel = tx_queue->channel; 2330 struct efx_nic *efx = tx_queue->efx; 2331 struct efx_ef10_nic_data *nic_data; 2332 efx_qword_t *txd; 2333 int rc; 2334 2335 nic_data = efx->nic_data; 2336 2337 /* Only attempt to enable TX timestamping if we have the license for it, 2338 * otherwise TXQ init will fail 2339 */ 2340 if (!(nic_data->licensed_features & 2341 (1 << LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN))) { 2342 tx_queue->timestamping = false; 2343 /* Disable sync events on this channel. */ 2344 if (efx->type->ptp_set_ts_sync_events) 2345 efx->type->ptp_set_ts_sync_events(efx, false, false); 2346 } 2347 2348 /* TSOv2 is a limited resource that can only be configured on a limited 2349 * number of queues. TSO without checksum offload is not really a thing, 2350 * so we only enable it for those queues. 2351 * TSOv2 cannot be used with Hardware timestamping, and is never needed 2352 * for XDP tx. 2353 */ 2354 if (efx_has_cap(efx, TX_TSO_V2)) { 2355 if ((csum_offload || inner_csum) && 2356 !tx_queue->timestamping && !tx_queue->xdp_tx) { 2357 tx_queue->tso_version = 2; 2358 netif_dbg(efx, hw, efx->net_dev, "Using TSOv2 for channel %u\n", 2359 channel->channel); 2360 } 2361 } else if (efx_has_cap(efx, TX_TSO)) { 2362 tx_queue->tso_version = 1; 2363 } 2364 2365 rc = efx_mcdi_tx_init(tx_queue); 2366 if (rc) 2367 goto fail; 2368 2369 /* A previous user of this TX queue might have set us up the 2370 * bomb by writing a descriptor to the TX push collector but 2371 * not the doorbell. (Each collector belongs to a port, not a 2372 * queue or function, so cannot easily be reset.) We must 2373 * attempt to push a no-op descriptor in its place. 2374 */ 2375 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 2376 tx_queue->insert_count = 1; 2377 txd = efx_tx_desc(tx_queue, 0); 2378 EFX_POPULATE_QWORD_7(*txd, 2379 ESF_DZ_TX_DESC_IS_OPT, true, 2380 ESF_DZ_TX_OPTION_TYPE, 2381 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 2382 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 2383 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload && tx_queue->tso_version != 2, 2384 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM, inner_csum, 2385 ESF_DZ_TX_OPTION_INNER_IP_CSUM, inner_csum && tx_queue->tso_version != 2, 2386 ESF_DZ_TX_TIMESTAMP, tx_queue->timestamping); 2387 tx_queue->write_count = 1; 2388 2389 if (tx_queue->tso_version == 2 && efx_has_cap(efx, TX_TSO_V2_ENCAP)) 2390 tx_queue->tso_encap = true; 2391 2392 wmb(); 2393 efx_ef10_push_tx_desc(tx_queue, txd); 2394 2395 return; 2396 2397fail: 2398 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 2399 tx_queue->queue); 2400} 2401 2402/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 2403static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 2404{ 2405 unsigned int write_ptr; 2406 efx_dword_t reg; 2407 2408 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2409 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 2410 efx_writed_page(tx_queue->efx, ®, 2411 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 2412} 2413 2414#define EFX_EF10_MAX_TX_DESCRIPTOR_LEN 0x3fff 2415 2416static unsigned int efx_ef10_tx_limit_len(struct efx_tx_queue *tx_queue, 2417 dma_addr_t dma_addr, unsigned int len) 2418{ 2419 if (len > EFX_EF10_MAX_TX_DESCRIPTOR_LEN) { 2420 /* If we need to break across multiple descriptors we should 2421 * stop at a page boundary. This assumes the length limit is 2422 * greater than the page size. 2423 */ 2424 dma_addr_t end = dma_addr + EFX_EF10_MAX_TX_DESCRIPTOR_LEN; 2425 2426 BUILD_BUG_ON(EFX_EF10_MAX_TX_DESCRIPTOR_LEN < EFX_PAGE_SIZE); 2427 len = (end & (~(EFX_PAGE_SIZE - 1))) - dma_addr; 2428 } 2429 2430 return len; 2431} 2432 2433static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 2434{ 2435 unsigned int old_write_count = tx_queue->write_count; 2436 struct efx_tx_buffer *buffer; 2437 unsigned int write_ptr; 2438 efx_qword_t *txd; 2439 2440 tx_queue->xmit_pending = false; 2441 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 2442 return; 2443 2444 do { 2445 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 2446 buffer = &tx_queue->buffer[write_ptr]; 2447 txd = efx_tx_desc(tx_queue, write_ptr); 2448 ++tx_queue->write_count; 2449 2450 /* Create TX descriptor ring entry */ 2451 if (buffer->flags & EFX_TX_BUF_OPTION) { 2452 *txd = buffer->option; 2453 if (EFX_QWORD_FIELD(*txd, ESF_DZ_TX_OPTION_TYPE) == 1) 2454 /* PIO descriptor */ 2455 tx_queue->packet_write_count = tx_queue->write_count; 2456 } else { 2457 tx_queue->packet_write_count = tx_queue->write_count; 2458 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 2459 EFX_POPULATE_QWORD_3( 2460 *txd, 2461 ESF_DZ_TX_KER_CONT, 2462 buffer->flags & EFX_TX_BUF_CONT, 2463 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 2464 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 2465 } 2466 } while (tx_queue->write_count != tx_queue->insert_count); 2467 2468 wmb(); /* Ensure descriptors are written before they are fetched */ 2469 2470 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 2471 txd = efx_tx_desc(tx_queue, 2472 old_write_count & tx_queue->ptr_mask); 2473 efx_ef10_push_tx_desc(tx_queue, txd); 2474 ++tx_queue->pushes; 2475 } else { 2476 efx_ef10_notify_tx_desc(tx_queue); 2477 } 2478} 2479 2480static int efx_ef10_probe_multicast_chaining(struct efx_nic *efx) 2481{ 2482 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2483 unsigned int enabled, implemented; 2484 bool want_workaround_26807; 2485 int rc; 2486 2487 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled); 2488 if (rc == -ENOSYS) { 2489 /* GET_WORKAROUNDS was implemented before this workaround, 2490 * thus it must be unavailable in this firmware. 2491 */ 2492 nic_data->workaround_26807 = false; 2493 return 0; 2494 } 2495 if (rc) 2496 return rc; 2497 want_workaround_26807 = 2498 implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807; 2499 nic_data->workaround_26807 = 2500 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807); 2501 2502 if (want_workaround_26807 && !nic_data->workaround_26807) { 2503 unsigned int flags; 2504 2505 rc = efx_mcdi_set_workaround(efx, 2506 MC_CMD_WORKAROUND_BUG26807, 2507 true, &flags); 2508 if (!rc) { 2509 if (flags & 2510 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) { 2511 netif_info(efx, drv, efx->net_dev, 2512 "other functions on NIC have been reset\n"); 2513 2514 /* With MCFW v4.6.x and earlier, the 2515 * boot count will have incremented, 2516 * so re-read the warm_boot_count 2517 * value now to ensure this function 2518 * doesn't think it has changed next 2519 * time it checks. 2520 */ 2521 rc = efx_ef10_get_warm_boot_count(efx); 2522 if (rc >= 0) { 2523 nic_data->warm_boot_count = rc; 2524 rc = 0; 2525 } 2526 } 2527 nic_data->workaround_26807 = true; 2528 } else if (rc == -EPERM) { 2529 rc = 0; 2530 } 2531 } 2532 return rc; 2533} 2534 2535static int efx_ef10_filter_table_probe(struct efx_nic *efx) 2536{ 2537 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2538 int rc = efx_ef10_probe_multicast_chaining(efx); 2539 struct efx_mcdi_filter_vlan *vlan; 2540 2541 if (rc) 2542 return rc; 2543 rc = efx_mcdi_filter_table_probe(efx, nic_data->workaround_26807); 2544 2545 if (rc) 2546 return rc; 2547 2548 list_for_each_entry(vlan, &nic_data->vlan_list, list) { 2549 rc = efx_mcdi_filter_add_vlan(efx, vlan->vid); 2550 if (rc) 2551 goto fail_add_vlan; 2552 } 2553 return 0; 2554 2555fail_add_vlan: 2556 efx_mcdi_filter_table_remove(efx); 2557 return rc; 2558} 2559 2560/* This creates an entry in the RX descriptor queue */ 2561static inline void 2562efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 2563{ 2564 struct efx_rx_buffer *rx_buf; 2565 efx_qword_t *rxd; 2566 2567 rxd = efx_rx_desc(rx_queue, index); 2568 rx_buf = efx_rx_buffer(rx_queue, index); 2569 EFX_POPULATE_QWORD_2(*rxd, 2570 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 2571 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 2572} 2573 2574static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 2575{ 2576 struct efx_nic *efx = rx_queue->efx; 2577 unsigned int write_count; 2578 efx_dword_t reg; 2579 2580 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 2581 write_count = rx_queue->added_count & ~7; 2582 if (rx_queue->notified_count == write_count) 2583 return; 2584 2585 do 2586 efx_ef10_build_rx_desc( 2587 rx_queue, 2588 rx_queue->notified_count & rx_queue->ptr_mask); 2589 while (++rx_queue->notified_count != write_count); 2590 2591 wmb(); 2592 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 2593 write_count & rx_queue->ptr_mask); 2594 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 2595 efx_rx_queue_index(rx_queue)); 2596} 2597 2598static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 2599 2600static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 2601{ 2602 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 2603 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2604 efx_qword_t event; 2605 2606 EFX_POPULATE_QWORD_2(event, 2607 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2608 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 2609 2610 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2611 2612 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2613 * already swapped the data to little-endian order. 2614 */ 2615 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2616 sizeof(efx_qword_t)); 2617 2618 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 2619 inbuf, sizeof(inbuf), 0, 2620 efx_ef10_rx_defer_refill_complete, 0); 2621} 2622 2623static void 2624efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 2625 int rc, efx_dword_t *outbuf, 2626 size_t outlen_actual) 2627{ 2628 /* nothing to do */ 2629} 2630 2631static int efx_ef10_ev_init(struct efx_channel *channel) 2632{ 2633 struct efx_nic *efx = channel->efx; 2634 struct efx_ef10_nic_data *nic_data; 2635 bool use_v2, cut_thru; 2636 2637 nic_data = efx->nic_data; 2638 use_v2 = nic_data->datapath_caps2 & 2639 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN; 2640 cut_thru = !(nic_data->datapath_caps & 2641 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 2642 return efx_mcdi_ev_init(channel, cut_thru, use_v2); 2643} 2644 2645static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 2646 unsigned int rx_queue_label) 2647{ 2648 struct efx_nic *efx = rx_queue->efx; 2649 2650 netif_info(efx, hw, efx->net_dev, 2651 "rx event arrived on queue %d labeled as queue %u\n", 2652 efx_rx_queue_index(rx_queue), rx_queue_label); 2653 2654 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2655} 2656 2657static void 2658efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 2659 unsigned int actual, unsigned int expected) 2660{ 2661 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 2662 struct efx_nic *efx = rx_queue->efx; 2663 2664 netif_info(efx, hw, efx->net_dev, 2665 "dropped %d events (index=%d expected=%d)\n", 2666 dropped, actual, expected); 2667 2668 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 2669} 2670 2671/* partially received RX was aborted. clean up. */ 2672static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 2673{ 2674 unsigned int rx_desc_ptr; 2675 2676 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 2677 "scattered RX aborted (dropping %u buffers)\n", 2678 rx_queue->scatter_n); 2679 2680 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 2681 2682 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 2683 0, EFX_RX_PKT_DISCARD); 2684 2685 rx_queue->removed_count += rx_queue->scatter_n; 2686 rx_queue->scatter_n = 0; 2687 rx_queue->scatter_len = 0; 2688 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 2689} 2690 2691static u16 efx_ef10_handle_rx_event_errors(struct efx_channel *channel, 2692 unsigned int n_packets, 2693 unsigned int rx_encap_hdr, 2694 unsigned int rx_l3_class, 2695 unsigned int rx_l4_class, 2696 const efx_qword_t *event) 2697{ 2698 struct efx_nic *efx = channel->efx; 2699 bool handled = false; 2700 2701 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)) { 2702 if (!(efx->net_dev->features & NETIF_F_RXALL)) { 2703 if (!efx->loopback_selftest) 2704 channel->n_rx_eth_crc_err += n_packets; 2705 return EFX_RX_PKT_DISCARD; 2706 } 2707 handled = true; 2708 } 2709 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR)) { 2710 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2711 rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2712 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2713 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2714 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2715 netdev_WARN(efx->net_dev, 2716 "invalid class for RX_IPCKSUM_ERR: event=" 2717 EFX_QWORD_FMT "\n", 2718 EFX_QWORD_VAL(*event)); 2719 if (!efx->loopback_selftest) 2720 *(rx_encap_hdr ? 2721 &channel->n_rx_outer_ip_hdr_chksum_err : 2722 &channel->n_rx_ip_hdr_chksum_err) += n_packets; 2723 return 0; 2724 } 2725 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) { 2726 if (unlikely(rx_encap_hdr != ESE_EZ_ENCAP_HDR_VXLAN && 2727 ((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2728 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2729 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2730 rx_l4_class != ESE_FZ_L4_CLASS_UDP)))) 2731 netdev_WARN(efx->net_dev, 2732 "invalid class for RX_TCPUDP_CKSUM_ERR: event=" 2733 EFX_QWORD_FMT "\n", 2734 EFX_QWORD_VAL(*event)); 2735 if (!efx->loopback_selftest) 2736 *(rx_encap_hdr ? 2737 &channel->n_rx_outer_tcp_udp_chksum_err : 2738 &channel->n_rx_tcp_udp_chksum_err) += n_packets; 2739 return 0; 2740 } 2741 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_IP_INNER_CHKSUM_ERR)) { 2742 if (unlikely(!rx_encap_hdr)) 2743 netdev_WARN(efx->net_dev, 2744 "invalid encapsulation type for RX_IP_INNER_CHKSUM_ERR: event=" 2745 EFX_QWORD_FMT "\n", 2746 EFX_QWORD_VAL(*event)); 2747 else if (unlikely(rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2748 rx_l3_class != ESE_DZ_L3_CLASS_IP4_FRAG && 2749 rx_l3_class != ESE_DZ_L3_CLASS_IP6 && 2750 rx_l3_class != ESE_DZ_L3_CLASS_IP6_FRAG)) 2751 netdev_WARN(efx->net_dev, 2752 "invalid class for RX_IP_INNER_CHKSUM_ERR: event=" 2753 EFX_QWORD_FMT "\n", 2754 EFX_QWORD_VAL(*event)); 2755 if (!efx->loopback_selftest) 2756 channel->n_rx_inner_ip_hdr_chksum_err += n_packets; 2757 return 0; 2758 } 2759 if (EFX_QWORD_FIELD(*event, ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR)) { 2760 if (unlikely(!rx_encap_hdr)) 2761 netdev_WARN(efx->net_dev, 2762 "invalid encapsulation type for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2763 EFX_QWORD_FMT "\n", 2764 EFX_QWORD_VAL(*event)); 2765 else if (unlikely((rx_l3_class != ESE_DZ_L3_CLASS_IP4 && 2766 rx_l3_class != ESE_DZ_L3_CLASS_IP6) || 2767 (rx_l4_class != ESE_FZ_L4_CLASS_TCP && 2768 rx_l4_class != ESE_FZ_L4_CLASS_UDP))) 2769 netdev_WARN(efx->net_dev, 2770 "invalid class for RX_TCP_UDP_INNER_CHKSUM_ERR: event=" 2771 EFX_QWORD_FMT "\n", 2772 EFX_QWORD_VAL(*event)); 2773 if (!efx->loopback_selftest) 2774 channel->n_rx_inner_tcp_udp_chksum_err += n_packets; 2775 return 0; 2776 } 2777 2778 WARN_ON(!handled); /* No error bits were recognised */ 2779 return 0; 2780} 2781 2782static int efx_ef10_handle_rx_event(struct efx_channel *channel, 2783 const efx_qword_t *event) 2784{ 2785 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label; 2786 unsigned int rx_l3_class, rx_l4_class, rx_encap_hdr; 2787 unsigned int n_descs, n_packets, i; 2788 struct efx_nic *efx = channel->efx; 2789 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2790 struct efx_rx_queue *rx_queue; 2791 efx_qword_t errors; 2792 bool rx_cont; 2793 u16 flags = 0; 2794 2795 if (unlikely(READ_ONCE(efx->reset_pending))) 2796 return 0; 2797 2798 /* Basic packet information */ 2799 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 2800 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 2801 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 2802 rx_l3_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L3_CLASS); 2803 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_FZ_RX_L4_CLASS); 2804 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 2805 rx_encap_hdr = 2806 nic_data->datapath_caps & 2807 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN) ? 2808 EFX_QWORD_FIELD(*event, ESF_EZ_RX_ENCAP_HDR) : 2809 ESE_EZ_ENCAP_HDR_NONE; 2810 2811 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 2812 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 2813 EFX_QWORD_FMT "\n", 2814 EFX_QWORD_VAL(*event)); 2815 2816 rx_queue = efx_channel_get_rx_queue(channel); 2817 2818 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 2819 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 2820 2821 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 2822 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2823 2824 if (n_descs != rx_queue->scatter_n + 1) { 2825 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2826 2827 /* detect rx abort */ 2828 if (unlikely(n_descs == rx_queue->scatter_n)) { 2829 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 2830 netdev_WARN(efx->net_dev, 2831 "invalid RX abort: scatter_n=%u event=" 2832 EFX_QWORD_FMT "\n", 2833 rx_queue->scatter_n, 2834 EFX_QWORD_VAL(*event)); 2835 efx_ef10_handle_rx_abort(rx_queue); 2836 return 0; 2837 } 2838 2839 /* Check that RX completion merging is valid, i.e. 2840 * the current firmware supports it and this is a 2841 * non-scattered packet. 2842 */ 2843 if (!(nic_data->datapath_caps & 2844 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 2845 rx_queue->scatter_n != 0 || rx_cont) { 2846 efx_ef10_handle_rx_bad_lbits( 2847 rx_queue, next_ptr_lbits, 2848 (rx_queue->removed_count + 2849 rx_queue->scatter_n + 1) & 2850 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 2851 return 0; 2852 } 2853 2854 /* Merged completion for multiple non-scattered packets */ 2855 rx_queue->scatter_n = 1; 2856 rx_queue->scatter_len = 0; 2857 n_packets = n_descs; 2858 ++channel->n_rx_merge_events; 2859 channel->n_rx_merge_packets += n_packets; 2860 flags |= EFX_RX_PKT_PREFIX_LEN; 2861 } else { 2862 ++rx_queue->scatter_n; 2863 rx_queue->scatter_len += rx_bytes; 2864 if (rx_cont) 2865 return 0; 2866 n_packets = 1; 2867 } 2868 2869 EFX_POPULATE_QWORD_5(errors, ESF_DZ_RX_ECRC_ERR, 1, 2870 ESF_DZ_RX_IPCKSUM_ERR, 1, 2871 ESF_DZ_RX_TCPUDP_CKSUM_ERR, 1, 2872 ESF_EZ_RX_IP_INNER_CHKSUM_ERR, 1, 2873 ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR, 1); 2874 EFX_AND_QWORD(errors, *event, errors); 2875 if (unlikely(!EFX_QWORD_IS_ZERO(errors))) { 2876 flags |= efx_ef10_handle_rx_event_errors(channel, n_packets, 2877 rx_encap_hdr, 2878 rx_l3_class, rx_l4_class, 2879 event); 2880 } else { 2881 bool tcpudp = rx_l4_class == ESE_FZ_L4_CLASS_TCP || 2882 rx_l4_class == ESE_FZ_L4_CLASS_UDP; 2883 2884 switch (rx_encap_hdr) { 2885 case ESE_EZ_ENCAP_HDR_VXLAN: /* VxLAN or GENEVE */ 2886 flags |= EFX_RX_PKT_CSUMMED; /* outer UDP csum */ 2887 if (tcpudp) 2888 flags |= EFX_RX_PKT_CSUM_LEVEL; /* inner L4 */ 2889 break; 2890 case ESE_EZ_ENCAP_HDR_GRE: 2891 case ESE_EZ_ENCAP_HDR_NONE: 2892 if (tcpudp) 2893 flags |= EFX_RX_PKT_CSUMMED; 2894 break; 2895 default: 2896 netdev_WARN(efx->net_dev, 2897 "unknown encapsulation type: event=" 2898 EFX_QWORD_FMT "\n", 2899 EFX_QWORD_VAL(*event)); 2900 } 2901 } 2902 2903 if (rx_l4_class == ESE_FZ_L4_CLASS_TCP) 2904 flags |= EFX_RX_PKT_TCP; 2905 2906 channel->irq_mod_score += 2 * n_packets; 2907 2908 /* Handle received packet(s) */ 2909 for (i = 0; i < n_packets; i++) { 2910 efx_rx_packet(rx_queue, 2911 rx_queue->removed_count & rx_queue->ptr_mask, 2912 rx_queue->scatter_n, rx_queue->scatter_len, 2913 flags); 2914 rx_queue->removed_count += rx_queue->scatter_n; 2915 } 2916 2917 rx_queue->scatter_n = 0; 2918 rx_queue->scatter_len = 0; 2919 2920 return n_packets; 2921} 2922 2923static u32 efx_ef10_extract_event_ts(efx_qword_t *event) 2924{ 2925 u32 tstamp; 2926 2927 tstamp = EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI); 2928 tstamp <<= 16; 2929 tstamp |= EFX_QWORD_FIELD(*event, TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO); 2930 2931 return tstamp; 2932} 2933 2934static void 2935efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 2936{ 2937 struct efx_nic *efx = channel->efx; 2938 struct efx_tx_queue *tx_queue; 2939 unsigned int tx_ev_desc_ptr; 2940 unsigned int tx_ev_q_label; 2941 unsigned int tx_ev_type; 2942 u64 ts_part; 2943 2944 if (unlikely(READ_ONCE(efx->reset_pending))) 2945 return; 2946 2947 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 2948 return; 2949 2950 /* Get the transmit queue */ 2951 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 2952 tx_queue = channel->tx_queue + (tx_ev_q_label % EFX_MAX_TXQ_PER_CHANNEL); 2953 2954 if (!tx_queue->timestamping) { 2955 /* Transmit completion */ 2956 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 2957 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 2958 return; 2959 } 2960 2961 /* Transmit timestamps are only available for 8XXX series. They result 2962 * in up to three events per packet. These occur in order, and are: 2963 * - the normal completion event (may be omitted) 2964 * - the low part of the timestamp 2965 * - the high part of the timestamp 2966 * 2967 * It's possible for multiple completion events to appear before the 2968 * corresponding timestamps. So we can for example get: 2969 * COMP N 2970 * COMP N+1 2971 * TS_LO N 2972 * TS_HI N 2973 * TS_LO N+1 2974 * TS_HI N+1 2975 * 2976 * In addition it's also possible for the adjacent completions to be 2977 * merged, so we may not see COMP N above. As such, the completion 2978 * events are not very useful here. 2979 * 2980 * Each part of the timestamp is itself split across two 16 bit 2981 * fields in the event. 2982 */ 2983 tx_ev_type = EFX_QWORD_FIELD(*event, ESF_EZ_TX_SOFT1); 2984 2985 switch (tx_ev_type) { 2986 case TX_TIMESTAMP_EVENT_TX_EV_COMPLETION: 2987 /* Ignore this event - see above. */ 2988 break; 2989 2990 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO: 2991 ts_part = efx_ef10_extract_event_ts(event); 2992 tx_queue->completed_timestamp_minor = ts_part; 2993 break; 2994 2995 case TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI: 2996 ts_part = efx_ef10_extract_event_ts(event); 2997 tx_queue->completed_timestamp_major = ts_part; 2998 2999 efx_xmit_done_single(tx_queue); 3000 break; 3001 3002 default: 3003 netif_err(efx, hw, efx->net_dev, 3004 "channel %d unknown tx event type %d (data " 3005 EFX_QWORD_FMT ")\n", 3006 channel->channel, tx_ev_type, 3007 EFX_QWORD_VAL(*event)); 3008 break; 3009 } 3010} 3011 3012static void 3013efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 3014{ 3015 struct efx_nic *efx = channel->efx; 3016 int subcode; 3017 3018 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 3019 3020 switch (subcode) { 3021 case ESE_DZ_DRV_TIMER_EV: 3022 case ESE_DZ_DRV_WAKE_UP_EV: 3023 break; 3024 case ESE_DZ_DRV_START_UP_EV: 3025 /* event queue init complete. ok. */ 3026 break; 3027 default: 3028 netif_err(efx, hw, efx->net_dev, 3029 "channel %d unknown driver event type %d" 3030 " (data " EFX_QWORD_FMT ")\n", 3031 channel->channel, subcode, 3032 EFX_QWORD_VAL(*event)); 3033 3034 } 3035} 3036 3037static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 3038 efx_qword_t *event) 3039{ 3040 struct efx_nic *efx = channel->efx; 3041 u32 subcode; 3042 3043 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 3044 3045 switch (subcode) { 3046 case EFX_EF10_TEST: 3047 channel->event_test_cpu = raw_smp_processor_id(); 3048 break; 3049 case EFX_EF10_REFILL: 3050 /* The queue must be empty, so we won't receive any rx 3051 * events, so efx_process_channel() won't refill the 3052 * queue. Refill it here 3053 */ 3054 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 3055 break; 3056 default: 3057 netif_err(efx, hw, efx->net_dev, 3058 "channel %d unknown driver event type %u" 3059 " (data " EFX_QWORD_FMT ")\n", 3060 channel->channel, (unsigned) subcode, 3061 EFX_QWORD_VAL(*event)); 3062 } 3063} 3064 3065static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 3066{ 3067 struct efx_nic *efx = channel->efx; 3068 efx_qword_t event, *p_event; 3069 unsigned int read_ptr; 3070 int ev_code; 3071 int spent = 0; 3072 3073 if (quota <= 0) 3074 return spent; 3075 3076 read_ptr = channel->eventq_read_ptr; 3077 3078 for (;;) { 3079 p_event = efx_event(channel, read_ptr); 3080 event = *p_event; 3081 3082 if (!efx_event_present(&event)) 3083 break; 3084 3085 EFX_SET_QWORD(*p_event); 3086 3087 ++read_ptr; 3088 3089 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 3090 3091 netif_vdbg(efx, drv, efx->net_dev, 3092 "processing event on %d " EFX_QWORD_FMT "\n", 3093 channel->channel, EFX_QWORD_VAL(event)); 3094 3095 switch (ev_code) { 3096 case ESE_DZ_EV_CODE_MCDI_EV: 3097 efx_mcdi_process_event(channel, &event); 3098 break; 3099 case ESE_DZ_EV_CODE_RX_EV: 3100 spent += efx_ef10_handle_rx_event(channel, &event); 3101 if (spent >= quota) { 3102 /* XXX can we split a merged event to 3103 * avoid going over-quota? 3104 */ 3105 spent = quota; 3106 goto out; 3107 } 3108 break; 3109 case ESE_DZ_EV_CODE_TX_EV: 3110 efx_ef10_handle_tx_event(channel, &event); 3111 break; 3112 case ESE_DZ_EV_CODE_DRIVER_EV: 3113 efx_ef10_handle_driver_event(channel, &event); 3114 if (++spent == quota) 3115 goto out; 3116 break; 3117 case EFX_EF10_DRVGEN_EV: 3118 efx_ef10_handle_driver_generated_event(channel, &event); 3119 break; 3120 default: 3121 netif_err(efx, hw, efx->net_dev, 3122 "channel %d unknown event type %d" 3123 " (data " EFX_QWORD_FMT ")\n", 3124 channel->channel, ev_code, 3125 EFX_QWORD_VAL(event)); 3126 } 3127 } 3128 3129out: 3130 channel->eventq_read_ptr = read_ptr; 3131 return spent; 3132} 3133 3134static void efx_ef10_ev_read_ack(struct efx_channel *channel) 3135{ 3136 struct efx_nic *efx = channel->efx; 3137 efx_dword_t rptr; 3138 3139 if (EFX_EF10_WORKAROUND_35388(efx)) { 3140 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 3141 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 3142 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 3143 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 3144 3145 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3146 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 3147 ERF_DD_EVQ_IND_RPTR, 3148 (channel->eventq_read_ptr & 3149 channel->eventq_mask) >> 3150 ERF_DD_EVQ_IND_RPTR_WIDTH); 3151 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3152 channel->channel); 3153 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 3154 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 3155 ERF_DD_EVQ_IND_RPTR, 3156 channel->eventq_read_ptr & 3157 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 3158 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 3159 channel->channel); 3160 } else { 3161 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 3162 channel->eventq_read_ptr & 3163 channel->eventq_mask); 3164 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 3165 } 3166} 3167 3168static void efx_ef10_ev_test_generate(struct efx_channel *channel) 3169{ 3170 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 3171 struct efx_nic *efx = channel->efx; 3172 efx_qword_t event; 3173 int rc; 3174 3175 EFX_POPULATE_QWORD_2(event, 3176 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 3177 ESF_DZ_EV_DATA, EFX_EF10_TEST); 3178 3179 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 3180 3181 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 3182 * already swapped the data to little-endian order. 3183 */ 3184 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 3185 sizeof(efx_qword_t)); 3186 3187 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 3188 NULL, 0, NULL); 3189 if (rc != 0) 3190 goto fail; 3191 3192 return; 3193 3194fail: 3195 WARN_ON(true); 3196 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 3197} 3198 3199static void efx_ef10_prepare_flr(struct efx_nic *efx) 3200{ 3201 atomic_set(&efx->active_queues, 0); 3202} 3203 3204static int efx_ef10_vport_set_mac_address(struct efx_nic *efx) 3205{ 3206 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3207 u8 mac_old[ETH_ALEN]; 3208 int rc, rc2; 3209 3210 /* Only reconfigure a PF-created vport */ 3211 if (is_zero_ether_addr(nic_data->vport_mac)) 3212 return 0; 3213 3214 efx_device_detach_sync(efx); 3215 efx_net_stop(efx->net_dev); 3216 down_write(&efx->filter_sem); 3217 efx_mcdi_filter_table_remove(efx); 3218 up_write(&efx->filter_sem); 3219 3220 rc = efx_ef10_vadaptor_free(efx, efx->vport_id); 3221 if (rc) 3222 goto restore_filters; 3223 3224 ether_addr_copy(mac_old, nic_data->vport_mac); 3225 rc = efx_ef10_vport_del_mac(efx, efx->vport_id, 3226 nic_data->vport_mac); 3227 if (rc) 3228 goto restore_vadaptor; 3229 3230 rc = efx_ef10_vport_add_mac(efx, efx->vport_id, 3231 efx->net_dev->dev_addr); 3232 if (!rc) { 3233 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr); 3234 } else { 3235 rc2 = efx_ef10_vport_add_mac(efx, efx->vport_id, mac_old); 3236 if (rc2) { 3237 /* Failed to add original MAC, so clear vport_mac */ 3238 eth_zero_addr(nic_data->vport_mac); 3239 goto reset_nic; 3240 } 3241 } 3242 3243restore_vadaptor: 3244 rc2 = efx_ef10_vadaptor_alloc(efx, efx->vport_id); 3245 if (rc2) 3246 goto reset_nic; 3247restore_filters: 3248 down_write(&efx->filter_sem); 3249 rc2 = efx_ef10_filter_table_probe(efx); 3250 up_write(&efx->filter_sem); 3251 if (rc2) 3252 goto reset_nic; 3253 3254 rc2 = efx_net_open(efx->net_dev); 3255 if (rc2) 3256 goto reset_nic; 3257 3258 efx_device_attach_if_not_resetting(efx); 3259 3260 return rc; 3261 3262reset_nic: 3263 netif_err(efx, drv, efx->net_dev, 3264 "Failed to restore when changing MAC address - scheduling reset\n"); 3265 efx_schedule_reset(efx, RESET_TYPE_DATAPATH); 3266 3267 return rc ? rc : rc2; 3268} 3269 3270static int efx_ef10_set_mac_address(struct efx_nic *efx) 3271{ 3272 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN); 3273 bool was_enabled = efx->port_enabled; 3274 int rc; 3275 3276#ifdef CONFIG_SFC_SRIOV 3277 /* If this function is a VF and we have access to the parent PF, 3278 * then use the PF control path to attempt to change the VF MAC address. 3279 */ 3280 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) { 3281 struct efx_nic *efx_pf = pci_get_drvdata(efx->pci_dev->physfn); 3282 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3283 u8 mac[ETH_ALEN]; 3284 3285 /* net_dev->dev_addr can be zeroed by efx_net_stop in 3286 * efx_ef10_sriov_set_vf_mac, so pass in a copy. 3287 */ 3288 ether_addr_copy(mac, efx->net_dev->dev_addr); 3289 3290 rc = efx_ef10_sriov_set_vf_mac(efx_pf, nic_data->vf_index, mac); 3291 if (!rc) 3292 return 0; 3293 3294 netif_dbg(efx, drv, efx->net_dev, 3295 "Updating VF mac via PF failed (%d), setting directly\n", 3296 rc); 3297 } 3298#endif 3299 3300 efx_device_detach_sync(efx); 3301 efx_net_stop(efx->net_dev); 3302 3303 mutex_lock(&efx->mac_lock); 3304 down_write(&efx->filter_sem); 3305 efx_mcdi_filter_table_remove(efx); 3306 3307 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR), 3308 efx->net_dev->dev_addr); 3309 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID, 3310 efx->vport_id); 3311 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf, 3312 sizeof(inbuf), NULL, 0, NULL); 3313 3314 efx_ef10_filter_table_probe(efx); 3315 up_write(&efx->filter_sem); 3316 mutex_unlock(&efx->mac_lock); 3317 3318 if (was_enabled) 3319 efx_net_open(efx->net_dev); 3320 efx_device_attach_if_not_resetting(efx); 3321 3322 if (rc == -EPERM) { 3323 netif_err(efx, drv, efx->net_dev, 3324 "Cannot change MAC address; use sfboot to enable" 3325 " mac-spoofing on this interface\n"); 3326 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) { 3327 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC 3328 * fall-back to the method of changing the MAC address on the 3329 * vport. This only applies to PFs because such versions of 3330 * MCFW do not support VFs. 3331 */ 3332 rc = efx_ef10_vport_set_mac_address(efx); 3333 } else if (rc) { 3334 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC, 3335 sizeof(inbuf), NULL, 0, rc); 3336 } 3337 3338 return rc; 3339} 3340 3341static int efx_ef10_mac_reconfigure(struct efx_nic *efx, bool mtu_only) 3342{ 3343 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 3344 3345 efx_mcdi_filter_sync_rx_mode(efx); 3346 3347 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 3348 return efx_mcdi_set_mtu(efx); 3349 return efx_mcdi_set_mac(efx); 3350} 3351 3352static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3353{ 3354 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3355 3356 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3357 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3358 NULL, 0, NULL); 3359} 3360 3361/* MC BISTs follow a different poll mechanism to phy BISTs. 3362 * The BIST is done in the poll handler on the MC, and the MCDI command 3363 * will block until the BIST is done. 3364 */ 3365static int efx_ef10_poll_bist(struct efx_nic *efx) 3366{ 3367 int rc; 3368 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3369 size_t outlen; 3370 u32 result; 3371 3372 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3373 outbuf, sizeof(outbuf), &outlen); 3374 if (rc != 0) 3375 return rc; 3376 3377 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3378 return -EIO; 3379 3380 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3381 switch (result) { 3382 case MC_CMD_POLL_BIST_PASSED: 3383 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3384 return 0; 3385 case MC_CMD_POLL_BIST_TIMEOUT: 3386 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3387 return -EIO; 3388 case MC_CMD_POLL_BIST_FAILED: 3389 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3390 return -EIO; 3391 default: 3392 netif_err(efx, hw, efx->net_dev, 3393 "BIST returned unknown result %u", result); 3394 return -EIO; 3395 } 3396} 3397 3398static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3399{ 3400 int rc; 3401 3402 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3403 3404 rc = efx_ef10_start_bist(efx, bist_type); 3405 if (rc != 0) 3406 return rc; 3407 3408 return efx_ef10_poll_bist(efx); 3409} 3410 3411static int 3412efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3413{ 3414 int rc, rc2; 3415 3416 efx_reset_down(efx, RESET_TYPE_WORLD); 3417 3418 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3419 NULL, 0, NULL, 0, NULL); 3420 if (rc != 0) 3421 goto out; 3422 3423 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3424 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3425 3426 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3427 3428out: 3429 if (rc == -EPERM) 3430 rc = 0; 3431 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3432 return rc ? rc : rc2; 3433} 3434 3435#ifdef CONFIG_SFC_MTD 3436 3437struct efx_ef10_nvram_type_info { 3438 u16 type, type_mask; 3439 u8 port; 3440 const char *name; 3441}; 3442 3443static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3444 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3445 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3446 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3447 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3448 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3449 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3450 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3451 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3452 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3453 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3454 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3455 { NVRAM_PARTITION_TYPE_MUM_FIRMWARE, 0, 0, "sfc_mumfw" }, 3456 { NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 0, 0, "sfc_uefi" }, 3457 { NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS, 0, 0, "sfc_dynamic_cfg_dflt" }, 3458 { NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS, 0, 0, "sfc_exp_rom_cfg_dflt" }, 3459 { NVRAM_PARTITION_TYPE_STATUS, 0, 0, "sfc_status" }, 3460 { NVRAM_PARTITION_TYPE_BUNDLE, 0, 0, "sfc_bundle" }, 3461 { NVRAM_PARTITION_TYPE_BUNDLE_METADATA, 0, 0, "sfc_bundle_metadata" }, 3462}; 3463#define EF10_NVRAM_PARTITION_COUNT ARRAY_SIZE(efx_ef10_nvram_types) 3464 3465static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3466 struct efx_mcdi_mtd_partition *part, 3467 unsigned int type, 3468 unsigned long *found) 3469{ 3470 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3471 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3472 const struct efx_ef10_nvram_type_info *info; 3473 size_t size, erase_size, outlen; 3474 int type_idx = 0; 3475 bool protected; 3476 int rc; 3477 3478 for (type_idx = 0; ; type_idx++) { 3479 if (type_idx == EF10_NVRAM_PARTITION_COUNT) 3480 return -ENODEV; 3481 info = efx_ef10_nvram_types + type_idx; 3482 if ((type & ~info->type_mask) == info->type) 3483 break; 3484 } 3485 if (info->port != efx_port_num(efx)) 3486 return -ENODEV; 3487 3488 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3489 if (rc) 3490 return rc; 3491 if (protected && 3492 (type != NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS && 3493 type != NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS)) 3494 /* Hide protected partitions that don't provide defaults. */ 3495 return -ENODEV; 3496 3497 if (protected) 3498 /* Protected partitions are read only. */ 3499 erase_size = 0; 3500 3501 /* If we've already exposed a partition of this type, hide this 3502 * duplicate. All operations on MTDs are keyed by the type anyway, 3503 * so we can't act on the duplicate. 3504 */ 3505 if (__test_and_set_bit(type_idx, found)) 3506 return -EEXIST; 3507 3508 part->nvram_type = type; 3509 3510 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3511 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3512 outbuf, sizeof(outbuf), &outlen); 3513 if (rc) 3514 return rc; 3515 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3516 return -EIO; 3517 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3518 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3519 part->fw_subtype = MCDI_DWORD(outbuf, 3520 NVRAM_METADATA_OUT_SUBTYPE); 3521 3522 part->common.dev_type_name = "EF10 NVRAM manager"; 3523 part->common.type_name = info->name; 3524 3525 part->common.mtd.type = MTD_NORFLASH; 3526 part->common.mtd.flags = MTD_CAP_NORFLASH; 3527 part->common.mtd.size = size; 3528 part->common.mtd.erasesize = erase_size; 3529 /* sfc_status is read-only */ 3530 if (!erase_size) 3531 part->common.mtd.flags |= MTD_NO_ERASE; 3532 3533 return 0; 3534} 3535 3536static int efx_ef10_mtd_probe(struct efx_nic *efx) 3537{ 3538 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3539 DECLARE_BITMAP(found, EF10_NVRAM_PARTITION_COUNT) = { 0 }; 3540 struct efx_mcdi_mtd_partition *parts; 3541 size_t outlen, n_parts_total, i, n_parts; 3542 unsigned int type; 3543 int rc; 3544 3545 ASSERT_RTNL(); 3546 3547 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3548 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3549 outbuf, sizeof(outbuf), &outlen); 3550 if (rc) 3551 return rc; 3552 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3553 return -EIO; 3554 3555 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3556 if (n_parts_total > 3557 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3558 return -EIO; 3559 3560 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3561 if (!parts) 3562 return -ENOMEM; 3563 3564 n_parts = 0; 3565 for (i = 0; i < n_parts_total; i++) { 3566 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3567 i); 3568 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type, 3569 found); 3570 if (rc == -EEXIST || rc == -ENODEV) 3571 continue; 3572 if (rc) 3573 goto fail; 3574 n_parts++; 3575 } 3576 3577 if (!n_parts) { 3578 kfree(parts); 3579 return 0; 3580 } 3581 3582 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3583fail: 3584 if (rc) 3585 kfree(parts); 3586 return rc; 3587} 3588 3589#endif /* CONFIG_SFC_MTD */ 3590 3591static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3592{ 3593 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3594} 3595 3596static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx, 3597 u32 host_time) {} 3598 3599static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3600 bool temp) 3601{ 3602 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3603 int rc; 3604 3605 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3606 channel->sync_events_state == SYNC_EVENTS_VALID || 3607 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3608 return 0; 3609 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3610 3611 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3612 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3613 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3614 channel->channel); 3615 3616 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3617 inbuf, sizeof(inbuf), NULL, 0, NULL); 3618 3619 if (rc != 0) 3620 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3621 SYNC_EVENTS_DISABLED; 3622 3623 return rc; 3624} 3625 3626static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3627 bool temp) 3628{ 3629 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3630 int rc; 3631 3632 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3633 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3634 return 0; 3635 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3636 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3637 return 0; 3638 } 3639 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3640 SYNC_EVENTS_DISABLED; 3641 3642 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3643 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3644 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3645 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3646 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3647 channel->channel); 3648 3649 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3650 inbuf, sizeof(inbuf), NULL, 0, NULL); 3651 3652 return rc; 3653} 3654 3655static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3656 bool temp) 3657{ 3658 int (*set)(struct efx_channel *channel, bool temp); 3659 struct efx_channel *channel; 3660 3661 set = en ? 3662 efx_ef10_rx_enable_timestamping : 3663 efx_ef10_rx_disable_timestamping; 3664 3665 channel = efx_ptp_channel(efx); 3666 if (channel) { 3667 int rc = set(channel, temp); 3668 if (en && rc != 0) { 3669 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3670 return rc; 3671 } 3672 } 3673 3674 return 0; 3675} 3676 3677static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx, 3678 struct hwtstamp_config *init) 3679{ 3680 return -EOPNOTSUPP; 3681} 3682 3683static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3684 struct hwtstamp_config *init) 3685{ 3686 int rc; 3687 3688 switch (init->rx_filter) { 3689 case HWTSTAMP_FILTER_NONE: 3690 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3691 /* if TX timestamping is still requested then leave PTP on */ 3692 return efx_ptp_change_mode(efx, 3693 init->tx_type != HWTSTAMP_TX_OFF, 0); 3694 case HWTSTAMP_FILTER_ALL: 3695 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3696 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3697 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3698 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3699 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3700 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3701 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3702 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3703 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3704 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3705 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3706 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3707 case HWTSTAMP_FILTER_NTP_ALL: 3708 init->rx_filter = HWTSTAMP_FILTER_ALL; 3709 rc = efx_ptp_change_mode(efx, true, 0); 3710 if (!rc) 3711 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3712 if (rc) 3713 efx_ptp_change_mode(efx, false, 0); 3714 return rc; 3715 default: 3716 return -ERANGE; 3717 } 3718} 3719 3720static int efx_ef10_get_phys_port_id(struct efx_nic *efx, 3721 struct netdev_phys_item_id *ppid) 3722{ 3723 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3724 3725 if (!is_valid_ether_addr(nic_data->port_id)) 3726 return -EOPNOTSUPP; 3727 3728 ppid->id_len = ETH_ALEN; 3729 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 3730 3731 return 0; 3732} 3733 3734static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3735{ 3736 if (proto != htons(ETH_P_8021Q)) 3737 return -EINVAL; 3738 3739 return efx_ef10_add_vlan(efx, vid); 3740} 3741 3742static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid) 3743{ 3744 if (proto != htons(ETH_P_8021Q)) 3745 return -EINVAL; 3746 3747 return efx_ef10_del_vlan(efx, vid); 3748} 3749 3750/* We rely on the MCDI wiping out our TX rings if it made any changes to the 3751 * ports table, ensuring that any TSO descriptors that were made on a now- 3752 * removed tunnel port will be blown away and won't break things when we try 3753 * to transmit them using the new ports table. 3754 */ 3755static int efx_ef10_set_udp_tnl_ports(struct efx_nic *efx, bool unloading) 3756{ 3757 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3758 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMAX); 3759 MCDI_DECLARE_BUF(outbuf, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_LEN); 3760 bool will_reset = false; 3761 size_t num_entries = 0; 3762 size_t inlen, outlen; 3763 size_t i; 3764 int rc; 3765 efx_dword_t flags_and_num_entries; 3766 3767 WARN_ON(!mutex_is_locked(&nic_data->udp_tunnels_lock)); 3768 3769 nic_data->udp_tunnels_dirty = false; 3770 3771 if (!(nic_data->datapath_caps & 3772 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) { 3773 efx_device_attach_if_not_resetting(efx); 3774 return 0; 3775 } 3776 3777 BUILD_BUG_ON(ARRAY_SIZE(nic_data->udp_tunnels) > 3778 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM); 3779 3780 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) { 3781 if (nic_data->udp_tunnels[i].type != 3782 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID) { 3783 efx_dword_t entry; 3784 3785 EFX_POPULATE_DWORD_2(entry, 3786 TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT, 3787 ntohs(nic_data->udp_tunnels[i].port), 3788 TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL, 3789 nic_data->udp_tunnels[i].type); 3790 *_MCDI_ARRAY_DWORD(inbuf, 3791 SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES, 3792 num_entries++) = entry; 3793 } 3794 } 3795 3796 BUILD_BUG_ON((MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_OFST - 3797 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST) * 8 != 3798 EFX_WORD_1_LBN); 3799 BUILD_BUG_ON(MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_NUM_ENTRIES_LEN * 8 != 3800 EFX_WORD_1_WIDTH); 3801 EFX_POPULATE_DWORD_2(flags_and_num_entries, 3802 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING, 3803 !!unloading, 3804 EFX_WORD_1, num_entries); 3805 *_MCDI_DWORD(inbuf, SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS) = 3806 flags_and_num_entries; 3807 3808 inlen = MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num_entries); 3809 3810 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS, 3811 inbuf, inlen, outbuf, sizeof(outbuf), &outlen); 3812 if (rc == -EIO) { 3813 /* Most likely the MC rebooted due to another function also 3814 * setting its tunnel port list. Mark the tunnel port list as 3815 * dirty, so it will be pushed upon coming up from the reboot. 3816 */ 3817 nic_data->udp_tunnels_dirty = true; 3818 return 0; 3819 } 3820 3821 if (rc) { 3822 /* expected not available on unprivileged functions */ 3823 if (rc != -EPERM) 3824 netif_warn(efx, drv, efx->net_dev, 3825 "Unable to set UDP tunnel ports; rc=%d.\n", rc); 3826 } else if (MCDI_DWORD(outbuf, SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS) & 3827 (1 << MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN)) { 3828 netif_info(efx, drv, efx->net_dev, 3829 "Rebooting MC due to UDP tunnel port list change\n"); 3830 will_reset = true; 3831 if (unloading) 3832 /* Delay for the MC reset to complete. This will make 3833 * unloading other functions a bit smoother. This is a 3834 * race, but the other unload will work whichever way 3835 * it goes, this just avoids an unnecessary error 3836 * message. 3837 */ 3838 msleep(100); 3839 } 3840 if (!will_reset && !unloading) { 3841 /* The caller will have detached, relying on the MC reset to 3842 * trigger a re-attach. Since there won't be an MC reset, we 3843 * have to do the attach ourselves. 3844 */ 3845 efx_device_attach_if_not_resetting(efx); 3846 } 3847 3848 return rc; 3849} 3850 3851static int efx_ef10_udp_tnl_push_ports(struct efx_nic *efx) 3852{ 3853 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3854 int rc = 0; 3855 3856 mutex_lock(&nic_data->udp_tunnels_lock); 3857 if (nic_data->udp_tunnels_dirty) { 3858 /* Make sure all TX are stopped while we modify the table, else 3859 * we might race against an efx_features_check(). 3860 */ 3861 efx_device_detach_sync(efx); 3862 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3863 } 3864 mutex_unlock(&nic_data->udp_tunnels_lock); 3865 return rc; 3866} 3867 3868static int efx_ef10_udp_tnl_set_port(struct net_device *dev, 3869 unsigned int table, unsigned int entry, 3870 struct udp_tunnel_info *ti) 3871{ 3872 struct efx_nic *efx = netdev_priv(dev); 3873 struct efx_ef10_nic_data *nic_data; 3874 int efx_tunnel_type, rc; 3875 3876 if (ti->type == UDP_TUNNEL_TYPE_VXLAN) 3877 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN; 3878 else 3879 efx_tunnel_type = TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE; 3880 3881 nic_data = efx->nic_data; 3882 if (!(nic_data->datapath_caps & 3883 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3884 return -EOPNOTSUPP; 3885 3886 mutex_lock(&nic_data->udp_tunnels_lock); 3887 /* Make sure all TX are stopped while we add to the table, else we 3888 * might race against an efx_features_check(). 3889 */ 3890 efx_device_detach_sync(efx); 3891 nic_data->udp_tunnels[entry].type = efx_tunnel_type; 3892 nic_data->udp_tunnels[entry].port = ti->port; 3893 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3894 mutex_unlock(&nic_data->udp_tunnels_lock); 3895 3896 return rc; 3897} 3898 3899/* Called under the TX lock with the TX queue running, hence no-one can be 3900 * in the middle of updating the UDP tunnels table. However, they could 3901 * have tried and failed the MCDI, in which case they'll have set the dirty 3902 * flag before dropping their locks. 3903 */ 3904static bool efx_ef10_udp_tnl_has_port(struct efx_nic *efx, __be16 port) 3905{ 3906 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3907 size_t i; 3908 3909 if (!(nic_data->datapath_caps & 3910 (1 << MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_LBN))) 3911 return false; 3912 3913 if (nic_data->udp_tunnels_dirty) 3914 /* SW table may not match HW state, so just assume we can't 3915 * use any UDP tunnel offloads. 3916 */ 3917 return false; 3918 3919 for (i = 0; i < ARRAY_SIZE(nic_data->udp_tunnels); ++i) 3920 if (nic_data->udp_tunnels[i].type != 3921 TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID && 3922 nic_data->udp_tunnels[i].port == port) 3923 return true; 3924 3925 return false; 3926} 3927 3928static int efx_ef10_udp_tnl_unset_port(struct net_device *dev, 3929 unsigned int table, unsigned int entry, 3930 struct udp_tunnel_info *ti) 3931{ 3932 struct efx_nic *efx = netdev_priv(dev); 3933 struct efx_ef10_nic_data *nic_data; 3934 int rc; 3935 3936 nic_data = efx->nic_data; 3937 3938 mutex_lock(&nic_data->udp_tunnels_lock); 3939 /* Make sure all TX are stopped while we remove from the table, else we 3940 * might race against an efx_features_check(). 3941 */ 3942 efx_device_detach_sync(efx); 3943 nic_data->udp_tunnels[entry].type = TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID; 3944 nic_data->udp_tunnels[entry].port = 0; 3945 rc = efx_ef10_set_udp_tnl_ports(efx, false); 3946 mutex_unlock(&nic_data->udp_tunnels_lock); 3947 3948 return rc; 3949} 3950 3951static const struct udp_tunnel_nic_info efx_ef10_udp_tunnels = { 3952 .set_port = efx_ef10_udp_tnl_set_port, 3953 .unset_port = efx_ef10_udp_tnl_unset_port, 3954 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP, 3955 .tables = { 3956 { 3957 .n_entries = 16, 3958 .tunnel_types = UDP_TUNNEL_TYPE_VXLAN | 3959 UDP_TUNNEL_TYPE_GENEVE, 3960 }, 3961 }, 3962}; 3963 3964/* EF10 may have multiple datapath firmware variants within a 3965 * single version. Report which variants are running. 3966 */ 3967static size_t efx_ef10_print_additional_fwver(struct efx_nic *efx, char *buf, 3968 size_t len) 3969{ 3970 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3971 3972 return scnprintf(buf, len, " rx%x tx%x", 3973 nic_data->rx_dpcpu_fw_id, 3974 nic_data->tx_dpcpu_fw_id); 3975} 3976 3977static unsigned int ef10_check_caps(const struct efx_nic *efx, 3978 u8 flag, 3979 u32 offset) 3980{ 3981 const struct efx_ef10_nic_data *nic_data = efx->nic_data; 3982 3983 switch (offset) { 3984 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST): 3985 return nic_data->datapath_caps & BIT_ULL(flag); 3986 case(MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_OFST): 3987 return nic_data->datapath_caps2 & BIT_ULL(flag); 3988 default: 3989 return 0; 3990 } 3991} 3992 3993#define EF10_OFFLOAD_FEATURES \ 3994 (NETIF_F_IP_CSUM | \ 3995 NETIF_F_HW_VLAN_CTAG_FILTER | \ 3996 NETIF_F_IPV6_CSUM | \ 3997 NETIF_F_RXHASH | \ 3998 NETIF_F_NTUPLE | \ 3999 NETIF_F_SG | \ 4000 NETIF_F_RXCSUM | \ 4001 NETIF_F_RXALL) 4002 4003const struct efx_nic_type efx_hunt_a0_vf_nic_type = { 4004 .is_vf = true, 4005 .mem_bar = efx_ef10_vf_mem_bar, 4006 .mem_map_size = efx_ef10_mem_map_size, 4007 .probe = efx_ef10_probe_vf, 4008 .remove = efx_ef10_remove, 4009 .dimension_resources = efx_ef10_dimension_resources, 4010 .init = efx_ef10_init_nic, 4011 .fini = efx_ef10_fini_nic, 4012 .map_reset_reason = efx_ef10_map_reset_reason, 4013 .map_reset_flags = efx_ef10_map_reset_flags, 4014 .reset = efx_ef10_reset, 4015 .probe_port = efx_mcdi_port_probe, 4016 .remove_port = efx_mcdi_port_remove, 4017 .fini_dmaq = efx_fini_dmaq, 4018 .prepare_flr = efx_ef10_prepare_flr, 4019 .finish_flr = efx_port_dummy_op_void, 4020 .describe_stats = efx_ef10_describe_stats, 4021 .update_stats = efx_ef10_update_stats_vf, 4022 .update_stats_atomic = efx_ef10_update_stats_atomic_vf, 4023 .start_stats = efx_port_dummy_op_void, 4024 .pull_stats = efx_port_dummy_op_void, 4025 .stop_stats = efx_port_dummy_op_void, 4026 .push_irq_moderation = efx_ef10_push_irq_moderation, 4027 .reconfigure_mac = efx_ef10_mac_reconfigure, 4028 .check_mac_fault = efx_mcdi_mac_check_fault, 4029 .reconfigure_port = efx_mcdi_port_reconfigure, 4030 .get_wol = efx_ef10_get_wol_vf, 4031 .set_wol = efx_ef10_set_wol_vf, 4032 .resume_wol = efx_port_dummy_op_void, 4033 .mcdi_request = efx_ef10_mcdi_request, 4034 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4035 .mcdi_read_response = efx_ef10_mcdi_read_response, 4036 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4037 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4038 .irq_enable_master = efx_port_dummy_op_void, 4039 .irq_test_generate = efx_ef10_irq_test_generate, 4040 .irq_disable_non_ev = efx_port_dummy_op_void, 4041 .irq_handle_msi = efx_ef10_msi_interrupt, 4042 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4043 .tx_probe = efx_ef10_tx_probe, 4044 .tx_init = efx_ef10_tx_init, 4045 .tx_remove = efx_mcdi_tx_remove, 4046 .tx_write = efx_ef10_tx_write, 4047 .tx_limit_len = efx_ef10_tx_limit_len, 4048 .tx_enqueue = __efx_enqueue_skb, 4049 .rx_push_rss_config = efx_mcdi_vf_rx_push_rss_config, 4050 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4051 .rx_probe = efx_mcdi_rx_probe, 4052 .rx_init = efx_mcdi_rx_init, 4053 .rx_remove = efx_mcdi_rx_remove, 4054 .rx_write = efx_ef10_rx_write, 4055 .rx_defer_refill = efx_ef10_rx_defer_refill, 4056 .rx_packet = __efx_rx_packet, 4057 .ev_probe = efx_mcdi_ev_probe, 4058 .ev_init = efx_ef10_ev_init, 4059 .ev_fini = efx_mcdi_ev_fini, 4060 .ev_remove = efx_mcdi_ev_remove, 4061 .ev_process = efx_ef10_ev_process, 4062 .ev_read_ack = efx_ef10_ev_read_ack, 4063 .ev_test_generate = efx_ef10_ev_test_generate, 4064 .filter_table_probe = efx_ef10_filter_table_probe, 4065 .filter_table_restore = efx_mcdi_filter_table_restore, 4066 .filter_table_remove = efx_mcdi_filter_table_remove, 4067 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4068 .filter_insert = efx_mcdi_filter_insert, 4069 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4070 .filter_get_safe = efx_mcdi_filter_get_safe, 4071 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4072 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4073 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4074 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4075#ifdef CONFIG_RFS_ACCEL 4076 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4077#endif 4078#ifdef CONFIG_SFC_MTD 4079 .mtd_probe = efx_port_dummy_op_int, 4080#endif 4081 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf, 4082 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf, 4083 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4084 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4085#ifdef CONFIG_SFC_SRIOV 4086 .vswitching_probe = efx_ef10_vswitching_probe_vf, 4087 .vswitching_restore = efx_ef10_vswitching_restore_vf, 4088 .vswitching_remove = efx_ef10_vswitching_remove_vf, 4089#endif 4090 .get_mac_address = efx_ef10_get_mac_address_vf, 4091 .set_mac_address = efx_ef10_set_mac_address, 4092 4093 .get_phys_port_id = efx_ef10_get_phys_port_id, 4094 .revision = EFX_REV_HUNT_A0, 4095 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4096 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4097 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4098 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4099 .can_rx_scatter = true, 4100 .always_rx_scatter = true, 4101 .min_interrupt_mode = EFX_INT_MODE_MSIX, 4102 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4103 .offload_features = EF10_OFFLOAD_FEATURES, 4104 .mcdi_max_ver = 2, 4105 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4106 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4107 1 << HWTSTAMP_FILTER_ALL, 4108 .rx_hash_key_size = 40, 4109 .check_caps = ef10_check_caps, 4110 .print_additional_fwver = efx_ef10_print_additional_fwver, 4111 .sensor_event = efx_mcdi_sensor_event, 4112}; 4113 4114const struct efx_nic_type efx_hunt_a0_nic_type = { 4115 .is_vf = false, 4116 .mem_bar = efx_ef10_pf_mem_bar, 4117 .mem_map_size = efx_ef10_mem_map_size, 4118 .probe = efx_ef10_probe_pf, 4119 .remove = efx_ef10_remove, 4120 .dimension_resources = efx_ef10_dimension_resources, 4121 .init = efx_ef10_init_nic, 4122 .fini = efx_ef10_fini_nic, 4123 .map_reset_reason = efx_ef10_map_reset_reason, 4124 .map_reset_flags = efx_ef10_map_reset_flags, 4125 .reset = efx_ef10_reset, 4126 .probe_port = efx_mcdi_port_probe, 4127 .remove_port = efx_mcdi_port_remove, 4128 .fini_dmaq = efx_fini_dmaq, 4129 .prepare_flr = efx_ef10_prepare_flr, 4130 .finish_flr = efx_port_dummy_op_void, 4131 .describe_stats = efx_ef10_describe_stats, 4132 .update_stats = efx_ef10_update_stats_pf, 4133 .start_stats = efx_mcdi_mac_start_stats, 4134 .pull_stats = efx_mcdi_mac_pull_stats, 4135 .stop_stats = efx_mcdi_mac_stop_stats, 4136 .push_irq_moderation = efx_ef10_push_irq_moderation, 4137 .reconfigure_mac = efx_ef10_mac_reconfigure, 4138 .check_mac_fault = efx_mcdi_mac_check_fault, 4139 .reconfigure_port = efx_mcdi_port_reconfigure, 4140 .get_wol = efx_ef10_get_wol, 4141 .set_wol = efx_ef10_set_wol, 4142 .resume_wol = efx_port_dummy_op_void, 4143 .test_chip = efx_ef10_test_chip, 4144 .test_nvram = efx_mcdi_nvram_test_all, 4145 .mcdi_request = efx_ef10_mcdi_request, 4146 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 4147 .mcdi_read_response = efx_ef10_mcdi_read_response, 4148 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 4149 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected, 4150 .irq_enable_master = efx_port_dummy_op_void, 4151 .irq_test_generate = efx_ef10_irq_test_generate, 4152 .irq_disable_non_ev = efx_port_dummy_op_void, 4153 .irq_handle_msi = efx_ef10_msi_interrupt, 4154 .irq_handle_legacy = efx_ef10_legacy_interrupt, 4155 .tx_probe = efx_ef10_tx_probe, 4156 .tx_init = efx_ef10_tx_init, 4157 .tx_remove = efx_mcdi_tx_remove, 4158 .tx_write = efx_ef10_tx_write, 4159 .tx_limit_len = efx_ef10_tx_limit_len, 4160 .tx_enqueue = __efx_enqueue_skb, 4161 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 4162 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 4163 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 4164 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 4165 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 4166 .rx_probe = efx_mcdi_rx_probe, 4167 .rx_init = efx_mcdi_rx_init, 4168 .rx_remove = efx_mcdi_rx_remove, 4169 .rx_write = efx_ef10_rx_write, 4170 .rx_defer_refill = efx_ef10_rx_defer_refill, 4171 .rx_packet = __efx_rx_packet, 4172 .ev_probe = efx_mcdi_ev_probe, 4173 .ev_init = efx_ef10_ev_init, 4174 .ev_fini = efx_mcdi_ev_fini, 4175 .ev_remove = efx_mcdi_ev_remove, 4176 .ev_process = efx_ef10_ev_process, 4177 .ev_read_ack = efx_ef10_ev_read_ack, 4178 .ev_test_generate = efx_ef10_ev_test_generate, 4179 .filter_table_probe = efx_ef10_filter_table_probe, 4180 .filter_table_restore = efx_mcdi_filter_table_restore, 4181 .filter_table_remove = efx_mcdi_filter_table_remove, 4182 .filter_update_rx_scatter = efx_mcdi_update_rx_scatter, 4183 .filter_insert = efx_mcdi_filter_insert, 4184 .filter_remove_safe = efx_mcdi_filter_remove_safe, 4185 .filter_get_safe = efx_mcdi_filter_get_safe, 4186 .filter_clear_rx = efx_mcdi_filter_clear_rx, 4187 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 4188 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 4189 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 4190#ifdef CONFIG_RFS_ACCEL 4191 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 4192#endif 4193#ifdef CONFIG_SFC_MTD 4194 .mtd_probe = efx_ef10_mtd_probe, 4195 .mtd_rename = efx_mcdi_mtd_rename, 4196 .mtd_read = efx_mcdi_mtd_read, 4197 .mtd_erase = efx_mcdi_mtd_erase, 4198 .mtd_write = efx_mcdi_mtd_write, 4199 .mtd_sync = efx_mcdi_mtd_sync, 4200#endif 4201 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 4202 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 4203 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 4204 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid, 4205 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid, 4206 .udp_tnl_push_ports = efx_ef10_udp_tnl_push_ports, 4207 .udp_tnl_has_port = efx_ef10_udp_tnl_has_port, 4208#ifdef CONFIG_SFC_SRIOV 4209 .sriov_configure = efx_ef10_sriov_configure, 4210 .sriov_init = efx_ef10_sriov_init, 4211 .sriov_fini = efx_ef10_sriov_fini, 4212 .sriov_wanted = efx_ef10_sriov_wanted, 4213 .sriov_reset = efx_ef10_sriov_reset, 4214 .sriov_flr = efx_ef10_sriov_flr, 4215 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac, 4216 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan, 4217 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk, 4218 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config, 4219 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state, 4220 .vswitching_probe = efx_ef10_vswitching_probe_pf, 4221 .vswitching_restore = efx_ef10_vswitching_restore_pf, 4222 .vswitching_remove = efx_ef10_vswitching_remove_pf, 4223#endif 4224 .get_mac_address = efx_ef10_get_mac_address_pf, 4225 .set_mac_address = efx_ef10_set_mac_address, 4226 .tso_versions = efx_ef10_tso_versions, 4227 4228 .get_phys_port_id = efx_ef10_get_phys_port_id, 4229 .revision = EFX_REV_HUNT_A0, 4230 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 4231 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 4232 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 4233 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 4234 .can_rx_scatter = true, 4235 .always_rx_scatter = true, 4236 .option_descriptors = true, 4237 .min_interrupt_mode = EFX_INT_MODE_LEGACY, 4238 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 4239 .offload_features = EF10_OFFLOAD_FEATURES, 4240 .mcdi_max_ver = 2, 4241 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 4242 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 4243 1 << HWTSTAMP_FILTER_ALL, 4244 .rx_hash_key_size = 40, 4245 .check_caps = ef10_check_caps, 4246 .print_additional_fwver = efx_ef10_print_additional_fwver, 4247 .sensor_event = efx_mcdi_sensor_event, 4248}; 4249