1 /*
2 * QorIQ 10G MDIO Controller
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Authors: Andy Fleming <afleming@freescale.com>
7 * Timur Tabi <timur@freescale.com>
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/phy.h>
19 #include <linux/mdio.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/of_mdio.h>
23
24 /* Number of microseconds to wait for a register to respond */
25 #define TIMEOUT 1000
26
27 struct tgec_mdio_controller {
28 __be32 reserved[12];
29 __be32 mdio_stat; /* MDIO configuration and status */
30 __be32 mdio_ctl; /* MDIO control */
31 __be32 mdio_data; /* MDIO data */
32 __be32 mdio_addr; /* MDIO address */
33 } __packed;
34
35 #define MDIO_STAT_ENC BIT(6)
36 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
37 #define MDIO_STAT_BSY BIT(0)
38 #define MDIO_STAT_RD_ER BIT(1)
39 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
40 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
41 #define MDIO_CTL_PRE_DIS BIT(10)
42 #define MDIO_CTL_SCAN_EN BIT(11)
43 #define MDIO_CTL_POST_INC BIT(14)
44 #define MDIO_CTL_READ BIT(15)
45
46 #define MDIO_DATA(x) (x & 0xffff)
47 #define MDIO_DATA_BSY BIT(31)
48
49 struct mdio_fsl_priv {
50 struct tgec_mdio_controller __iomem *mdio_base;
51 bool is_little_endian;
52 bool has_a009885;
53 bool has_a011043;
54 };
55
xgmac_read32(void __iomem *regs, bool is_little_endian)56 static u32 xgmac_read32(void __iomem *regs,
57 bool is_little_endian)
58 {
59 if (is_little_endian)
60 return ioread32(regs);
61 else
62 return ioread32be(regs);
63 }
64
xgmac_write32(u32 value, void __iomem *regs, bool is_little_endian)65 static void xgmac_write32(u32 value,
66 void __iomem *regs,
67 bool is_little_endian)
68 {
69 if (is_little_endian)
70 iowrite32(value, regs);
71 else
72 iowrite32be(value, regs);
73 }
74
75 /*
76 * Wait until the MDIO bus is free
77 */
xgmac_wait_until_free(struct device *dev, struct tgec_mdio_controller __iomem *regs, bool is_little_endian)78 static int xgmac_wait_until_free(struct device *dev,
79 struct tgec_mdio_controller __iomem *regs,
80 bool is_little_endian)
81 {
82 unsigned int timeout;
83
84 /* Wait till the bus is free */
85 timeout = TIMEOUT;
86 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
87 MDIO_STAT_BSY) && timeout) {
88 cpu_relax();
89 timeout--;
90 }
91
92 if (!timeout) {
93 dev_err(dev, "timeout waiting for bus to be free\n");
94 return -ETIMEDOUT;
95 }
96
97 return 0;
98 }
99
100 /*
101 * Wait till the MDIO read or write operation is complete
102 */
xgmac_wait_until_done(struct device *dev, struct tgec_mdio_controller __iomem *regs, bool is_little_endian)103 static int xgmac_wait_until_done(struct device *dev,
104 struct tgec_mdio_controller __iomem *regs,
105 bool is_little_endian)
106 {
107 unsigned int timeout;
108
109 /* Wait till the MDIO write is complete */
110 timeout = TIMEOUT;
111 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
112 MDIO_STAT_BSY) && timeout) {
113 cpu_relax();
114 timeout--;
115 }
116
117 if (!timeout) {
118 dev_err(dev, "timeout waiting for operation to complete\n");
119 return -ETIMEDOUT;
120 }
121
122 return 0;
123 }
124
125 /*
126 * Write value to the PHY for this device to the register at regnum,waiting
127 * until the write is done before it returns. All PHY configuration has to be
128 * done through the TSEC1 MIIM regs.
129 */
xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)130 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
131 {
132 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
133 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
134 uint16_t dev_addr;
135 u32 mdio_ctl, mdio_stat;
136 int ret;
137 bool endian = priv->is_little_endian;
138
139 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
140 if (regnum & MII_ADDR_C45) {
141 /* Clause 45 (ie 10G) */
142 dev_addr = (regnum >> 16) & 0x1f;
143 mdio_stat |= MDIO_STAT_ENC;
144 } else {
145 /* Clause 22 (ie 1G) */
146 dev_addr = regnum & 0x1f;
147 mdio_stat &= ~MDIO_STAT_ENC;
148 }
149
150 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
151
152 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
153 if (ret)
154 return ret;
155
156 /* Set the port and dev addr */
157 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
158 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
159
160 /* Set the register address */
161 if (regnum & MII_ADDR_C45) {
162 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
163
164 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
165 if (ret)
166 return ret;
167 }
168
169 /* Write the value to the register */
170 xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
171
172 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
173 if (ret)
174 return ret;
175
176 return 0;
177 }
178
179 /*
180 * Reads from register regnum in the PHY for device dev, returning the value.
181 * Clears miimcom first. All PHY configuration has to be done through the
182 * TSEC1 MIIM regs.
183 */
xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)184 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
185 {
186 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
187 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
188 unsigned long flags;
189 uint16_t dev_addr;
190 uint32_t mdio_stat;
191 uint32_t mdio_ctl;
192 int ret;
193 bool endian = priv->is_little_endian;
194
195 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
196 if (regnum & MII_ADDR_C45) {
197 dev_addr = (regnum >> 16) & 0x1f;
198 mdio_stat |= MDIO_STAT_ENC;
199 } else {
200 dev_addr = regnum & 0x1f;
201 mdio_stat &= ~MDIO_STAT_ENC;
202 }
203
204 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
205
206 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
207 if (ret)
208 return ret;
209
210 /* Set the Port and Device Addrs */
211 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
212 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
213
214 /* Set the register address */
215 if (regnum & MII_ADDR_C45) {
216 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
217
218 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
219 if (ret)
220 return ret;
221 }
222
223 if (priv->has_a009885)
224 /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we
225 * must read back the data register within 16 MDC cycles.
226 */
227 local_irq_save(flags);
228
229 /* Initiate the read */
230 xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
231
232 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
233 if (ret)
234 goto irq_restore;
235
236 /* Return all Fs if nothing was there */
237 if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
238 !priv->has_a011043) {
239 dev_dbg(&bus->dev,
240 "Error while reading PHY%d reg at %d.%hhu\n",
241 phy_id, dev_addr, regnum);
242 ret = 0xffff;
243 } else {
244 ret = xgmac_read32(®s->mdio_data, endian) & 0xffff;
245 dev_dbg(&bus->dev, "read %04x\n", ret);
246 }
247
248 irq_restore:
249 if (priv->has_a009885)
250 local_irq_restore(flags);
251
252 return ret;
253 }
254
xgmac_mdio_probe(struct platform_device *pdev)255 static int xgmac_mdio_probe(struct platform_device *pdev)
256 {
257 struct device_node *np = pdev->dev.of_node;
258 struct mii_bus *bus;
259 struct resource *res;
260 struct mdio_fsl_priv *priv;
261 int ret;
262
263 /* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
264 * defines a register space that spans a large area, covering all the
265 * subdevice areas. Therefore, MDIO cannot claim exclusive access to
266 * this register area.
267 */
268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
269 if (!res) {
270 dev_err(&pdev->dev, "could not obtain address\n");
271 return -EINVAL;
272 }
273
274 bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
275 if (!bus)
276 return -ENOMEM;
277
278 bus->name = "Freescale XGMAC MDIO Bus";
279 bus->read = xgmac_mdio_read;
280 bus->write = xgmac_mdio_write;
281 bus->parent = &pdev->dev;
282 bus->probe_capabilities = MDIOBUS_C22_C45;
283 snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
284
285 /* Set the PHY base address */
286 priv = bus->priv;
287 priv->mdio_base = ioremap(res->start, resource_size(res));
288 if (!priv->mdio_base) {
289 ret = -ENOMEM;
290 goto err_ioremap;
291 }
292
293 priv->is_little_endian = device_property_read_bool(&pdev->dev,
294 "little-endian");
295
296 priv->has_a009885 = device_property_read_bool(&pdev->dev,
297 "fsl,erratum-a009885");
298 priv->has_a011043 = device_property_read_bool(&pdev->dev,
299 "fsl,erratum-a011043");
300
301 ret = of_mdiobus_register(bus, np);
302 if (ret) {
303 dev_err(&pdev->dev, "cannot register MDIO bus\n");
304 goto err_registration;
305 }
306
307 platform_set_drvdata(pdev, bus);
308
309 return 0;
310
311 err_registration:
312 iounmap(priv->mdio_base);
313
314 err_ioremap:
315 mdiobus_free(bus);
316
317 return ret;
318 }
319
xgmac_mdio_remove(struct platform_device *pdev)320 static int xgmac_mdio_remove(struct platform_device *pdev)
321 {
322 struct mii_bus *bus = platform_get_drvdata(pdev);
323 struct mdio_fsl_priv *priv = bus->priv;
324
325 mdiobus_unregister(bus);
326 iounmap(priv->mdio_base);
327 mdiobus_free(bus);
328
329 return 0;
330 }
331
332 static const struct of_device_id xgmac_mdio_match[] = {
333 {
334 .compatible = "fsl,fman-xmdio",
335 },
336 {
337 .compatible = "fsl,fman-memac-mdio",
338 },
339 {},
340 };
341 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
342
343 static const struct acpi_device_id xgmac_acpi_match[] = {
344 { "NXP0006" },
345 { }
346 };
347 MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
348
349 static struct platform_driver xgmac_mdio_driver = {
350 .driver = {
351 .name = "fsl-fman_xmdio",
352 .of_match_table = xgmac_mdio_match,
353 .acpi_match_table = xgmac_acpi_match,
354 },
355 .probe = xgmac_mdio_probe,
356 .remove = xgmac_mdio_remove,
357 };
358
359 module_platform_driver(xgmac_mdio_driver);
360
361 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
362 MODULE_LICENSE("GPL v2");
363