1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 5 * 6 * Right now, I am very wasteful with the buffers. I allocate memory 7 * pages and then divide them into 2K frame buffers. This way I know I 8 * have buffers large enough to hold one frame within one buffer descriptor. 9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 10 * will be much more memory efficient and will easily handle lots of 11 * small packets. 12 * 13 * Much better multiple PHY support by Magnus Damm. 14 * Copyright (c) 2000 Ericsson Radio Systems AB. 15 * 16 * Support for FEC controller of ColdFire processors. 17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 18 * 19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 20 * Copyright (c) 2004-2006 Macq Electronique SA. 21 * 22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 23 */ 24 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/string.h> 28#include <linux/pm_runtime.h> 29#include <linux/ptrace.h> 30#include <linux/errno.h> 31#include <linux/ioport.h> 32#include <linux/slab.h> 33#include <linux/interrupt.h> 34#include <linux/delay.h> 35#include <linux/netdevice.h> 36#include <linux/etherdevice.h> 37#include <linux/skbuff.h> 38#include <linux/in.h> 39#include <linux/ip.h> 40#include <net/ip.h> 41#include <net/tso.h> 42#include <linux/tcp.h> 43#include <linux/udp.h> 44#include <linux/icmp.h> 45#include <linux/spinlock.h> 46#include <linux/workqueue.h> 47#include <linux/bitops.h> 48#include <linux/io.h> 49#include <linux/irq.h> 50#include <linux/clk.h> 51#include <linux/crc32.h> 52#include <linux/platform_device.h> 53#include <linux/mdio.h> 54#include <linux/phy.h> 55#include <linux/fec.h> 56#include <linux/of.h> 57#include <linux/of_device.h> 58#include <linux/of_gpio.h> 59#include <linux/of_mdio.h> 60#include <linux/of_net.h> 61#include <linux/regulator/consumer.h> 62#include <linux/if_vlan.h> 63#include <linux/pinctrl/consumer.h> 64#include <linux/prefetch.h> 65#include <linux/mfd/syscon.h> 66#include <linux/regmap.h> 67#include <soc/imx/cpuidle.h> 68 69#include <asm/cacheflush.h> 70 71#include "fec.h" 72 73static void set_multicast_list(struct net_device *ndev); 74static void fec_enet_itr_coal_init(struct net_device *ndev); 75 76#define DRIVER_NAME "fec" 77 78static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2}; 79 80/* Pause frame feild and FIFO threshold */ 81#define FEC_ENET_FCE (1 << 5) 82#define FEC_ENET_RSEM_V 0x84 83#define FEC_ENET_RSFL_V 16 84#define FEC_ENET_RAEM_V 0x8 85#define FEC_ENET_RAFL_V 0x8 86#define FEC_ENET_OPD_V 0xFFF0 87#define FEC_MDIO_PM_TIMEOUT 100 /* ms */ 88 89struct fec_devinfo { 90 u32 quirks; 91}; 92 93static const struct fec_devinfo fec_imx25_info = { 94 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 95 FEC_QUIRK_HAS_FRREG, 96}; 97 98static const struct fec_devinfo fec_imx27_info = { 99 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 100}; 101 102static const struct fec_devinfo fec_imx28_info = { 103 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 104 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 105 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII, 106}; 107 108static const struct fec_devinfo fec_imx6q_info = { 109 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 | 112 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII, 113}; 114 115static const struct fec_devinfo fec_mvf600_info = { 116 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC, 117}; 118 119static const struct fec_devinfo fec_imx6x_info = { 120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB | 123 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE | 124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE | 125 FEC_QUIRK_CLEAR_SETUP_MII, 126}; 127 128static const struct fec_devinfo fec_imx6ul_info = { 129 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | 130 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | 131 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 | 132 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC | 133 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII, 134}; 135 136static struct platform_device_id fec_devtype[] = { 137 { 138 /* keep it for coldfire */ 139 .name = DRIVER_NAME, 140 .driver_data = 0, 141 }, { 142 .name = "imx25-fec", 143 .driver_data = (kernel_ulong_t)&fec_imx25_info, 144 }, { 145 .name = "imx27-fec", 146 .driver_data = (kernel_ulong_t)&fec_imx27_info, 147 }, { 148 .name = "imx28-fec", 149 .driver_data = (kernel_ulong_t)&fec_imx28_info, 150 }, { 151 .name = "imx6q-fec", 152 .driver_data = (kernel_ulong_t)&fec_imx6q_info, 153 }, { 154 .name = "mvf600-fec", 155 .driver_data = (kernel_ulong_t)&fec_mvf600_info, 156 }, { 157 .name = "imx6sx-fec", 158 .driver_data = (kernel_ulong_t)&fec_imx6x_info, 159 }, { 160 .name = "imx6ul-fec", 161 .driver_data = (kernel_ulong_t)&fec_imx6ul_info, 162 }, { 163 /* sentinel */ 164 } 165}; 166MODULE_DEVICE_TABLE(platform, fec_devtype); 167 168enum imx_fec_type { 169 IMX25_FEC = 1, /* runs on i.mx25/50/53 */ 170 IMX27_FEC, /* runs on i.mx27/35/51 */ 171 IMX28_FEC, 172 IMX6Q_FEC, 173 MVF600_FEC, 174 IMX6SX_FEC, 175 IMX6UL_FEC, 176}; 177 178static const struct of_device_id fec_dt_ids[] = { 179 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, 180 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, 181 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, 182 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, 183 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, 184 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], }, 185 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], }, 186 { /* sentinel */ } 187}; 188MODULE_DEVICE_TABLE(of, fec_dt_ids); 189 190static unsigned char macaddr[ETH_ALEN]; 191module_param_array(macaddr, byte, NULL, 0); 192MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 193 194#if defined(CONFIG_M5272) 195/* 196 * Some hardware gets it MAC address out of local flash memory. 197 * if this is non-zero then assume it is the address to get MAC from. 198 */ 199#if defined(CONFIG_NETtel) 200#define FEC_FLASHMAC 0xf0006006 201#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 202#define FEC_FLASHMAC 0xf0006000 203#elif defined(CONFIG_CANCam) 204#define FEC_FLASHMAC 0xf0020000 205#elif defined (CONFIG_M5272C3) 206#define FEC_FLASHMAC (0xffe04000 + 4) 207#elif defined(CONFIG_MOD5272) 208#define FEC_FLASHMAC 0xffc0406b 209#else 210#define FEC_FLASHMAC 0 211#endif 212#endif /* CONFIG_M5272 */ 213 214/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. 215 * 216 * 2048 byte skbufs are allocated. However, alignment requirements 217 * varies between FEC variants. Worst case is 64, so round down by 64. 218 */ 219#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64)) 220#define PKT_MINBUF_SIZE 64 221 222/* FEC receive acceleration */ 223#define FEC_RACC_IPDIS (1 << 1) 224#define FEC_RACC_PRODIS (1 << 2) 225#define FEC_RACC_SHIFT16 BIT(7) 226#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) 227 228/* MIB Control Register */ 229#define FEC_MIB_CTRLSTAT_DISABLE BIT(31) 230 231/* 232 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 233 * size bits. Other FEC hardware does not, so we need to take that into 234 * account when setting it. 235 */ 236#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 237 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 238 defined(CONFIG_ARM64) 239#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 240#else 241#define OPT_FRAME_SIZE 0 242#endif 243 244/* FEC MII MMFR bits definition */ 245#define FEC_MMFR_ST (1 << 30) 246#define FEC_MMFR_ST_C45 (0) 247#define FEC_MMFR_OP_READ (2 << 28) 248#define FEC_MMFR_OP_READ_C45 (3 << 28) 249#define FEC_MMFR_OP_WRITE (1 << 28) 250#define FEC_MMFR_OP_ADDR_WRITE (0) 251#define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 252#define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 253#define FEC_MMFR_TA (2 << 16) 254#define FEC_MMFR_DATA(v) (v & 0xffff) 255/* FEC ECR bits definition */ 256#define FEC_ECR_MAGICEN (1 << 2) 257#define FEC_ECR_SLEEP (1 << 3) 258 259#define FEC_MII_TIMEOUT 30000 /* us */ 260 261/* Transmitter timeout */ 262#define TX_TIMEOUT (2 * HZ) 263 264#define FEC_PAUSE_FLAG_AUTONEG 0x1 265#define FEC_PAUSE_FLAG_ENABLE 0x2 266#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0) 267#define FEC_WOL_FLAG_ENABLE (0x1 << 1) 268#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2) 269 270#define COPYBREAK_DEFAULT 256 271 272/* Max number of allowed TCP segments for software TSO */ 273#define FEC_MAX_TSO_SEGS 100 274#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 275 276#define IS_TSO_HEADER(txq, addr) \ 277 ((addr >= txq->tso_hdrs_dma) && \ 278 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE)) 279 280static int mii_cnt; 281 282static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, 283 struct bufdesc_prop *bd) 284{ 285 return (bdp >= bd->last) ? bd->base 286 : (struct bufdesc *)(((void *)bdp) + bd->dsize); 287} 288 289static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, 290 struct bufdesc_prop *bd) 291{ 292 return (bdp <= bd->base) ? bd->last 293 : (struct bufdesc *)(((void *)bdp) - bd->dsize); 294} 295 296static int fec_enet_get_bd_index(struct bufdesc *bdp, 297 struct bufdesc_prop *bd) 298{ 299 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2; 300} 301 302static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq) 303{ 304 int entries; 305 306 entries = (((const char *)txq->dirty_tx - 307 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1; 308 309 return entries >= 0 ? entries : entries + txq->bd.ring_size; 310} 311 312static void swap_buffer(void *bufaddr, int len) 313{ 314 int i; 315 unsigned int *buf = bufaddr; 316 317 for (i = 0; i < len; i += 4, buf++) 318 swab32s(buf); 319} 320 321static void swap_buffer2(void *dst_buf, void *src_buf, int len) 322{ 323 int i; 324 unsigned int *src = src_buf; 325 unsigned int *dst = dst_buf; 326 327 for (i = 0; i < len; i += 4, src++, dst++) 328 *dst = swab32p(src); 329} 330 331static void fec_dump(struct net_device *ndev) 332{ 333 struct fec_enet_private *fep = netdev_priv(ndev); 334 struct bufdesc *bdp; 335 struct fec_enet_priv_tx_q *txq; 336 int index = 0; 337 338 netdev_info(ndev, "TX ring dump\n"); 339 pr_info("Nr SC addr len SKB\n"); 340 341 txq = fep->tx_queue[0]; 342 bdp = txq->bd.base; 343 344 do { 345 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n", 346 index, 347 bdp == txq->bd.cur ? 'S' : ' ', 348 bdp == txq->dirty_tx ? 'H' : ' ', 349 fec16_to_cpu(bdp->cbd_sc), 350 fec32_to_cpu(bdp->cbd_bufaddr), 351 fec16_to_cpu(bdp->cbd_datlen), 352 txq->tx_skbuff[index]); 353 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 354 index++; 355 } while (bdp != txq->bd.base); 356} 357 358static inline bool is_ipv4_pkt(struct sk_buff *skb) 359{ 360 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 361} 362 363static int 364fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) 365{ 366 /* Only run for packets requiring a checksum. */ 367 if (skb->ip_summed != CHECKSUM_PARTIAL) 368 return 0; 369 370 if (unlikely(skb_cow_head(skb, 0))) 371 return -1; 372 373 if (is_ipv4_pkt(skb)) 374 ip_hdr(skb)->check = 0; 375 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; 376 377 return 0; 378} 379 380static struct bufdesc * 381fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq, 382 struct sk_buff *skb, 383 struct net_device *ndev) 384{ 385 struct fec_enet_private *fep = netdev_priv(ndev); 386 struct bufdesc *bdp = txq->bd.cur; 387 struct bufdesc_ex *ebdp; 388 int nr_frags = skb_shinfo(skb)->nr_frags; 389 int frag, frag_len; 390 unsigned short status; 391 unsigned int estatus = 0; 392 skb_frag_t *this_frag; 393 unsigned int index; 394 void *bufaddr; 395 dma_addr_t addr; 396 int i; 397 398 for (frag = 0; frag < nr_frags; frag++) { 399 this_frag = &skb_shinfo(skb)->frags[frag]; 400 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 401 ebdp = (struct bufdesc_ex *)bdp; 402 403 status = fec16_to_cpu(bdp->cbd_sc); 404 status &= ~BD_ENET_TX_STATS; 405 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 406 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]); 407 408 /* Handle the last BD specially */ 409 if (frag == nr_frags - 1) { 410 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 411 if (fep->bufdesc_ex) { 412 estatus |= BD_ENET_TX_INT; 413 if (unlikely(skb_shinfo(skb)->tx_flags & 414 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 415 estatus |= BD_ENET_TX_TS; 416 } 417 } 418 419 if (fep->bufdesc_ex) { 420 if (fep->quirks & FEC_QUIRK_HAS_AVB) 421 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 422 if (skb->ip_summed == CHECKSUM_PARTIAL) 423 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 424 ebdp->cbd_bdu = 0; 425 ebdp->cbd_esc = cpu_to_fec32(estatus); 426 } 427 428 bufaddr = skb_frag_address(this_frag); 429 430 index = fec_enet_get_bd_index(bdp, &txq->bd); 431 if (((unsigned long) bufaddr) & fep->tx_align || 432 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 433 memcpy(txq->tx_bounce[index], bufaddr, frag_len); 434 bufaddr = txq->tx_bounce[index]; 435 436 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 437 swap_buffer(bufaddr, frag_len); 438 } 439 440 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len, 441 DMA_TO_DEVICE); 442 if (dma_mapping_error(&fep->pdev->dev, addr)) { 443 if (net_ratelimit()) 444 netdev_err(ndev, "Tx DMA memory map failed\n"); 445 goto dma_mapping_error; 446 } 447 448 bdp->cbd_bufaddr = cpu_to_fec32(addr); 449 bdp->cbd_datlen = cpu_to_fec16(frag_len); 450 /* Make sure the updates to rest of the descriptor are 451 * performed before transferring ownership. 452 */ 453 wmb(); 454 bdp->cbd_sc = cpu_to_fec16(status); 455 } 456 457 return bdp; 458dma_mapping_error: 459 bdp = txq->bd.cur; 460 for (i = 0; i < frag; i++) { 461 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 462 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr), 463 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE); 464 } 465 return ERR_PTR(-ENOMEM); 466} 467 468static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq, 469 struct sk_buff *skb, struct net_device *ndev) 470{ 471 struct fec_enet_private *fep = netdev_priv(ndev); 472 int nr_frags = skb_shinfo(skb)->nr_frags; 473 struct bufdesc *bdp, *last_bdp; 474 void *bufaddr; 475 dma_addr_t addr; 476 unsigned short status; 477 unsigned short buflen; 478 unsigned int estatus = 0; 479 unsigned int index; 480 int entries_free; 481 482 entries_free = fec_enet_get_free_txdesc_num(txq); 483 if (entries_free < MAX_SKB_FRAGS + 1) { 484 dev_kfree_skb_any(skb); 485 if (net_ratelimit()) 486 netdev_err(ndev, "NOT enough BD for SG!\n"); 487 return NETDEV_TX_OK; 488 } 489 490 /* Protocol checksum off-load for TCP and UDP. */ 491 if (fec_enet_clear_csum(skb, ndev)) { 492 dev_kfree_skb_any(skb); 493 return NETDEV_TX_OK; 494 } 495 496 /* Fill in a Tx ring entry */ 497 bdp = txq->bd.cur; 498 last_bdp = bdp; 499 status = fec16_to_cpu(bdp->cbd_sc); 500 status &= ~BD_ENET_TX_STATS; 501 502 /* Set buffer length and buffer pointer */ 503 bufaddr = skb->data; 504 buflen = skb_headlen(skb); 505 506 index = fec_enet_get_bd_index(bdp, &txq->bd); 507 if (((unsigned long) bufaddr) & fep->tx_align || 508 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 509 memcpy(txq->tx_bounce[index], skb->data, buflen); 510 bufaddr = txq->tx_bounce[index]; 511 512 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 513 swap_buffer(bufaddr, buflen); 514 } 515 516 /* Push the data cache so the CPM does not get stale memory data. */ 517 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE); 518 if (dma_mapping_error(&fep->pdev->dev, addr)) { 519 dev_kfree_skb_any(skb); 520 if (net_ratelimit()) 521 netdev_err(ndev, "Tx DMA memory map failed\n"); 522 return NETDEV_TX_OK; 523 } 524 525 if (nr_frags) { 526 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev); 527 if (IS_ERR(last_bdp)) { 528 dma_unmap_single(&fep->pdev->dev, addr, 529 buflen, DMA_TO_DEVICE); 530 dev_kfree_skb_any(skb); 531 return NETDEV_TX_OK; 532 } 533 } else { 534 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST); 535 if (fep->bufdesc_ex) { 536 estatus = BD_ENET_TX_INT; 537 if (unlikely(skb_shinfo(skb)->tx_flags & 538 SKBTX_HW_TSTAMP && fep->hwts_tx_en)) 539 estatus |= BD_ENET_TX_TS; 540 } 541 } 542 bdp->cbd_bufaddr = cpu_to_fec32(addr); 543 bdp->cbd_datlen = cpu_to_fec16(buflen); 544 545 if (fep->bufdesc_ex) { 546 547 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 548 549 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 550 fep->hwts_tx_en)) 551 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 552 553 if (fep->quirks & FEC_QUIRK_HAS_AVB) 554 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 555 556 if (skb->ip_summed == CHECKSUM_PARTIAL) 557 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 558 559 ebdp->cbd_bdu = 0; 560 ebdp->cbd_esc = cpu_to_fec32(estatus); 561 } 562 563 index = fec_enet_get_bd_index(last_bdp, &txq->bd); 564 /* Save skb pointer */ 565 txq->tx_skbuff[index] = skb; 566 567 /* Make sure the updates to rest of the descriptor are performed before 568 * transferring ownership. 569 */ 570 wmb(); 571 572 /* Send it on its way. Tell FEC it's ready, interrupt when done, 573 * it's the last BD of the frame, and to put the CRC on the end. 574 */ 575 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC); 576 bdp->cbd_sc = cpu_to_fec16(status); 577 578 /* If this was the last BD in the ring, start at the beginning again. */ 579 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd); 580 581 skb_tx_timestamp(skb); 582 583 /* Make sure the update to bdp and tx_skbuff are performed before 584 * txq->bd.cur. 585 */ 586 wmb(); 587 txq->bd.cur = bdp; 588 589 /* Trigger transmission start */ 590 writel(0, txq->bd.reg_desc_active); 591 592 return 0; 593} 594 595static int 596fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb, 597 struct net_device *ndev, 598 struct bufdesc *bdp, int index, char *data, 599 int size, bool last_tcp, bool is_last) 600{ 601 struct fec_enet_private *fep = netdev_priv(ndev); 602 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 603 unsigned short status; 604 unsigned int estatus = 0; 605 dma_addr_t addr; 606 607 status = fec16_to_cpu(bdp->cbd_sc); 608 status &= ~BD_ENET_TX_STATS; 609 610 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 611 612 if (((unsigned long) data) & fep->tx_align || 613 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 614 memcpy(txq->tx_bounce[index], data, size); 615 data = txq->tx_bounce[index]; 616 617 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 618 swap_buffer(data, size); 619 } 620 621 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE); 622 if (dma_mapping_error(&fep->pdev->dev, addr)) { 623 dev_kfree_skb_any(skb); 624 if (net_ratelimit()) 625 netdev_err(ndev, "Tx DMA memory map failed\n"); 626 return NETDEV_TX_OK; 627 } 628 629 bdp->cbd_datlen = cpu_to_fec16(size); 630 bdp->cbd_bufaddr = cpu_to_fec32(addr); 631 632 if (fep->bufdesc_ex) { 633 if (fep->quirks & FEC_QUIRK_HAS_AVB) 634 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 635 if (skb->ip_summed == CHECKSUM_PARTIAL) 636 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 637 ebdp->cbd_bdu = 0; 638 ebdp->cbd_esc = cpu_to_fec32(estatus); 639 } 640 641 /* Handle the last BD specially */ 642 if (last_tcp) 643 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC); 644 if (is_last) { 645 status |= BD_ENET_TX_INTR; 646 if (fep->bufdesc_ex) 647 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT); 648 } 649 650 bdp->cbd_sc = cpu_to_fec16(status); 651 652 return 0; 653} 654 655static int 656fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq, 657 struct sk_buff *skb, struct net_device *ndev, 658 struct bufdesc *bdp, int index) 659{ 660 struct fec_enet_private *fep = netdev_priv(ndev); 661 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 662 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc); 663 void *bufaddr; 664 unsigned long dmabuf; 665 unsigned short status; 666 unsigned int estatus = 0; 667 668 status = fec16_to_cpu(bdp->cbd_sc); 669 status &= ~BD_ENET_TX_STATS; 670 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY); 671 672 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 673 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE; 674 if (((unsigned long)bufaddr) & fep->tx_align || 675 fep->quirks & FEC_QUIRK_SWAP_FRAME) { 676 memcpy(txq->tx_bounce[index], skb->data, hdr_len); 677 bufaddr = txq->tx_bounce[index]; 678 679 if (fep->quirks & FEC_QUIRK_SWAP_FRAME) 680 swap_buffer(bufaddr, hdr_len); 681 682 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr, 683 hdr_len, DMA_TO_DEVICE); 684 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) { 685 dev_kfree_skb_any(skb); 686 if (net_ratelimit()) 687 netdev_err(ndev, "Tx DMA memory map failed\n"); 688 return NETDEV_TX_OK; 689 } 690 } 691 692 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf); 693 bdp->cbd_datlen = cpu_to_fec16(hdr_len); 694 695 if (fep->bufdesc_ex) { 696 if (fep->quirks & FEC_QUIRK_HAS_AVB) 697 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid); 698 if (skb->ip_summed == CHECKSUM_PARTIAL) 699 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS; 700 ebdp->cbd_bdu = 0; 701 ebdp->cbd_esc = cpu_to_fec32(estatus); 702 } 703 704 bdp->cbd_sc = cpu_to_fec16(status); 705 706 return 0; 707} 708 709static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq, 710 struct sk_buff *skb, 711 struct net_device *ndev) 712{ 713 struct fec_enet_private *fep = netdev_priv(ndev); 714 int hdr_len, total_len, data_left; 715 struct bufdesc *bdp = txq->bd.cur; 716 struct tso_t tso; 717 unsigned int index = 0; 718 int ret; 719 720 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) { 721 dev_kfree_skb_any(skb); 722 if (net_ratelimit()) 723 netdev_err(ndev, "NOT enough BD for TSO!\n"); 724 return NETDEV_TX_OK; 725 } 726 727 /* Protocol checksum off-load for TCP and UDP. */ 728 if (fec_enet_clear_csum(skb, ndev)) { 729 dev_kfree_skb_any(skb); 730 return NETDEV_TX_OK; 731 } 732 733 /* Initialize the TSO handler, and prepare the first payload */ 734 hdr_len = tso_start(skb, &tso); 735 736 total_len = skb->len - hdr_len; 737 while (total_len > 0) { 738 char *hdr; 739 740 index = fec_enet_get_bd_index(bdp, &txq->bd); 741 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 742 total_len -= data_left; 743 744 /* prepare packet headers: MAC + IP + TCP */ 745 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE; 746 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 747 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index); 748 if (ret) 749 goto err_release; 750 751 while (data_left > 0) { 752 int size; 753 754 size = min_t(int, tso.size, data_left); 755 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 756 index = fec_enet_get_bd_index(bdp, &txq->bd); 757 ret = fec_enet_txq_put_data_tso(txq, skb, ndev, 758 bdp, index, 759 tso.data, size, 760 size == data_left, 761 total_len == 0); 762 if (ret) 763 goto err_release; 764 765 data_left -= size; 766 tso_build_data(skb, &tso, size); 767 } 768 769 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 770 } 771 772 /* Save skb pointer */ 773 txq->tx_skbuff[index] = skb; 774 775 skb_tx_timestamp(skb); 776 txq->bd.cur = bdp; 777 778 /* Trigger transmission start */ 779 if (!(fep->quirks & FEC_QUIRK_ERR007885) || 780 !readl(txq->bd.reg_desc_active) || 781 !readl(txq->bd.reg_desc_active) || 782 !readl(txq->bd.reg_desc_active) || 783 !readl(txq->bd.reg_desc_active)) 784 writel(0, txq->bd.reg_desc_active); 785 786 return 0; 787 788err_release: 789 /* TODO: Release all used data descriptors for TSO */ 790 return ret; 791} 792 793static netdev_tx_t 794fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) 795{ 796 struct fec_enet_private *fep = netdev_priv(ndev); 797 int entries_free; 798 unsigned short queue; 799 struct fec_enet_priv_tx_q *txq; 800 struct netdev_queue *nq; 801 int ret; 802 803 queue = skb_get_queue_mapping(skb); 804 txq = fep->tx_queue[queue]; 805 nq = netdev_get_tx_queue(ndev, queue); 806 807 if (skb_is_gso(skb)) 808 ret = fec_enet_txq_submit_tso(txq, skb, ndev); 809 else 810 ret = fec_enet_txq_submit_skb(txq, skb, ndev); 811 if (ret) 812 return ret; 813 814 entries_free = fec_enet_get_free_txdesc_num(txq); 815 if (entries_free <= txq->tx_stop_threshold) 816 netif_tx_stop_queue(nq); 817 818 return NETDEV_TX_OK; 819} 820 821/* Init RX & TX buffer descriptors 822 */ 823static void fec_enet_bd_init(struct net_device *dev) 824{ 825 struct fec_enet_private *fep = netdev_priv(dev); 826 struct fec_enet_priv_tx_q *txq; 827 struct fec_enet_priv_rx_q *rxq; 828 struct bufdesc *bdp; 829 unsigned int i; 830 unsigned int q; 831 832 for (q = 0; q < fep->num_rx_queues; q++) { 833 /* Initialize the receive buffer descriptors. */ 834 rxq = fep->rx_queue[q]; 835 bdp = rxq->bd.base; 836 837 for (i = 0; i < rxq->bd.ring_size; i++) { 838 839 /* Initialize the BD for every fragment in the page. */ 840 if (bdp->cbd_bufaddr) 841 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 842 else 843 bdp->cbd_sc = cpu_to_fec16(0); 844 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 845 } 846 847 /* Set the last buffer to wrap */ 848 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 849 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 850 851 rxq->bd.cur = rxq->bd.base; 852 } 853 854 for (q = 0; q < fep->num_tx_queues; q++) { 855 /* ...and the same for transmit */ 856 txq = fep->tx_queue[q]; 857 bdp = txq->bd.base; 858 txq->bd.cur = bdp; 859 860 for (i = 0; i < txq->bd.ring_size; i++) { 861 /* Initialize the BD for every fragment in the page. */ 862 bdp->cbd_sc = cpu_to_fec16(0); 863 if (bdp->cbd_bufaddr && 864 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 865 dma_unmap_single(&fep->pdev->dev, 866 fec32_to_cpu(bdp->cbd_bufaddr), 867 fec16_to_cpu(bdp->cbd_datlen), 868 DMA_TO_DEVICE); 869 if (txq->tx_skbuff[i]) { 870 dev_kfree_skb_any(txq->tx_skbuff[i]); 871 txq->tx_skbuff[i] = NULL; 872 } 873 bdp->cbd_bufaddr = cpu_to_fec32(0); 874 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 875 } 876 877 /* Set the last buffer to wrap */ 878 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 879 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 880 txq->dirty_tx = bdp; 881 } 882} 883 884static void fec_enet_active_rxring(struct net_device *ndev) 885{ 886 struct fec_enet_private *fep = netdev_priv(ndev); 887 int i; 888 889 for (i = 0; i < fep->num_rx_queues; i++) 890 writel(0, fep->rx_queue[i]->bd.reg_desc_active); 891} 892 893static void fec_enet_enable_ring(struct net_device *ndev) 894{ 895 struct fec_enet_private *fep = netdev_priv(ndev); 896 struct fec_enet_priv_tx_q *txq; 897 struct fec_enet_priv_rx_q *rxq; 898 int i; 899 900 for (i = 0; i < fep->num_rx_queues; i++) { 901 rxq = fep->rx_queue[i]; 902 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); 903 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i)); 904 905 /* enable DMA1/2 */ 906 if (i) 907 writel(RCMR_MATCHEN | RCMR_CMP(i), 908 fep->hwp + FEC_RCMR(i)); 909 } 910 911 for (i = 0; i < fep->num_tx_queues; i++) { 912 txq = fep->tx_queue[i]; 913 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); 914 915 /* enable DMA1/2 */ 916 if (i) 917 writel(DMA_CLASS_EN | IDLE_SLOPE(i), 918 fep->hwp + FEC_DMA_CFG(i)); 919 } 920} 921 922static void fec_enet_reset_skb(struct net_device *ndev) 923{ 924 struct fec_enet_private *fep = netdev_priv(ndev); 925 struct fec_enet_priv_tx_q *txq; 926 int i, j; 927 928 for (i = 0; i < fep->num_tx_queues; i++) { 929 txq = fep->tx_queue[i]; 930 931 for (j = 0; j < txq->bd.ring_size; j++) { 932 if (txq->tx_skbuff[j]) { 933 dev_kfree_skb_any(txq->tx_skbuff[j]); 934 txq->tx_skbuff[j] = NULL; 935 } 936 } 937 } 938} 939 940/* 941 * This function is called to start or restart the FEC during a link 942 * change, transmit timeout, or to reconfigure the FEC. The network 943 * packet processing for this device must be stopped before this call. 944 */ 945static void 946fec_restart(struct net_device *ndev) 947{ 948 struct fec_enet_private *fep = netdev_priv(ndev); 949 u32 val; 950 u32 temp_mac[2]; 951 u32 rcntl = OPT_FRAME_SIZE | 0x04; 952 u32 ecntl = 0x2; /* ETHEREN */ 953 954 /* Whack a reset. We should wait for this. 955 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 956 * instead of reset MAC itself. 957 */ 958 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 959 writel(0, fep->hwp + FEC_ECNTRL); 960 } else { 961 writel(1, fep->hwp + FEC_ECNTRL); 962 udelay(10); 963 } 964 965 /* 966 * enet-mac reset will reset mac address registers too, 967 * so need to reconfigure it. 968 */ 969 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); 970 writel((__force u32)cpu_to_be32(temp_mac[0]), 971 fep->hwp + FEC_ADDR_LOW); 972 writel((__force u32)cpu_to_be32(temp_mac[1]), 973 fep->hwp + FEC_ADDR_HIGH); 974 975 /* Clear any outstanding interrupt, except MDIO. */ 976 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); 977 978 fec_enet_bd_init(ndev); 979 980 fec_enet_enable_ring(ndev); 981 982 /* Reset tx SKB buffers. */ 983 fec_enet_reset_skb(ndev); 984 985 /* Enable MII mode */ 986 if (fep->full_duplex == DUPLEX_FULL) { 987 /* FD enable */ 988 writel(0x04, fep->hwp + FEC_X_CNTRL); 989 } else { 990 /* No Rcv on Xmit */ 991 rcntl |= 0x02; 992 writel(0x0, fep->hwp + FEC_X_CNTRL); 993 } 994 995 /* Set MII speed */ 996 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 997 998#if !defined(CONFIG_M5272) 999 if (fep->quirks & FEC_QUIRK_HAS_RACC) { 1000 val = readl(fep->hwp + FEC_RACC); 1001 /* align IP header */ 1002 val |= FEC_RACC_SHIFT16; 1003 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) 1004 /* set RX checksum */ 1005 val |= FEC_RACC_OPTIONS; 1006 else 1007 val &= ~FEC_RACC_OPTIONS; 1008 writel(val, fep->hwp + FEC_RACC); 1009 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL); 1010 } 1011#endif 1012 1013 /* 1014 * The phy interface and speed need to get configured 1015 * differently on enet-mac. 1016 */ 1017 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1018 /* Enable flow control and length check */ 1019 rcntl |= 0x40000000 | 0x00000020; 1020 1021 /* RGMII, RMII or MII */ 1022 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII || 1023 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1024 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || 1025 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1026 rcntl |= (1 << 6); 1027 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1028 rcntl |= (1 << 8); 1029 else 1030 rcntl &= ~(1 << 8); 1031 1032 /* 1G, 100M or 10M */ 1033 if (ndev->phydev) { 1034 if (ndev->phydev->speed == SPEED_1000) 1035 ecntl |= (1 << 5); 1036 else if (ndev->phydev->speed == SPEED_100) 1037 rcntl &= ~(1 << 9); 1038 else 1039 rcntl |= (1 << 9); 1040 } 1041 } else { 1042#ifdef FEC_MIIGSK_ENR 1043 if (fep->quirks & FEC_QUIRK_USE_GASKET) { 1044 u32 cfgr; 1045 /* disable the gasket and wait */ 1046 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1047 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1048 udelay(1); 1049 1050 /* 1051 * configure the gasket: 1052 * RMII, 50 MHz, no loopback, no echo 1053 * MII, 25 MHz, no loopback, no echo 1054 */ 1055 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) 1056 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; 1057 if (ndev->phydev && ndev->phydev->speed == SPEED_10) 1058 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; 1059 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); 1060 1061 /* re-enable the gasket */ 1062 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1063 } 1064#endif 1065 } 1066 1067#if !defined(CONFIG_M5272) 1068 /* enable pause frame*/ 1069 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || 1070 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && 1071 ndev->phydev && ndev->phydev->pause)) { 1072 rcntl |= FEC_ENET_FCE; 1073 1074 /* set FIFO threshold parameter to reduce overrun */ 1075 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); 1076 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); 1077 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); 1078 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); 1079 1080 /* OPD */ 1081 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); 1082 } else { 1083 rcntl &= ~FEC_ENET_FCE; 1084 } 1085#endif /* !defined(CONFIG_M5272) */ 1086 1087 writel(rcntl, fep->hwp + FEC_R_CNTRL); 1088 1089 /* Setup multicast filter. */ 1090 set_multicast_list(ndev); 1091#ifndef CONFIG_M5272 1092 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1093 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1094#endif 1095 1096 if (fep->quirks & FEC_QUIRK_ENET_MAC) { 1097 /* enable ENET endian swap */ 1098 ecntl |= (1 << 8); 1099 /* enable ENET store and forward mode */ 1100 writel(1 << 8, fep->hwp + FEC_X_WMRK); 1101 } 1102 1103 if (fep->bufdesc_ex) 1104 ecntl |= (1 << 4); 1105 1106#ifndef CONFIG_M5272 1107 /* Enable the MIB statistic event counters */ 1108 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); 1109#endif 1110 1111 /* And last, enable the transmit and receive processing */ 1112 writel(ecntl, fep->hwp + FEC_ECNTRL); 1113 fec_enet_active_rxring(ndev); 1114 1115 if (fep->bufdesc_ex) 1116 fec_ptp_start_cyclecounter(ndev); 1117 1118 /* Enable interrupts we wish to service */ 1119 if (fep->link) 1120 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1121 else 1122 writel(0, fep->hwp + FEC_IMASK); 1123 1124 /* Init the interrupt coalescing */ 1125 fec_enet_itr_coal_init(ndev); 1126 1127} 1128 1129static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled) 1130{ 1131 struct fec_platform_data *pdata = fep->pdev->dev.platform_data; 1132 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr; 1133 1134 if (stop_gpr->gpr) { 1135 if (enabled) 1136 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1137 BIT(stop_gpr->bit), 1138 BIT(stop_gpr->bit)); 1139 else 1140 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg, 1141 BIT(stop_gpr->bit), 0); 1142 } else if (pdata && pdata->sleep_mode_enable) { 1143 pdata->sleep_mode_enable(enabled); 1144 } 1145} 1146 1147static void 1148fec_stop(struct net_device *ndev) 1149{ 1150 struct fec_enet_private *fep = netdev_priv(ndev); 1151 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); 1152 u32 val; 1153 1154 /* We cannot expect a graceful transmit stop without link !!! */ 1155 if (fep->link) { 1156 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1157 udelay(10); 1158 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1159 netdev_err(ndev, "Graceful transmit stop did not complete!\n"); 1160 } 1161 1162 /* Whack a reset. We should wait for this. 1163 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC 1164 * instead of reset MAC itself. 1165 */ 1166 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1167 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 1168 writel(0, fep->hwp + FEC_ECNTRL); 1169 } else { 1170 writel(1, fep->hwp + FEC_ECNTRL); 1171 udelay(10); 1172 } 1173 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1174 } else { 1175 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); 1176 val = readl(fep->hwp + FEC_ECNTRL); 1177 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 1178 writel(val, fep->hwp + FEC_ECNTRL); 1179 fec_enet_stop_mode(fep, true); 1180 } 1181 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1182 1183 /* We have to keep ENET enabled to have MII interrupt stay working */ 1184 if (fep->quirks & FEC_QUIRK_ENET_MAC && 1185 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { 1186 writel(2, fep->hwp + FEC_ECNTRL); 1187 writel(rmii_mode, fep->hwp + FEC_R_CNTRL); 1188 } 1189} 1190 1191 1192static void 1193fec_timeout(struct net_device *ndev, unsigned int txqueue) 1194{ 1195 struct fec_enet_private *fep = netdev_priv(ndev); 1196 1197 fec_dump(ndev); 1198 1199 ndev->stats.tx_errors++; 1200 1201 schedule_work(&fep->tx_timeout_work); 1202} 1203 1204static void fec_enet_timeout_work(struct work_struct *work) 1205{ 1206 struct fec_enet_private *fep = 1207 container_of(work, struct fec_enet_private, tx_timeout_work); 1208 struct net_device *ndev = fep->netdev; 1209 1210 rtnl_lock(); 1211 if (netif_device_present(ndev) || netif_running(ndev)) { 1212 napi_disable(&fep->napi); 1213 netif_tx_lock_bh(ndev); 1214 fec_restart(ndev); 1215 netif_tx_wake_all_queues(ndev); 1216 netif_tx_unlock_bh(ndev); 1217 napi_enable(&fep->napi); 1218 } 1219 rtnl_unlock(); 1220} 1221 1222static void 1223fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts, 1224 struct skb_shared_hwtstamps *hwtstamps) 1225{ 1226 unsigned long flags; 1227 u64 ns; 1228 1229 spin_lock_irqsave(&fep->tmreg_lock, flags); 1230 ns = timecounter_cyc2time(&fep->tc, ts); 1231 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 1232 1233 memset(hwtstamps, 0, sizeof(*hwtstamps)); 1234 hwtstamps->hwtstamp = ns_to_ktime(ns); 1235} 1236 1237static void 1238fec_enet_tx_queue(struct net_device *ndev, u16 queue_id) 1239{ 1240 struct fec_enet_private *fep; 1241 struct bufdesc *bdp; 1242 unsigned short status; 1243 struct sk_buff *skb; 1244 struct fec_enet_priv_tx_q *txq; 1245 struct netdev_queue *nq; 1246 int index = 0; 1247 int entries_free; 1248 1249 fep = netdev_priv(ndev); 1250 1251 txq = fep->tx_queue[queue_id]; 1252 /* get next bdp of dirty_tx */ 1253 nq = netdev_get_tx_queue(ndev, queue_id); 1254 bdp = txq->dirty_tx; 1255 1256 /* get next bdp of dirty_tx */ 1257 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1258 1259 while (bdp != READ_ONCE(txq->bd.cur)) { 1260 /* Order the load of bd.cur and cbd_sc */ 1261 rmb(); 1262 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc)); 1263 if (status & BD_ENET_TX_READY) 1264 break; 1265 1266 index = fec_enet_get_bd_index(bdp, &txq->bd); 1267 1268 skb = txq->tx_skbuff[index]; 1269 txq->tx_skbuff[index] = NULL; 1270 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr))) 1271 dma_unmap_single(&fep->pdev->dev, 1272 fec32_to_cpu(bdp->cbd_bufaddr), 1273 fec16_to_cpu(bdp->cbd_datlen), 1274 DMA_TO_DEVICE); 1275 bdp->cbd_bufaddr = cpu_to_fec32(0); 1276 if (!skb) 1277 goto skb_done; 1278 1279 /* Check for errors. */ 1280 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 1281 BD_ENET_TX_RL | BD_ENET_TX_UN | 1282 BD_ENET_TX_CSL)) { 1283 ndev->stats.tx_errors++; 1284 if (status & BD_ENET_TX_HB) /* No heartbeat */ 1285 ndev->stats.tx_heartbeat_errors++; 1286 if (status & BD_ENET_TX_LC) /* Late collision */ 1287 ndev->stats.tx_window_errors++; 1288 if (status & BD_ENET_TX_RL) /* Retrans limit */ 1289 ndev->stats.tx_aborted_errors++; 1290 if (status & BD_ENET_TX_UN) /* Underrun */ 1291 ndev->stats.tx_fifo_errors++; 1292 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 1293 ndev->stats.tx_carrier_errors++; 1294 } else { 1295 ndev->stats.tx_packets++; 1296 ndev->stats.tx_bytes += skb->len; 1297 } 1298 1299 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who 1300 * are to time stamp the packet, so we still need to check time 1301 * stamping enabled flag. 1302 */ 1303 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS && 1304 fep->hwts_tx_en) && 1305 fep->bufdesc_ex) { 1306 struct skb_shared_hwtstamps shhwtstamps; 1307 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1308 1309 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps); 1310 skb_tstamp_tx(skb, &shhwtstamps); 1311 } 1312 1313 /* Deferred means some collisions occurred during transmit, 1314 * but we eventually sent the packet OK. 1315 */ 1316 if (status & BD_ENET_TX_DEF) 1317 ndev->stats.collisions++; 1318 1319 /* Free the sk buffer associated with this last transmit */ 1320 dev_kfree_skb_any(skb); 1321skb_done: 1322 /* Make sure the update to bdp and tx_skbuff are performed 1323 * before dirty_tx 1324 */ 1325 wmb(); 1326 txq->dirty_tx = bdp; 1327 1328 /* Update pointer to next buffer descriptor to be transmitted */ 1329 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 1330 1331 /* Since we have freed up a buffer, the ring is no longer full 1332 */ 1333 if (netif_tx_queue_stopped(nq)) { 1334 entries_free = fec_enet_get_free_txdesc_num(txq); 1335 if (entries_free >= txq->tx_wake_threshold) 1336 netif_tx_wake_queue(nq); 1337 } 1338 } 1339 1340 /* ERR006358: Keep the transmitter going */ 1341 if (bdp != txq->bd.cur && 1342 readl(txq->bd.reg_desc_active) == 0) 1343 writel(0, txq->bd.reg_desc_active); 1344} 1345 1346static void fec_enet_tx(struct net_device *ndev) 1347{ 1348 struct fec_enet_private *fep = netdev_priv(ndev); 1349 int i; 1350 1351 /* Make sure that AVB queues are processed first. */ 1352 for (i = fep->num_tx_queues - 1; i >= 0; i--) 1353 fec_enet_tx_queue(ndev, i); 1354} 1355 1356static int 1357fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb) 1358{ 1359 struct fec_enet_private *fep = netdev_priv(ndev); 1360 int off; 1361 1362 off = ((unsigned long)skb->data) & fep->rx_align; 1363 if (off) 1364 skb_reserve(skb, fep->rx_align + 1 - off); 1365 1366 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE)); 1367 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) { 1368 if (net_ratelimit()) 1369 netdev_err(ndev, "Rx DMA memory map failed\n"); 1370 return -ENOMEM; 1371 } 1372 1373 return 0; 1374} 1375 1376static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb, 1377 struct bufdesc *bdp, u32 length, bool swap) 1378{ 1379 struct fec_enet_private *fep = netdev_priv(ndev); 1380 struct sk_buff *new_skb; 1381 1382 if (length > fep->rx_copybreak) 1383 return false; 1384 1385 new_skb = netdev_alloc_skb(ndev, length); 1386 if (!new_skb) 1387 return false; 1388 1389 dma_sync_single_for_cpu(&fep->pdev->dev, 1390 fec32_to_cpu(bdp->cbd_bufaddr), 1391 FEC_ENET_RX_FRSIZE - fep->rx_align, 1392 DMA_FROM_DEVICE); 1393 if (!swap) 1394 memcpy(new_skb->data, (*skb)->data, length); 1395 else 1396 swap_buffer2(new_skb->data, (*skb)->data, length); 1397 *skb = new_skb; 1398 1399 return true; 1400} 1401 1402/* During a receive, the bd_rx.cur points to the current incoming buffer. 1403 * When we update through the ring, if the next incoming buffer has 1404 * not been given to the system, we just set the empty indicator, 1405 * effectively tossing the packet. 1406 */ 1407static int 1408fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id) 1409{ 1410 struct fec_enet_private *fep = netdev_priv(ndev); 1411 struct fec_enet_priv_rx_q *rxq; 1412 struct bufdesc *bdp; 1413 unsigned short status; 1414 struct sk_buff *skb_new = NULL; 1415 struct sk_buff *skb; 1416 ushort pkt_len; 1417 __u8 *data; 1418 int pkt_received = 0; 1419 struct bufdesc_ex *ebdp = NULL; 1420 bool vlan_packet_rcvd = false; 1421 u16 vlan_tag; 1422 int index = 0; 1423 bool is_copybreak; 1424 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME; 1425 1426#ifdef CONFIG_M532x 1427 flush_cache_all(); 1428#endif 1429 rxq = fep->rx_queue[queue_id]; 1430 1431 /* First, grab all of the stats for the incoming packet. 1432 * These get messed up if we get called due to a busy condition. 1433 */ 1434 bdp = rxq->bd.cur; 1435 1436 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) { 1437 1438 if (pkt_received >= budget) 1439 break; 1440 pkt_received++; 1441 1442 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT); 1443 1444 /* Check for errors. */ 1445 status ^= BD_ENET_RX_LAST; 1446 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 1447 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST | 1448 BD_ENET_RX_CL)) { 1449 ndev->stats.rx_errors++; 1450 if (status & BD_ENET_RX_OV) { 1451 /* FIFO overrun */ 1452 ndev->stats.rx_fifo_errors++; 1453 goto rx_processing_done; 1454 } 1455 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH 1456 | BD_ENET_RX_LAST)) { 1457 /* Frame too long or too short. */ 1458 ndev->stats.rx_length_errors++; 1459 if (status & BD_ENET_RX_LAST) 1460 netdev_err(ndev, "rcv is not +last\n"); 1461 } 1462 if (status & BD_ENET_RX_CR) /* CRC Error */ 1463 ndev->stats.rx_crc_errors++; 1464 /* Report late collisions as a frame error. */ 1465 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL)) 1466 ndev->stats.rx_frame_errors++; 1467 goto rx_processing_done; 1468 } 1469 1470 /* Process the incoming frame. */ 1471 ndev->stats.rx_packets++; 1472 pkt_len = fec16_to_cpu(bdp->cbd_datlen); 1473 ndev->stats.rx_bytes += pkt_len; 1474 1475 index = fec_enet_get_bd_index(bdp, &rxq->bd); 1476 skb = rxq->rx_skbuff[index]; 1477 1478 /* The packet length includes FCS, but we don't want to 1479 * include that when passing upstream as it messes up 1480 * bridging applications. 1481 */ 1482 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4, 1483 need_swap); 1484 if (!is_copybreak) { 1485 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 1486 if (unlikely(!skb_new)) { 1487 ndev->stats.rx_dropped++; 1488 goto rx_processing_done; 1489 } 1490 dma_unmap_single(&fep->pdev->dev, 1491 fec32_to_cpu(bdp->cbd_bufaddr), 1492 FEC_ENET_RX_FRSIZE - fep->rx_align, 1493 DMA_FROM_DEVICE); 1494 } 1495 1496 prefetch(skb->data - NET_IP_ALIGN); 1497 skb_put(skb, pkt_len - 4); 1498 data = skb->data; 1499 1500 if (!is_copybreak && need_swap) 1501 swap_buffer(data, pkt_len); 1502 1503#if !defined(CONFIG_M5272) 1504 if (fep->quirks & FEC_QUIRK_HAS_RACC) 1505 data = skb_pull_inline(skb, 2); 1506#endif 1507 1508 /* Extract the enhanced buffer descriptor */ 1509 ebdp = NULL; 1510 if (fep->bufdesc_ex) 1511 ebdp = (struct bufdesc_ex *)bdp; 1512 1513 /* If this is a VLAN packet remove the VLAN Tag */ 1514 vlan_packet_rcvd = false; 1515 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1516 fep->bufdesc_ex && 1517 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) { 1518 /* Push and remove the vlan tag */ 1519 struct vlan_hdr *vlan_header = 1520 (struct vlan_hdr *) (data + ETH_HLEN); 1521 vlan_tag = ntohs(vlan_header->h_vlan_TCI); 1522 1523 vlan_packet_rcvd = true; 1524 1525 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2); 1526 skb_pull(skb, VLAN_HLEN); 1527 } 1528 1529 skb->protocol = eth_type_trans(skb, ndev); 1530 1531 /* Get receive timestamp from the skb */ 1532 if (fep->hwts_rx_en && fep->bufdesc_ex) 1533 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), 1534 skb_hwtstamps(skb)); 1535 1536 if (fep->bufdesc_ex && 1537 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { 1538 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) { 1539 /* don't check it */ 1540 skb->ip_summed = CHECKSUM_UNNECESSARY; 1541 } else { 1542 skb_checksum_none_assert(skb); 1543 } 1544 } 1545 1546 /* Handle received VLAN packets */ 1547 if (vlan_packet_rcvd) 1548 __vlan_hwaccel_put_tag(skb, 1549 htons(ETH_P_8021Q), 1550 vlan_tag); 1551 1552 skb_record_rx_queue(skb, queue_id); 1553 napi_gro_receive(&fep->napi, skb); 1554 1555 if (is_copybreak) { 1556 dma_sync_single_for_device(&fep->pdev->dev, 1557 fec32_to_cpu(bdp->cbd_bufaddr), 1558 FEC_ENET_RX_FRSIZE - fep->rx_align, 1559 DMA_FROM_DEVICE); 1560 } else { 1561 rxq->rx_skbuff[index] = skb_new; 1562 fec_enet_new_rxbdp(ndev, bdp, skb_new); 1563 } 1564 1565rx_processing_done: 1566 /* Clear the status flags for this buffer */ 1567 status &= ~BD_ENET_RX_STATS; 1568 1569 /* Mark the buffer empty */ 1570 status |= BD_ENET_RX_EMPTY; 1571 1572 if (fep->bufdesc_ex) { 1573 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 1574 1575 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 1576 ebdp->cbd_prot = 0; 1577 ebdp->cbd_bdu = 0; 1578 } 1579 /* Make sure the updates to rest of the descriptor are 1580 * performed before transferring ownership. 1581 */ 1582 wmb(); 1583 bdp->cbd_sc = cpu_to_fec16(status); 1584 1585 /* Update BD pointer to next entry */ 1586 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 1587 1588 /* Doing this here will keep the FEC running while we process 1589 * incoming frames. On a heavily loaded network, we should be 1590 * able to keep up at the expense of system resources. 1591 */ 1592 writel(0, rxq->bd.reg_desc_active); 1593 } 1594 rxq->bd.cur = bdp; 1595 return pkt_received; 1596} 1597 1598static int fec_enet_rx(struct net_device *ndev, int budget) 1599{ 1600 struct fec_enet_private *fep = netdev_priv(ndev); 1601 int i, done = 0; 1602 1603 /* Make sure that AVB queues are processed first. */ 1604 for (i = fep->num_rx_queues - 1; i >= 0; i--) 1605 done += fec_enet_rx_queue(ndev, budget - done, i); 1606 1607 return done; 1608} 1609 1610static bool fec_enet_collect_events(struct fec_enet_private *fep) 1611{ 1612 uint int_events; 1613 1614 int_events = readl(fep->hwp + FEC_IEVENT); 1615 1616 /* Don't clear MDIO events, we poll for those */ 1617 int_events &= ~FEC_ENET_MII; 1618 1619 writel(int_events, fep->hwp + FEC_IEVENT); 1620 1621 return int_events != 0; 1622} 1623 1624static irqreturn_t 1625fec_enet_interrupt(int irq, void *dev_id) 1626{ 1627 struct net_device *ndev = dev_id; 1628 struct fec_enet_private *fep = netdev_priv(ndev); 1629 irqreturn_t ret = IRQ_NONE; 1630 1631 if (fec_enet_collect_events(fep) && fep->link) { 1632 ret = IRQ_HANDLED; 1633 1634 if (napi_schedule_prep(&fep->napi)) { 1635 /* Disable interrupts */ 1636 writel(0, fep->hwp + FEC_IMASK); 1637 __napi_schedule(&fep->napi); 1638 } 1639 } 1640 1641 return ret; 1642} 1643 1644static int fec_enet_rx_napi(struct napi_struct *napi, int budget) 1645{ 1646 struct net_device *ndev = napi->dev; 1647 struct fec_enet_private *fep = netdev_priv(ndev); 1648 int done = 0; 1649 1650 do { 1651 done += fec_enet_rx(ndev, budget - done); 1652 fec_enet_tx(ndev); 1653 } while ((done < budget) && fec_enet_collect_events(fep)); 1654 1655 if (done < budget) { 1656 napi_complete_done(napi, done); 1657 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1658 } 1659 1660 return done; 1661} 1662 1663/* ------------------------------------------------------------------------- */ 1664static void fec_get_mac(struct net_device *ndev) 1665{ 1666 struct fec_enet_private *fep = netdev_priv(ndev); 1667 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); 1668 unsigned char *iap, tmpaddr[ETH_ALEN]; 1669 1670 /* 1671 * try to get mac address in following order: 1672 * 1673 * 1) module parameter via kernel command line in form 1674 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 1675 */ 1676 iap = macaddr; 1677 1678 /* 1679 * 2) from device tree data 1680 */ 1681 if (!is_valid_ether_addr(iap)) { 1682 struct device_node *np = fep->pdev->dev.of_node; 1683 if (np) { 1684 const char *mac = of_get_mac_address(np); 1685 if (!IS_ERR(mac)) 1686 iap = (unsigned char *) mac; 1687 } 1688 } 1689 1690 /* 1691 * 3) from flash or fuse (via platform data) 1692 */ 1693 if (!is_valid_ether_addr(iap)) { 1694#ifdef CONFIG_M5272 1695 if (FEC_FLASHMAC) 1696 iap = (unsigned char *)FEC_FLASHMAC; 1697#else 1698 if (pdata) 1699 iap = (unsigned char *)&pdata->mac; 1700#endif 1701 } 1702 1703 /* 1704 * 4) FEC mac registers set by bootloader 1705 */ 1706 if (!is_valid_ether_addr(iap)) { 1707 *((__be32 *) &tmpaddr[0]) = 1708 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); 1709 *((__be16 *) &tmpaddr[4]) = 1710 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 1711 iap = &tmpaddr[0]; 1712 } 1713 1714 /* 1715 * 5) random mac address 1716 */ 1717 if (!is_valid_ether_addr(iap)) { 1718 /* Report it and use a random ethernet address instead */ 1719 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap); 1720 eth_hw_addr_random(ndev); 1721 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n", 1722 ndev->dev_addr); 1723 return; 1724 } 1725 1726 memcpy(ndev->dev_addr, iap, ETH_ALEN); 1727 1728 /* Adjust MAC if using macaddr */ 1729 if (iap == macaddr) 1730 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; 1731} 1732 1733/* ------------------------------------------------------------------------- */ 1734 1735/* 1736 * Phy section 1737 */ 1738static void fec_enet_adjust_link(struct net_device *ndev) 1739{ 1740 struct fec_enet_private *fep = netdev_priv(ndev); 1741 struct phy_device *phy_dev = ndev->phydev; 1742 int status_change = 0; 1743 1744 /* 1745 * If the netdev is down, or is going down, we're not interested 1746 * in link state events, so just mark our idea of the link as down 1747 * and ignore the event. 1748 */ 1749 if (!netif_running(ndev) || !netif_device_present(ndev)) { 1750 fep->link = 0; 1751 } else if (phy_dev->link) { 1752 if (!fep->link) { 1753 fep->link = phy_dev->link; 1754 status_change = 1; 1755 } 1756 1757 if (fep->full_duplex != phy_dev->duplex) { 1758 fep->full_duplex = phy_dev->duplex; 1759 status_change = 1; 1760 } 1761 1762 if (phy_dev->speed != fep->speed) { 1763 fep->speed = phy_dev->speed; 1764 status_change = 1; 1765 } 1766 1767 /* if any of the above changed restart the FEC */ 1768 if (status_change) { 1769 netif_stop_queue(ndev); 1770 napi_disable(&fep->napi); 1771 netif_tx_lock_bh(ndev); 1772 fec_restart(ndev); 1773 netif_tx_wake_all_queues(ndev); 1774 netif_tx_unlock_bh(ndev); 1775 napi_enable(&fep->napi); 1776 } 1777 } else { 1778 if (fep->link) { 1779 netif_stop_queue(ndev); 1780 napi_disable(&fep->napi); 1781 netif_tx_lock_bh(ndev); 1782 fec_stop(ndev); 1783 netif_tx_unlock_bh(ndev); 1784 napi_enable(&fep->napi); 1785 fep->link = phy_dev->link; 1786 status_change = 1; 1787 } 1788 } 1789 1790 if (status_change) 1791 phy_print_status(phy_dev); 1792} 1793 1794static int fec_enet_mdio_wait(struct fec_enet_private *fep) 1795{ 1796 uint ievent; 1797 int ret; 1798 1799 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, 1800 ievent & FEC_ENET_MII, 2, 30000); 1801 1802 if (!ret) 1803 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 1804 1805 return ret; 1806} 1807 1808static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 1809{ 1810 struct fec_enet_private *fep = bus->priv; 1811 struct device *dev = &fep->pdev->dev; 1812 int ret = 0, frame_start, frame_addr, frame_op; 1813 bool is_c45 = !!(regnum & MII_ADDR_C45); 1814 1815 ret = pm_runtime_resume_and_get(dev); 1816 if (ret < 0) 1817 return ret; 1818 1819 if (is_c45) { 1820 frame_start = FEC_MMFR_ST_C45; 1821 1822 /* write address */ 1823 frame_addr = (regnum >> 16); 1824 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1825 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1826 FEC_MMFR_TA | (regnum & 0xFFFF), 1827 fep->hwp + FEC_MII_DATA); 1828 1829 /* wait for end of transfer */ 1830 ret = fec_enet_mdio_wait(fep); 1831 if (ret) { 1832 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1833 goto out; 1834 } 1835 1836 frame_op = FEC_MMFR_OP_READ_C45; 1837 1838 } else { 1839 /* C22 read */ 1840 frame_op = FEC_MMFR_OP_READ; 1841 frame_start = FEC_MMFR_ST; 1842 frame_addr = regnum; 1843 } 1844 1845 /* start a read op */ 1846 writel(frame_start | frame_op | 1847 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1848 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 1849 1850 /* wait for end of transfer */ 1851 ret = fec_enet_mdio_wait(fep); 1852 if (ret) { 1853 netdev_err(fep->netdev, "MDIO read timeout\n"); 1854 goto out; 1855 } 1856 1857 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 1858 1859out: 1860 pm_runtime_mark_last_busy(dev); 1861 pm_runtime_put_autosuspend(dev); 1862 1863 return ret; 1864} 1865 1866static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 1867 u16 value) 1868{ 1869 struct fec_enet_private *fep = bus->priv; 1870 struct device *dev = &fep->pdev->dev; 1871 int ret, frame_start, frame_addr; 1872 bool is_c45 = !!(regnum & MII_ADDR_C45); 1873 1874 ret = pm_runtime_resume_and_get(dev); 1875 if (ret < 0) 1876 return ret; 1877 1878 if (is_c45) { 1879 frame_start = FEC_MMFR_ST_C45; 1880 1881 /* write address */ 1882 frame_addr = (regnum >> 16); 1883 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | 1884 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1885 FEC_MMFR_TA | (regnum & 0xFFFF), 1886 fep->hwp + FEC_MII_DATA); 1887 1888 /* wait for end of transfer */ 1889 ret = fec_enet_mdio_wait(fep); 1890 if (ret) { 1891 netdev_err(fep->netdev, "MDIO address write timeout\n"); 1892 goto out; 1893 } 1894 } else { 1895 /* C22 write */ 1896 frame_start = FEC_MMFR_ST; 1897 frame_addr = regnum; 1898 } 1899 1900 /* start a write op */ 1901 writel(frame_start | FEC_MMFR_OP_WRITE | 1902 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | 1903 FEC_MMFR_TA | FEC_MMFR_DATA(value), 1904 fep->hwp + FEC_MII_DATA); 1905 1906 /* wait for end of transfer */ 1907 ret = fec_enet_mdio_wait(fep); 1908 if (ret) 1909 netdev_err(fep->netdev, "MDIO write timeout\n"); 1910 1911out: 1912 pm_runtime_mark_last_busy(dev); 1913 pm_runtime_put_autosuspend(dev); 1914 1915 return ret; 1916} 1917 1918static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev) 1919{ 1920 struct fec_enet_private *fep = netdev_priv(ndev); 1921 struct phy_device *phy_dev = ndev->phydev; 1922 1923 if (phy_dev) { 1924 phy_reset_after_clk_enable(phy_dev); 1925 } else if (fep->phy_node) { 1926 /* 1927 * If the PHY still is not bound to the MAC, but there is 1928 * OF PHY node and a matching PHY device instance already, 1929 * use the OF PHY node to obtain the PHY device instance, 1930 * and then use that PHY device instance when triggering 1931 * the PHY reset. 1932 */ 1933 phy_dev = of_phy_find_device(fep->phy_node); 1934 phy_reset_after_clk_enable(phy_dev); 1935 put_device(&phy_dev->mdio.dev); 1936 } 1937} 1938 1939static int fec_enet_clk_enable(struct net_device *ndev, bool enable) 1940{ 1941 struct fec_enet_private *fep = netdev_priv(ndev); 1942 int ret; 1943 1944 if (enable) { 1945 ret = clk_prepare_enable(fep->clk_enet_out); 1946 if (ret) 1947 return ret; 1948 1949 if (fep->clk_ptp) { 1950 mutex_lock(&fep->ptp_clk_mutex); 1951 ret = clk_prepare_enable(fep->clk_ptp); 1952 if (ret) { 1953 mutex_unlock(&fep->ptp_clk_mutex); 1954 goto failed_clk_ptp; 1955 } else { 1956 fep->ptp_clk_on = true; 1957 } 1958 mutex_unlock(&fep->ptp_clk_mutex); 1959 } 1960 1961 ret = clk_prepare_enable(fep->clk_ref); 1962 if (ret) 1963 goto failed_clk_ref; 1964 1965 fec_enet_phy_reset_after_clk_enable(ndev); 1966 } else { 1967 clk_disable_unprepare(fep->clk_enet_out); 1968 if (fep->clk_ptp) { 1969 mutex_lock(&fep->ptp_clk_mutex); 1970 clk_disable_unprepare(fep->clk_ptp); 1971 fep->ptp_clk_on = false; 1972 mutex_unlock(&fep->ptp_clk_mutex); 1973 } 1974 clk_disable_unprepare(fep->clk_ref); 1975 } 1976 1977 return 0; 1978 1979failed_clk_ref: 1980 if (fep->clk_ptp) { 1981 mutex_lock(&fep->ptp_clk_mutex); 1982 clk_disable_unprepare(fep->clk_ptp); 1983 fep->ptp_clk_on = false; 1984 mutex_unlock(&fep->ptp_clk_mutex); 1985 } 1986failed_clk_ptp: 1987 clk_disable_unprepare(fep->clk_enet_out); 1988 1989 return ret; 1990} 1991 1992static int fec_enet_mii_probe(struct net_device *ndev) 1993{ 1994 struct fec_enet_private *fep = netdev_priv(ndev); 1995 struct phy_device *phy_dev = NULL; 1996 char mdio_bus_id[MII_BUS_ID_SIZE]; 1997 char phy_name[MII_BUS_ID_SIZE + 3]; 1998 int phy_id; 1999 int dev_id = fep->dev_id; 2000 2001 if (fep->phy_node) { 2002 phy_dev = of_phy_connect(ndev, fep->phy_node, 2003 &fec_enet_adjust_link, 0, 2004 fep->phy_interface); 2005 if (!phy_dev) { 2006 netdev_err(ndev, "Unable to connect to phy\n"); 2007 return -ENODEV; 2008 } 2009 } else { 2010 /* check for attached phy */ 2011 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 2012 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id)) 2013 continue; 2014 if (dev_id--) 2015 continue; 2016 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 2017 break; 2018 } 2019 2020 if (phy_id >= PHY_MAX_ADDR) { 2021 netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); 2022 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); 2023 phy_id = 0; 2024 } 2025 2026 snprintf(phy_name, sizeof(phy_name), 2027 PHY_ID_FMT, mdio_bus_id, phy_id); 2028 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 2029 fep->phy_interface); 2030 } 2031 2032 if (IS_ERR(phy_dev)) { 2033 netdev_err(ndev, "could not attach to PHY\n"); 2034 return PTR_ERR(phy_dev); 2035 } 2036 2037 /* mask with MAC supported features */ 2038 if (fep->quirks & FEC_QUIRK_HAS_GBIT) { 2039 phy_set_max_speed(phy_dev, 1000); 2040 phy_remove_link_mode(phy_dev, 2041 ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 2042#if !defined(CONFIG_M5272) 2043 phy_support_sym_pause(phy_dev); 2044#endif 2045 } 2046 else 2047 phy_set_max_speed(phy_dev, 100); 2048 2049 fep->link = 0; 2050 fep->full_duplex = 0; 2051 2052 phy_attached_info(phy_dev); 2053 2054 return 0; 2055} 2056 2057static int fec_enet_mii_init(struct platform_device *pdev) 2058{ 2059 static struct mii_bus *fec0_mii_bus; 2060 struct net_device *ndev = platform_get_drvdata(pdev); 2061 struct fec_enet_private *fep = netdev_priv(ndev); 2062 bool suppress_preamble = false; 2063 struct device_node *node; 2064 int err = -ENXIO; 2065 u32 mii_speed, holdtime; 2066 u32 bus_freq; 2067 2068 /* 2069 * The i.MX28 dual fec interfaces are not equal. 2070 * Here are the differences: 2071 * 2072 * - fec0 supports MII & RMII modes while fec1 only supports RMII 2073 * - fec0 acts as the 1588 time master while fec1 is slave 2074 * - external phys can only be configured by fec0 2075 * 2076 * That is to say fec1 can not work independently. It only works 2077 * when fec0 is working. The reason behind this design is that the 2078 * second interface is added primarily for Switch mode. 2079 * 2080 * Because of the last point above, both phys are attached on fec0 2081 * mdio interface in board design, and need to be configured by 2082 * fec0 mii_bus. 2083 */ 2084 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) { 2085 /* fec1 uses fec0 mii_bus */ 2086 if (mii_cnt && fec0_mii_bus) { 2087 fep->mii_bus = fec0_mii_bus; 2088 mii_cnt++; 2089 return 0; 2090 } 2091 return -ENOENT; 2092 } 2093 2094 bus_freq = 2500000; /* 2.5MHz by default */ 2095 node = of_get_child_by_name(pdev->dev.of_node, "mdio"); 2096 if (node) { 2097 of_property_read_u32(node, "clock-frequency", &bus_freq); 2098 suppress_preamble = of_property_read_bool(node, 2099 "suppress-preamble"); 2100 } 2101 2102 /* 2103 * Set MII speed (= clk_get_rate() / 2 * phy_speed) 2104 * 2105 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while 2106 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 2107 * Reference Manual has an error on this, and gets fixed on i.MX6Q 2108 * document. 2109 */ 2110 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2); 2111 if (fep->quirks & FEC_QUIRK_ENET_MAC) 2112 mii_speed--; 2113 if (mii_speed > 63) { 2114 dev_err(&pdev->dev, 2115 "fec clock (%lu) too fast to get right mii speed\n", 2116 clk_get_rate(fep->clk_ipg)); 2117 err = -EINVAL; 2118 goto err_out; 2119 } 2120 2121 /* 2122 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka 2123 * MII_SPEED) register that defines the MDIO output hold time. Earlier 2124 * versions are RAZ there, so just ignore the difference and write the 2125 * register always. 2126 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. 2127 * HOLDTIME + 1 is the number of clk cycles the fec is holding the 2128 * output. 2129 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). 2130 * Given that ceil(clkrate / 5000000) <= 64, the calculation for 2131 * holdtime cannot result in a value greater than 3. 2132 */ 2133 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1; 2134 2135 fep->phy_speed = mii_speed << 1 | holdtime << 8; 2136 2137 if (suppress_preamble) 2138 fep->phy_speed |= BIT(7); 2139 2140 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) { 2141 /* Clear MMFR to avoid to generate MII event by writing MSCR. 2142 * MII event generation condition: 2143 * - writing MSCR: 2144 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & 2145 * mscr_reg_data_in[7:0] != 0 2146 * - writing MMFR: 2147 * - mscr[7:0]_not_zero 2148 */ 2149 writel(0, fep->hwp + FEC_MII_DATA); 2150 } 2151 2152 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 2153 2154 /* Clear any pending transaction complete indication */ 2155 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); 2156 2157 fep->mii_bus = mdiobus_alloc(); 2158 if (fep->mii_bus == NULL) { 2159 err = -ENOMEM; 2160 goto err_out; 2161 } 2162 2163 fep->mii_bus->name = "fec_enet_mii_bus"; 2164 fep->mii_bus->read = fec_enet_mdio_read; 2165 fep->mii_bus->write = fec_enet_mdio_write; 2166 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2167 pdev->name, fep->dev_id + 1); 2168 fep->mii_bus->priv = fep; 2169 fep->mii_bus->parent = &pdev->dev; 2170 2171 err = of_mdiobus_register(fep->mii_bus, node); 2172 if (err) 2173 goto err_out_free_mdiobus; 2174 of_node_put(node); 2175 2176 mii_cnt++; 2177 2178 /* save fec0 mii_bus */ 2179 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO) 2180 fec0_mii_bus = fep->mii_bus; 2181 2182 return 0; 2183 2184err_out_free_mdiobus: 2185 mdiobus_free(fep->mii_bus); 2186err_out: 2187 of_node_put(node); 2188 return err; 2189} 2190 2191static void fec_enet_mii_remove(struct fec_enet_private *fep) 2192{ 2193 if (--mii_cnt == 0) { 2194 mdiobus_unregister(fep->mii_bus); 2195 mdiobus_free(fep->mii_bus); 2196 } 2197} 2198 2199static void fec_enet_get_drvinfo(struct net_device *ndev, 2200 struct ethtool_drvinfo *info) 2201{ 2202 struct fec_enet_private *fep = netdev_priv(ndev); 2203 2204 strlcpy(info->driver, fep->pdev->dev.driver->name, 2205 sizeof(info->driver)); 2206 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); 2207} 2208 2209static int fec_enet_get_regs_len(struct net_device *ndev) 2210{ 2211 struct fec_enet_private *fep = netdev_priv(ndev); 2212 struct resource *r; 2213 int s = 0; 2214 2215 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0); 2216 if (r) 2217 s = resource_size(r); 2218 2219 return s; 2220} 2221 2222/* List of registers that can be safety be read to dump them with ethtool */ 2223#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2224 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2225 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2226static __u32 fec_enet_register_version = 2; 2227static u32 fec_enet_register_offset[] = { 2228 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2229 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2230 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1, 2231 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH, 2232 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, 2233 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1, 2234 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2, 2235 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0, 2236 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2237 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2, 2238 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1, 2239 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME, 2240 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2241 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2242 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2243 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2244 RMON_T_P_GTE2048, RMON_T_OCTETS, 2245 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2246 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2247 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2248 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2249 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2250 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2251 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2252 RMON_R_P_GTE2048, RMON_R_OCTETS, 2253 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2254 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2255}; 2256/* for i.MX6ul */ 2257static u32 fec_enet_register_offset_6ul[] = { 2258 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0, 2259 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL, 2260 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0, 2261 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, 2262 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0, 2263 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM, 2264 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, 2265 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT, 2266 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG, 2267 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255, 2268 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047, 2269 RMON_T_P_GTE2048, RMON_T_OCTETS, 2270 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF, 2271 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE, 2272 IEEE_T_FDXFC, IEEE_T_OCTETS_OK, 2273 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN, 2274 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB, 2275 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255, 2276 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047, 2277 RMON_R_P_GTE2048, RMON_R_OCTETS, 2278 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR, 2279 IEEE_R_FDXFC, IEEE_R_OCTETS_OK 2280}; 2281#else 2282static __u32 fec_enet_register_version = 1; 2283static u32 fec_enet_register_offset[] = { 2284 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0, 2285 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0, 2286 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED, 2287 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL, 2288 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, 2289 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0, 2290 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0, 2291 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0, 2292 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2 2293}; 2294#endif 2295 2296static void fec_enet_get_regs(struct net_device *ndev, 2297 struct ethtool_regs *regs, void *regbuf) 2298{ 2299 struct fec_enet_private *fep = netdev_priv(ndev); 2300 u32 __iomem *theregs = (u32 __iomem *)fep->hwp; 2301 struct device *dev = &fep->pdev->dev; 2302 u32 *buf = (u32 *)regbuf; 2303 u32 i, off; 2304 int ret; 2305#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 2306 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 2307 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 2308 u32 *reg_list; 2309 u32 reg_cnt; 2310 2311 if (!of_machine_is_compatible("fsl,imx6ul")) { 2312 reg_list = fec_enet_register_offset; 2313 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2314 } else { 2315 reg_list = fec_enet_register_offset_6ul; 2316 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul); 2317 } 2318#else 2319 /* coldfire */ 2320 static u32 *reg_list = fec_enet_register_offset; 2321 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset); 2322#endif 2323 ret = pm_runtime_resume_and_get(dev); 2324 if (ret < 0) 2325 return; 2326 2327 regs->version = fec_enet_register_version; 2328 2329 memset(buf, 0, regs->len); 2330 2331 for (i = 0; i < reg_cnt; i++) { 2332 off = reg_list[i]; 2333 2334 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2335 !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2336 continue; 2337 2338 off >>= 2; 2339 buf[off] = readl(&theregs[off]); 2340 } 2341 2342 pm_runtime_mark_last_busy(dev); 2343 pm_runtime_put_autosuspend(dev); 2344} 2345 2346static int fec_enet_get_ts_info(struct net_device *ndev, 2347 struct ethtool_ts_info *info) 2348{ 2349 struct fec_enet_private *fep = netdev_priv(ndev); 2350 2351 if (fep->bufdesc_ex) { 2352 2353 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 2354 SOF_TIMESTAMPING_RX_SOFTWARE | 2355 SOF_TIMESTAMPING_SOFTWARE | 2356 SOF_TIMESTAMPING_TX_HARDWARE | 2357 SOF_TIMESTAMPING_RX_HARDWARE | 2358 SOF_TIMESTAMPING_RAW_HARDWARE; 2359 if (fep->ptp_clock) 2360 info->phc_index = ptp_clock_index(fep->ptp_clock); 2361 else 2362 info->phc_index = -1; 2363 2364 info->tx_types = (1 << HWTSTAMP_TX_OFF) | 2365 (1 << HWTSTAMP_TX_ON); 2366 2367 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 2368 (1 << HWTSTAMP_FILTER_ALL); 2369 return 0; 2370 } else { 2371 return ethtool_op_get_ts_info(ndev, info); 2372 } 2373} 2374 2375#if !defined(CONFIG_M5272) 2376 2377static void fec_enet_get_pauseparam(struct net_device *ndev, 2378 struct ethtool_pauseparam *pause) 2379{ 2380 struct fec_enet_private *fep = netdev_priv(ndev); 2381 2382 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; 2383 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; 2384 pause->rx_pause = pause->tx_pause; 2385} 2386 2387static int fec_enet_set_pauseparam(struct net_device *ndev, 2388 struct ethtool_pauseparam *pause) 2389{ 2390 struct fec_enet_private *fep = netdev_priv(ndev); 2391 2392 if (!ndev->phydev) 2393 return -ENODEV; 2394 2395 if (pause->tx_pause != pause->rx_pause) { 2396 netdev_info(ndev, 2397 "hardware only support enable/disable both tx and rx"); 2398 return -EINVAL; 2399 } 2400 2401 fep->pause_flag = 0; 2402 2403 /* tx pause must be same as rx pause */ 2404 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; 2405 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; 2406 2407 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause, 2408 pause->autoneg); 2409 2410 if (pause->autoneg) { 2411 if (netif_running(ndev)) 2412 fec_stop(ndev); 2413 phy_start_aneg(ndev->phydev); 2414 } 2415 if (netif_running(ndev)) { 2416 napi_disable(&fep->napi); 2417 netif_tx_lock_bh(ndev); 2418 fec_restart(ndev); 2419 netif_tx_wake_all_queues(ndev); 2420 netif_tx_unlock_bh(ndev); 2421 napi_enable(&fep->napi); 2422 } 2423 2424 return 0; 2425} 2426 2427static const struct fec_stat { 2428 char name[ETH_GSTRING_LEN]; 2429 u16 offset; 2430} fec_stats[] = { 2431 /* RMON TX */ 2432 { "tx_dropped", RMON_T_DROP }, 2433 { "tx_packets", RMON_T_PACKETS }, 2434 { "tx_broadcast", RMON_T_BC_PKT }, 2435 { "tx_multicast", RMON_T_MC_PKT }, 2436 { "tx_crc_errors", RMON_T_CRC_ALIGN }, 2437 { "tx_undersize", RMON_T_UNDERSIZE }, 2438 { "tx_oversize", RMON_T_OVERSIZE }, 2439 { "tx_fragment", RMON_T_FRAG }, 2440 { "tx_jabber", RMON_T_JAB }, 2441 { "tx_collision", RMON_T_COL }, 2442 { "tx_64byte", RMON_T_P64 }, 2443 { "tx_65to127byte", RMON_T_P65TO127 }, 2444 { "tx_128to255byte", RMON_T_P128TO255 }, 2445 { "tx_256to511byte", RMON_T_P256TO511 }, 2446 { "tx_512to1023byte", RMON_T_P512TO1023 }, 2447 { "tx_1024to2047byte", RMON_T_P1024TO2047 }, 2448 { "tx_GTE2048byte", RMON_T_P_GTE2048 }, 2449 { "tx_octets", RMON_T_OCTETS }, 2450 2451 /* IEEE TX */ 2452 { "IEEE_tx_drop", IEEE_T_DROP }, 2453 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, 2454 { "IEEE_tx_1col", IEEE_T_1COL }, 2455 { "IEEE_tx_mcol", IEEE_T_MCOL }, 2456 { "IEEE_tx_def", IEEE_T_DEF }, 2457 { "IEEE_tx_lcol", IEEE_T_LCOL }, 2458 { "IEEE_tx_excol", IEEE_T_EXCOL }, 2459 { "IEEE_tx_macerr", IEEE_T_MACERR }, 2460 { "IEEE_tx_cserr", IEEE_T_CSERR }, 2461 { "IEEE_tx_sqe", IEEE_T_SQE }, 2462 { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, 2463 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, 2464 2465 /* RMON RX */ 2466 { "rx_packets", RMON_R_PACKETS }, 2467 { "rx_broadcast", RMON_R_BC_PKT }, 2468 { "rx_multicast", RMON_R_MC_PKT }, 2469 { "rx_crc_errors", RMON_R_CRC_ALIGN }, 2470 { "rx_undersize", RMON_R_UNDERSIZE }, 2471 { "rx_oversize", RMON_R_OVERSIZE }, 2472 { "rx_fragment", RMON_R_FRAG }, 2473 { "rx_jabber", RMON_R_JAB }, 2474 { "rx_64byte", RMON_R_P64 }, 2475 { "rx_65to127byte", RMON_R_P65TO127 }, 2476 { "rx_128to255byte", RMON_R_P128TO255 }, 2477 { "rx_256to511byte", RMON_R_P256TO511 }, 2478 { "rx_512to1023byte", RMON_R_P512TO1023 }, 2479 { "rx_1024to2047byte", RMON_R_P1024TO2047 }, 2480 { "rx_GTE2048byte", RMON_R_P_GTE2048 }, 2481 { "rx_octets", RMON_R_OCTETS }, 2482 2483 /* IEEE RX */ 2484 { "IEEE_rx_drop", IEEE_R_DROP }, 2485 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, 2486 { "IEEE_rx_crc", IEEE_R_CRC }, 2487 { "IEEE_rx_align", IEEE_R_ALIGN }, 2488 { "IEEE_rx_macerr", IEEE_R_MACERR }, 2489 { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, 2490 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, 2491}; 2492 2493#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64)) 2494 2495static void fec_enet_update_ethtool_stats(struct net_device *dev) 2496{ 2497 struct fec_enet_private *fep = netdev_priv(dev); 2498 int i; 2499 2500 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2501 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset); 2502} 2503 2504static void fec_enet_get_ethtool_stats(struct net_device *dev, 2505 struct ethtool_stats *stats, u64 *data) 2506{ 2507 struct fec_enet_private *fep = netdev_priv(dev); 2508 2509 if (netif_running(dev)) 2510 fec_enet_update_ethtool_stats(dev); 2511 2512 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE); 2513} 2514 2515static void fec_enet_get_strings(struct net_device *netdev, 2516 u32 stringset, u8 *data) 2517{ 2518 int i; 2519 switch (stringset) { 2520 case ETH_SS_STATS: 2521 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2522 memcpy(data + i * ETH_GSTRING_LEN, 2523 fec_stats[i].name, ETH_GSTRING_LEN); 2524 break; 2525 } 2526} 2527 2528static int fec_enet_get_sset_count(struct net_device *dev, int sset) 2529{ 2530 switch (sset) { 2531 case ETH_SS_STATS: 2532 return ARRAY_SIZE(fec_stats); 2533 default: 2534 return -EOPNOTSUPP; 2535 } 2536} 2537 2538static void fec_enet_clear_ethtool_stats(struct net_device *dev) 2539{ 2540 struct fec_enet_private *fep = netdev_priv(dev); 2541 int i; 2542 2543 /* Disable MIB statistics counters */ 2544 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); 2545 2546 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) 2547 writel(0, fep->hwp + fec_stats[i].offset); 2548 2549 /* Don't disable MIB statistics counters */ 2550 writel(0, fep->hwp + FEC_MIB_CTRLSTAT); 2551} 2552 2553#else /* !defined(CONFIG_M5272) */ 2554#define FEC_STATS_SIZE 0 2555static inline void fec_enet_update_ethtool_stats(struct net_device *dev) 2556{ 2557} 2558 2559static inline void fec_enet_clear_ethtool_stats(struct net_device *dev) 2560{ 2561} 2562#endif /* !defined(CONFIG_M5272) */ 2563 2564/* ITR clock source is enet system clock (clk_ahb). 2565 * TCTT unit is cycle_ns * 64 cycle 2566 * So, the ICTT value = X us / (cycle_ns * 64) 2567 */ 2568static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us) 2569{ 2570 struct fec_enet_private *fep = netdev_priv(ndev); 2571 2572 return us * (fep->itr_clk_rate / 64000) / 1000; 2573} 2574 2575/* Set threshold for interrupt coalescing */ 2576static void fec_enet_itr_coal_set(struct net_device *ndev) 2577{ 2578 struct fec_enet_private *fep = netdev_priv(ndev); 2579 int rx_itr, tx_itr; 2580 2581 /* Must be greater than zero to avoid unpredictable behavior */ 2582 if (!fep->rx_time_itr || !fep->rx_pkts_itr || 2583 !fep->tx_time_itr || !fep->tx_pkts_itr) 2584 return; 2585 2586 /* Select enet system clock as Interrupt Coalescing 2587 * timer Clock Source 2588 */ 2589 rx_itr = FEC_ITR_CLK_SEL; 2590 tx_itr = FEC_ITR_CLK_SEL; 2591 2592 /* set ICFT and ICTT */ 2593 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr); 2594 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr)); 2595 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr); 2596 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr)); 2597 2598 rx_itr |= FEC_ITR_EN; 2599 tx_itr |= FEC_ITR_EN; 2600 2601 writel(tx_itr, fep->hwp + FEC_TXIC0); 2602 writel(rx_itr, fep->hwp + FEC_RXIC0); 2603 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 2604 writel(tx_itr, fep->hwp + FEC_TXIC1); 2605 writel(rx_itr, fep->hwp + FEC_RXIC1); 2606 writel(tx_itr, fep->hwp + FEC_TXIC2); 2607 writel(rx_itr, fep->hwp + FEC_RXIC2); 2608 } 2609} 2610 2611static int 2612fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2613{ 2614 struct fec_enet_private *fep = netdev_priv(ndev); 2615 2616 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2617 return -EOPNOTSUPP; 2618 2619 ec->rx_coalesce_usecs = fep->rx_time_itr; 2620 ec->rx_max_coalesced_frames = fep->rx_pkts_itr; 2621 2622 ec->tx_coalesce_usecs = fep->tx_time_itr; 2623 ec->tx_max_coalesced_frames = fep->tx_pkts_itr; 2624 2625 return 0; 2626} 2627 2628static int 2629fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec) 2630{ 2631 struct fec_enet_private *fep = netdev_priv(ndev); 2632 struct device *dev = &fep->pdev->dev; 2633 unsigned int cycle; 2634 2635 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE)) 2636 return -EOPNOTSUPP; 2637 2638 if (ec->rx_max_coalesced_frames > 255) { 2639 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n"); 2640 return -EINVAL; 2641 } 2642 2643 if (ec->tx_max_coalesced_frames > 255) { 2644 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n"); 2645 return -EINVAL; 2646 } 2647 2648 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs); 2649 if (cycle > 0xFFFF) { 2650 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n"); 2651 return -EINVAL; 2652 } 2653 2654 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs); 2655 if (cycle > 0xFFFF) { 2656 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n"); 2657 return -EINVAL; 2658 } 2659 2660 fep->rx_time_itr = ec->rx_coalesce_usecs; 2661 fep->rx_pkts_itr = ec->rx_max_coalesced_frames; 2662 2663 fep->tx_time_itr = ec->tx_coalesce_usecs; 2664 fep->tx_pkts_itr = ec->tx_max_coalesced_frames; 2665 2666 fec_enet_itr_coal_set(ndev); 2667 2668 return 0; 2669} 2670 2671static void fec_enet_itr_coal_init(struct net_device *ndev) 2672{ 2673 struct ethtool_coalesce ec; 2674 2675 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2676 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2677 2678 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT; 2679 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT; 2680 2681 fec_enet_set_coalesce(ndev, &ec); 2682} 2683 2684static int fec_enet_get_tunable(struct net_device *netdev, 2685 const struct ethtool_tunable *tuna, 2686 void *data) 2687{ 2688 struct fec_enet_private *fep = netdev_priv(netdev); 2689 int ret = 0; 2690 2691 switch (tuna->id) { 2692 case ETHTOOL_RX_COPYBREAK: 2693 *(u32 *)data = fep->rx_copybreak; 2694 break; 2695 default: 2696 ret = -EINVAL; 2697 break; 2698 } 2699 2700 return ret; 2701} 2702 2703static int fec_enet_set_tunable(struct net_device *netdev, 2704 const struct ethtool_tunable *tuna, 2705 const void *data) 2706{ 2707 struct fec_enet_private *fep = netdev_priv(netdev); 2708 int ret = 0; 2709 2710 switch (tuna->id) { 2711 case ETHTOOL_RX_COPYBREAK: 2712 fep->rx_copybreak = *(u32 *)data; 2713 break; 2714 default: 2715 ret = -EINVAL; 2716 break; 2717 } 2718 2719 return ret; 2720} 2721 2722static void 2723fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2724{ 2725 struct fec_enet_private *fep = netdev_priv(ndev); 2726 2727 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) { 2728 wol->supported = WAKE_MAGIC; 2729 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0; 2730 } else { 2731 wol->supported = wol->wolopts = 0; 2732 } 2733} 2734 2735static int 2736fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2737{ 2738 struct fec_enet_private *fep = netdev_priv(ndev); 2739 2740 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET)) 2741 return -EINVAL; 2742 2743 if (wol->wolopts & ~WAKE_MAGIC) 2744 return -EINVAL; 2745 2746 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); 2747 if (device_may_wakeup(&ndev->dev)) { 2748 fep->wol_flag |= FEC_WOL_FLAG_ENABLE; 2749 if (fep->irq[0] > 0) 2750 enable_irq_wake(fep->irq[0]); 2751 } else { 2752 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE); 2753 if (fep->irq[0] > 0) 2754 disable_irq_wake(fep->irq[0]); 2755 } 2756 2757 return 0; 2758} 2759 2760static const struct ethtool_ops fec_enet_ethtool_ops = { 2761 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2762 ETHTOOL_COALESCE_MAX_FRAMES, 2763 .get_drvinfo = fec_enet_get_drvinfo, 2764 .get_regs_len = fec_enet_get_regs_len, 2765 .get_regs = fec_enet_get_regs, 2766 .nway_reset = phy_ethtool_nway_reset, 2767 .get_link = ethtool_op_get_link, 2768 .get_coalesce = fec_enet_get_coalesce, 2769 .set_coalesce = fec_enet_set_coalesce, 2770#ifndef CONFIG_M5272 2771 .get_pauseparam = fec_enet_get_pauseparam, 2772 .set_pauseparam = fec_enet_set_pauseparam, 2773 .get_strings = fec_enet_get_strings, 2774 .get_ethtool_stats = fec_enet_get_ethtool_stats, 2775 .get_sset_count = fec_enet_get_sset_count, 2776#endif 2777 .get_ts_info = fec_enet_get_ts_info, 2778 .get_tunable = fec_enet_get_tunable, 2779 .set_tunable = fec_enet_set_tunable, 2780 .get_wol = fec_enet_get_wol, 2781 .set_wol = fec_enet_set_wol, 2782 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2783 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2784}; 2785 2786static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2787{ 2788 struct fec_enet_private *fep = netdev_priv(ndev); 2789 struct phy_device *phydev = ndev->phydev; 2790 2791 if (!netif_running(ndev)) 2792 return -EINVAL; 2793 2794 if (!phydev) 2795 return -ENODEV; 2796 2797 if (fep->bufdesc_ex) { 2798 bool use_fec_hwts = !phy_has_hwtstamp(phydev); 2799 2800 if (cmd == SIOCSHWTSTAMP) { 2801 if (use_fec_hwts) 2802 return fec_ptp_set(ndev, rq); 2803 fec_ptp_disable_hwts(ndev); 2804 } else if (cmd == SIOCGHWTSTAMP) { 2805 if (use_fec_hwts) 2806 return fec_ptp_get(ndev, rq); 2807 } 2808 } 2809 2810 return phy_mii_ioctl(phydev, rq, cmd); 2811} 2812 2813static void fec_enet_free_buffers(struct net_device *ndev) 2814{ 2815 struct fec_enet_private *fep = netdev_priv(ndev); 2816 unsigned int i; 2817 struct sk_buff *skb; 2818 struct bufdesc *bdp; 2819 struct fec_enet_priv_tx_q *txq; 2820 struct fec_enet_priv_rx_q *rxq; 2821 unsigned int q; 2822 2823 for (q = 0; q < fep->num_rx_queues; q++) { 2824 rxq = fep->rx_queue[q]; 2825 bdp = rxq->bd.base; 2826 for (i = 0; i < rxq->bd.ring_size; i++) { 2827 skb = rxq->rx_skbuff[i]; 2828 rxq->rx_skbuff[i] = NULL; 2829 if (skb) { 2830 dma_unmap_single(&fep->pdev->dev, 2831 fec32_to_cpu(bdp->cbd_bufaddr), 2832 FEC_ENET_RX_FRSIZE - fep->rx_align, 2833 DMA_FROM_DEVICE); 2834 dev_kfree_skb(skb); 2835 } 2836 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2837 } 2838 } 2839 2840 for (q = 0; q < fep->num_tx_queues; q++) { 2841 txq = fep->tx_queue[q]; 2842 for (i = 0; i < txq->bd.ring_size; i++) { 2843 kfree(txq->tx_bounce[i]); 2844 txq->tx_bounce[i] = NULL; 2845 skb = txq->tx_skbuff[i]; 2846 txq->tx_skbuff[i] = NULL; 2847 dev_kfree_skb(skb); 2848 } 2849 } 2850} 2851 2852static void fec_enet_free_queue(struct net_device *ndev) 2853{ 2854 struct fec_enet_private *fep = netdev_priv(ndev); 2855 int i; 2856 struct fec_enet_priv_tx_q *txq; 2857 2858 for (i = 0; i < fep->num_tx_queues; i++) 2859 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) { 2860 txq = fep->tx_queue[i]; 2861 dma_free_coherent(&fep->pdev->dev, 2862 txq->bd.ring_size * TSO_HEADER_SIZE, 2863 txq->tso_hdrs, 2864 txq->tso_hdrs_dma); 2865 } 2866 2867 for (i = 0; i < fep->num_rx_queues; i++) 2868 kfree(fep->rx_queue[i]); 2869 for (i = 0; i < fep->num_tx_queues; i++) 2870 kfree(fep->tx_queue[i]); 2871} 2872 2873static int fec_enet_alloc_queue(struct net_device *ndev) 2874{ 2875 struct fec_enet_private *fep = netdev_priv(ndev); 2876 int i; 2877 int ret = 0; 2878 struct fec_enet_priv_tx_q *txq; 2879 2880 for (i = 0; i < fep->num_tx_queues; i++) { 2881 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 2882 if (!txq) { 2883 ret = -ENOMEM; 2884 goto alloc_failed; 2885 } 2886 2887 fep->tx_queue[i] = txq; 2888 txq->bd.ring_size = TX_RING_SIZE; 2889 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size; 2890 2891 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS; 2892 txq->tx_wake_threshold = 2893 (txq->bd.ring_size - txq->tx_stop_threshold) / 2; 2894 2895 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev, 2896 txq->bd.ring_size * TSO_HEADER_SIZE, 2897 &txq->tso_hdrs_dma, 2898 GFP_KERNEL); 2899 if (!txq->tso_hdrs) { 2900 ret = -ENOMEM; 2901 goto alloc_failed; 2902 } 2903 } 2904 2905 for (i = 0; i < fep->num_rx_queues; i++) { 2906 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]), 2907 GFP_KERNEL); 2908 if (!fep->rx_queue[i]) { 2909 ret = -ENOMEM; 2910 goto alloc_failed; 2911 } 2912 2913 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE; 2914 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size; 2915 } 2916 return ret; 2917 2918alloc_failed: 2919 fec_enet_free_queue(ndev); 2920 return ret; 2921} 2922 2923static int 2924fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue) 2925{ 2926 struct fec_enet_private *fep = netdev_priv(ndev); 2927 unsigned int i; 2928 struct sk_buff *skb; 2929 struct bufdesc *bdp; 2930 struct fec_enet_priv_rx_q *rxq; 2931 2932 rxq = fep->rx_queue[queue]; 2933 bdp = rxq->bd.base; 2934 for (i = 0; i < rxq->bd.ring_size; i++) { 2935 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); 2936 if (!skb) 2937 goto err_alloc; 2938 2939 if (fec_enet_new_rxbdp(ndev, bdp, skb)) { 2940 dev_kfree_skb(skb); 2941 goto err_alloc; 2942 } 2943 2944 rxq->rx_skbuff[i] = skb; 2945 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY); 2946 2947 if (fep->bufdesc_ex) { 2948 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2949 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT); 2950 } 2951 2952 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd); 2953 } 2954 2955 /* Set the last buffer to wrap. */ 2956 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd); 2957 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2958 return 0; 2959 2960 err_alloc: 2961 fec_enet_free_buffers(ndev); 2962 return -ENOMEM; 2963} 2964 2965static int 2966fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue) 2967{ 2968 struct fec_enet_private *fep = netdev_priv(ndev); 2969 unsigned int i; 2970 struct bufdesc *bdp; 2971 struct fec_enet_priv_tx_q *txq; 2972 2973 txq = fep->tx_queue[queue]; 2974 bdp = txq->bd.base; 2975 for (i = 0; i < txq->bd.ring_size; i++) { 2976 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 2977 if (!txq->tx_bounce[i]) 2978 goto err_alloc; 2979 2980 bdp->cbd_sc = cpu_to_fec16(0); 2981 bdp->cbd_bufaddr = cpu_to_fec32(0); 2982 2983 if (fep->bufdesc_ex) { 2984 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; 2985 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT); 2986 } 2987 2988 bdp = fec_enet_get_nextdesc(bdp, &txq->bd); 2989 } 2990 2991 /* Set the last buffer to wrap. */ 2992 bdp = fec_enet_get_prevdesc(bdp, &txq->bd); 2993 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP); 2994 2995 return 0; 2996 2997 err_alloc: 2998 fec_enet_free_buffers(ndev); 2999 return -ENOMEM; 3000} 3001 3002static int fec_enet_alloc_buffers(struct net_device *ndev) 3003{ 3004 struct fec_enet_private *fep = netdev_priv(ndev); 3005 unsigned int i; 3006 3007 for (i = 0; i < fep->num_rx_queues; i++) 3008 if (fec_enet_alloc_rxq_buffers(ndev, i)) 3009 return -ENOMEM; 3010 3011 for (i = 0; i < fep->num_tx_queues; i++) 3012 if (fec_enet_alloc_txq_buffers(ndev, i)) 3013 return -ENOMEM; 3014 return 0; 3015} 3016 3017static int 3018fec_enet_open(struct net_device *ndev) 3019{ 3020 struct fec_enet_private *fep = netdev_priv(ndev); 3021 int ret; 3022 bool reset_again; 3023 3024 ret = pm_runtime_resume_and_get(&fep->pdev->dev); 3025 if (ret < 0) 3026 return ret; 3027 3028 pinctrl_pm_select_default_state(&fep->pdev->dev); 3029 ret = fec_enet_clk_enable(ndev, true); 3030 if (ret) 3031 goto clk_enable; 3032 3033 /* During the first fec_enet_open call the PHY isn't probed at this 3034 * point. Therefore the phy_reset_after_clk_enable() call within 3035 * fec_enet_clk_enable() fails. As we need this reset in order to be 3036 * sure the PHY is working correctly we check if we need to reset again 3037 * later when the PHY is probed 3038 */ 3039 if (ndev->phydev && ndev->phydev->drv) 3040 reset_again = false; 3041 else 3042 reset_again = true; 3043 3044 /* I should reset the ring buffers here, but I don't yet know 3045 * a simple way to do that. 3046 */ 3047 3048 ret = fec_enet_alloc_buffers(ndev); 3049 if (ret) 3050 goto err_enet_alloc; 3051 3052 /* Init MAC prior to mii bus probe */ 3053 fec_restart(ndev); 3054 3055 /* Call phy_reset_after_clk_enable() again if it failed during 3056 * phy_reset_after_clk_enable() before because the PHY wasn't probed. 3057 */ 3058 if (reset_again) 3059 fec_enet_phy_reset_after_clk_enable(ndev); 3060 3061 /* Probe and connect to PHY when open the interface */ 3062 ret = fec_enet_mii_probe(ndev); 3063 if (ret) 3064 goto err_enet_mii_probe; 3065 3066 if (fep->quirks & FEC_QUIRK_ERR006687) 3067 imx6q_cpuidle_fec_irqs_used(); 3068 3069 napi_enable(&fep->napi); 3070 phy_start(ndev->phydev); 3071 netif_tx_start_all_queues(ndev); 3072 3073 device_set_wakeup_enable(&ndev->dev, fep->wol_flag & 3074 FEC_WOL_FLAG_ENABLE); 3075 3076 return 0; 3077 3078err_enet_mii_probe: 3079 fec_enet_free_buffers(ndev); 3080err_enet_alloc: 3081 fec_enet_clk_enable(ndev, false); 3082clk_enable: 3083 pm_runtime_mark_last_busy(&fep->pdev->dev); 3084 pm_runtime_put_autosuspend(&fep->pdev->dev); 3085 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3086 return ret; 3087} 3088 3089static int 3090fec_enet_close(struct net_device *ndev) 3091{ 3092 struct fec_enet_private *fep = netdev_priv(ndev); 3093 3094 phy_stop(ndev->phydev); 3095 3096 if (netif_device_present(ndev)) { 3097 napi_disable(&fep->napi); 3098 netif_tx_disable(ndev); 3099 fec_stop(ndev); 3100 } 3101 3102 phy_disconnect(ndev->phydev); 3103 3104 if (fep->quirks & FEC_QUIRK_ERR006687) 3105 imx6q_cpuidle_fec_irqs_unused(); 3106 3107 fec_enet_update_ethtool_stats(ndev); 3108 3109 fec_enet_clk_enable(ndev, false); 3110 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3111 pm_runtime_mark_last_busy(&fep->pdev->dev); 3112 pm_runtime_put_autosuspend(&fep->pdev->dev); 3113 3114 fec_enet_free_buffers(ndev); 3115 3116 return 0; 3117} 3118 3119/* Set or clear the multicast filter for this adaptor. 3120 * Skeleton taken from sunlance driver. 3121 * The CPM Ethernet implementation allows Multicast as well as individual 3122 * MAC address filtering. Some of the drivers check to make sure it is 3123 * a group multicast address, and discard those that are not. I guess I 3124 * will do the same for now, but just remove the test if you want 3125 * individual filtering as well (do the upper net layers want or support 3126 * this kind of feature?). 3127 */ 3128 3129#define FEC_HASH_BITS 6 /* #bits in hash */ 3130 3131static void set_multicast_list(struct net_device *ndev) 3132{ 3133 struct fec_enet_private *fep = netdev_priv(ndev); 3134 struct netdev_hw_addr *ha; 3135 unsigned int crc, tmp; 3136 unsigned char hash; 3137 unsigned int hash_high = 0, hash_low = 0; 3138 3139 if (ndev->flags & IFF_PROMISC) { 3140 tmp = readl(fep->hwp + FEC_R_CNTRL); 3141 tmp |= 0x8; 3142 writel(tmp, fep->hwp + FEC_R_CNTRL); 3143 return; 3144 } 3145 3146 tmp = readl(fep->hwp + FEC_R_CNTRL); 3147 tmp &= ~0x8; 3148 writel(tmp, fep->hwp + FEC_R_CNTRL); 3149 3150 if (ndev->flags & IFF_ALLMULTI) { 3151 /* Catch all multicast addresses, so set the 3152 * filter to all 1's 3153 */ 3154 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3155 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3156 3157 return; 3158 } 3159 3160 /* Add the addresses in hash register */ 3161 netdev_for_each_mc_addr(ha, ndev) { 3162 /* calculate crc32 value of mac address */ 3163 crc = ether_crc_le(ndev->addr_len, ha->addr); 3164 3165 /* only upper 6 bits (FEC_HASH_BITS) are used 3166 * which point to specific bit in the hash registers 3167 */ 3168 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f; 3169 3170 if (hash > 31) 3171 hash_high |= 1 << (hash - 32); 3172 else 3173 hash_low |= 1 << hash; 3174 } 3175 3176 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 3177 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 3178} 3179 3180/* Set a MAC change in hardware. */ 3181static int 3182fec_set_mac_address(struct net_device *ndev, void *p) 3183{ 3184 struct fec_enet_private *fep = netdev_priv(ndev); 3185 struct sockaddr *addr = p; 3186 3187 if (addr) { 3188 if (!is_valid_ether_addr(addr->sa_data)) 3189 return -EADDRNOTAVAIL; 3190 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); 3191 } 3192 3193 /* Add netif status check here to avoid system hang in below case: 3194 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx; 3195 * After ethx down, fec all clocks are gated off and then register 3196 * access causes system hang. 3197 */ 3198 if (!netif_running(ndev)) 3199 return 0; 3200 3201 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | 3202 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), 3203 fep->hwp + FEC_ADDR_LOW); 3204 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), 3205 fep->hwp + FEC_ADDR_HIGH); 3206 return 0; 3207} 3208 3209#ifdef CONFIG_NET_POLL_CONTROLLER 3210/** 3211 * fec_poll_controller - FEC Poll controller function 3212 * @dev: The FEC network adapter 3213 * 3214 * Polled functionality used by netconsole and others in non interrupt mode 3215 * 3216 */ 3217static void fec_poll_controller(struct net_device *dev) 3218{ 3219 int i; 3220 struct fec_enet_private *fep = netdev_priv(dev); 3221 3222 for (i = 0; i < FEC_IRQ_NUM; i++) { 3223 if (fep->irq[i] > 0) { 3224 disable_irq(fep->irq[i]); 3225 fec_enet_interrupt(fep->irq[i], dev); 3226 enable_irq(fep->irq[i]); 3227 } 3228 } 3229} 3230#endif 3231 3232static inline void fec_enet_set_netdev_features(struct net_device *netdev, 3233 netdev_features_t features) 3234{ 3235 struct fec_enet_private *fep = netdev_priv(netdev); 3236 netdev_features_t changed = features ^ netdev->features; 3237 3238 netdev->features = features; 3239 3240 /* Receive checksum has been changed */ 3241 if (changed & NETIF_F_RXCSUM) { 3242 if (features & NETIF_F_RXCSUM) 3243 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3244 else 3245 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; 3246 } 3247} 3248 3249static int fec_set_features(struct net_device *netdev, 3250 netdev_features_t features) 3251{ 3252 struct fec_enet_private *fep = netdev_priv(netdev); 3253 netdev_features_t changed = features ^ netdev->features; 3254 3255 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) { 3256 napi_disable(&fep->napi); 3257 netif_tx_lock_bh(netdev); 3258 fec_stop(netdev); 3259 fec_enet_set_netdev_features(netdev, features); 3260 fec_restart(netdev); 3261 netif_tx_wake_all_queues(netdev); 3262 netif_tx_unlock_bh(netdev); 3263 napi_enable(&fep->napi); 3264 } else { 3265 fec_enet_set_netdev_features(netdev, features); 3266 } 3267 3268 return 0; 3269} 3270 3271static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb, 3272 struct net_device *sb_dev) 3273{ 3274 struct fec_enet_private *fep = netdev_priv(ndev); 3275 u16 vlan_tag = 0; 3276 3277 if (!(fep->quirks & FEC_QUIRK_HAS_AVB)) 3278 return netdev_pick_tx(ndev, skb, NULL); 3279 3280 /* VLAN is present in the payload.*/ 3281 if (eth_type_vlan(skb->protocol)) { 3282 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb); 3283 3284 vlan_tag = ntohs(vhdr->h_vlan_TCI); 3285 /* VLAN is present in the skb but not yet pushed in the payload.*/ 3286 } else if (skb_vlan_tag_present(skb)) { 3287 vlan_tag = skb->vlan_tci; 3288 } else { 3289 return vlan_tag; 3290 } 3291 3292 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13]; 3293} 3294 3295static const struct net_device_ops fec_netdev_ops = { 3296 .ndo_open = fec_enet_open, 3297 .ndo_stop = fec_enet_close, 3298 .ndo_start_xmit = fec_enet_start_xmit, 3299 .ndo_select_queue = fec_enet_select_queue, 3300 .ndo_set_rx_mode = set_multicast_list, 3301 .ndo_validate_addr = eth_validate_addr, 3302 .ndo_tx_timeout = fec_timeout, 3303 .ndo_set_mac_address = fec_set_mac_address, 3304 .ndo_do_ioctl = fec_enet_ioctl, 3305#ifdef CONFIG_NET_POLL_CONTROLLER 3306 .ndo_poll_controller = fec_poll_controller, 3307#endif 3308 .ndo_set_features = fec_set_features, 3309}; 3310 3311static const unsigned short offset_des_active_rxq[] = { 3312 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2 3313}; 3314 3315static const unsigned short offset_des_active_txq[] = { 3316 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2 3317}; 3318 3319 /* 3320 * XXX: We need to clean up on failure exits here. 3321 * 3322 */ 3323static int fec_enet_init(struct net_device *ndev) 3324{ 3325 struct fec_enet_private *fep = netdev_priv(ndev); 3326 struct bufdesc *cbd_base; 3327 dma_addr_t bd_dma; 3328 int bd_size; 3329 unsigned int i; 3330 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) : 3331 sizeof(struct bufdesc); 3332 unsigned dsize_log2 = __fls(dsize); 3333 int ret; 3334 3335 WARN_ON(dsize != (1 << dsize_log2)); 3336#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 3337 fep->rx_align = 0xf; 3338 fep->tx_align = 0xf; 3339#else 3340 fep->rx_align = 0x3; 3341 fep->tx_align = 0x3; 3342#endif 3343 3344 /* Check mask of the streaming and coherent API */ 3345 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32)); 3346 if (ret < 0) { 3347 dev_warn(&fep->pdev->dev, "No suitable DMA available\n"); 3348 return ret; 3349 } 3350 3351 ret = fec_enet_alloc_queue(ndev); 3352 if (ret) 3353 return ret; 3354 3355 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize; 3356 3357 /* Allocate memory for buffer descriptors. */ 3358 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma, 3359 GFP_KERNEL); 3360 if (!cbd_base) { 3361 ret = -ENOMEM; 3362 goto free_queue_mem; 3363 } 3364 3365 /* Get the Ethernet address */ 3366 fec_get_mac(ndev); 3367 /* make sure MAC we just acquired is programmed into the hw */ 3368 fec_set_mac_address(ndev, NULL); 3369 3370 /* Set receive and transmit descriptor base. */ 3371 for (i = 0; i < fep->num_rx_queues; i++) { 3372 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i]; 3373 unsigned size = dsize * rxq->bd.ring_size; 3374 3375 rxq->bd.qid = i; 3376 rxq->bd.base = cbd_base; 3377 rxq->bd.cur = cbd_base; 3378 rxq->bd.dma = bd_dma; 3379 rxq->bd.dsize = dsize; 3380 rxq->bd.dsize_log2 = dsize_log2; 3381 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i]; 3382 bd_dma += size; 3383 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3384 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3385 } 3386 3387 for (i = 0; i < fep->num_tx_queues; i++) { 3388 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i]; 3389 unsigned size = dsize * txq->bd.ring_size; 3390 3391 txq->bd.qid = i; 3392 txq->bd.base = cbd_base; 3393 txq->bd.cur = cbd_base; 3394 txq->bd.dma = bd_dma; 3395 txq->bd.dsize = dsize; 3396 txq->bd.dsize_log2 = dsize_log2; 3397 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i]; 3398 bd_dma += size; 3399 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size); 3400 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize); 3401 } 3402 3403 3404 /* The FEC Ethernet specific entries in the device structure */ 3405 ndev->watchdog_timeo = TX_TIMEOUT; 3406 ndev->netdev_ops = &fec_netdev_ops; 3407 ndev->ethtool_ops = &fec_enet_ethtool_ops; 3408 3409 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); 3410 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT); 3411 3412 if (fep->quirks & FEC_QUIRK_HAS_VLAN) 3413 /* enable hw VLAN support */ 3414 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 3415 3416 if (fep->quirks & FEC_QUIRK_HAS_CSUM) { 3417 ndev->gso_max_segs = FEC_MAX_TSO_SEGS; 3418 3419 /* enable hw accelerator */ 3420 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM 3421 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO); 3422 fep->csum_flags |= FLAG_RX_CSUM_ENABLED; 3423 } 3424 3425 if (fep->quirks & FEC_QUIRK_HAS_AVB) { 3426 fep->tx_align = 0; 3427 fep->rx_align = 0x3f; 3428 } 3429 3430 ndev->hw_features = ndev->features; 3431 3432 fec_restart(ndev); 3433 3434 if (fep->quirks & FEC_QUIRK_MIB_CLEAR) 3435 fec_enet_clear_ethtool_stats(ndev); 3436 else 3437 fec_enet_update_ethtool_stats(ndev); 3438 3439 return 0; 3440 3441free_queue_mem: 3442 fec_enet_free_queue(ndev); 3443 return ret; 3444} 3445 3446#ifdef CONFIG_OF 3447static int fec_reset_phy(struct platform_device *pdev) 3448{ 3449 int err, phy_reset; 3450 bool active_high = false; 3451 int msec = 1, phy_post_delay = 0; 3452 struct device_node *np = pdev->dev.of_node; 3453 3454 if (!np) 3455 return 0; 3456 3457 err = of_property_read_u32(np, "phy-reset-duration", &msec); 3458 /* A sane reset duration should not be longer than 1s */ 3459 if (!err && msec > 1000) 3460 msec = 1; 3461 3462 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); 3463 if (phy_reset == -EPROBE_DEFER) 3464 return phy_reset; 3465 else if (!gpio_is_valid(phy_reset)) 3466 return 0; 3467 3468 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay); 3469 /* valid reset duration should be less than 1s */ 3470 if (!err && phy_post_delay > 1000) 3471 return -EINVAL; 3472 3473 active_high = of_property_read_bool(np, "phy-reset-active-high"); 3474 3475 err = devm_gpio_request_one(&pdev->dev, phy_reset, 3476 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, 3477 "phy-reset"); 3478 if (err) { 3479 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); 3480 return err; 3481 } 3482 3483 if (msec > 20) 3484 msleep(msec); 3485 else 3486 usleep_range(msec * 1000, msec * 1000 + 1000); 3487 3488 gpio_set_value_cansleep(phy_reset, !active_high); 3489 3490 if (!phy_post_delay) 3491 return 0; 3492 3493 if (phy_post_delay > 20) 3494 msleep(phy_post_delay); 3495 else 3496 usleep_range(phy_post_delay * 1000, 3497 phy_post_delay * 1000 + 1000); 3498 3499 return 0; 3500} 3501#else /* CONFIG_OF */ 3502static int fec_reset_phy(struct platform_device *pdev) 3503{ 3504 /* 3505 * In case of platform probe, the reset has been done 3506 * by machine code. 3507 */ 3508 return 0; 3509} 3510#endif /* CONFIG_OF */ 3511 3512static void 3513fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx) 3514{ 3515 struct device_node *np = pdev->dev.of_node; 3516 3517 *num_tx = *num_rx = 1; 3518 3519 if (!np || !of_device_is_available(np)) 3520 return; 3521 3522 /* parse the num of tx and rx queues */ 3523 of_property_read_u32(np, "fsl,num-tx-queues", num_tx); 3524 3525 of_property_read_u32(np, "fsl,num-rx-queues", num_rx); 3526 3527 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) { 3528 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n", 3529 *num_tx); 3530 *num_tx = 1; 3531 return; 3532 } 3533 3534 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) { 3535 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n", 3536 *num_rx); 3537 *num_rx = 1; 3538 return; 3539 } 3540 3541} 3542 3543static int fec_enet_get_irq_cnt(struct platform_device *pdev) 3544{ 3545 int irq_cnt = platform_irq_count(pdev); 3546 3547 if (irq_cnt > FEC_IRQ_NUM) 3548 irq_cnt = FEC_IRQ_NUM; /* last for pps */ 3549 else if (irq_cnt == 2) 3550 irq_cnt = 1; /* last for pps */ 3551 else if (irq_cnt <= 0) 3552 irq_cnt = 1; /* At least 1 irq is needed */ 3553 return irq_cnt; 3554} 3555 3556static int fec_enet_init_stop_mode(struct fec_enet_private *fep, 3557 struct device_node *np) 3558{ 3559 struct device_node *gpr_np; 3560 u32 out_val[3]; 3561 int ret = 0; 3562 3563 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0); 3564 if (!gpr_np) 3565 return 0; 3566 3567 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 3568 ARRAY_SIZE(out_val)); 3569 if (ret) { 3570 dev_dbg(&fep->pdev->dev, "no stop mode property\n"); 3571 goto out; 3572 } 3573 3574 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np); 3575 if (IS_ERR(fep->stop_gpr.gpr)) { 3576 dev_err(&fep->pdev->dev, "could not find gpr regmap\n"); 3577 ret = PTR_ERR(fep->stop_gpr.gpr); 3578 fep->stop_gpr.gpr = NULL; 3579 goto out; 3580 } 3581 3582 fep->stop_gpr.reg = out_val[1]; 3583 fep->stop_gpr.bit = out_val[2]; 3584 3585out: 3586 of_node_put(gpr_np); 3587 3588 return ret; 3589} 3590 3591static int 3592fec_probe(struct platform_device *pdev) 3593{ 3594 struct fec_enet_private *fep; 3595 struct fec_platform_data *pdata; 3596 phy_interface_t interface; 3597 struct net_device *ndev; 3598 int i, irq, ret = 0; 3599 const struct of_device_id *of_id; 3600 static int dev_id; 3601 struct device_node *np = pdev->dev.of_node, *phy_node; 3602 int num_tx_qs; 3603 int num_rx_qs; 3604 char irq_name[8]; 3605 int irq_cnt; 3606 struct fec_devinfo *dev_info; 3607 3608 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs); 3609 3610 /* Init network device */ 3611 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) + 3612 FEC_STATS_SIZE, num_tx_qs, num_rx_qs); 3613 if (!ndev) 3614 return -ENOMEM; 3615 3616 SET_NETDEV_DEV(ndev, &pdev->dev); 3617 3618 /* setup board info structure */ 3619 fep = netdev_priv(ndev); 3620 3621 of_id = of_match_device(fec_dt_ids, &pdev->dev); 3622 if (of_id) 3623 pdev->id_entry = of_id->data; 3624 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data; 3625 if (dev_info) 3626 fep->quirks = dev_info->quirks; 3627 3628 fep->netdev = ndev; 3629 fep->num_rx_queues = num_rx_qs; 3630 fep->num_tx_queues = num_tx_qs; 3631 3632#if !defined(CONFIG_M5272) 3633 /* default enable pause frame auto negotiation */ 3634 if (fep->quirks & FEC_QUIRK_HAS_GBIT) 3635 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; 3636#endif 3637 3638 /* Select default pin state */ 3639 pinctrl_pm_select_default_state(&pdev->dev); 3640 3641 fep->hwp = devm_platform_ioremap_resource(pdev, 0); 3642 if (IS_ERR(fep->hwp)) { 3643 ret = PTR_ERR(fep->hwp); 3644 goto failed_ioremap; 3645 } 3646 3647 fep->pdev = pdev; 3648 fep->dev_id = dev_id++; 3649 3650 platform_set_drvdata(pdev, ndev); 3651 3652 if ((of_machine_is_compatible("fsl,imx6q") || 3653 of_machine_is_compatible("fsl,imx6dl")) && 3654 !of_property_read_bool(np, "fsl,err006687-workaround-present")) 3655 fep->quirks |= FEC_QUIRK_ERR006687; 3656 3657 if (of_get_property(np, "fsl,magic-packet", NULL)) 3658 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET; 3659 3660 ret = fec_enet_init_stop_mode(fep, np); 3661 if (ret) 3662 goto failed_stop_mode; 3663 3664 phy_node = of_parse_phandle(np, "phy-handle", 0); 3665 if (!phy_node && of_phy_is_fixed_link(np)) { 3666 ret = of_phy_register_fixed_link(np); 3667 if (ret < 0) { 3668 dev_err(&pdev->dev, 3669 "broken fixed-link specification\n"); 3670 goto failed_phy; 3671 } 3672 phy_node = of_node_get(np); 3673 } 3674 fep->phy_node = phy_node; 3675 3676 ret = of_get_phy_mode(pdev->dev.of_node, &interface); 3677 if (ret) { 3678 pdata = dev_get_platdata(&pdev->dev); 3679 if (pdata) 3680 fep->phy_interface = pdata->phy; 3681 else 3682 fep->phy_interface = PHY_INTERFACE_MODE_MII; 3683 } else { 3684 fep->phy_interface = interface; 3685 } 3686 3687 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 3688 if (IS_ERR(fep->clk_ipg)) { 3689 ret = PTR_ERR(fep->clk_ipg); 3690 goto failed_clk; 3691 } 3692 3693 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 3694 if (IS_ERR(fep->clk_ahb)) { 3695 ret = PTR_ERR(fep->clk_ahb); 3696 goto failed_clk; 3697 } 3698 3699 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb); 3700 3701 /* enet_out is optional, depends on board */ 3702 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); 3703 if (IS_ERR(fep->clk_enet_out)) 3704 fep->clk_enet_out = NULL; 3705 3706 fep->ptp_clk_on = false; 3707 mutex_init(&fep->ptp_clk_mutex); 3708 3709 /* clk_ref is optional, depends on board */ 3710 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref"); 3711 if (IS_ERR(fep->clk_ref)) 3712 fep->clk_ref = NULL; 3713 3714 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX; 3715 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); 3716 if (IS_ERR(fep->clk_ptp)) { 3717 fep->clk_ptp = NULL; 3718 fep->bufdesc_ex = false; 3719 } 3720 3721 ret = fec_enet_clk_enable(ndev, true); 3722 if (ret) 3723 goto failed_clk; 3724 3725 ret = clk_prepare_enable(fep->clk_ipg); 3726 if (ret) 3727 goto failed_clk_ipg; 3728 ret = clk_prepare_enable(fep->clk_ahb); 3729 if (ret) 3730 goto failed_clk_ahb; 3731 3732 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy"); 3733 if (!IS_ERR(fep->reg_phy)) { 3734 ret = regulator_enable(fep->reg_phy); 3735 if (ret) { 3736 dev_err(&pdev->dev, 3737 "Failed to enable phy regulator: %d\n", ret); 3738 goto failed_regulator; 3739 } 3740 } else { 3741 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) { 3742 ret = -EPROBE_DEFER; 3743 goto failed_regulator; 3744 } 3745 fep->reg_phy = NULL; 3746 } 3747 3748 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT); 3749 pm_runtime_use_autosuspend(&pdev->dev); 3750 pm_runtime_get_noresume(&pdev->dev); 3751 pm_runtime_set_active(&pdev->dev); 3752 pm_runtime_enable(&pdev->dev); 3753 3754 ret = fec_reset_phy(pdev); 3755 if (ret) 3756 goto failed_reset; 3757 3758 irq_cnt = fec_enet_get_irq_cnt(pdev); 3759 if (fep->bufdesc_ex) 3760 fec_ptp_init(pdev, irq_cnt); 3761 3762 ret = fec_enet_init(ndev); 3763 if (ret) 3764 goto failed_init; 3765 3766 for (i = 0; i < irq_cnt; i++) { 3767 snprintf(irq_name, sizeof(irq_name), "int%d", i); 3768 irq = platform_get_irq_byname_optional(pdev, irq_name); 3769 if (irq < 0) 3770 irq = platform_get_irq(pdev, i); 3771 if (irq < 0) { 3772 ret = irq; 3773 goto failed_irq; 3774 } 3775 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt, 3776 0, pdev->name, ndev); 3777 if (ret) 3778 goto failed_irq; 3779 3780 fep->irq[i] = irq; 3781 } 3782 3783 ret = fec_enet_mii_init(pdev); 3784 if (ret) 3785 goto failed_mii_init; 3786 3787 /* Carrier starts down, phylib will bring it up */ 3788 netif_carrier_off(ndev); 3789 fec_enet_clk_enable(ndev, false); 3790 pinctrl_pm_select_sleep_state(&pdev->dev); 3791 3792 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN; 3793 3794 ret = register_netdev(ndev); 3795 if (ret) 3796 goto failed_register; 3797 3798 device_init_wakeup(&ndev->dev, fep->wol_flag & 3799 FEC_WOL_HAS_MAGIC_PACKET); 3800 3801 if (fep->bufdesc_ex && fep->ptp_clock) 3802 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); 3803 3804 fep->rx_copybreak = COPYBREAK_DEFAULT; 3805 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work); 3806 3807 pm_runtime_mark_last_busy(&pdev->dev); 3808 pm_runtime_put_autosuspend(&pdev->dev); 3809 3810 return 0; 3811 3812failed_register: 3813 fec_enet_mii_remove(fep); 3814failed_mii_init: 3815failed_irq: 3816failed_init: 3817 fec_ptp_stop(pdev); 3818failed_reset: 3819 pm_runtime_put_noidle(&pdev->dev); 3820 pm_runtime_disable(&pdev->dev); 3821 if (fep->reg_phy) 3822 regulator_disable(fep->reg_phy); 3823failed_regulator: 3824 clk_disable_unprepare(fep->clk_ahb); 3825failed_clk_ahb: 3826 clk_disable_unprepare(fep->clk_ipg); 3827failed_clk_ipg: 3828 fec_enet_clk_enable(ndev, false); 3829failed_clk: 3830 if (of_phy_is_fixed_link(np)) 3831 of_phy_deregister_fixed_link(np); 3832 of_node_put(phy_node); 3833failed_stop_mode: 3834failed_phy: 3835 dev_id--; 3836failed_ioremap: 3837 free_netdev(ndev); 3838 3839 return ret; 3840} 3841 3842static int 3843fec_drv_remove(struct platform_device *pdev) 3844{ 3845 struct net_device *ndev = platform_get_drvdata(pdev); 3846 struct fec_enet_private *fep = netdev_priv(ndev); 3847 struct device_node *np = pdev->dev.of_node; 3848 int ret; 3849 3850 ret = pm_runtime_get_sync(&pdev->dev); 3851 if (ret < 0) 3852 dev_err(&pdev->dev, 3853 "Failed to resume device in remove callback (%pe)\n", 3854 ERR_PTR(ret)); 3855 3856 cancel_work_sync(&fep->tx_timeout_work); 3857 fec_ptp_stop(pdev); 3858 unregister_netdev(ndev); 3859 fec_enet_mii_remove(fep); 3860 if (fep->reg_phy) 3861 regulator_disable(fep->reg_phy); 3862 3863 if (of_phy_is_fixed_link(np)) 3864 of_phy_deregister_fixed_link(np); 3865 of_node_put(fep->phy_node); 3866 3867 /* After pm_runtime_get_sync() failed, the clks are still off, so skip 3868 * disabling them again. 3869 */ 3870 if (ret >= 0) { 3871 clk_disable_unprepare(fep->clk_ahb); 3872 clk_disable_unprepare(fep->clk_ipg); 3873 } 3874 pm_runtime_put_noidle(&pdev->dev); 3875 pm_runtime_disable(&pdev->dev); 3876 3877 free_netdev(ndev); 3878 return 0; 3879} 3880 3881static int __maybe_unused fec_suspend(struct device *dev) 3882{ 3883 struct net_device *ndev = dev_get_drvdata(dev); 3884 struct fec_enet_private *fep = netdev_priv(ndev); 3885 3886 rtnl_lock(); 3887 if (netif_running(ndev)) { 3888 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) 3889 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON; 3890 phy_stop(ndev->phydev); 3891 napi_disable(&fep->napi); 3892 netif_tx_lock_bh(ndev); 3893 netif_device_detach(ndev); 3894 netif_tx_unlock_bh(ndev); 3895 fec_stop(ndev); 3896 fec_enet_clk_enable(ndev, false); 3897 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3898 pinctrl_pm_select_sleep_state(&fep->pdev->dev); 3899 } 3900 rtnl_unlock(); 3901 3902 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) 3903 regulator_disable(fep->reg_phy); 3904 3905 /* SOC supply clock to phy, when clock is disabled, phy link down 3906 * SOC control phy regulator, when regulator is disabled, phy link down 3907 */ 3908 if (fep->clk_enet_out || fep->reg_phy) 3909 fep->link = 0; 3910 3911 return 0; 3912} 3913 3914static int __maybe_unused fec_resume(struct device *dev) 3915{ 3916 struct net_device *ndev = dev_get_drvdata(dev); 3917 struct fec_enet_private *fep = netdev_priv(ndev); 3918 int ret; 3919 int val; 3920 3921 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { 3922 ret = regulator_enable(fep->reg_phy); 3923 if (ret) 3924 return ret; 3925 } 3926 3927 rtnl_lock(); 3928 if (netif_running(ndev)) { 3929 ret = fec_enet_clk_enable(ndev, true); 3930 if (ret) { 3931 rtnl_unlock(); 3932 goto failed_clk; 3933 } 3934 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) { 3935 fec_enet_stop_mode(fep, false); 3936 3937 val = readl(fep->hwp + FEC_ECNTRL); 3938 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); 3939 writel(val, fep->hwp + FEC_ECNTRL); 3940 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON; 3941 } else { 3942 pinctrl_pm_select_default_state(&fep->pdev->dev); 3943 } 3944 fec_restart(ndev); 3945 netif_tx_lock_bh(ndev); 3946 netif_device_attach(ndev); 3947 netif_tx_unlock_bh(ndev); 3948 napi_enable(&fep->napi); 3949 phy_start(ndev->phydev); 3950 } 3951 rtnl_unlock(); 3952 3953 return 0; 3954 3955failed_clk: 3956 if (fep->reg_phy) 3957 regulator_disable(fep->reg_phy); 3958 return ret; 3959} 3960 3961static int __maybe_unused fec_runtime_suspend(struct device *dev) 3962{ 3963 struct net_device *ndev = dev_get_drvdata(dev); 3964 struct fec_enet_private *fep = netdev_priv(ndev); 3965 3966 clk_disable_unprepare(fep->clk_ahb); 3967 clk_disable_unprepare(fep->clk_ipg); 3968 3969 return 0; 3970} 3971 3972static int __maybe_unused fec_runtime_resume(struct device *dev) 3973{ 3974 struct net_device *ndev = dev_get_drvdata(dev); 3975 struct fec_enet_private *fep = netdev_priv(ndev); 3976 int ret; 3977 3978 ret = clk_prepare_enable(fep->clk_ahb); 3979 if (ret) 3980 return ret; 3981 ret = clk_prepare_enable(fep->clk_ipg); 3982 if (ret) 3983 goto failed_clk_ipg; 3984 3985 return 0; 3986 3987failed_clk_ipg: 3988 clk_disable_unprepare(fep->clk_ahb); 3989 return ret; 3990} 3991 3992static const struct dev_pm_ops fec_pm_ops = { 3993 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume) 3994 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL) 3995}; 3996 3997static struct platform_driver fec_driver = { 3998 .driver = { 3999 .name = DRIVER_NAME, 4000 .pm = &fec_pm_ops, 4001 .of_match_table = fec_dt_ids, 4002 .suppress_bind_attrs = true, 4003 }, 4004 .id_table = fec_devtype, 4005 .probe = fec_probe, 4006 .remove = fec_drv_remove, 4007}; 4008 4009module_platform_driver(fec_driver); 4010 4011MODULE_ALIAS("platform:"DRIVER_NAME); 4012MODULE_LICENSE("GPL"); 4013