1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2017 ATMEL 4 * Copyright 2017 Free Electrons 5 * 6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com> 7 * 8 * Derived from the atmel_nand.c driver which contained the following 9 * copyrights: 10 * 11 * Copyright 2003 Rick Bronson 12 * 13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8) 14 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de) 15 * 16 * Derived from drivers/mtd/spia.c (removed in v3.8) 17 * Copyright 2000 Steven J. Hill (sjhill@cotw.com) 18 * 19 * 20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 21 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007 22 * 23 * Derived from Das U-Boot source code 24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) 25 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas 26 * 27 * Add Programmable Multibit ECC support for various AT91 SoC 28 * Copyright 2012 ATMEL, Hong Xu 29 * 30 * Add Nand Flash Controller support for SAMA5 SoC 31 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) 32 * 33 * A few words about the naming convention in this file. This convention 34 * applies to structure and function names. 35 * 36 * Prefixes: 37 * 38 * - atmel_nand_: all generic structures/functions 39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface 40 * (at91sam9 and avr32 SoCs) 41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface 42 * (sama5 SoCs and later) 43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block 44 * that is available in the HSMC block 45 * - <soc>_nand_: all SoC specific structures/functions 46 */ 47 48#include <linux/clk.h> 49#include <linux/dma-mapping.h> 50#include <linux/dmaengine.h> 51#include <linux/genalloc.h> 52#include <linux/gpio/consumer.h> 53#include <linux/interrupt.h> 54#include <linux/mfd/syscon.h> 55#include <linux/mfd/syscon/atmel-matrix.h> 56#include <linux/mfd/syscon/atmel-smc.h> 57#include <linux/module.h> 58#include <linux/mtd/rawnand.h> 59#include <linux/of_address.h> 60#include <linux/of_irq.h> 61#include <linux/of_platform.h> 62#include <linux/iopoll.h> 63#include <linux/platform_device.h> 64#include <linux/regmap.h> 65#include <soc/at91/atmel-sfr.h> 66 67#include "pmecc.h" 68 69#define ATMEL_HSMC_NFC_CFG 0x0 70#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24) 71#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24) 72#define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20)) 73#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16) 74#define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13) 75#define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12) 76#define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9) 77#define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8) 78#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0) 79#define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1) 80 81#define ATMEL_HSMC_NFC_CTRL 0x4 82#define ATMEL_HSMC_NFC_CTRL_EN BIT(0) 83#define ATMEL_HSMC_NFC_CTRL_DIS BIT(1) 84 85#define ATMEL_HSMC_NFC_SR 0x8 86#define ATMEL_HSMC_NFC_IER 0xc 87#define ATMEL_HSMC_NFC_IDR 0x10 88#define ATMEL_HSMC_NFC_IMR 0x14 89#define ATMEL_HSMC_NFC_SR_ENABLED BIT(1) 90#define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4) 91#define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5) 92#define ATMEL_HSMC_NFC_SR_BUSY BIT(8) 93#define ATMEL_HSMC_NFC_SR_WR BIT(11) 94#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12) 95#define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16) 96#define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17) 97#define ATMEL_HSMC_NFC_SR_DTOE BIT(20) 98#define ATMEL_HSMC_NFC_SR_UNDEF BIT(21) 99#define ATMEL_HSMC_NFC_SR_AWB BIT(22) 100#define ATMEL_HSMC_NFC_SR_NFCASE BIT(23) 101#define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \ 102 ATMEL_HSMC_NFC_SR_UNDEF | \ 103 ATMEL_HSMC_NFC_SR_AWB | \ 104 ATMEL_HSMC_NFC_SR_NFCASE) 105#define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24) 106 107#define ATMEL_HSMC_NFC_ADDR 0x18 108#define ATMEL_HSMC_NFC_BANK 0x1c 109 110#define ATMEL_NFC_MAX_RB_ID 7 111 112#define ATMEL_NFC_SRAM_SIZE 0x2400 113 114#define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2)) 115#define ATMEL_NFC_VCMD2 BIT(18) 116#define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19) 117#define ATMEL_NFC_CSID(cs) ((cs) << 22) 118#define ATMEL_NFC_DATAEN BIT(25) 119#define ATMEL_NFC_NFCWR BIT(26) 120 121#define ATMEL_NFC_MAX_ADDR_CYCLES 5 122 123#define ATMEL_NAND_ALE_OFFSET BIT(21) 124#define ATMEL_NAND_CLE_OFFSET BIT(22) 125 126#define DEFAULT_TIMEOUT_MS 1000 127#define MIN_DMA_LEN 128 128 129static bool atmel_nand_avoid_dma __read_mostly; 130 131MODULE_PARM_DESC(avoiddma, "Avoid using DMA"); 132module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400); 133 134enum atmel_nand_rb_type { 135 ATMEL_NAND_NO_RB, 136 ATMEL_NAND_NATIVE_RB, 137 ATMEL_NAND_GPIO_RB, 138}; 139 140struct atmel_nand_rb { 141 enum atmel_nand_rb_type type; 142 union { 143 struct gpio_desc *gpio; 144 int id; 145 }; 146}; 147 148struct atmel_nand_cs { 149 int id; 150 struct atmel_nand_rb rb; 151 struct gpio_desc *csgpio; 152 struct { 153 void __iomem *virt; 154 dma_addr_t dma; 155 } io; 156 157 struct atmel_smc_cs_conf smcconf; 158}; 159 160struct atmel_nand { 161 struct list_head node; 162 struct device *dev; 163 struct nand_chip base; 164 struct atmel_nand_cs *activecs; 165 struct atmel_pmecc_user *pmecc; 166 struct gpio_desc *cdgpio; 167 int numcs; 168 struct atmel_nand_cs cs[]; 169}; 170 171static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip) 172{ 173 return container_of(chip, struct atmel_nand, base); 174} 175 176enum atmel_nfc_data_xfer { 177 ATMEL_NFC_NO_DATA, 178 ATMEL_NFC_READ_DATA, 179 ATMEL_NFC_WRITE_DATA, 180}; 181 182struct atmel_nfc_op { 183 u8 cs; 184 u8 ncmds; 185 u8 cmds[2]; 186 u8 naddrs; 187 u8 addrs[5]; 188 enum atmel_nfc_data_xfer data; 189 u32 wait; 190 u32 errors; 191}; 192 193struct atmel_nand_controller; 194struct atmel_nand_controller_caps; 195 196struct atmel_nand_controller_ops { 197 int (*probe)(struct platform_device *pdev, 198 const struct atmel_nand_controller_caps *caps); 199 int (*remove)(struct atmel_nand_controller *nc); 200 void (*nand_init)(struct atmel_nand_controller *nc, 201 struct atmel_nand *nand); 202 int (*ecc_init)(struct nand_chip *chip); 203 int (*setup_interface)(struct atmel_nand *nand, int csline, 204 const struct nand_interface_config *conf); 205 int (*exec_op)(struct atmel_nand *nand, 206 const struct nand_operation *op, bool check_only); 207}; 208 209struct atmel_nand_controller_caps { 210 bool has_dma; 211 bool legacy_of_bindings; 212 u32 ale_offs; 213 u32 cle_offs; 214 const char *ebi_csa_regmap_name; 215 const struct atmel_nand_controller_ops *ops; 216}; 217 218struct atmel_nand_controller { 219 struct nand_controller base; 220 const struct atmel_nand_controller_caps *caps; 221 struct device *dev; 222 struct regmap *smc; 223 struct dma_chan *dmac; 224 struct atmel_pmecc *pmecc; 225 struct list_head chips; 226 struct clk *mck; 227}; 228 229static inline struct atmel_nand_controller * 230to_nand_controller(struct nand_controller *ctl) 231{ 232 return container_of(ctl, struct atmel_nand_controller, base); 233} 234 235struct atmel_smc_nand_ebi_csa_cfg { 236 u32 offs; 237 u32 nfd0_on_d16; 238}; 239 240struct atmel_smc_nand_controller { 241 struct atmel_nand_controller base; 242 struct regmap *ebi_csa_regmap; 243 struct atmel_smc_nand_ebi_csa_cfg *ebi_csa; 244}; 245 246static inline struct atmel_smc_nand_controller * 247to_smc_nand_controller(struct nand_controller *ctl) 248{ 249 return container_of(to_nand_controller(ctl), 250 struct atmel_smc_nand_controller, base); 251} 252 253struct atmel_hsmc_nand_controller { 254 struct atmel_nand_controller base; 255 struct { 256 struct gen_pool *pool; 257 void __iomem *virt; 258 dma_addr_t dma; 259 } sram; 260 const struct atmel_hsmc_reg_layout *hsmc_layout; 261 struct regmap *io; 262 struct atmel_nfc_op op; 263 struct completion complete; 264 u32 cfg; 265 int irq; 266 267 /* Only used when instantiating from legacy DT bindings. */ 268 struct clk *clk; 269}; 270 271static inline struct atmel_hsmc_nand_controller * 272to_hsmc_nand_controller(struct nand_controller *ctl) 273{ 274 return container_of(to_nand_controller(ctl), 275 struct atmel_hsmc_nand_controller, base); 276} 277 278static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status) 279{ 280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS; 281 op->wait ^= status & op->wait; 282 283 return !op->wait || op->errors; 284} 285 286static irqreturn_t atmel_nfc_interrupt(int irq, void *data) 287{ 288 struct atmel_hsmc_nand_controller *nc = data; 289 u32 sr, rcvd; 290 bool done; 291 292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr); 293 294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); 295 done = atmel_nfc_op_done(&nc->op, sr); 296 297 if (rcvd) 298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd); 299 300 if (done) 301 complete(&nc->complete); 302 303 return rcvd ? IRQ_HANDLED : IRQ_NONE; 304} 305 306static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll, 307 unsigned int timeout_ms) 308{ 309 int ret; 310 311 if (!timeout_ms) 312 timeout_ms = DEFAULT_TIMEOUT_MS; 313 314 if (poll) { 315 u32 status; 316 317 ret = regmap_read_poll_timeout(nc->base.smc, 318 ATMEL_HSMC_NFC_SR, status, 319 atmel_nfc_op_done(&nc->op, 320 status), 321 0, timeout_ms * 1000); 322 } else { 323 init_completion(&nc->complete); 324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER, 325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS); 326 ret = wait_for_completion_timeout(&nc->complete, 327 msecs_to_jiffies(timeout_ms)); 328 if (!ret) 329 ret = -ETIMEDOUT; 330 else 331 ret = 0; 332 333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); 334 } 335 336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) { 337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); 338 ret = -ETIMEDOUT; 339 } 340 341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) { 342 dev_err(nc->base.dev, "Access to an undefined area\n"); 343 ret = -EIO; 344 } 345 346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) { 347 dev_err(nc->base.dev, "Access while busy\n"); 348 ret = -EIO; 349 } 350 351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) { 352 dev_err(nc->base.dev, "Wrong access size\n"); 353 ret = -EIO; 354 } 355 356 return ret; 357} 358 359static void atmel_nand_dma_transfer_finished(void *data) 360{ 361 struct completion *finished = data; 362 363 complete(finished); 364} 365 366static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc, 367 void *buf, dma_addr_t dev_dma, size_t len, 368 enum dma_data_direction dir) 369{ 370 DECLARE_COMPLETION_ONSTACK(finished); 371 dma_addr_t src_dma, dst_dma, buf_dma; 372 struct dma_async_tx_descriptor *tx; 373 dma_cookie_t cookie; 374 375 buf_dma = dma_map_single(nc->dev, buf, len, dir); 376 if (dma_mapping_error(nc->dev, dev_dma)) { 377 dev_err(nc->dev, 378 "Failed to prepare a buffer for DMA access\n"); 379 goto err; 380 } 381 382 if (dir == DMA_FROM_DEVICE) { 383 src_dma = dev_dma; 384 dst_dma = buf_dma; 385 } else { 386 src_dma = buf_dma; 387 dst_dma = dev_dma; 388 } 389 390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len, 391 DMA_CTRL_ACK | DMA_PREP_INTERRUPT); 392 if (!tx) { 393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n"); 394 goto err_unmap; 395 } 396 397 tx->callback = atmel_nand_dma_transfer_finished; 398 tx->callback_param = &finished; 399 400 cookie = dmaengine_submit(tx); 401 if (dma_submit_error(cookie)) { 402 dev_err(nc->dev, "Failed to do DMA tx_submit\n"); 403 goto err_unmap; 404 } 405 406 dma_async_issue_pending(nc->dmac); 407 wait_for_completion(&finished); 408 dma_unmap_single(nc->dev, buf_dma, len, dir); 409 410 return 0; 411 412err_unmap: 413 dma_unmap_single(nc->dev, buf_dma, len, dir); 414 415err: 416 dev_dbg(nc->dev, "Fall back to CPU I/O\n"); 417 418 return -EIO; 419} 420 421static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll) 422{ 423 u8 *addrs = nc->op.addrs; 424 unsigned int op = 0; 425 u32 addr, val; 426 int i, ret; 427 428 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE; 429 430 for (i = 0; i < nc->op.ncmds; i++) 431 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]); 432 433 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) 434 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); 435 436 op |= ATMEL_NFC_CSID(nc->op.cs) | 437 ATMEL_NFC_ACYCLE(nc->op.naddrs); 438 439 if (nc->op.ncmds > 1) 440 op |= ATMEL_NFC_VCMD2; 441 442 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) | 443 (addrs[3] << 24); 444 445 if (nc->op.data != ATMEL_NFC_NO_DATA) { 446 op |= ATMEL_NFC_DATAEN; 447 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE; 448 449 if (nc->op.data == ATMEL_NFC_WRITE_DATA) 450 op |= ATMEL_NFC_NFCWR; 451 } 452 453 /* Clear all flags. */ 454 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); 455 456 /* Send the command. */ 457 regmap_write(nc->io, op, addr); 458 459 ret = atmel_nfc_wait(nc, poll, 0); 460 if (ret) 461 dev_err(nc->base.dev, 462 "Failed to send NAND command (err = %d)!", 463 ret); 464 465 /* Reset the op state. */ 466 memset(&nc->op, 0, sizeof(nc->op)); 467 468 return ret; 469} 470 471static void atmel_nand_data_in(struct atmel_nand *nand, void *buf, 472 unsigned int len, bool force_8bit) 473{ 474 struct atmel_nand_controller *nc; 475 476 nc = to_nand_controller(nand->base.controller); 477 478 /* 479 * If the controller supports DMA, the buffer address is DMA-able and 480 * len is long enough to make DMA transfers profitable, let's trigger 481 * a DMA transfer. If it fails, fallback to PIO mode. 482 */ 483 if (nc->dmac && virt_addr_valid(buf) && 484 len >= MIN_DMA_LEN && !force_8bit && 485 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, 486 DMA_FROM_DEVICE)) 487 return; 488 489 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) 490 ioread16_rep(nand->activecs->io.virt, buf, len / 2); 491 else 492 ioread8_rep(nand->activecs->io.virt, buf, len); 493} 494 495static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf, 496 unsigned int len, bool force_8bit) 497{ 498 struct atmel_nand_controller *nc; 499 500 nc = to_nand_controller(nand->base.controller); 501 502 /* 503 * If the controller supports DMA, the buffer address is DMA-able and 504 * len is long enough to make DMA transfers profitable, let's trigger 505 * a DMA transfer. If it fails, fallback to PIO mode. 506 */ 507 if (nc->dmac && virt_addr_valid(buf) && 508 len >= MIN_DMA_LEN && !force_8bit && 509 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, 510 len, DMA_TO_DEVICE)) 511 return; 512 513 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) 514 iowrite16_rep(nand->activecs->io.virt, buf, len / 2); 515 else 516 iowrite8_rep(nand->activecs->io.virt, buf, len); 517} 518 519static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms) 520{ 521 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB) 522 return nand_soft_waitrdy(&nand->base, timeout_ms); 523 524 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio, 525 timeout_ms); 526} 527 528static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand, 529 unsigned int timeout_ms) 530{ 531 struct atmel_hsmc_nand_controller *nc; 532 u32 status, mask; 533 534 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) 535 return atmel_nand_waitrdy(nand, timeout_ms); 536 537 nc = to_hsmc_nand_controller(nand->base.controller); 538 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); 539 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR, 540 status, status & mask, 541 10, timeout_ms * 1000); 542} 543 544static void atmel_nand_select_target(struct atmel_nand *nand, 545 unsigned int cs) 546{ 547 nand->activecs = &nand->cs[cs]; 548} 549 550static void atmel_hsmc_nand_select_target(struct atmel_nand *nand, 551 unsigned int cs) 552{ 553 struct mtd_info *mtd = nand_to_mtd(&nand->base); 554 struct atmel_hsmc_nand_controller *nc; 555 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | 556 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | 557 ATMEL_HSMC_NFC_CFG_RSPARE; 558 559 nand->activecs = &nand->cs[cs]; 560 nc = to_hsmc_nand_controller(nand->base.controller); 561 if (nc->cfg == cfg) 562 return; 563 564 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, 565 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK | 566 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK | 567 ATMEL_HSMC_NFC_CFG_RSPARE | 568 ATMEL_HSMC_NFC_CFG_WSPARE, 569 cfg); 570 nc->cfg = cfg; 571} 572 573static int atmel_smc_nand_exec_instr(struct atmel_nand *nand, 574 const struct nand_op_instr *instr) 575{ 576 struct atmel_nand_controller *nc; 577 unsigned int i; 578 579 nc = to_nand_controller(nand->base.controller); 580 switch (instr->type) { 581 case NAND_OP_CMD_INSTR: 582 writeb(instr->ctx.cmd.opcode, 583 nand->activecs->io.virt + nc->caps->cle_offs); 584 return 0; 585 case NAND_OP_ADDR_INSTR: 586 for (i = 0; i < instr->ctx.addr.naddrs; i++) 587 writeb(instr->ctx.addr.addrs[i], 588 nand->activecs->io.virt + nc->caps->ale_offs); 589 return 0; 590 case NAND_OP_DATA_IN_INSTR: 591 atmel_nand_data_in(nand, instr->ctx.data.buf.in, 592 instr->ctx.data.len, 593 instr->ctx.data.force_8bit); 594 return 0; 595 case NAND_OP_DATA_OUT_INSTR: 596 atmel_nand_data_out(nand, instr->ctx.data.buf.out, 597 instr->ctx.data.len, 598 instr->ctx.data.force_8bit); 599 return 0; 600 case NAND_OP_WAITRDY_INSTR: 601 return atmel_nand_waitrdy(nand, 602 instr->ctx.waitrdy.timeout_ms); 603 default: 604 break; 605 } 606 607 return -EINVAL; 608} 609 610static int atmel_smc_nand_exec_op(struct atmel_nand *nand, 611 const struct nand_operation *op, 612 bool check_only) 613{ 614 unsigned int i; 615 int ret = 0; 616 617 if (check_only) 618 return 0; 619 620 atmel_nand_select_target(nand, op->cs); 621 gpiod_set_value(nand->activecs->csgpio, 0); 622 for (i = 0; i < op->ninstrs; i++) { 623 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); 624 if (ret) 625 break; 626 } 627 gpiod_set_value(nand->activecs->csgpio, 1); 628 629 return ret; 630} 631 632static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip, 633 const struct nand_subop *subop) 634{ 635 struct atmel_nand *nand = to_atmel_nand(chip); 636 struct atmel_hsmc_nand_controller *nc; 637 unsigned int i, j; 638 639 nc = to_hsmc_nand_controller(chip->controller); 640 641 nc->op.cs = nand->activecs->id; 642 for (i = 0; i < subop->ninstrs; i++) { 643 const struct nand_op_instr *instr = &subop->instrs[i]; 644 645 if (instr->type == NAND_OP_CMD_INSTR) { 646 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode; 647 continue; 648 } 649 650 for (j = nand_subop_get_addr_start_off(subop, i); 651 j < nand_subop_get_num_addr_cyc(subop, i); j++) { 652 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j]; 653 nc->op.naddrs++; 654 } 655 } 656 657 return atmel_nfc_exec_op(nc, true); 658} 659 660static int atmel_hsmc_exec_rw(struct nand_chip *chip, 661 const struct nand_subop *subop) 662{ 663 const struct nand_op_instr *instr = subop->instrs; 664 struct atmel_nand *nand = to_atmel_nand(chip); 665 666 if (instr->type == NAND_OP_DATA_IN_INSTR) 667 atmel_nand_data_in(nand, instr->ctx.data.buf.in, 668 instr->ctx.data.len, 669 instr->ctx.data.force_8bit); 670 else 671 atmel_nand_data_out(nand, instr->ctx.data.buf.out, 672 instr->ctx.data.len, 673 instr->ctx.data.force_8bit); 674 675 return 0; 676} 677 678static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip, 679 const struct nand_subop *subop) 680{ 681 const struct nand_op_instr *instr = subop->instrs; 682 struct atmel_nand *nand = to_atmel_nand(chip); 683 684 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms); 685} 686 687static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER( 688 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr, 689 NAND_OP_PARSER_PAT_CMD_ELEM(true), 690 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5), 691 NAND_OP_PARSER_PAT_CMD_ELEM(true)), 692 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw, 693 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)), 694 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw, 695 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)), 696 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy, 697 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 698); 699 700static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand, 701 const struct nand_operation *op, 702 bool check_only) 703{ 704 int ret; 705 706 if (check_only) 707 return nand_op_parser_exec_op(&nand->base, 708 &atmel_hsmc_op_parser, op, true); 709 710 atmel_hsmc_nand_select_target(nand, op->cs); 711 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op, 712 false); 713 714 return ret; 715} 716 717static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf, 718 bool oob_required) 719{ 720 struct mtd_info *mtd = nand_to_mtd(chip); 721 struct atmel_hsmc_nand_controller *nc; 722 int ret = -EIO; 723 724 nc = to_hsmc_nand_controller(chip->controller); 725 726 if (nc->base.dmac) 727 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf, 728 nc->sram.dma, mtd->writesize, 729 DMA_TO_DEVICE); 730 731 /* Falling back to CPU copy. */ 732 if (ret) 733 memcpy_toio(nc->sram.virt, buf, mtd->writesize); 734 735 if (oob_required) 736 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, 737 mtd->oobsize); 738} 739 740static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf, 741 bool oob_required) 742{ 743 struct mtd_info *mtd = nand_to_mtd(chip); 744 struct atmel_hsmc_nand_controller *nc; 745 int ret = -EIO; 746 747 nc = to_hsmc_nand_controller(chip->controller); 748 749 if (nc->base.dmac) 750 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma, 751 mtd->writesize, DMA_FROM_DEVICE); 752 753 /* Falling back to CPU copy. */ 754 if (ret) 755 memcpy_fromio(buf, nc->sram.virt, mtd->writesize); 756 757 if (oob_required) 758 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, 759 mtd->oobsize); 760} 761 762static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column) 763{ 764 struct mtd_info *mtd = nand_to_mtd(chip); 765 struct atmel_hsmc_nand_controller *nc; 766 767 nc = to_hsmc_nand_controller(chip->controller); 768 769 if (column >= 0) { 770 nc->op.addrs[nc->op.naddrs++] = column; 771 772 /* 773 * 2 address cycles for the column offset on large page NANDs. 774 */ 775 if (mtd->writesize > 512) 776 nc->op.addrs[nc->op.naddrs++] = column >> 8; 777 } 778 779 if (page >= 0) { 780 nc->op.addrs[nc->op.naddrs++] = page; 781 nc->op.addrs[nc->op.naddrs++] = page >> 8; 782 783 if (chip->options & NAND_ROW_ADDR_3) 784 nc->op.addrs[nc->op.naddrs++] = page >> 16; 785 } 786} 787 788static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw) 789{ 790 struct atmel_nand *nand = to_atmel_nand(chip); 791 struct atmel_nand_controller *nc; 792 int ret; 793 794 nc = to_nand_controller(chip->controller); 795 796 if (raw) 797 return 0; 798 799 ret = atmel_pmecc_enable(nand->pmecc, op); 800 if (ret) 801 dev_err(nc->dev, 802 "Failed to enable ECC engine (err = %d)\n", ret); 803 804 return ret; 805} 806 807static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw) 808{ 809 struct atmel_nand *nand = to_atmel_nand(chip); 810 811 if (!raw) 812 atmel_pmecc_disable(nand->pmecc); 813} 814 815static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw) 816{ 817 struct atmel_nand *nand = to_atmel_nand(chip); 818 struct mtd_info *mtd = nand_to_mtd(chip); 819 struct atmel_nand_controller *nc; 820 struct mtd_oob_region oobregion; 821 void *eccbuf; 822 int ret, i; 823 824 nc = to_nand_controller(chip->controller); 825 826 if (raw) 827 return 0; 828 829 ret = atmel_pmecc_wait_rdy(nand->pmecc); 830 if (ret) { 831 dev_err(nc->dev, 832 "Failed to transfer NAND page data (err = %d)\n", 833 ret); 834 return ret; 835 } 836 837 mtd_ooblayout_ecc(mtd, 0, &oobregion); 838 eccbuf = chip->oob_poi + oobregion.offset; 839 840 for (i = 0; i < chip->ecc.steps; i++) { 841 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i, 842 eccbuf); 843 eccbuf += chip->ecc.bytes; 844 } 845 846 return 0; 847} 848 849static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf, 850 bool raw) 851{ 852 struct atmel_nand *nand = to_atmel_nand(chip); 853 struct mtd_info *mtd = nand_to_mtd(chip); 854 struct atmel_nand_controller *nc; 855 struct mtd_oob_region oobregion; 856 int ret, i, max_bitflips = 0; 857 void *databuf, *eccbuf; 858 859 nc = to_nand_controller(chip->controller); 860 861 if (raw) 862 return 0; 863 864 ret = atmel_pmecc_wait_rdy(nand->pmecc); 865 if (ret) { 866 dev_err(nc->dev, 867 "Failed to read NAND page data (err = %d)\n", 868 ret); 869 return ret; 870 } 871 872 mtd_ooblayout_ecc(mtd, 0, &oobregion); 873 eccbuf = chip->oob_poi + oobregion.offset; 874 databuf = buf; 875 876 for (i = 0; i < chip->ecc.steps; i++) { 877 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf, 878 eccbuf); 879 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc)) 880 ret = nand_check_erased_ecc_chunk(databuf, 881 chip->ecc.size, 882 eccbuf, 883 chip->ecc.bytes, 884 NULL, 0, 885 chip->ecc.strength); 886 887 if (ret >= 0) { 888 mtd->ecc_stats.corrected += ret; 889 max_bitflips = max(ret, max_bitflips); 890 } else { 891 mtd->ecc_stats.failed++; 892 } 893 894 databuf += chip->ecc.size; 895 eccbuf += chip->ecc.bytes; 896 } 897 898 return max_bitflips; 899} 900 901static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf, 902 bool oob_required, int page, bool raw) 903{ 904 struct mtd_info *mtd = nand_to_mtd(chip); 905 struct atmel_nand *nand = to_atmel_nand(chip); 906 int ret; 907 908 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 909 910 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw); 911 if (ret) 912 return ret; 913 914 nand_write_data_op(chip, buf, mtd->writesize, false); 915 916 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw); 917 if (ret) { 918 atmel_pmecc_disable(nand->pmecc); 919 return ret; 920 } 921 922 atmel_nand_pmecc_disable(chip, raw); 923 924 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 925 926 return nand_prog_page_end_op(chip); 927} 928 929static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf, 930 int oob_required, int page) 931{ 932 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false); 933} 934 935static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip, 936 const u8 *buf, int oob_required, 937 int page) 938{ 939 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true); 940} 941 942static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf, 943 bool oob_required, int page, bool raw) 944{ 945 struct mtd_info *mtd = nand_to_mtd(chip); 946 int ret; 947 948 nand_read_page_op(chip, page, 0, NULL, 0); 949 950 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw); 951 if (ret) 952 return ret; 953 954 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false); 955 if (ret) 956 goto out_disable; 957 958 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false); 959 if (ret) 960 goto out_disable; 961 962 ret = atmel_nand_pmecc_correct_data(chip, buf, raw); 963 964out_disable: 965 atmel_nand_pmecc_disable(chip, raw); 966 967 return ret; 968} 969 970static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf, 971 int oob_required, int page) 972{ 973 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false); 974} 975 976static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf, 977 int oob_required, int page) 978{ 979 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true); 980} 981 982static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip, 983 const u8 *buf, bool oob_required, 984 int page, bool raw) 985{ 986 struct mtd_info *mtd = nand_to_mtd(chip); 987 struct atmel_nand *nand = to_atmel_nand(chip); 988 struct atmel_hsmc_nand_controller *nc; 989 int ret; 990 991 atmel_hsmc_nand_select_target(nand, chip->cur_cs); 992 nc = to_hsmc_nand_controller(chip->controller); 993 994 atmel_nfc_copy_to_sram(chip, buf, false); 995 996 nc->op.cmds[0] = NAND_CMD_SEQIN; 997 nc->op.ncmds = 1; 998 atmel_nfc_set_op_addr(chip, page, 0x0); 999 nc->op.cs = nand->activecs->id; 1000 nc->op.data = ATMEL_NFC_WRITE_DATA; 1001 1002 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw); 1003 if (ret) 1004 return ret; 1005 1006 ret = atmel_nfc_exec_op(nc, false); 1007 if (ret) { 1008 atmel_nand_pmecc_disable(chip, raw); 1009 dev_err(nc->base.dev, 1010 "Failed to transfer NAND page data (err = %d)\n", 1011 ret); 1012 return ret; 1013 } 1014 1015 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw); 1016 1017 atmel_nand_pmecc_disable(chip, raw); 1018 1019 if (ret) 1020 return ret; 1021 1022 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 1023 1024 return nand_prog_page_end_op(chip); 1025} 1026 1027static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip, 1028 const u8 *buf, int oob_required, 1029 int page) 1030{ 1031 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page, 1032 false); 1033} 1034 1035static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip, 1036 const u8 *buf, 1037 int oob_required, int page) 1038{ 1039 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page, 1040 true); 1041} 1042 1043static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf, 1044 bool oob_required, int page, 1045 bool raw) 1046{ 1047 struct mtd_info *mtd = nand_to_mtd(chip); 1048 struct atmel_nand *nand = to_atmel_nand(chip); 1049 struct atmel_hsmc_nand_controller *nc; 1050 int ret; 1051 1052 atmel_hsmc_nand_select_target(nand, chip->cur_cs); 1053 nc = to_hsmc_nand_controller(chip->controller); 1054 1055 /* 1056 * Optimized read page accessors only work when the NAND R/B pin is 1057 * connected to a native SoC R/B pin. If that's not the case, fallback 1058 * to the non-optimized one. 1059 */ 1060 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) 1061 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, 1062 raw); 1063 1064 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; 1065 1066 if (mtd->writesize > 512) 1067 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART; 1068 1069 atmel_nfc_set_op_addr(chip, page, 0x0); 1070 nc->op.cs = nand->activecs->id; 1071 nc->op.data = ATMEL_NFC_READ_DATA; 1072 1073 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw); 1074 if (ret) 1075 return ret; 1076 1077 ret = atmel_nfc_exec_op(nc, false); 1078 if (ret) { 1079 atmel_nand_pmecc_disable(chip, raw); 1080 dev_err(nc->base.dev, 1081 "Failed to load NAND page data (err = %d)\n", 1082 ret); 1083 return ret; 1084 } 1085 1086 atmel_nfc_copy_from_sram(chip, buf, true); 1087 1088 ret = atmel_nand_pmecc_correct_data(chip, buf, raw); 1089 1090 atmel_nand_pmecc_disable(chip, raw); 1091 1092 return ret; 1093} 1094 1095static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf, 1096 int oob_required, int page) 1097{ 1098 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page, 1099 false); 1100} 1101 1102static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip, 1103 u8 *buf, int oob_required, 1104 int page) 1105{ 1106 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page, 1107 true); 1108} 1109 1110static int atmel_nand_pmecc_init(struct nand_chip *chip) 1111{ 1112 const struct nand_ecc_props *requirements = 1113 nanddev_get_ecc_requirements(&chip->base); 1114 struct mtd_info *mtd = nand_to_mtd(chip); 1115 struct nand_device *nanddev = mtd_to_nanddev(mtd); 1116 struct atmel_nand *nand = to_atmel_nand(chip); 1117 struct atmel_nand_controller *nc; 1118 struct atmel_pmecc_user_req req; 1119 1120 nc = to_nand_controller(chip->controller); 1121 1122 if (!nc->pmecc) { 1123 dev_err(nc->dev, "HW ECC not supported\n"); 1124 return -ENOTSUPP; 1125 } 1126 1127 if (nc->caps->legacy_of_bindings) { 1128 u32 val; 1129 1130 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap", 1131 &val)) 1132 chip->ecc.strength = val; 1133 1134 if (!of_property_read_u32(nc->dev->of_node, 1135 "atmel,pmecc-sector-size", 1136 &val)) 1137 chip->ecc.size = val; 1138 } 1139 1140 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) 1141 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; 1142 else if (chip->ecc.strength) 1143 req.ecc.strength = chip->ecc.strength; 1144 else if (requirements->strength) 1145 req.ecc.strength = requirements->strength; 1146 else 1147 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; 1148 1149 if (chip->ecc.size) 1150 req.ecc.sectorsize = chip->ecc.size; 1151 else if (requirements->step_size) 1152 req.ecc.sectorsize = requirements->step_size; 1153 else 1154 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; 1155 1156 req.pagesize = mtd->writesize; 1157 req.oobsize = mtd->oobsize; 1158 1159 if (mtd->writesize <= 512) { 1160 req.ecc.bytes = 4; 1161 req.ecc.ooboffset = 0; 1162 } else { 1163 req.ecc.bytes = mtd->oobsize - 2; 1164 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO; 1165 } 1166 1167 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req); 1168 if (IS_ERR(nand->pmecc)) 1169 return PTR_ERR(nand->pmecc); 1170 1171 chip->ecc.algo = NAND_ECC_ALGO_BCH; 1172 chip->ecc.size = req.ecc.sectorsize; 1173 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; 1174 chip->ecc.strength = req.ecc.strength; 1175 1176 chip->options |= NAND_NO_SUBPAGE_WRITE; 1177 1178 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 1179 1180 return 0; 1181} 1182 1183static int atmel_nand_ecc_init(struct nand_chip *chip) 1184{ 1185 struct atmel_nand_controller *nc; 1186 int ret; 1187 1188 nc = to_nand_controller(chip->controller); 1189 1190 switch (chip->ecc.engine_type) { 1191 case NAND_ECC_ENGINE_TYPE_NONE: 1192 case NAND_ECC_ENGINE_TYPE_SOFT: 1193 /* 1194 * Nothing to do, the core will initialize everything for us. 1195 */ 1196 break; 1197 1198 case NAND_ECC_ENGINE_TYPE_ON_HOST: 1199 ret = atmel_nand_pmecc_init(chip); 1200 if (ret) 1201 return ret; 1202 1203 chip->ecc.read_page = atmel_nand_pmecc_read_page; 1204 chip->ecc.write_page = atmel_nand_pmecc_write_page; 1205 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw; 1206 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw; 1207 break; 1208 1209 default: 1210 /* Other modes are not supported. */ 1211 dev_err(nc->dev, "Unsupported ECC mode: %d\n", 1212 chip->ecc.engine_type); 1213 return -ENOTSUPP; 1214 } 1215 1216 return 0; 1217} 1218 1219static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip) 1220{ 1221 int ret; 1222 1223 ret = atmel_nand_ecc_init(chip); 1224 if (ret) 1225 return ret; 1226 1227 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 1228 return 0; 1229 1230 /* Adjust the ECC operations for the HSMC IP. */ 1231 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page; 1232 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; 1233 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; 1234 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; 1235 1236 return 0; 1237} 1238 1239static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, 1240 const struct nand_interface_config *conf, 1241 struct atmel_smc_cs_conf *smcconf) 1242{ 1243 u32 ncycles, totalcycles, timeps, mckperiodps; 1244 struct atmel_nand_controller *nc; 1245 int ret; 1246 1247 nc = to_nand_controller(nand->base.controller); 1248 1249 /* DDR interface not supported. */ 1250 if (!nand_interface_is_sdr(conf)) 1251 return -ENOTSUPP; 1252 1253 /* 1254 * tRC < 30ns implies EDO mode. This controller does not support this 1255 * mode. 1256 */ 1257 if (conf->timings.sdr.tRC_min < 30000) 1258 return -ENOTSUPP; 1259 1260 atmel_smc_cs_conf_init(smcconf); 1261 1262 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck); 1263 mckperiodps *= 1000; 1264 1265 /* 1266 * Set write pulse timing. This one is easy to extract: 1267 * 1268 * NWE_PULSE = tWP 1269 */ 1270 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); 1271 totalcycles = ncycles; 1272 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT, 1273 ncycles); 1274 if (ret) 1275 return ret; 1276 1277 /* 1278 * The write setup timing depends on the operation done on the NAND. 1279 * All operations goes through the same data bus, but the operation 1280 * type depends on the address we are writing to (ALE/CLE address 1281 * lines). 1282 * Since we have no way to differentiate the different operations at 1283 * the SMC level, we must consider the worst case (the biggest setup 1284 * time among all operation types): 1285 * 1286 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE 1287 */ 1288 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, 1289 conf->timings.sdr.tALS_min); 1290 timeps = max(timeps, conf->timings.sdr.tDS_min); 1291 ncycles = DIV_ROUND_UP(timeps, mckperiodps); 1292 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0; 1293 totalcycles += ncycles; 1294 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT, 1295 ncycles); 1296 if (ret) 1297 return ret; 1298 1299 /* 1300 * As for the write setup timing, the write hold timing depends on the 1301 * operation done on the NAND: 1302 * 1303 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH) 1304 */ 1305 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, 1306 conf->timings.sdr.tALH_min); 1307 timeps = max3(timeps, conf->timings.sdr.tDH_min, 1308 conf->timings.sdr.tWH_min); 1309 ncycles = DIV_ROUND_UP(timeps, mckperiodps); 1310 totalcycles += ncycles; 1311 1312 /* 1313 * The write cycle timing is directly matching tWC, but is also 1314 * dependent on the other timings on the setup and hold timings we 1315 * calculated earlier, which gives: 1316 * 1317 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD) 1318 */ 1319 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); 1320 ncycles = max(totalcycles, ncycles); 1321 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT, 1322 ncycles); 1323 if (ret) 1324 return ret; 1325 1326 /* 1327 * We don't want the CS line to be toggled between each byte/word 1328 * transfer to the NAND. The only way to guarantee that is to have the 1329 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means: 1330 * 1331 * NCS_WR_PULSE = NWE_CYCLE 1332 */ 1333 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT, 1334 ncycles); 1335 if (ret) 1336 return ret; 1337 1338 /* 1339 * As for the write setup timing, the read hold timing depends on the 1340 * operation done on the NAND: 1341 * 1342 * NRD_HOLD = max(tREH, tRHOH) 1343 */ 1344 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min); 1345 ncycles = DIV_ROUND_UP(timeps, mckperiodps); 1346 totalcycles = ncycles; 1347 1348 /* 1349 * TDF = tRHZ - NRD_HOLD 1350 */ 1351 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps); 1352 ncycles -= totalcycles; 1353 1354 /* 1355 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and 1356 * we might end up with a config that does not fit in the TDF field. 1357 * Just take the max value in this case and hope that the NAND is more 1358 * tolerant than advertised. 1359 */ 1360 if (ncycles > ATMEL_SMC_MODE_TDF_MAX) 1361 ncycles = ATMEL_SMC_MODE_TDF_MAX; 1362 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN) 1363 ncycles = ATMEL_SMC_MODE_TDF_MIN; 1364 1365 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) | 1366 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED; 1367 1368 /* 1369 * Read pulse timing directly matches tRP: 1370 * 1371 * NRD_PULSE = tRP 1372 */ 1373 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); 1374 totalcycles += ncycles; 1375 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT, 1376 ncycles); 1377 if (ret) 1378 return ret; 1379 1380 /* 1381 * The write cycle timing is directly matching tWC, but is also 1382 * dependent on the setup and hold timings we calculated earlier, 1383 * which gives: 1384 * 1385 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD) 1386 * 1387 * NRD_SETUP is always 0. 1388 */ 1389 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); 1390 ncycles = max(totalcycles, ncycles); 1391 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT, 1392 ncycles); 1393 if (ret) 1394 return ret; 1395 1396 /* 1397 * We don't want the CS line to be toggled between each byte/word 1398 * transfer from the NAND. The only way to guarantee that is to have 1399 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means: 1400 * 1401 * NCS_RD_PULSE = NRD_CYCLE 1402 */ 1403 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT, 1404 ncycles); 1405 if (ret) 1406 return ret; 1407 1408 /* Txxx timings are directly matching tXXX ones. */ 1409 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps); 1410 ret = atmel_smc_cs_conf_set_timing(smcconf, 1411 ATMEL_HSMC_TIMINGS_TCLR_SHIFT, 1412 ncycles); 1413 if (ret) 1414 return ret; 1415 1416 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps); 1417 ret = atmel_smc_cs_conf_set_timing(smcconf, 1418 ATMEL_HSMC_TIMINGS_TADL_SHIFT, 1419 ncycles); 1420 /* 1421 * Version 4 of the ONFI spec mandates that tADL be at least 400 1422 * nanoseconds, but, depending on the master clock rate, 400 ns may not 1423 * fit in the tADL field of the SMC reg. We need to relax the check and 1424 * accept the -ERANGE return code. 1425 * 1426 * Note that previous versions of the ONFI spec had a lower tADL_min 1427 * (100 or 200 ns). It's not clear why this timing constraint got 1428 * increased but it seems most NANDs are fine with values lower than 1429 * 400ns, so we should be safe. 1430 */ 1431 if (ret && ret != -ERANGE) 1432 return ret; 1433 1434 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps); 1435 ret = atmel_smc_cs_conf_set_timing(smcconf, 1436 ATMEL_HSMC_TIMINGS_TAR_SHIFT, 1437 ncycles); 1438 if (ret) 1439 return ret; 1440 1441 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps); 1442 ret = atmel_smc_cs_conf_set_timing(smcconf, 1443 ATMEL_HSMC_TIMINGS_TRR_SHIFT, 1444 ncycles); 1445 if (ret) 1446 return ret; 1447 1448 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); 1449 ret = atmel_smc_cs_conf_set_timing(smcconf, 1450 ATMEL_HSMC_TIMINGS_TWB_SHIFT, 1451 ncycles); 1452 if (ret) 1453 return ret; 1454 1455 /* Attach the CS line to the NFC logic. */ 1456 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL; 1457 1458 /* Set the appropriate data bus width. */ 1459 if (nand->base.options & NAND_BUSWIDTH_16) 1460 smcconf->mode |= ATMEL_SMC_MODE_DBW_16; 1461 1462 /* Operate in NRD/NWE READ/WRITEMODE. */ 1463 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD | 1464 ATMEL_SMC_MODE_WRITEMODE_NWE; 1465 1466 return 0; 1467} 1468 1469static int atmel_smc_nand_setup_interface(struct atmel_nand *nand, 1470 int csline, 1471 const struct nand_interface_config *conf) 1472{ 1473 struct atmel_nand_controller *nc; 1474 struct atmel_smc_cs_conf smcconf; 1475 struct atmel_nand_cs *cs; 1476 int ret; 1477 1478 nc = to_nand_controller(nand->base.controller); 1479 1480 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); 1481 if (ret) 1482 return ret; 1483 1484 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1485 return 0; 1486 1487 cs = &nand->cs[csline]; 1488 cs->smcconf = smcconf; 1489 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); 1490 1491 return 0; 1492} 1493 1494static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand, 1495 int csline, 1496 const struct nand_interface_config *conf) 1497{ 1498 struct atmel_hsmc_nand_controller *nc; 1499 struct atmel_smc_cs_conf smcconf; 1500 struct atmel_nand_cs *cs; 1501 int ret; 1502 1503 nc = to_hsmc_nand_controller(nand->base.controller); 1504 1505 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); 1506 if (ret) 1507 return ret; 1508 1509 if (csline == NAND_DATA_IFACE_CHECK_ONLY) 1510 return 0; 1511 1512 cs = &nand->cs[csline]; 1513 cs->smcconf = smcconf; 1514 1515 if (cs->rb.type == ATMEL_NAND_NATIVE_RB) 1516 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); 1517 1518 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, 1519 &cs->smcconf); 1520 1521 return 0; 1522} 1523 1524static int atmel_nand_setup_interface(struct nand_chip *chip, int csline, 1525 const struct nand_interface_config *conf) 1526{ 1527 struct atmel_nand *nand = to_atmel_nand(chip); 1528 struct atmel_nand_controller *nc; 1529 1530 nc = to_nand_controller(nand->base.controller); 1531 1532 if (csline >= nand->numcs || 1533 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY)) 1534 return -EINVAL; 1535 1536 return nc->caps->ops->setup_interface(nand, csline, conf); 1537} 1538 1539static int atmel_nand_exec_op(struct nand_chip *chip, 1540 const struct nand_operation *op, 1541 bool check_only) 1542{ 1543 struct atmel_nand *nand = to_atmel_nand(chip); 1544 struct atmel_nand_controller *nc; 1545 1546 nc = to_nand_controller(nand->base.controller); 1547 1548 return nc->caps->ops->exec_op(nand, op, check_only); 1549} 1550 1551static void atmel_nand_init(struct atmel_nand_controller *nc, 1552 struct atmel_nand *nand) 1553{ 1554 struct nand_chip *chip = &nand->base; 1555 struct mtd_info *mtd = nand_to_mtd(chip); 1556 1557 mtd->dev.parent = nc->dev; 1558 nand->base.controller = &nc->base; 1559 1560 if (!nc->mck || !nc->caps->ops->setup_interface) 1561 chip->options |= NAND_KEEP_TIMINGS; 1562 1563 /* 1564 * Use a bounce buffer when the buffer passed by the MTD user is not 1565 * suitable for DMA. 1566 */ 1567 if (nc->dmac) 1568 chip->options |= NAND_USES_DMA; 1569 1570 /* Default to HW ECC if pmecc is available. */ 1571 if (nc->pmecc) 1572 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1573} 1574 1575static void atmel_smc_nand_init(struct atmel_nand_controller *nc, 1576 struct atmel_nand *nand) 1577{ 1578 struct nand_chip *chip = &nand->base; 1579 struct atmel_smc_nand_controller *smc_nc; 1580 int i; 1581 1582 atmel_nand_init(nc, nand); 1583 1584 smc_nc = to_smc_nand_controller(chip->controller); 1585 if (!smc_nc->ebi_csa_regmap) 1586 return; 1587 1588 /* Attach the CS to the NAND Flash logic. */ 1589 for (i = 0; i < nand->numcs; i++) 1590 regmap_update_bits(smc_nc->ebi_csa_regmap, 1591 smc_nc->ebi_csa->offs, 1592 BIT(nand->cs[i].id), BIT(nand->cs[i].id)); 1593 1594 if (smc_nc->ebi_csa->nfd0_on_d16) 1595 regmap_update_bits(smc_nc->ebi_csa_regmap, 1596 smc_nc->ebi_csa->offs, 1597 smc_nc->ebi_csa->nfd0_on_d16, 1598 smc_nc->ebi_csa->nfd0_on_d16); 1599} 1600 1601static int atmel_nand_controller_remove_nand(struct atmel_nand *nand) 1602{ 1603 struct nand_chip *chip = &nand->base; 1604 struct mtd_info *mtd = nand_to_mtd(chip); 1605 int ret; 1606 1607 ret = mtd_device_unregister(mtd); 1608 if (ret) 1609 return ret; 1610 1611 nand_cleanup(chip); 1612 list_del(&nand->node); 1613 1614 return 0; 1615} 1616 1617static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc, 1618 struct device_node *np, 1619 int reg_cells) 1620{ 1621 struct atmel_nand *nand; 1622 struct gpio_desc *gpio; 1623 int numcs, ret, i; 1624 1625 numcs = of_property_count_elems_of_size(np, "reg", 1626 reg_cells * sizeof(u32)); 1627 if (numcs < 1) { 1628 dev_err(nc->dev, "Missing or invalid reg property\n"); 1629 return ERR_PTR(-EINVAL); 1630 } 1631 1632 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL); 1633 if (!nand) { 1634 dev_err(nc->dev, "Failed to allocate NAND object\n"); 1635 return ERR_PTR(-ENOMEM); 1636 } 1637 1638 nand->numcs = numcs; 1639 1640 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np), 1641 "det", GPIOD_IN, "nand-det"); 1642 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { 1643 dev_err(nc->dev, 1644 "Failed to get detect gpio (err = %ld)\n", 1645 PTR_ERR(gpio)); 1646 return ERR_CAST(gpio); 1647 } 1648 1649 if (!IS_ERR(gpio)) 1650 nand->cdgpio = gpio; 1651 1652 for (i = 0; i < numcs; i++) { 1653 struct resource res; 1654 u32 val; 1655 1656 ret = of_address_to_resource(np, 0, &res); 1657 if (ret) { 1658 dev_err(nc->dev, "Invalid reg property (err = %d)\n", 1659 ret); 1660 return ERR_PTR(ret); 1661 } 1662 1663 ret = of_property_read_u32_index(np, "reg", i * reg_cells, 1664 &val); 1665 if (ret) { 1666 dev_err(nc->dev, "Invalid reg property (err = %d)\n", 1667 ret); 1668 return ERR_PTR(ret); 1669 } 1670 1671 nand->cs[i].id = val; 1672 1673 nand->cs[i].io.dma = res.start; 1674 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res); 1675 if (IS_ERR(nand->cs[i].io.virt)) 1676 return ERR_CAST(nand->cs[i].io.virt); 1677 1678 if (!of_property_read_u32(np, "atmel,rb", &val)) { 1679 if (val > ATMEL_NFC_MAX_RB_ID) 1680 return ERR_PTR(-EINVAL); 1681 1682 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB; 1683 nand->cs[i].rb.id = val; 1684 } else { 1685 gpio = devm_fwnode_gpiod_get_index(nc->dev, 1686 of_fwnode_handle(np), 1687 "rb", i, GPIOD_IN, 1688 "nand-rb"); 1689 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { 1690 dev_err(nc->dev, 1691 "Failed to get R/B gpio (err = %ld)\n", 1692 PTR_ERR(gpio)); 1693 return ERR_CAST(gpio); 1694 } 1695 1696 if (!IS_ERR(gpio)) { 1697 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB; 1698 nand->cs[i].rb.gpio = gpio; 1699 } 1700 } 1701 1702 gpio = devm_fwnode_gpiod_get_index(nc->dev, 1703 of_fwnode_handle(np), 1704 "cs", i, GPIOD_OUT_HIGH, 1705 "nand-cs"); 1706 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) { 1707 dev_err(nc->dev, 1708 "Failed to get CS gpio (err = %ld)\n", 1709 PTR_ERR(gpio)); 1710 return ERR_CAST(gpio); 1711 } 1712 1713 if (!IS_ERR(gpio)) 1714 nand->cs[i].csgpio = gpio; 1715 } 1716 1717 nand_set_flash_node(&nand->base, np); 1718 1719 return nand; 1720} 1721 1722static int 1723atmel_nand_controller_add_nand(struct atmel_nand_controller *nc, 1724 struct atmel_nand *nand) 1725{ 1726 struct nand_chip *chip = &nand->base; 1727 struct mtd_info *mtd = nand_to_mtd(chip); 1728 int ret; 1729 1730 /* No card inserted, skip this NAND. */ 1731 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) { 1732 dev_info(nc->dev, "No SmartMedia card inserted.\n"); 1733 return 0; 1734 } 1735 1736 nc->caps->ops->nand_init(nc, nand); 1737 1738 ret = nand_scan(chip, nand->numcs); 1739 if (ret) { 1740 dev_err(nc->dev, "NAND scan failed: %d\n", ret); 1741 return ret; 1742 } 1743 1744 ret = mtd_device_register(mtd, NULL, 0); 1745 if (ret) { 1746 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret); 1747 nand_cleanup(chip); 1748 return ret; 1749 } 1750 1751 list_add_tail(&nand->node, &nc->chips); 1752 1753 return 0; 1754} 1755 1756static int 1757atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc) 1758{ 1759 struct atmel_nand *nand, *tmp; 1760 int ret; 1761 1762 list_for_each_entry_safe(nand, tmp, &nc->chips, node) { 1763 ret = atmel_nand_controller_remove_nand(nand); 1764 if (ret) 1765 return ret; 1766 } 1767 1768 return 0; 1769} 1770 1771static int 1772atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc) 1773{ 1774 struct device *dev = nc->dev; 1775 struct platform_device *pdev = to_platform_device(dev); 1776 struct atmel_nand *nand; 1777 struct gpio_desc *gpio; 1778 struct resource *res; 1779 1780 /* 1781 * Legacy bindings only allow connecting a single NAND with a unique CS 1782 * line to the controller. 1783 */ 1784 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs), 1785 GFP_KERNEL); 1786 if (!nand) 1787 return -ENOMEM; 1788 1789 nand->numcs = 1; 1790 1791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1792 nand->cs[0].io.virt = devm_ioremap_resource(dev, res); 1793 if (IS_ERR(nand->cs[0].io.virt)) 1794 return PTR_ERR(nand->cs[0].io.virt); 1795 1796 nand->cs[0].io.dma = res->start; 1797 1798 /* 1799 * The old driver was hardcoding the CS id to 3 for all sama5 1800 * controllers. Since this id is only meaningful for the sama5 1801 * controller we can safely assign this id to 3 no matter the 1802 * controller. 1803 * If one wants to connect a NAND to a different CS line, he will 1804 * have to use the new bindings. 1805 */ 1806 nand->cs[0].id = 3; 1807 1808 /* R/B GPIO. */ 1809 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN); 1810 if (IS_ERR(gpio)) { 1811 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n", 1812 PTR_ERR(gpio)); 1813 return PTR_ERR(gpio); 1814 } 1815 1816 if (gpio) { 1817 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB; 1818 nand->cs[0].rb.gpio = gpio; 1819 } 1820 1821 /* CS GPIO. */ 1822 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH); 1823 if (IS_ERR(gpio)) { 1824 dev_err(dev, "Failed to get CS gpio (err = %ld)\n", 1825 PTR_ERR(gpio)); 1826 return PTR_ERR(gpio); 1827 } 1828 1829 nand->cs[0].csgpio = gpio; 1830 1831 /* Card detect GPIO. */ 1832 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN); 1833 if (IS_ERR(gpio)) { 1834 dev_err(dev, 1835 "Failed to get detect gpio (err = %ld)\n", 1836 PTR_ERR(gpio)); 1837 return PTR_ERR(gpio); 1838 } 1839 1840 nand->cdgpio = gpio; 1841 1842 nand_set_flash_node(&nand->base, nc->dev->of_node); 1843 1844 return atmel_nand_controller_add_nand(nc, nand); 1845} 1846 1847static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc) 1848{ 1849 struct device_node *np, *nand_np; 1850 struct device *dev = nc->dev; 1851 int ret, reg_cells; 1852 u32 val; 1853 1854 /* We do not retrieve the SMC syscon when parsing old DTs. */ 1855 if (nc->caps->legacy_of_bindings) 1856 return atmel_nand_controller_legacy_add_nands(nc); 1857 1858 np = dev->of_node; 1859 1860 ret = of_property_read_u32(np, "#address-cells", &val); 1861 if (ret) { 1862 dev_err(dev, "missing #address-cells property\n"); 1863 return ret; 1864 } 1865 1866 reg_cells = val; 1867 1868 ret = of_property_read_u32(np, "#size-cells", &val); 1869 if (ret) { 1870 dev_err(dev, "missing #size-cells property\n"); 1871 return ret; 1872 } 1873 1874 reg_cells += val; 1875 1876 for_each_child_of_node(np, nand_np) { 1877 struct atmel_nand *nand; 1878 1879 nand = atmel_nand_create(nc, nand_np, reg_cells); 1880 if (IS_ERR(nand)) { 1881 ret = PTR_ERR(nand); 1882 goto err; 1883 } 1884 1885 ret = atmel_nand_controller_add_nand(nc, nand); 1886 if (ret) 1887 goto err; 1888 } 1889 1890 return 0; 1891 1892err: 1893 atmel_nand_controller_remove_nands(nc); 1894 1895 return ret; 1896} 1897 1898static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc) 1899{ 1900 if (nc->dmac) 1901 dma_release_channel(nc->dmac); 1902 1903 clk_put(nc->mck); 1904} 1905 1906static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = { 1907 .offs = AT91SAM9260_MATRIX_EBICSA, 1908}; 1909 1910static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = { 1911 .offs = AT91SAM9261_MATRIX_EBICSA, 1912}; 1913 1914static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = { 1915 .offs = AT91SAM9263_MATRIX_EBI0CSA, 1916}; 1917 1918static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = { 1919 .offs = AT91SAM9RL_MATRIX_EBICSA, 1920}; 1921 1922static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = { 1923 .offs = AT91SAM9G45_MATRIX_EBICSA, 1924}; 1925 1926static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = { 1927 .offs = AT91SAM9N12_MATRIX_EBICSA, 1928}; 1929 1930static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = { 1931 .offs = AT91SAM9X5_MATRIX_EBICSA, 1932}; 1933 1934static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = { 1935 .offs = AT91_SFR_CCFG_EBICSA, 1936 .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16, 1937}; 1938 1939static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = { 1940 { 1941 .compatible = "atmel,at91sam9260-matrix", 1942 .data = &at91sam9260_ebi_csa, 1943 }, 1944 { 1945 .compatible = "atmel,at91sam9261-matrix", 1946 .data = &at91sam9261_ebi_csa, 1947 }, 1948 { 1949 .compatible = "atmel,at91sam9263-matrix", 1950 .data = &at91sam9263_ebi_csa, 1951 }, 1952 { 1953 .compatible = "atmel,at91sam9rl-matrix", 1954 .data = &at91sam9rl_ebi_csa, 1955 }, 1956 { 1957 .compatible = "atmel,at91sam9g45-matrix", 1958 .data = &at91sam9g45_ebi_csa, 1959 }, 1960 { 1961 .compatible = "atmel,at91sam9n12-matrix", 1962 .data = &at91sam9n12_ebi_csa, 1963 }, 1964 { 1965 .compatible = "atmel,at91sam9x5-matrix", 1966 .data = &at91sam9x5_ebi_csa, 1967 }, 1968 { 1969 .compatible = "microchip,sam9x60-sfr", 1970 .data = &sam9x60_ebi_csa, 1971 }, 1972 { /* sentinel */ }, 1973}; 1974 1975static int atmel_nand_attach_chip(struct nand_chip *chip) 1976{ 1977 struct atmel_nand_controller *nc = to_nand_controller(chip->controller); 1978 struct atmel_nand *nand = to_atmel_nand(chip); 1979 struct mtd_info *mtd = nand_to_mtd(chip); 1980 int ret; 1981 1982 ret = nc->caps->ops->ecc_init(chip); 1983 if (ret) 1984 return ret; 1985 1986 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) { 1987 /* 1988 * We keep the MTD name unchanged to avoid breaking platforms 1989 * where the MTD cmdline parser is used and the bootloader 1990 * has not been updated to use the new naming scheme. 1991 */ 1992 mtd->name = "atmel_nand"; 1993 } else if (!mtd->name) { 1994 /* 1995 * If the new bindings are used and the bootloader has not been 1996 * updated to pass a new mtdparts parameter on the cmdline, you 1997 * should define the following property in your nand node: 1998 * 1999 * label = "atmel_nand"; 2000 * 2001 * This way, mtd->name will be set by the core when 2002 * nand_set_flash_node() is called. 2003 */ 2004 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL, 2005 "%s:nand.%d", dev_name(nc->dev), 2006 nand->cs[0].id); 2007 if (!mtd->name) { 2008 dev_err(nc->dev, "Failed to allocate mtd->name\n"); 2009 return -ENOMEM; 2010 } 2011 } 2012 2013 return 0; 2014} 2015 2016static const struct nand_controller_ops atmel_nand_controller_ops = { 2017 .attach_chip = atmel_nand_attach_chip, 2018 .setup_interface = atmel_nand_setup_interface, 2019 .exec_op = atmel_nand_exec_op, 2020}; 2021 2022static int atmel_nand_controller_init(struct atmel_nand_controller *nc, 2023 struct platform_device *pdev, 2024 const struct atmel_nand_controller_caps *caps) 2025{ 2026 struct device *dev = &pdev->dev; 2027 struct device_node *np = dev->of_node; 2028 int ret; 2029 2030 nand_controller_init(&nc->base); 2031 nc->base.ops = &atmel_nand_controller_ops; 2032 INIT_LIST_HEAD(&nc->chips); 2033 nc->dev = dev; 2034 nc->caps = caps; 2035 2036 platform_set_drvdata(pdev, nc); 2037 2038 nc->pmecc = devm_atmel_pmecc_get(dev); 2039 if (IS_ERR(nc->pmecc)) 2040 return dev_err_probe(dev, PTR_ERR(nc->pmecc), 2041 "Could not get PMECC object\n"); 2042 2043 if (nc->caps->has_dma && !atmel_nand_avoid_dma) { 2044 dma_cap_mask_t mask; 2045 2046 dma_cap_zero(mask); 2047 dma_cap_set(DMA_MEMCPY, mask); 2048 2049 nc->dmac = dma_request_channel(mask, NULL, NULL); 2050 if (!nc->dmac) 2051 dev_err(nc->dev, "Failed to request DMA channel\n"); 2052 } 2053 2054 /* We do not retrieve the SMC syscon when parsing old DTs. */ 2055 if (nc->caps->legacy_of_bindings) 2056 return 0; 2057 2058 nc->mck = of_clk_get(dev->parent->of_node, 0); 2059 if (IS_ERR(nc->mck)) { 2060 dev_err(dev, "Failed to retrieve MCK clk\n"); 2061 ret = PTR_ERR(nc->mck); 2062 goto out_release_dma; 2063 } 2064 2065 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); 2066 if (!np) { 2067 dev_err(dev, "Missing or invalid atmel,smc property\n"); 2068 ret = -EINVAL; 2069 goto out_release_dma; 2070 } 2071 2072 nc->smc = syscon_node_to_regmap(np); 2073 of_node_put(np); 2074 if (IS_ERR(nc->smc)) { 2075 ret = PTR_ERR(nc->smc); 2076 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret); 2077 goto out_release_dma; 2078 } 2079 2080 return 0; 2081 2082out_release_dma: 2083 if (nc->dmac) 2084 dma_release_channel(nc->dmac); 2085 2086 return ret; 2087} 2088 2089static int 2090atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc) 2091{ 2092 struct device *dev = nc->base.dev; 2093 const struct of_device_id *match; 2094 struct device_node *np; 2095 int ret; 2096 2097 /* We do not retrieve the EBICSA regmap when parsing old DTs. */ 2098 if (nc->base.caps->legacy_of_bindings) 2099 return 0; 2100 2101 np = of_parse_phandle(dev->parent->of_node, 2102 nc->base.caps->ebi_csa_regmap_name, 0); 2103 if (!np) 2104 return 0; 2105 2106 match = of_match_node(atmel_ebi_csa_regmap_of_ids, np); 2107 if (!match) { 2108 of_node_put(np); 2109 return 0; 2110 } 2111 2112 nc->ebi_csa_regmap = syscon_node_to_regmap(np); 2113 of_node_put(np); 2114 if (IS_ERR(nc->ebi_csa_regmap)) { 2115 ret = PTR_ERR(nc->ebi_csa_regmap); 2116 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret); 2117 return ret; 2118 } 2119 2120 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data; 2121 2122 /* 2123 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1 2124 * add 4 to ->ebi_csa->offs. 2125 */ 2126 if (of_device_is_compatible(dev->parent->of_node, 2127 "atmel,at91sam9263-ebi1")) 2128 nc->ebi_csa->offs += 4; 2129 2130 return 0; 2131} 2132 2133static int 2134atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc) 2135{ 2136 struct regmap_config regmap_conf = { 2137 .reg_bits = 32, 2138 .val_bits = 32, 2139 .reg_stride = 4, 2140 }; 2141 2142 struct device *dev = nc->base.dev; 2143 struct device_node *nand_np, *nfc_np; 2144 void __iomem *iomem; 2145 struct resource res; 2146 int ret; 2147 2148 nand_np = dev->of_node; 2149 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc"); 2150 if (!nfc_np) { 2151 dev_err(dev, "Could not find device node for sama5d3-nfc\n"); 2152 return -ENODEV; 2153 } 2154 2155 nc->clk = of_clk_get(nfc_np, 0); 2156 if (IS_ERR(nc->clk)) { 2157 ret = PTR_ERR(nc->clk); 2158 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n", 2159 ret); 2160 goto out; 2161 } 2162 2163 ret = clk_prepare_enable(nc->clk); 2164 if (ret) { 2165 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n", 2166 ret); 2167 goto out; 2168 } 2169 2170 nc->irq = of_irq_get(nand_np, 0); 2171 if (nc->irq <= 0) { 2172 ret = nc->irq ?: -ENXIO; 2173 if (ret != -EPROBE_DEFER) 2174 dev_err(dev, "Failed to get IRQ number (err = %d)\n", 2175 ret); 2176 goto out; 2177 } 2178 2179 ret = of_address_to_resource(nfc_np, 0, &res); 2180 if (ret) { 2181 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n", 2182 ret); 2183 goto out; 2184 } 2185 2186 iomem = devm_ioremap_resource(dev, &res); 2187 if (IS_ERR(iomem)) { 2188 ret = PTR_ERR(iomem); 2189 goto out; 2190 } 2191 2192 regmap_conf.name = "nfc-io"; 2193 regmap_conf.max_register = resource_size(&res) - 4; 2194 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf); 2195 if (IS_ERR(nc->io)) { 2196 ret = PTR_ERR(nc->io); 2197 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n", 2198 ret); 2199 goto out; 2200 } 2201 2202 ret = of_address_to_resource(nfc_np, 1, &res); 2203 if (ret) { 2204 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n", 2205 ret); 2206 goto out; 2207 } 2208 2209 iomem = devm_ioremap_resource(dev, &res); 2210 if (IS_ERR(iomem)) { 2211 ret = PTR_ERR(iomem); 2212 goto out; 2213 } 2214 2215 regmap_conf.name = "smc"; 2216 regmap_conf.max_register = resource_size(&res) - 4; 2217 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf); 2218 if (IS_ERR(nc->base.smc)) { 2219 ret = PTR_ERR(nc->base.smc); 2220 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n", 2221 ret); 2222 goto out; 2223 } 2224 2225 ret = of_address_to_resource(nfc_np, 2, &res); 2226 if (ret) { 2227 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n", 2228 ret); 2229 goto out; 2230 } 2231 2232 nc->sram.virt = devm_ioremap_resource(dev, &res); 2233 if (IS_ERR(nc->sram.virt)) { 2234 ret = PTR_ERR(nc->sram.virt); 2235 goto out; 2236 } 2237 2238 nc->sram.dma = res.start; 2239 2240out: 2241 of_node_put(nfc_np); 2242 2243 return ret; 2244} 2245 2246static int 2247atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc) 2248{ 2249 struct device *dev = nc->base.dev; 2250 struct device_node *np; 2251 int ret; 2252 2253 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0); 2254 if (!np) { 2255 dev_err(dev, "Missing or invalid atmel,smc property\n"); 2256 return -EINVAL; 2257 } 2258 2259 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np); 2260 2261 nc->irq = of_irq_get(np, 0); 2262 of_node_put(np); 2263 if (nc->irq <= 0) { 2264 ret = nc->irq ?: -ENXIO; 2265 if (ret != -EPROBE_DEFER) 2266 dev_err(dev, "Failed to get IRQ number (err = %d)\n", 2267 ret); 2268 return ret; 2269 } 2270 2271 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0); 2272 if (!np) { 2273 dev_err(dev, "Missing or invalid atmel,nfc-io property\n"); 2274 return -EINVAL; 2275 } 2276 2277 nc->io = syscon_node_to_regmap(np); 2278 of_node_put(np); 2279 if (IS_ERR(nc->io)) { 2280 ret = PTR_ERR(nc->io); 2281 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret); 2282 return ret; 2283 } 2284 2285 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node, 2286 "atmel,nfc-sram", 0); 2287 if (!nc->sram.pool) { 2288 dev_err(nc->base.dev, "Missing SRAM\n"); 2289 return -ENOMEM; 2290 } 2291 2292 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool, 2293 ATMEL_NFC_SRAM_SIZE, 2294 &nc->sram.dma); 2295 if (!nc->sram.virt) { 2296 dev_err(nc->base.dev, 2297 "Could not allocate memory from the NFC SRAM pool\n"); 2298 return -ENOMEM; 2299 } 2300 2301 return 0; 2302} 2303 2304static int 2305atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc) 2306{ 2307 struct atmel_hsmc_nand_controller *hsmc_nc; 2308 int ret; 2309 2310 ret = atmel_nand_controller_remove_nands(nc); 2311 if (ret) 2312 return ret; 2313 2314 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base); 2315 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL, 2316 ATMEL_HSMC_NFC_CTRL_DIS); 2317 2318 if (hsmc_nc->sram.pool) 2319 gen_pool_free(hsmc_nc->sram.pool, 2320 (unsigned long)hsmc_nc->sram.virt, 2321 ATMEL_NFC_SRAM_SIZE); 2322 2323 if (hsmc_nc->clk) { 2324 clk_disable_unprepare(hsmc_nc->clk); 2325 clk_put(hsmc_nc->clk); 2326 } 2327 2328 atmel_nand_controller_cleanup(nc); 2329 2330 return 0; 2331} 2332 2333static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev, 2334 const struct atmel_nand_controller_caps *caps) 2335{ 2336 struct device *dev = &pdev->dev; 2337 struct atmel_hsmc_nand_controller *nc; 2338 int ret; 2339 2340 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL); 2341 if (!nc) 2342 return -ENOMEM; 2343 2344 ret = atmel_nand_controller_init(&nc->base, pdev, caps); 2345 if (ret) 2346 return ret; 2347 2348 if (caps->legacy_of_bindings) 2349 ret = atmel_hsmc_nand_controller_legacy_init(nc); 2350 else 2351 ret = atmel_hsmc_nand_controller_init(nc); 2352 2353 if (ret) 2354 return ret; 2355 2356 /* Make sure all irqs are masked before registering our IRQ handler. */ 2357 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); 2358 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt, 2359 IRQF_SHARED, "nfc", nc); 2360 if (ret) { 2361 dev_err(dev, 2362 "Could not get register NFC interrupt handler (err = %d)\n", 2363 ret); 2364 goto err; 2365 } 2366 2367 /* Initial NFC configuration. */ 2368 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, 2369 ATMEL_HSMC_NFC_CFG_DTO_MAX); 2370 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, 2371 ATMEL_HSMC_NFC_CTRL_EN); 2372 2373 ret = atmel_nand_controller_add_nands(&nc->base); 2374 if (ret) 2375 goto err; 2376 2377 return 0; 2378 2379err: 2380 atmel_hsmc_nand_controller_remove(&nc->base); 2381 2382 return ret; 2383} 2384 2385static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = { 2386 .probe = atmel_hsmc_nand_controller_probe, 2387 .remove = atmel_hsmc_nand_controller_remove, 2388 .ecc_init = atmel_hsmc_nand_ecc_init, 2389 .nand_init = atmel_nand_init, 2390 .setup_interface = atmel_hsmc_nand_setup_interface, 2391 .exec_op = atmel_hsmc_nand_exec_op, 2392}; 2393 2394static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = { 2395 .has_dma = true, 2396 .ale_offs = BIT(21), 2397 .cle_offs = BIT(22), 2398 .ops = &atmel_hsmc_nc_ops, 2399}; 2400 2401/* Only used to parse old bindings. */ 2402static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = { 2403 .has_dma = true, 2404 .ale_offs = BIT(21), 2405 .cle_offs = BIT(22), 2406 .ops = &atmel_hsmc_nc_ops, 2407 .legacy_of_bindings = true, 2408}; 2409 2410static int atmel_smc_nand_controller_probe(struct platform_device *pdev, 2411 const struct atmel_nand_controller_caps *caps) 2412{ 2413 struct device *dev = &pdev->dev; 2414 struct atmel_smc_nand_controller *nc; 2415 int ret; 2416 2417 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL); 2418 if (!nc) 2419 return -ENOMEM; 2420 2421 ret = atmel_nand_controller_init(&nc->base, pdev, caps); 2422 if (ret) 2423 return ret; 2424 2425 ret = atmel_smc_nand_controller_init(nc); 2426 if (ret) 2427 return ret; 2428 2429 return atmel_nand_controller_add_nands(&nc->base); 2430} 2431 2432static int 2433atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc) 2434{ 2435 int ret; 2436 2437 ret = atmel_nand_controller_remove_nands(nc); 2438 if (ret) 2439 return ret; 2440 2441 atmel_nand_controller_cleanup(nc); 2442 2443 return 0; 2444} 2445 2446/* 2447 * The SMC reg layout of at91rm9200 is completely different which prevents us 2448 * from re-using atmel_smc_nand_setup_interface() for the 2449 * ->setup_interface() hook. 2450 * At this point, there's no support for the at91rm9200 SMC IP, so we leave 2451 * ->setup_interface() unassigned. 2452 */ 2453static const struct atmel_nand_controller_ops at91rm9200_nc_ops = { 2454 .probe = atmel_smc_nand_controller_probe, 2455 .remove = atmel_smc_nand_controller_remove, 2456 .ecc_init = atmel_nand_ecc_init, 2457 .nand_init = atmel_smc_nand_init, 2458 .exec_op = atmel_smc_nand_exec_op, 2459}; 2460 2461static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = { 2462 .ale_offs = BIT(21), 2463 .cle_offs = BIT(22), 2464 .ebi_csa_regmap_name = "atmel,matrix", 2465 .ops = &at91rm9200_nc_ops, 2466}; 2467 2468static const struct atmel_nand_controller_ops atmel_smc_nc_ops = { 2469 .probe = atmel_smc_nand_controller_probe, 2470 .remove = atmel_smc_nand_controller_remove, 2471 .ecc_init = atmel_nand_ecc_init, 2472 .nand_init = atmel_smc_nand_init, 2473 .setup_interface = atmel_smc_nand_setup_interface, 2474 .exec_op = atmel_smc_nand_exec_op, 2475}; 2476 2477static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = { 2478 .ale_offs = BIT(21), 2479 .cle_offs = BIT(22), 2480 .ebi_csa_regmap_name = "atmel,matrix", 2481 .ops = &atmel_smc_nc_ops, 2482}; 2483 2484static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = { 2485 .ale_offs = BIT(22), 2486 .cle_offs = BIT(21), 2487 .ebi_csa_regmap_name = "atmel,matrix", 2488 .ops = &atmel_smc_nc_ops, 2489}; 2490 2491static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = { 2492 .has_dma = true, 2493 .ale_offs = BIT(21), 2494 .cle_offs = BIT(22), 2495 .ebi_csa_regmap_name = "atmel,matrix", 2496 .ops = &atmel_smc_nc_ops, 2497}; 2498 2499static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = { 2500 .has_dma = true, 2501 .ale_offs = BIT(21), 2502 .cle_offs = BIT(22), 2503 .ebi_csa_regmap_name = "microchip,sfr", 2504 .ops = &atmel_smc_nc_ops, 2505}; 2506 2507/* Only used to parse old bindings. */ 2508static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = { 2509 .ale_offs = BIT(21), 2510 .cle_offs = BIT(22), 2511 .ops = &atmel_smc_nc_ops, 2512 .legacy_of_bindings = true, 2513}; 2514 2515static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = { 2516 .ale_offs = BIT(22), 2517 .cle_offs = BIT(21), 2518 .ops = &atmel_smc_nc_ops, 2519 .legacy_of_bindings = true, 2520}; 2521 2522static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = { 2523 .has_dma = true, 2524 .ale_offs = BIT(21), 2525 .cle_offs = BIT(22), 2526 .ops = &atmel_smc_nc_ops, 2527 .legacy_of_bindings = true, 2528}; 2529 2530static const struct of_device_id atmel_nand_controller_of_ids[] = { 2531 { 2532 .compatible = "atmel,at91rm9200-nand-controller", 2533 .data = &atmel_rm9200_nc_caps, 2534 }, 2535 { 2536 .compatible = "atmel,at91sam9260-nand-controller", 2537 .data = &atmel_sam9260_nc_caps, 2538 }, 2539 { 2540 .compatible = "atmel,at91sam9261-nand-controller", 2541 .data = &atmel_sam9261_nc_caps, 2542 }, 2543 { 2544 .compatible = "atmel,at91sam9g45-nand-controller", 2545 .data = &atmel_sam9g45_nc_caps, 2546 }, 2547 { 2548 .compatible = "atmel,sama5d3-nand-controller", 2549 .data = &atmel_sama5_nc_caps, 2550 }, 2551 { 2552 .compatible = "microchip,sam9x60-nand-controller", 2553 .data = µchip_sam9x60_nc_caps, 2554 }, 2555 /* Support for old/deprecated bindings: */ 2556 { 2557 .compatible = "atmel,at91rm9200-nand", 2558 .data = &atmel_rm9200_nand_caps, 2559 }, 2560 { 2561 .compatible = "atmel,sama5d4-nand", 2562 .data = &atmel_rm9200_nand_caps, 2563 }, 2564 { 2565 .compatible = "atmel,sama5d2-nand", 2566 .data = &atmel_rm9200_nand_caps, 2567 }, 2568 { /* sentinel */ }, 2569}; 2570MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids); 2571 2572static int atmel_nand_controller_probe(struct platform_device *pdev) 2573{ 2574 const struct atmel_nand_controller_caps *caps; 2575 2576 if (pdev->id_entry) 2577 caps = (void *)pdev->id_entry->driver_data; 2578 else 2579 caps = of_device_get_match_data(&pdev->dev); 2580 2581 if (!caps) { 2582 dev_err(&pdev->dev, "Could not retrieve NFC caps\n"); 2583 return -EINVAL; 2584 } 2585 2586 if (caps->legacy_of_bindings) { 2587 struct device_node *nfc_node; 2588 u32 ale_offs = 21; 2589 2590 /* 2591 * If we are parsing legacy DT props and the DT contains a 2592 * valid NFC node, forward the request to the sama5 logic. 2593 */ 2594 nfc_node = of_get_compatible_child(pdev->dev.of_node, 2595 "atmel,sama5d3-nfc"); 2596 if (nfc_node) { 2597 caps = &atmel_sama5_nand_caps; 2598 of_node_put(nfc_node); 2599 } 2600 2601 /* 2602 * Even if the compatible says we are dealing with an 2603 * at91rm9200 controller, the atmel,nand-has-dma specify that 2604 * this controller supports DMA, which means we are in fact 2605 * dealing with an at91sam9g45+ controller. 2606 */ 2607 if (!caps->has_dma && 2608 of_property_read_bool(pdev->dev.of_node, 2609 "atmel,nand-has-dma")) 2610 caps = &atmel_sam9g45_nand_caps; 2611 2612 /* 2613 * All SoCs except the at91sam9261 are assigning ALE to A21 and 2614 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're 2615 * actually dealing with an at91sam9261 controller. 2616 */ 2617 of_property_read_u32(pdev->dev.of_node, 2618 "atmel,nand-addr-offset", &ale_offs); 2619 if (ale_offs != 21) 2620 caps = &atmel_sam9261_nand_caps; 2621 } 2622 2623 return caps->ops->probe(pdev, caps); 2624} 2625 2626static int atmel_nand_controller_remove(struct platform_device *pdev) 2627{ 2628 struct atmel_nand_controller *nc = platform_get_drvdata(pdev); 2629 2630 return nc->caps->ops->remove(nc); 2631} 2632 2633static __maybe_unused int atmel_nand_controller_resume(struct device *dev) 2634{ 2635 struct atmel_nand_controller *nc = dev_get_drvdata(dev); 2636 struct atmel_nand *nand; 2637 2638 if (nc->pmecc) 2639 atmel_pmecc_reset(nc->pmecc); 2640 2641 list_for_each_entry(nand, &nc->chips, node) { 2642 int i; 2643 2644 for (i = 0; i < nand->numcs; i++) 2645 nand_reset(&nand->base, i); 2646 } 2647 2648 return 0; 2649} 2650 2651static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL, 2652 atmel_nand_controller_resume); 2653 2654static struct platform_driver atmel_nand_controller_driver = { 2655 .driver = { 2656 .name = "atmel-nand-controller", 2657 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids), 2658 .pm = &atmel_nand_controller_pm_ops, 2659 }, 2660 .probe = atmel_nand_controller_probe, 2661 .remove = atmel_nand_controller_remove, 2662}; 2663module_platform_driver(atmel_nand_controller_driver); 2664 2665MODULE_LICENSE("GPL"); 2666MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>"); 2667MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs"); 2668MODULE_ALIAS("platform:atmel-nand-controller"); 2669