1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c 4 * 5 * Copyright (C) 2013 ARM Limited 6 * Copyright (C) 2017 Red Hat 7 */ 8 9#include <linux/atomic.h> 10#include <linux/bitfield.h> 11#include <linux/clk.h> 12#include <linux/delay.h> 13#include <linux/dma-iommu.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/interrupt.h> 17#include <linux/io.h> 18#include <linux/io-64-nonatomic-hi-lo.h> 19#include <linux/io-pgtable.h> 20#include <linux/iommu.h> 21#include <linux/iopoll.h> 22#include <linux/kconfig.h> 23#include <linux/init.h> 24#include <linux/mutex.h> 25#include <linux/of.h> 26#include <linux/of_address.h> 27#include <linux/of_device.h> 28#include <linux/of_iommu.h> 29#include <linux/platform_device.h> 30#include <linux/pm.h> 31#include <linux/pm_runtime.h> 32#include <linux/qcom_scm.h> 33#include <linux/slab.h> 34#include <linux/spinlock.h> 35 36#include "arm-smmu.h" 37 38#define SMMU_INTR_SEL_NS 0x2000 39 40enum qcom_iommu_clk { 41 CLK_IFACE, 42 CLK_BUS, 43 CLK_TBU, 44 CLK_NUM, 45}; 46 47struct qcom_iommu_ctx; 48 49struct qcom_iommu_dev { 50 /* IOMMU core code handle */ 51 struct iommu_device iommu; 52 struct device *dev; 53 struct clk_bulk_data clks[CLK_NUM]; 54 void __iomem *local_base; 55 u32 sec_id; 56 u8 num_ctxs; 57 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */ 58}; 59 60struct qcom_iommu_ctx { 61 struct device *dev; 62 void __iomem *base; 63 bool secure_init; 64 u8 asid; /* asid and ctx bank # are 1:1 */ 65 struct iommu_domain *domain; 66}; 67 68struct qcom_iommu_domain { 69 struct io_pgtable_ops *pgtbl_ops; 70 spinlock_t pgtbl_lock; 71 struct mutex init_mutex; /* Protects iommu pointer */ 72 struct iommu_domain domain; 73 struct qcom_iommu_dev *iommu; 74 struct iommu_fwspec *fwspec; 75}; 76 77static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom) 78{ 79 return container_of(dom, struct qcom_iommu_domain, domain); 80} 81 82static const struct iommu_ops qcom_iommu_ops; 83 84static struct qcom_iommu_dev * to_iommu(struct device *dev) 85{ 86 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 87 88 if (!fwspec || fwspec->ops != &qcom_iommu_ops) 89 return NULL; 90 91 return dev_iommu_priv_get(dev); 92} 93 94static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) 95{ 96 struct qcom_iommu_dev *qcom_iommu = d->iommu; 97 if (!qcom_iommu) 98 return NULL; 99 return qcom_iommu->ctxs[asid - 1]; 100} 101 102static inline void 103iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val) 104{ 105 writel_relaxed(val, ctx->base + reg); 106} 107 108static inline void 109iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val) 110{ 111 writeq_relaxed(val, ctx->base + reg); 112} 113 114static inline u32 115iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg) 116{ 117 return readl_relaxed(ctx->base + reg); 118} 119 120static inline u64 121iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) 122{ 123 return readq_relaxed(ctx->base + reg); 124} 125 126static void qcom_iommu_tlb_sync(void *cookie) 127{ 128 struct qcom_iommu_domain *qcom_domain = cookie; 129 struct iommu_fwspec *fwspec = qcom_domain->fwspec; 130 unsigned i; 131 132 for (i = 0; i < fwspec->num_ids; i++) { 133 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 134 unsigned int val, ret; 135 136 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0); 137 138 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, 139 (val & 0x1) == 0, 0, 5000000); 140 if (ret) 141 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n"); 142 } 143} 144 145static void qcom_iommu_tlb_inv_context(void *cookie) 146{ 147 struct qcom_iommu_domain *qcom_domain = cookie; 148 struct iommu_fwspec *fwspec = qcom_domain->fwspec; 149 unsigned i; 150 151 for (i = 0; i < fwspec->num_ids; i++) { 152 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 153 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); 154 } 155 156 qcom_iommu_tlb_sync(cookie); 157} 158 159static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, 160 size_t granule, bool leaf, void *cookie) 161{ 162 struct qcom_iommu_domain *qcom_domain = cookie; 163 struct iommu_fwspec *fwspec = qcom_domain->fwspec; 164 unsigned i, reg; 165 166 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; 167 168 for (i = 0; i < fwspec->num_ids; i++) { 169 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 170 size_t s = size; 171 172 iova = (iova >> 12) << 12; 173 iova |= ctx->asid; 174 do { 175 iommu_writel(ctx, reg, iova); 176 iova += granule; 177 } while (s -= granule); 178 } 179} 180 181static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size, 182 size_t granule, void *cookie) 183{ 184 qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie); 185 qcom_iommu_tlb_sync(cookie); 186} 187 188static void qcom_iommu_tlb_flush_leaf(unsigned long iova, size_t size, 189 size_t granule, void *cookie) 190{ 191 qcom_iommu_tlb_inv_range_nosync(iova, size, granule, true, cookie); 192 qcom_iommu_tlb_sync(cookie); 193} 194 195static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather, 196 unsigned long iova, size_t granule, 197 void *cookie) 198{ 199 qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie); 200} 201 202static const struct iommu_flush_ops qcom_flush_ops = { 203 .tlb_flush_all = qcom_iommu_tlb_inv_context, 204 .tlb_flush_walk = qcom_iommu_tlb_flush_walk, 205 .tlb_flush_leaf = qcom_iommu_tlb_flush_leaf, 206 .tlb_add_page = qcom_iommu_tlb_add_page, 207}; 208 209static irqreturn_t qcom_iommu_fault(int irq, void *dev) 210{ 211 struct qcom_iommu_ctx *ctx = dev; 212 u32 fsr, fsynr; 213 u64 iova; 214 215 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR); 216 217 if (!(fsr & ARM_SMMU_FSR_FAULT)) 218 return IRQ_NONE; 219 220 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0); 221 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR); 222 223 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) { 224 dev_err_ratelimited(ctx->dev, 225 "Unhandled context fault: fsr=0x%x, " 226 "iova=0x%016llx, fsynr=0x%x, cb=%d\n", 227 fsr, iova, fsynr, ctx->asid); 228 } 229 230 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr); 231 iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE); 232 233 return IRQ_HANDLED; 234} 235 236static int qcom_iommu_init_domain(struct iommu_domain *domain, 237 struct qcom_iommu_dev *qcom_iommu, 238 struct device *dev) 239{ 240 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 241 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 242 struct io_pgtable_ops *pgtbl_ops; 243 struct io_pgtable_cfg pgtbl_cfg; 244 int i, ret = 0; 245 u32 reg; 246 247 mutex_lock(&qcom_domain->init_mutex); 248 if (qcom_domain->iommu) 249 goto out_unlock; 250 251 pgtbl_cfg = (struct io_pgtable_cfg) { 252 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap, 253 .ias = 32, 254 .oas = 40, 255 .tlb = &qcom_flush_ops, 256 .iommu_dev = qcom_iommu->dev, 257 }; 258 259 qcom_domain->iommu = qcom_iommu; 260 qcom_domain->fwspec = fwspec; 261 262 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain); 263 if (!pgtbl_ops) { 264 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n"); 265 ret = -ENOMEM; 266 goto out_clear_iommu; 267 } 268 269 /* Update the domain's page sizes to reflect the page table format */ 270 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; 271 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; 272 domain->geometry.force_aperture = true; 273 274 for (i = 0; i < fwspec->num_ids; i++) { 275 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 276 277 if (!ctx->secure_init) { 278 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); 279 if (ret) { 280 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret); 281 goto out_clear_iommu; 282 } 283 ctx->secure_init = true; 284 } 285 286 /* Disable context bank before programming */ 287 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); 288 289 /* Clear context bank fault address fault status registers */ 290 iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); 291 iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); 292 293 /* TTBRs */ 294 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 295 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | 296 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); 297 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); 298 299 /* TCR */ 300 iommu_writel(ctx, ARM_SMMU_CB_TCR2, 301 arm_smmu_lpae_tcr2(&pgtbl_cfg)); 302 iommu_writel(ctx, ARM_SMMU_CB_TCR, 303 arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE); 304 305 /* MAIRs (stage-1 only) */ 306 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 307 pgtbl_cfg.arm_lpae_s1_cfg.mair); 308 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 309 pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32); 310 311 /* SCTLR */ 312 reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE | 313 ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE | 314 ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE | 315 ARM_SMMU_SCTLR_CFCFG; 316 317 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 318 reg |= ARM_SMMU_SCTLR_E; 319 320 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg); 321 322 ctx->domain = domain; 323 } 324 325 mutex_unlock(&qcom_domain->init_mutex); 326 327 /* Publish page table ops for map/unmap */ 328 qcom_domain->pgtbl_ops = pgtbl_ops; 329 330 return 0; 331 332out_clear_iommu: 333 qcom_domain->iommu = NULL; 334out_unlock: 335 mutex_unlock(&qcom_domain->init_mutex); 336 return ret; 337} 338 339static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type) 340{ 341 struct qcom_iommu_domain *qcom_domain; 342 343 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA) 344 return NULL; 345 /* 346 * Allocate the domain and initialise some of its data structures. 347 * We can't really do anything meaningful until we've added a 348 * master. 349 */ 350 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL); 351 if (!qcom_domain) 352 return NULL; 353 354 if (type == IOMMU_DOMAIN_DMA && 355 iommu_get_dma_cookie(&qcom_domain->domain)) { 356 kfree(qcom_domain); 357 return NULL; 358 } 359 360 mutex_init(&qcom_domain->init_mutex); 361 spin_lock_init(&qcom_domain->pgtbl_lock); 362 363 return &qcom_domain->domain; 364} 365 366static void qcom_iommu_domain_free(struct iommu_domain *domain) 367{ 368 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 369 370 iommu_put_dma_cookie(domain); 371 372 if (qcom_domain->iommu) { 373 /* 374 * NOTE: unmap can be called after client device is powered 375 * off, for example, with GPUs or anything involving dma-buf. 376 * So we cannot rely on the device_link. Make sure the IOMMU 377 * is on to avoid unclocked accesses in the TLB inv path: 378 */ 379 pm_runtime_get_sync(qcom_domain->iommu->dev); 380 free_io_pgtable_ops(qcom_domain->pgtbl_ops); 381 pm_runtime_put_sync(qcom_domain->iommu->dev); 382 } 383 384 kfree(qcom_domain); 385} 386 387static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) 388{ 389 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 390 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 391 int ret; 392 393 if (!qcom_iommu) { 394 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n"); 395 return -ENXIO; 396 } 397 398 /* Ensure that the domain is finalized */ 399 pm_runtime_get_sync(qcom_iommu->dev); 400 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev); 401 pm_runtime_put_sync(qcom_iommu->dev); 402 if (ret < 0) 403 return ret; 404 405 /* 406 * Sanity check the domain. We don't support domains across 407 * different IOMMUs. 408 */ 409 if (qcom_domain->iommu != qcom_iommu) { 410 dev_err(dev, "cannot attach to IOMMU %s while already " 411 "attached to domain on IOMMU %s\n", 412 dev_name(qcom_domain->iommu->dev), 413 dev_name(qcom_iommu->dev)); 414 return -EINVAL; 415 } 416 417 return 0; 418} 419 420static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev) 421{ 422 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 423 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 424 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 425 unsigned i; 426 427 if (WARN_ON(!qcom_domain->iommu)) 428 return; 429 430 pm_runtime_get_sync(qcom_iommu->dev); 431 for (i = 0; i < fwspec->num_ids; i++) { 432 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); 433 434 /* Disable the context bank: */ 435 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); 436 437 ctx->domain = NULL; 438 } 439 pm_runtime_put_sync(qcom_iommu->dev); 440} 441 442static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova, 443 phys_addr_t paddr, size_t size, int prot, gfp_t gfp) 444{ 445 int ret; 446 unsigned long flags; 447 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 448 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; 449 450 if (!ops) 451 return -ENODEV; 452 453 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); 454 ret = ops->map(ops, iova, paddr, size, prot, GFP_ATOMIC); 455 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); 456 return ret; 457} 458 459static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova, 460 size_t size, struct iommu_iotlb_gather *gather) 461{ 462 size_t ret; 463 unsigned long flags; 464 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 465 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; 466 467 if (!ops) 468 return 0; 469 470 /* NOTE: unmap can be called after client device is powered off, 471 * for example, with GPUs or anything involving dma-buf. So we 472 * cannot rely on the device_link. Make sure the IOMMU is on to 473 * avoid unclocked accesses in the TLB inv path: 474 */ 475 pm_runtime_get_sync(qcom_domain->iommu->dev); 476 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); 477 ret = ops->unmap(ops, iova, size, gather); 478 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); 479 pm_runtime_put_sync(qcom_domain->iommu->dev); 480 481 return ret; 482} 483 484static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain) 485{ 486 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 487 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops, 488 struct io_pgtable, ops); 489 if (!qcom_domain->pgtbl_ops) 490 return; 491 492 pm_runtime_get_sync(qcom_domain->iommu->dev); 493 qcom_iommu_tlb_sync(pgtable->cookie); 494 pm_runtime_put_sync(qcom_domain->iommu->dev); 495} 496 497static void qcom_iommu_iotlb_sync(struct iommu_domain *domain, 498 struct iommu_iotlb_gather *gather) 499{ 500 qcom_iommu_flush_iotlb_all(domain); 501} 502 503static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain, 504 dma_addr_t iova) 505{ 506 phys_addr_t ret; 507 unsigned long flags; 508 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); 509 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; 510 511 if (!ops) 512 return 0; 513 514 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); 515 ret = ops->iova_to_phys(ops, iova); 516 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); 517 518 return ret; 519} 520 521static bool qcom_iommu_capable(enum iommu_cap cap) 522{ 523 switch (cap) { 524 case IOMMU_CAP_CACHE_COHERENCY: 525 /* 526 * Return true here as the SMMU can always send out coherent 527 * requests. 528 */ 529 return true; 530 case IOMMU_CAP_NOEXEC: 531 return true; 532 default: 533 return false; 534 } 535} 536 537static struct iommu_device *qcom_iommu_probe_device(struct device *dev) 538{ 539 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 540 struct device_link *link; 541 542 if (!qcom_iommu) 543 return ERR_PTR(-ENODEV); 544 545 /* 546 * Establish the link between iommu and master, so that the 547 * iommu gets runtime enabled/disabled as per the master's 548 * needs. 549 */ 550 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME); 551 if (!link) { 552 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", 553 dev_name(qcom_iommu->dev), dev_name(dev)); 554 return ERR_PTR(-ENODEV); 555 } 556 557 return &qcom_iommu->iommu; 558} 559 560static void qcom_iommu_release_device(struct device *dev) 561{ 562 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev); 563 564 if (!qcom_iommu) 565 return; 566 567 iommu_fwspec_free(dev); 568} 569 570static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) 571{ 572 struct qcom_iommu_dev *qcom_iommu; 573 struct platform_device *iommu_pdev; 574 unsigned asid = args->args[0]; 575 576 if (args->args_count != 1) { 577 dev_err(dev, "incorrect number of iommu params found for %s " 578 "(found %d, expected 1)\n", 579 args->np->full_name, args->args_count); 580 return -EINVAL; 581 } 582 583 iommu_pdev = of_find_device_by_node(args->np); 584 if (WARN_ON(!iommu_pdev)) 585 return -EINVAL; 586 587 qcom_iommu = platform_get_drvdata(iommu_pdev); 588 589 /* make sure the asid specified in dt is valid, so we don't have 590 * to sanity check this elsewhere, since 'asid - 1' is used to 591 * index into qcom_iommu->ctxs: 592 */ 593 if (WARN_ON(asid < 1) || 594 WARN_ON(asid > qcom_iommu->num_ctxs)) { 595 put_device(&iommu_pdev->dev); 596 return -EINVAL; 597 } 598 599 if (!dev_iommu_priv_get(dev)) { 600 dev_iommu_priv_set(dev, qcom_iommu); 601 } else { 602 /* make sure devices iommus dt node isn't referring to 603 * multiple different iommu devices. Multiple context 604 * banks are ok, but multiple devices are not: 605 */ 606 if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) { 607 put_device(&iommu_pdev->dev); 608 return -EINVAL; 609 } 610 } 611 612 return iommu_fwspec_add_ids(dev, &asid, 1); 613} 614 615static const struct iommu_ops qcom_iommu_ops = { 616 .capable = qcom_iommu_capable, 617 .domain_alloc = qcom_iommu_domain_alloc, 618 .domain_free = qcom_iommu_domain_free, 619 .attach_dev = qcom_iommu_attach_dev, 620 .detach_dev = qcom_iommu_detach_dev, 621 .map = qcom_iommu_map, 622 .unmap = qcom_iommu_unmap, 623 .flush_iotlb_all = qcom_iommu_flush_iotlb_all, 624 .iotlb_sync = qcom_iommu_iotlb_sync, 625 .iova_to_phys = qcom_iommu_iova_to_phys, 626 .probe_device = qcom_iommu_probe_device, 627 .release_device = qcom_iommu_release_device, 628 .device_group = generic_device_group, 629 .of_xlate = qcom_iommu_of_xlate, 630 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, 631}; 632 633static int qcom_iommu_sec_ptbl_init(struct device *dev) 634{ 635 size_t psize = 0; 636 unsigned int spare = 0; 637 void *cpu_addr; 638 dma_addr_t paddr; 639 unsigned long attrs; 640 static bool allocated = false; 641 int ret; 642 643 if (allocated) 644 return 0; 645 646 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize); 647 if (ret) { 648 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n", 649 ret); 650 return ret; 651 } 652 653 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize); 654 655 attrs = DMA_ATTR_NO_KERNEL_MAPPING; 656 657 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs); 658 if (!cpu_addr) { 659 dev_err(dev, "failed to allocate %zu bytes for pgtable\n", 660 psize); 661 return -ENOMEM; 662 } 663 664 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare); 665 if (ret) { 666 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret); 667 goto free_mem; 668 } 669 670 allocated = true; 671 return 0; 672 673free_mem: 674 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs); 675 return ret; 676} 677 678static int get_asid(const struct device_node *np) 679{ 680 u32 reg; 681 682 /* read the "reg" property directly to get the relative address 683 * of the context bank, and calculate the asid from that: 684 */ 685 if (of_property_read_u32_index(np, "reg", 0, ®)) 686 return -ENODEV; 687 688 return reg / 0x1000; /* context banks are 0x1000 apart */ 689} 690 691static int qcom_iommu_ctx_probe(struct platform_device *pdev) 692{ 693 struct qcom_iommu_ctx *ctx; 694 struct device *dev = &pdev->dev; 695 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent); 696 struct resource *res; 697 int ret, irq; 698 699 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 700 if (!ctx) 701 return -ENOMEM; 702 703 ctx->dev = dev; 704 platform_set_drvdata(pdev, ctx); 705 706 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 707 ctx->base = devm_ioremap_resource(dev, res); 708 if (IS_ERR(ctx->base)) 709 return PTR_ERR(ctx->base); 710 711 irq = platform_get_irq(pdev, 0); 712 if (irq < 0) 713 return -ENODEV; 714 715 /* clear IRQs before registering fault handler, just in case the 716 * boot-loader left us a surprise: 717 */ 718 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR)); 719 720 ret = devm_request_irq(dev, irq, 721 qcom_iommu_fault, 722 IRQF_SHARED, 723 "qcom-iommu-fault", 724 ctx); 725 if (ret) { 726 dev_err(dev, "failed to request IRQ %u\n", irq); 727 return ret; 728 } 729 730 ret = get_asid(dev->of_node); 731 if (ret < 0) { 732 dev_err(dev, "missing reg property\n"); 733 return ret; 734 } 735 736 ctx->asid = ret; 737 738 dev_dbg(dev, "found asid %u\n", ctx->asid); 739 740 qcom_iommu->ctxs[ctx->asid - 1] = ctx; 741 742 return 0; 743} 744 745static int qcom_iommu_ctx_remove(struct platform_device *pdev) 746{ 747 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent); 748 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev); 749 750 platform_set_drvdata(pdev, NULL); 751 752 qcom_iommu->ctxs[ctx->asid - 1] = NULL; 753 754 return 0; 755} 756 757static const struct of_device_id ctx_of_match[] = { 758 { .compatible = "qcom,msm-iommu-v1-ns" }, 759 { .compatible = "qcom,msm-iommu-v1-sec" }, 760 { /* sentinel */ } 761}; 762 763static struct platform_driver qcom_iommu_ctx_driver = { 764 .driver = { 765 .name = "qcom-iommu-ctx", 766 .of_match_table = ctx_of_match, 767 }, 768 .probe = qcom_iommu_ctx_probe, 769 .remove = qcom_iommu_ctx_remove, 770}; 771 772static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) 773{ 774 struct device_node *child; 775 776 for_each_child_of_node(qcom_iommu->dev->of_node, child) { 777 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) { 778 of_node_put(child); 779 return true; 780 } 781 } 782 783 return false; 784} 785 786static int qcom_iommu_device_probe(struct platform_device *pdev) 787{ 788 struct device_node *child; 789 struct qcom_iommu_dev *qcom_iommu; 790 struct device *dev = &pdev->dev; 791 struct resource *res; 792 struct clk *clk; 793 int ret, max_asid = 0; 794 795 /* find the max asid (which is 1:1 to ctx bank idx), so we know how 796 * many child ctx devices we have: 797 */ 798 for_each_child_of_node(dev->of_node, child) 799 max_asid = max(max_asid, get_asid(child)); 800 801 qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid), 802 GFP_KERNEL); 803 if (!qcom_iommu) 804 return -ENOMEM; 805 qcom_iommu->num_ctxs = max_asid; 806 qcom_iommu->dev = dev; 807 808 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 809 if (res) { 810 qcom_iommu->local_base = devm_ioremap_resource(dev, res); 811 if (IS_ERR(qcom_iommu->local_base)) 812 return PTR_ERR(qcom_iommu->local_base); 813 } 814 815 clk = devm_clk_get(dev, "iface"); 816 if (IS_ERR(clk)) { 817 dev_err(dev, "failed to get iface clock\n"); 818 return PTR_ERR(clk); 819 } 820 qcom_iommu->clks[CLK_IFACE].clk = clk; 821 822 clk = devm_clk_get(dev, "bus"); 823 if (IS_ERR(clk)) { 824 dev_err(dev, "failed to get bus clock\n"); 825 return PTR_ERR(clk); 826 } 827 qcom_iommu->clks[CLK_BUS].clk = clk; 828 829 clk = devm_clk_get_optional(dev, "tbu"); 830 if (IS_ERR(clk)) { 831 dev_err(dev, "failed to get tbu clock\n"); 832 return PTR_ERR(clk); 833 } 834 qcom_iommu->clks[CLK_TBU].clk = clk; 835 836 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", 837 &qcom_iommu->sec_id)) { 838 dev_err(dev, "missing qcom,iommu-secure-id property\n"); 839 return -ENODEV; 840 } 841 842 if (qcom_iommu_has_secure_context(qcom_iommu)) { 843 ret = qcom_iommu_sec_ptbl_init(dev); 844 if (ret) { 845 dev_err(dev, "cannot init secure pg table(%d)\n", ret); 846 return ret; 847 } 848 } 849 850 platform_set_drvdata(pdev, qcom_iommu); 851 852 pm_runtime_enable(dev); 853 854 /* register context bank devices, which are child nodes: */ 855 ret = devm_of_platform_populate(dev); 856 if (ret) { 857 dev_err(dev, "Failed to populate iommu contexts\n"); 858 return ret; 859 } 860 861 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL, 862 dev_name(dev)); 863 if (ret) { 864 dev_err(dev, "Failed to register iommu in sysfs\n"); 865 return ret; 866 } 867 868 iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops); 869 iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode); 870 871 ret = iommu_device_register(&qcom_iommu->iommu); 872 if (ret) { 873 dev_err(dev, "Failed to register iommu\n"); 874 return ret; 875 } 876 877 bus_set_iommu(&platform_bus_type, &qcom_iommu_ops); 878 879 if (qcom_iommu->local_base) { 880 pm_runtime_get_sync(dev); 881 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS); 882 pm_runtime_put_sync(dev); 883 } 884 885 return 0; 886} 887 888static int qcom_iommu_device_remove(struct platform_device *pdev) 889{ 890 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev); 891 892 bus_set_iommu(&platform_bus_type, NULL); 893 894 pm_runtime_force_suspend(&pdev->dev); 895 platform_set_drvdata(pdev, NULL); 896 iommu_device_sysfs_remove(&qcom_iommu->iommu); 897 iommu_device_unregister(&qcom_iommu->iommu); 898 899 return 0; 900} 901 902static int __maybe_unused qcom_iommu_resume(struct device *dev) 903{ 904 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev); 905 906 return clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks); 907} 908 909static int __maybe_unused qcom_iommu_suspend(struct device *dev) 910{ 911 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev); 912 913 clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks); 914 915 return 0; 916} 917 918static const struct dev_pm_ops qcom_iommu_pm_ops = { 919 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL) 920 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 921 pm_runtime_force_resume) 922}; 923 924static const struct of_device_id qcom_iommu_of_match[] = { 925 { .compatible = "qcom,msm-iommu-v1" }, 926 { /* sentinel */ } 927}; 928 929static struct platform_driver qcom_iommu_driver = { 930 .driver = { 931 .name = "qcom-iommu", 932 .of_match_table = qcom_iommu_of_match, 933 .pm = &qcom_iommu_pm_ops, 934 }, 935 .probe = qcom_iommu_device_probe, 936 .remove = qcom_iommu_device_remove, 937}; 938 939static int __init qcom_iommu_init(void) 940{ 941 int ret; 942 943 ret = platform_driver_register(&qcom_iommu_ctx_driver); 944 if (ret) 945 return ret; 946 947 ret = platform_driver_register(&qcom_iommu_driver); 948 if (ret) 949 platform_driver_unregister(&qcom_iommu_ctx_driver); 950 951 return ret; 952} 953device_initcall(qcom_iommu_init); 954